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Code Issues Packages Projects Releases Wiki Activity

Update On Wed May 28 20:37:22 CEST 2025

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This commit is contained in:
github-action[bot]
2025-05-28 20:37:22 +02:00
parent e252910be8
commit abf8045e42
234 changed files with 30216 additions and 497 deletions
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1
.github/update.log vendored
View File

@@ -1012,3 +1012,4 @@ Update On Sat May 24 20:33:25 CEST 2025
Update On Sun May 25 20:34:05 CEST 2025
Update On Mon May 26 20:35:45 CEST 2025
Update On Tue May 27 20:37:03 CEST 2025
Update On Wed May 28 20:37:14 CEST 2025

29
clash-meta/component/sniffer/dispatcher.go
View File

@@ -72,8 +72,16 @@ func (sd *Dispatcher) UDPSniff(packet C.PacketAdapter, packetSender C.PacketSend
overrideDest := config.OverrideDest
if inWhitelist {
replaceDomain := func(metadata *C.Metadata, host string) {
if sd.domainCanReplace(host) {
replaceDomain(metadata, host, overrideDest)
} else {
log.Debugln("[Sniffer] Skip sni[%s]", host)
}
}
if wrapable, ok := current.(sniffer.MultiPacketSniffer); ok {
return wrapable.WrapperSender(packetSender, overrideDest)
return wrapable.WrapperSender(packetSender, replaceDomain)
}
host, err := current.SniffData(packet.Data())
@@ -81,7 +89,7 @@ func (sd *Dispatcher) UDPSniff(packet C.PacketAdapter, packetSender C.PacketSend
continue
}
replaceDomain(metadata, host, overrideDest)
replaceDomain(metadata, host)
return packetSender
}
}
@@ -128,11 +136,9 @@ func (sd *Dispatcher) TCPSniff(conn *N.BufferedConn, metadata *C.Metadata) bool
return false
}
for _, matcher := range sd.skipDomain {
if matcher.MatchDomain(host) {
log.Debugln("[Sniffer] Skip sni[%s]", host)
return false
}
if !sd.domainCanReplace(host) {
log.Debugln("[Sniffer] Skip sni[%s]", host)
return false
}
sd.skipList.Delete(dst)
@@ -157,6 +163,15 @@ func replaceDomain(metadata *C.Metadata, host string, overrideDest bool) {
metadata.DNSMode = C.DNSNormal
}
func (sd *Dispatcher) domainCanReplace(host string) bool {
for _, matcher := range sd.skipDomain {
if matcher.MatchDomain(host) {
return false
}
}
return true
}
func (sd *Dispatcher) Enable() bool {
return sd != nil && sd.enable
}

26
clash-meta/component/sniffer/quic_sniffer.go
View File

@@ -74,22 +74,23 @@ func (sniffer *QuicSniffer) SniffData(b []byte) (string, error) {
return "", ErrorUnsupportedSniffer
}
func (sniffer *QuicSniffer) WrapperSender(packetSender constant.PacketSender, override bool) constant.PacketSender {
func (sniffer *QuicSniffer) WrapperSender(packetSender constant.PacketSender, replaceDomain sniffer.ReplaceDomain) constant.PacketSender {
return &quicPacketSender{
PacketSender: packetSender,
chClose: make(chan struct{}),
override: override,
PacketSender: packetSender,
replaceDomain: replaceDomain,
chClose: make(chan struct{}),
}
}
var _ constant.PacketSender = (*quicPacketSender)(nil)
type quicPacketSender struct {
lock sync.RWMutex
ranges utils.IntRanges[uint64]
buffer []byte
result string
override bool
lock sync.RWMutex
ranges utils.IntRanges[uint64]
buffer []byte
result *string
replaceDomain sniffer.ReplaceDomain
constant.PacketSender
@@ -121,7 +122,10 @@ func (q *quicPacketSender) DoSniff(metadata *constant.Metadata) error {
select {
case <-q.chClose:
q.lock.RLock()
replaceDomain(metadata, q.result, q.override)
if q.result != nil {
host := *q.result
q.replaceDomain(metadata, host)
}
q.lock.RUnlock()
break
case <-time.After(quicWaitConn):
@@ -428,7 +432,7 @@ func (q *quicPacketSender) tryAssemble() error {
}
q.lock.Lock()
q.result = *domain
q.result = domain
q.closeLocked()
q.lock.Unlock()

38
clash-meta/component/sniffer/sniff_test.go
View File

@@ -67,19 +67,23 @@ func asPacket(data string) constant.PacketAdapter {
return pktAdp
}
func testQuicSniffer(data []string, async bool) (string, error) {
const fakeHost = "fake.host.com"
func testQuicSniffer(data []string, async bool) (string, string, error) {
q, err := NewQuicSniffer(SnifferConfig{})
if err != nil {
return "", err
return "", "", err
}
resultCh := make(chan *constant.Metadata, 1)
emptySender := &fakeSender{}
sender := q.WrapperSender(emptySender, true)
sender := q.WrapperSender(emptySender, func(metadata *constant.Metadata, host string) {
replaceDomain(metadata, host, true)
})
go func() {
meta := constant.Metadata{}
meta := constant.Metadata{Host: fakeHost}
err := sender.DoSniff(&meta)
if err != nil {
panic(err)
@@ -96,14 +100,15 @@ func testQuicSniffer(data []string, async bool) (string, error) {
}
meta := <-resultCh
return meta.SniffHost, nil
return meta.SniffHost, meta.Host, nil
}
func TestQuicHeaders(t *testing.T) {
cases := []struct {
input []string
domain string
input []string
domain string
invalid bool
}{
//Normal domain quic sniff
{
@@ -161,16 +166,31 @@ func TestQuicHeaders(t *testing.T) {
},
domain: "www.google.com",
},
// invalid packet
{
input: []string{"00000000000000000000"},
invalid: true,
},
}
for _, test := range cases {
data, err := testQuicSniffer(test.input, true)
data, host, err := testQuicSniffer(test.input, true)
assert.NoError(t, err)
assert.Equal(t, test.domain, data)
if test.invalid {
assert.Equal(t, fakeHost, host)
} else {
assert.Equal(t, test.domain, host)
}
data, err = testQuicSniffer(test.input, false)
data, host, err = testQuicSniffer(test.input, false)
assert.NoError(t, err)
assert.Equal(t, test.domain, data)
if test.invalid {
assert.Equal(t, fakeHost, host)
} else {
assert.Equal(t, test.domain, host)
}
}
}

4
clash-meta/constant/sniffer/sniffer.go
View File

@@ -10,8 +10,10 @@ type Sniffer interface {
SupportPort(port uint16) bool
}
type ReplaceDomain func(metadata *constant.Metadata, host string)
type MultiPacketSniffer interface {
WrapperSender(packetSender constant.PacketSender, override bool) constant.PacketSender
WrapperSender(packetSender constant.PacketSender, replaceDomain ReplaceDomain) constant.PacketSender
}
const (

2
clash-meta/go.mod
View File

@@ -32,7 +32,7 @@ require (
github.com/metacubex/sing-shadowsocks2 v0.2.4
github.com/metacubex/sing-shadowtls v0.0.0-20250503063515-5d9f966d17a2
github.com/metacubex/sing-tun v0.4.6-0.20250524142129-9d110c0af70c
github.com/metacubex/sing-vmess v0.2.1
github.com/metacubex/sing-vmess v0.2.2
github.com/metacubex/sing-wireguard v0.0.0-20250503063753-2dc62acc626f
github.com/metacubex/smux v0.0.0-20250503055512-501391591dee
github.com/metacubex/tfo-go v0.0.0-20250516165257-e29c16ae41d4

4
clash-meta/go.sum
View File

@@ -130,8 +130,8 @@ github.com/metacubex/sing-shadowtls v0.0.0-20250503063515-5d9f966d17a2 h1:gXU+MY
github.com/metacubex/sing-shadowtls v0.0.0-20250503063515-5d9f966d17a2/go.mod h1:mbfboaXauKJNIHJYxQRa+NJs4JU9NZfkA+I33dS2+9E=
github.com/metacubex/sing-tun v0.4.6-0.20250524142129-9d110c0af70c h1:Y6jk7AH5BEg9Dsvczrf/KokYsvxeKSZZlCLHg+hC4ro=
github.com/metacubex/sing-tun v0.4.6-0.20250524142129-9d110c0af70c/go.mod h1:HDaHDL6onAX2ZGbAGUXKp++PohRdNb7Nzt6zxzhox+U=
github.com/metacubex/sing-vmess v0.2.1 h1:I6gM3VUjtvJ15D805EUbNH+SRBuqzJeFnuIbKYUsWZ0=
github.com/metacubex/sing-vmess v0.2.1/go.mod h1:DsODWItJtOMZNna8Qhheg8r3tUivrcO3vWgaTYKnfTo=
github.com/metacubex/sing-vmess v0.2.2 h1:nG6GIKF1UOGmlzs+BIetdGHkFZ20YqFVIYp5Htqzp+4=
github.com/metacubex/sing-vmess v0.2.2/go.mod h1:CVDNcdSLVYFgTHQlubr88d8CdqupAUDqLjROos+H9xk=
github.com/metacubex/sing-wireguard v0.0.0-20250503063753-2dc62acc626f h1:Sr/DYKYofKHKc4GF3qkRGNuj6XA6c0eqPgEDN+VAsYU=
github.com/metacubex/sing-wireguard v0.0.0-20250503063753-2dc62acc626f/go.mod h1:jpAkVLPnCpGSfNyVmj6Cq4YbuZsFepm/Dc+9BAOcR80=
github.com/metacubex/smux v0.0.0-20250503055512-501391591dee h1:lp6hJ+4wCLZu113awp7P6odM2okB5s60HUyF0FMqKmo=

4
clash-nyanpasu/frontend/nyanpasu/package.json
View File

@@ -33,7 +33,7 @@
"dayjs": "1.11.13",
"framer-motion": "12.11.4",
"i18next": "25.1.3",
"jotai": "2.12.4",
"jotai": "2.12.5",
"json-schema": "0.4.0",
"material-react-table": "3.2.1",
"monaco-editor": "0.52.2",
@@ -86,7 +86,7 @@
"shiki": "2.5.0",
"unplugin-auto-import": "19.2.0",
"unplugin-icons": "22.1.0",
"validator": "13.15.0",
"validator": "13.15.15",
"vite": "6.3.5",
"vite-plugin-html": "3.2.2",
"vite-plugin-sass-dts": "1.3.31",

4
clash-nyanpasu/manifest/version.json
View File

@@ -2,7 +2,7 @@
"manifest_version": 1,
"latest": {
"mihomo": "v1.19.9",
"mihomo_alpha": "alpha-12e3952",
"mihomo_alpha": "alpha-689c58f",
"clash_rs": "v0.7.8",
"clash_premium": "2023-09-05-gdcc8d87",
"clash_rs_alpha": "0.7.8-alpha+sha.f762b51"
@@ -69,5 +69,5 @@
"linux-armv7hf": "clash-armv7-unknown-linux-gnueabihf"
}
},
"updated_at": "2025-05-26T22:20:55.318Z"
"updated_at": "2025-05-27T22:21:00.999Z"
}

2
clash-nyanpasu/package.json
View File

@@ -65,7 +65,7 @@
"@tauri-apps/cli": "2.5.0",
"@types/fs-extra": "11.0.4",
"@types/lodash-es": "4.17.12",
"@types/node": "22.15.21",
"@types/node": "22.15.23",
"@typescript-eslint/eslint-plugin": "8.32.1",
"@typescript-eslint/parser": "8.32.1",
"autoprefixer": "10.4.21",

160
clash-nyanpasu/pnpm-lock.yaml generated
View File

@@ -21,7 +21,7 @@ importers:
devDependencies:
'@commitlint/cli':
specifier: 19.8.1
version: 19.8.1(@types/node@22.15.21)(typescript@5.8.3)
version: 19.8.1(@types/node@22.15.23)(typescript@5.8.3)
'@commitlint/config-conventional':
specifier: 19.8.1
version: 19.8.1
@@ -44,8 +44,8 @@ importers:
specifier: 4.17.12
version: 4.17.12
'@types/node':
specifier: 22.15.21
version: 22.15.21
specifier: 22.15.23
version: 22.15.23
'@typescript-eslint/eslint-plugin':
specifier: 8.32.1
version: 8.32.1(@typescript-eslint/parser@8.32.1(eslint@9.26.0(jiti@2.4.2))(typescript@5.8.3))(eslint@9.26.0(jiti@2.4.2))(typescript@5.8.3)
@@ -102,7 +102,7 @@ importers:
version: 16.2.0
knip:
specifier: 5.58.1
version: 5.58.1(@types/node@22.15.21)(typescript@5.8.3)
version: 5.58.1(@types/node@22.15.23)(typescript@5.8.3)
lint-staged:
specifier: 16.0.0
version: 16.0.0
@@ -276,8 +276,8 @@ importers:
specifier: 25.1.3
version: 25.1.3(typescript@5.8.3)
jotai:
specifier: 2.12.4
version: 2.12.4(@types/react@19.1.6)(react@19.1.0)
specifier: 2.12.5
version: 2.12.5(@types/react@19.1.6)(react@19.1.0)
json-schema:
specifier: 0.4.0
version: 0.4.0
@@ -353,7 +353,7 @@ importers:
version: 1.120.11(@tanstack/react-router@1.120.11(react-dom@19.1.0(react@19.1.0))(react@19.1.0))(@tanstack/router-core@1.120.10)(csstype@3.1.3)(react-dom@19.1.0(react@19.1.0))(react@19.1.0)(tiny-invariant@1.3.3)
'@tanstack/router-plugin':
specifier: 1.120.11
version: 1.120.11(@tanstack/react-router@1.120.11(react-dom@19.1.0(react@19.1.0))(react@19.1.0))(vite@6.3.5(@types/node@22.15.21)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
version: 1.120.11(@tanstack/react-router@1.120.11(react-dom@19.1.0(react@19.1.0))(react@19.1.0))(vite@6.3.5(@types/node@22.15.23)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
'@tauri-apps/plugin-clipboard-manager':
specifier: 2.2.2
version: 2.2.2
@@ -389,13 +389,13 @@ importers:
version: 13.15.1
'@vitejs/plugin-legacy':
specifier: 6.1.1
version: 6.1.1(terser@5.36.0)(vite@6.3.5(@types/node@22.15.21)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
version: 6.1.1(terser@5.36.0)(vite@6.3.5(@types/node@22.15.23)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
'@vitejs/plugin-react':
specifier: 4.4.1
version: 4.4.1(vite@6.3.5(@types/node@22.15.21)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
version: 4.4.1(vite@6.3.5(@types/node@22.15.23)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
'@vitejs/plugin-react-swc':
specifier: 3.9.0
version: 3.9.0(vite@6.3.5(@types/node@22.15.21)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
version: 3.9.0(vite@6.3.5(@types/node@22.15.23)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
change-case:
specifier: 5.4.4
version: 5.4.4
@@ -430,23 +430,23 @@ importers:
specifier: 22.1.0
version: 22.1.0(@svgr/core@8.1.0(typescript@5.8.3))
validator:
specifier: 13.15.0
version: 13.15.0
specifier: 13.15.15
version: 13.15.15
vite:
specifier: 6.3.5
version: 6.3.5(@types/node@22.15.21)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0)
version: 6.3.5(@types/node@22.15.23)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0)
vite-plugin-html:
specifier: 3.2.2
version: 3.2.2(vite@6.3.5(@types/node@22.15.21)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
version: 3.2.2(vite@6.3.5(@types/node@22.15.23)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
vite-plugin-sass-dts:
specifier: 1.3.31
version: 1.3.31(postcss@8.5.3)(prettier@3.5.3)(sass-embedded@1.88.0)(vite@6.3.5(@types/node@22.15.21)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
version: 1.3.31(postcss@8.5.3)(prettier@3.5.3)(sass-embedded@1.88.0)(vite@6.3.5(@types/node@22.15.23)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
vite-plugin-svgr:
specifier: 4.3.0
version: 4.3.0(rollup@4.40.0)(typescript@5.8.3)(vite@6.3.5(@types/node@22.15.21)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
version: 4.3.0(rollup@4.40.0)(typescript@5.8.3)(vite@6.3.5(@types/node@22.15.23)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
vite-tsconfig-paths:
specifier: 5.1.4
version: 5.1.4(typescript@5.8.3)(vite@6.3.5(@types/node@22.15.21)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
version: 5.1.4(typescript@5.8.3)(vite@6.3.5(@types/node@22.15.23)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
zod:
specifier: 3.24.4
version: 3.24.4
@@ -482,7 +482,7 @@ importers:
version: 19.1.6
'@vitejs/plugin-react':
specifier: 4.4.1
version: 4.4.1(vite@6.3.5(@types/node@22.15.21)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
version: 4.4.1(vite@6.3.5(@types/node@22.15.23)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
ahooks:
specifier: 3.8.5
version: 3.8.5(react@19.1.0)
@@ -512,10 +512,10 @@ importers:
version: 4.1.7
vite:
specifier: 6.3.5
version: 6.3.5(@types/node@22.15.21)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0)
version: 6.3.5(@types/node@22.15.23)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0)
vite-tsconfig-paths:
specifier: 5.1.4
version: 5.1.4(typescript@5.8.3)(vite@6.3.5(@types/node@22.15.21)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
version: 5.1.4(typescript@5.8.3)(vite@6.3.5(@types/node@22.15.23)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
devDependencies:
'@emotion/react':
specifier: 11.14.0
@@ -540,7 +540,7 @@ importers:
version: 5.1.0(typescript@5.8.3)
vite-plugin-dts:
specifier: 4.5.4
version: 4.5.4(@types/node@22.15.21)(rollup@4.40.0)(typescript@5.8.3)(vite@6.3.5(@types/node@22.15.21)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0))
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scripts:
dependencies:
@@ -3168,8 +3168,8 @@ packages:
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@@ -5592,8 +5592,8 @@ packages:
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jotai@2.12.5:
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engines: {node: '>=12.20.0'}
peerDependencies:
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@@ -8013,8 +8013,8 @@ packages:
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engines: {node: '>= 0.10'}
varint@6.0.0:
@@ -9129,11 +9129,11 @@ snapshots:
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'@commitlint/read': 19.8.1
'@commitlint/types': 19.8.1
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@@ -9180,7 +9180,7 @@ snapshots:
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dependencies:
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'@commitlint/execute-rule': 19.8.1
@@ -9188,7 +9188,7 @@ snapshots:
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cosmiconfig-typescript-loader: 6.1.0(@types/node@22.15.23)(cosmiconfig@9.0.0(typescript@5.8.3))(typescript@5.8.3)
lodash.isplainobject: 4.0.6
lodash.merge: 4.6.2
lodash.uniq: 4.5.0
@@ -9638,23 +9638,23 @@ snapshots:
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transitivePeerDependencies:
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'@rushstack/terminal': 0.15.0(@types/node@22.15.21)
'@rushstack/ts-command-line': 4.23.5(@types/node@22.15.21)
'@rushstack/terminal': 0.15.0(@types/node@22.15.23)
'@rushstack/ts-command-line': 4.23.5(@types/node@22.15.23)
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@@ -10331,7 +10331,7 @@ snapshots:
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'@rushstack/node-core-library@5.11.0(@types/node@22.15.23)':
dependencies:
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ajv-draft-04: 1.0.0(ajv@8.13.0)
@@ -10342,23 +10342,23 @@ snapshots:
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semver: 7.5.4
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'@rushstack/terminal@0.15.0(@types/node@22.15.21)':
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'@rushstack/node-core-library': 5.11.0(@types/node@22.15.23)
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string-argv: 0.3.2
@@ -10692,7 +10692,7 @@ snapshots:
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@@ -10713,7 +10713,7 @@ snapshots:
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transitivePeerDependencies:
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@@ -10875,12 +10875,12 @@ snapshots:
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'@types/keyv': 3.1.4
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'@types/responselike': 1.0.3
'@types/conventional-commits-parser@5.0.0':
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'@types/node': 22.15.23
'@types/d3-array@3.2.1': {}
@@ -11018,7 +11018,7 @@ snapshots:
'@types/fs-extra@11.0.4':
dependencies:
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'@types/node': 22.15.21
'@types/node': 22.15.23
'@types/geojson@7946.0.14': {}
@@ -11036,11 +11036,11 @@ snapshots:
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'@types/lodash-es@4.17.12':
dependencies:
@@ -11056,7 +11056,7 @@ snapshots:
'@types/node@16.18.108': {}
'@types/node@22.15.21':
'@types/node@22.15.23':
dependencies:
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@@ -11090,7 +11090,7 @@ snapshots:
'@types/responselike@1.0.3':
dependencies:
'@types/node': 22.15.21
'@types/node': 22.15.23
'@types/retry@0.12.2': {}
@@ -11110,7 +11110,7 @@ snapshots:
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'@types/node': 22.15.23
optional: true
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@@ -11229,7 +11229,7 @@ snapshots:
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'@babel/preset-env': 7.26.9(@babel/core@7.26.10)
@@ -11240,25 +11240,25 @@ snapshots:
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vite: 6.3.5(@types/node@22.15.23)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0)
transitivePeerDependencies:
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transitivePeerDependencies:
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vite: 6.3.5(@types/node@22.15.23)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0)
transitivePeerDependencies:
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@@ -11930,9 +11930,9 @@ snapshots:
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vary: 1.1.2
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cosmiconfig: 9.0.0(typescript@5.8.3)
jiti: 2.4.2
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@@ -13904,7 +13904,7 @@ snapshots:
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jotai@2.12.4(@types/react@19.1.6)(react@19.1.0):
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react: 19.1.0
@@ -13984,10 +13984,10 @@ snapshots:
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knip@5.58.1(@types/node@22.15.21)(typescript@5.8.3):
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'@types/node': 22.15.21
'@types/node': 22.15.23
fast-glob: 3.3.3
formatly: 0.2.3
jiti: 2.4.2
@@ -16556,7 +16556,7 @@ snapshots:
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validator@13.15.0: {}
validator@13.15.15: {}
varint@6.0.0: {}
@@ -16589,9 +16589,9 @@ snapshots:
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- supports-color
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'@volar/typescript': 2.4.11
'@vue/language-core': 2.2.0(typescript@5.8.3)
@@ -16602,13 +16602,13 @@ snapshots:
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typescript: 5.8.3
optionalDependencies:
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vite: 6.3.5(@types/node@22.15.23)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0)
transitivePeerDependencies:
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- rollup
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dependencies:
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colorette: 2.0.20
@@ -16622,39 +16622,39 @@ snapshots:
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node-html-parser: 5.4.2
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postcss-js: 4.0.1(postcss@8.5.3)
prettier: 3.5.3
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'@svgr/plugin-jsx': 8.1.0(@svgr/core@8.1.0(typescript@5.8.3))
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transitivePeerDependencies:
- rollup
- supports-color
- typescript
vite-tsconfig-paths@5.1.4(typescript@5.8.3)(vite@6.3.5(@types/node@22.15.21)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0)):
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dependencies:
debug: 4.3.7
globrex: 0.1.2
tsconfck: 3.0.3(typescript@5.8.3)
optionalDependencies:
vite: 6.3.5(@types/node@22.15.21)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0)
vite: 6.3.5(@types/node@22.15.23)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0)
transitivePeerDependencies:
- supports-color
- typescript
vite@6.3.5(@types/node@22.15.21)(jiti@2.4.2)(less@4.2.0)(lightningcss@1.30.1)(sass-embedded@1.88.0)(sass@1.83.0)(stylus@0.62.0)(terser@5.36.0)(tsx@4.19.4)(yaml@2.8.0):
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dependencies:
esbuild: 0.25.0
fdir: 6.4.4(picomatch@4.0.2)
@@ -16663,7 +16663,7 @@ snapshots:
rollup: 4.40.0
tinyglobby: 0.2.13
optionalDependencies:
'@types/node': 22.15.21
'@types/node': 22.15.23
fsevents: 2.3.3
jiti: 2.4.2
less: 4.2.0

6
clash-verge-rev/UPDATELOG.md
View File

@@ -1,9 +1,12 @@
## v2.2.4-alpha
尽管外部控制密钥已自动补全默认值且不允许为空。仍然推荐自行修改外部控制密钥。
#### 已知问题
- 仅在Ubuntu 22.04/24.04，Fedora 41 **Gnome桌面环境** 做过简单测试，不保证其他其他Linux发行版可用，将在未来做进一步适配和调优
- MacOS 下 墙贴主要为浅色，Tray 图标深色时图标闪烁；彩色 Tray 速率颜色淡
- 窗口状态管理器已确定上游存在缺陷，暂时移除。当前不再内置窗口大小和位置记忆。
- MacOS 下卸载服务后需手动重启软件才能与内核通信。
### 2.2.4 相对于 2.2.3
#### 修复了：
@@ -24,6 +27,7 @@
- 无法修改配置更新 HTTP 请求超时
- 修复 getDelayFix 钩子问题
- 使用外部扩展脚本覆写代理组时首页无法显示代理组
- 导出诊断 Verge 版本与设置页面不同步
#### 新增了：
- Mihomo(Meta)内核升级至 1.19.9
@@ -50,6 +54,7 @@
- 切换、升级、重启内核的状态管理
- 更精细化控制自动日志清理，新增1天选项
- Winodws 快捷键名称改为 `Clash Verge`
- 配置加载阶段自动补全 external-controller secret 字段。
#### 优化了：
- 系统代理 Bypass 设置
@@ -79,6 +84,7 @@
- 优化端口设置退出和保存机制
- 强制为 Mihomo 配置补全并覆盖 external-controller-cors 字段，默认不允许跨域和仅本地请求，提升 cors 安全性，升级配置时自动覆盖
- 修改 端口检测范围 （1111-65536）
- 配置文件缺失 secret 字段时自动填充默认值 set-your-secret
#### 移除了：
- 窗口状态管理器

8
clash-verge-rev/src-tauri/src/config/clash.rs
View File

@@ -20,6 +20,12 @@ impl IClashTemp {
map.insert(key.clone(), template.0.get(key).unwrap().clone());
}
});
// 确保 secret 字段存在且不为空
if let Some(Value::String(s)) = map.get_mut("secret") {
if s.is_empty() {
*s = "set-your-secret".to_string();
}
}
Self(Self::guard(map))
}
Err(err) => {
@@ -64,7 +70,7 @@ impl IClashTemp {
]
.into(),
);
map.insert("secret".into(), "".into());
map.insert("secret".into(), "set-your-secret".into());
map.insert("tun".into(), tun.into());
map.insert("external-controller-cors".into(), cors_map.into());
map.insert("unified-delay".into(), true.into());

3
clash-verge-rev/src-tauri/src/module/sysinfo.rs
View File

@@ -33,8 +33,7 @@ impl PlatformSpecification {
let system_arch = System::cpu_arch();
let handler = handle::Handle::global().app_handle().unwrap();
let config = handler.config();
let verge_version = config.version.clone().unwrap_or("Null".into());
let verge_version = handler.package_info().version.to_string();
// 使用默认值避免在同步上下文中执行异步操作
let running_mode = "NotRunning".to_string();

25
clash-verge-rev/src/components/setting/mods/controller-viewer.tsx
View File

@@ -42,7 +42,12 @@ export const ControllerViewer = forwardRef<DialogRef>((props, ref) => {
// 保存配置
const onSave = useLockFn(async () => {
if (!controller.trim()) {
showNotice('info', t("Controller address cannot be empty"), 3000);
showNotice('error', t("Controller address cannot be empty"), 3000);
return;
}
if (!secret.trim()) {
showNotice('error', t("Secret cannot be empty"), 3000);
return;
}
@@ -95,14 +100,13 @@ export const ControllerViewer = forwardRef<DialogRef>((props, ref) => {
size="small"
sx={{
width: 175,
opacity: 0.7,
pointerEvents: 'none'
opacity: 1,
pointerEvents: 'auto'
}}
value={controller}
placeholder="Required"
onChange={() => {}}
disabled={true}
inputProps={{ readOnly: true }}
onChange={e => setController(e.target.value)}
disabled={isSaving}
/>
<Tooltip title={t("Copy to clipboard")}>
<IconButton
@@ -124,14 +128,13 @@ export const ControllerViewer = forwardRef<DialogRef>((props, ref) => {
size="small"
sx={{
width: 175,
opacity: 0.7,
pointerEvents: 'none'
opacity: 1,
pointerEvents: 'auto'
}}
value={secret}
placeholder={t("Recommended")}
onChange={() => {}}
disabled={true}
inputProps={{ readOnly: true }}
onChange={e => setSecret(e.target.value)}
disabled={isSaving}
/>
<Tooltip title={t("Copy to clipboard")}>
<IconButton

2
dns-over-https/systemd/doh-client.service
View File

@@ -4,6 +4,7 @@ Documentation=https://github.com/m13253/dns-over-https
After=network.target
Before=nss-lookup.target
Wants=nss-lookup.target
StartLimitIntervalSec=0
[Service]
AmbientCapabilities=CAP_NET_BIND_SERVICE
@@ -13,7 +14,6 @@ Restart=always
RestartSec=1s
RestartMaxDelaySec=76s
RestartSteps=9
StartLimitIntervalSec=0
Type=simple
DynamicUser=yes

2
dns-over-https/systemd/doh-server.service
View File

@@ -2,6 +2,7 @@
Description=DNS-over-HTTPS Server
Documentation=https://github.com/m13253/dns-over-https
After=network.target
StartLimitIntervalSec=0
[Service]
AmbientCapabilities=CAP_NET_BIND_SERVICE
@@ -11,7 +12,6 @@ Restart=always
RestartSec=1s
RestartMaxDelaySec=76s
RestartSteps=9
StartLimitIntervalSec=0
Type=simple
DynamicUser=yes

2
lede/feeds.conf.default
View File

@@ -1,6 +1,6 @@
src-git packages https://github.com/coolsnowwolf/packages
#src-git luci https://github.com/coolsnowwolf/luci
src-git luci https://github.com/coolsnowwolf/luci.git;openwrt-23.05
src-git luci https://github.com/coolsnowwolf/luci.git;openwrt-24.10
src-git routing https://github.com/coolsnowwolf/routing
src-git telephony https://github.com/coolsnowwolf/telephony.git
#src-git helloworld https://github.com/fw876/helloworld.git

26
lede/package/kernel/linux/modules/netdevices.mk
View File

@@ -425,7 +425,8 @@ define KernelPackage/phy-realtek
KCONFIG:=CONFIG_REALTEK_PHY \
CONFIG_REALTEK_PHY_HWMON=y
DEPENDS:=+kmod-libphy +kmod-hwmon-core
FILES:=$(LINUX_DIR)/drivers/net/phy/realtek/realtek.ko
FILES:=$(LINUX_DIR)/drivers/net/phy/realtek.ko@lt6.12 \
$(LINUX_DIR)/drivers/net/phy/realtek/realtek.ko@ge6.12
AUTOLOAD:=$(call AutoLoad,18,realtek,1)
endef
@@ -1052,29 +1053,28 @@ $(eval $(call KernelPackage,e1000e))
define KernelPackage/libie
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Intel Ethernet library
DEPENDS:=@PCI_SUPPORT +kmod-i2c-core +kmod-i2c-algo-bit +kmod-ptp +kmod-hwmon-core
DEPENDS:=@LINUX_6_12 +kmod-libeth
KCONFIG:=CONFIG_LIBIE
HIDDEN:=1
FILES:=$(LINUX_DIR)/drivers/net/ethernet/intel/libie/libie.ko
AUTOLOAD:=$(call AutoLoad,30,libie,1)
endef
define KernelPackage/libie/description
Kernel modules for libie (Intel Ethernet library) common library
Intel Ethernet library
endef
$(eval $(call KernelPackage,libie))
define KernelPackage/libeth
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Intel Ethernet PHY library
DEPENDS:=@PCI_SUPPORT +kmod-i2c-core +kmod-i2c-algo-bit +kmod-ptp +kmod-hwmon-core
KCONFIG:=CONFIG_LIBIE
TITLE:=Common Intel Ethernet library
KCONFIG:=CONFIG_LIBETH
HIDDEN:=1
FILES:=$(LINUX_DIR)/drivers/net/ethernet/intel/libeth/libeth.ko
AUTOLOAD:=$(call AutoLoad,30,libeth,1)
endef
define KernelPackage/libeth/description
Kernel modules for libeth (Intel Ethernet library) common library
Common Intel Ethernet library
endef
$(eval $(call KernelPackage,libeth))
@@ -1158,7 +1158,7 @@ define KernelPackage/i40e
KCONFIG:=CONFIG_I40E \
CONFIG_I40E_DCB=y
FILES:=$(LINUX_DIR)/drivers/net/ethernet/intel/i40e/i40e.ko
AUTOLOAD:=$(call AutoProbe,i40e)
AUTOLOAD:=$(call AutoLoad,36,i40e,1)
endef
define KernelPackage/i40e/description
@@ -1171,13 +1171,12 @@ $(eval $(call KernelPackage,i40e))
define KernelPackage/iavf
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Intel(R) Ethernet Adaptive Virtual Function support
DEPENDS:=@PCI_SUPPORT +LINUX_6_12:kmod-libie +LINUX_6_12:kmod-libeth
DEPENDS:=@PCI_SUPPORT +LINUX_6_12:kmod-libie
KCONFIG:= \
CONFIG_I40EVF \
CONFIG_IAVF
FILES:= \
$(LINUX_DIR)/drivers/net/ethernet/intel/iavf/iavf.ko
AUTOLOAD:=$(call AutoProbe,i40evf iavf)
AUTOLOAD:=$(call AutoProbe,iavf)
endef
@@ -1193,8 +1192,9 @@ $(eval $(call KernelPackage,iavf))
define KernelPackage/ice
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Intel(R) Ethernet Controller E810 Series support
DEPENDS:=@PCI_SUPPORT +kmod-ptp
DEPENDS:=@PCI_SUPPORT +kmod-ptp +LINUX_6_12:kmod-hwmon-core +LINUX_6_12:kmod-libie
KCONFIG:=CONFIG_ICE \
CONFIG_ICE_HWMON=y \
CONFIG_ICE_HWTS=n \
CONFIG_ICE_SWITCHDEV=y
FILES:=$(LINUX_DIR)/drivers/net/ethernet/intel/ice/ice.ko

2
lede/package/kernel/mt76/Makefile
View File

@@ -1,7 +1,7 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=mt76
PKG_RELEASE=2
PKG_RELEASE=3
PKG_LICENSE:=GPLv2
PKG_LICENSE_FILES:=

98
lede/package/kernel/mt76/patches-6.x/300-wifi-mt76-convert-platform-driver-.remove-to-.remove.patch Normal file
View File

@@ -0,0 +1,98 @@
From: Shiji Yang <yangshiji66@outlook.com>
Date: Mon, 28 Apr 2025 22:16:03 +0800
Subject: [PATCH] wifi: mt76: convert platform driver .remove to .remove_new
This conversion can make the mt76 driver compatible with both
the 6.6 and 6.12 kernels. Fixes build error on 6.12:
/workspaces/openwrt/build_dir/target-x86_64_musl/linux-x86_64/mt76-2025.04.11~be28ef77/mt7603/soc.c:77:27: error: initialization of 'void (*)(struct platform_device *)' from incompatible pointer type 'int (*)(struct platform_device *)' [-Werror=incompatible-pointer-types]
77 | .remove = mt76_wmac_remove,
| ^~~~~~~~~~~~~~~~
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
---
mt7603/soc.c | 6 ++----
mt7615/soc.c | 6 ++----
mt7915/soc.c | 6 ++----
3 files changed, 6 insertions(+), 12 deletions(-)
--- a/mt7603/soc.c
+++ b/mt7603/soc.c
@@ -52,15 +52,13 @@ error:
return ret;
}
-static int
+static void
mt76_wmac_remove(struct platform_device *pdev)
{
struct mt76_dev *mdev = platform_get_drvdata(pdev);
struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
mt7603_unregister_device(dev);
-
- return 0;
}
static const struct of_device_id of_wmac_match[] = {
@@ -74,7 +72,7 @@ MODULE_FIRMWARE(MT7628_FIRMWARE_E2);
struct platform_driver mt76_wmac_driver = {
.probe = mt76_wmac_probe,
- .remove = mt76_wmac_remove,
+ .remove_new = mt76_wmac_remove,
.driver = {
.name = "mt76_wmac",
.of_match_table = of_wmac_match,
--- a/mt7615/soc.c
+++ b/mt7615/soc.c
@@ -45,13 +45,11 @@ static int mt7622_wmac_probe(struct plat
return mt7615_mmio_probe(&pdev->dev, mem_base, irq, mt7615e_reg_map);
}
-static int mt7622_wmac_remove(struct platform_device *pdev)
+static void mt7622_wmac_remove(struct platform_device *pdev)
{
struct mt7615_dev *dev = platform_get_drvdata(pdev);
mt7615_unregister_device(dev);
-
- return 0;
}
static const struct of_device_id mt7622_wmac_of_match[] = {
@@ -65,7 +63,7 @@ struct platform_driver mt7622_wmac_drive
.of_match_table = mt7622_wmac_of_match,
},
.probe = mt7622_wmac_probe,
- .remove = mt7622_wmac_remove,
+ .remove_new = mt7622_wmac_remove,
};
MODULE_FIRMWARE(MT7622_FIRMWARE_N9);
--- a/mt7915/soc.c
+++ b/mt7915/soc.c
@@ -1283,13 +1283,11 @@ free_device:
return ret;
}
-static int mt798x_wmac_remove(struct platform_device *pdev)
+static void mt798x_wmac_remove(struct platform_device *pdev)
{
struct mt7915_dev *dev = platform_get_drvdata(pdev);
mt7915_unregister_device(dev);
-
- return 0;
}
static const struct of_device_id mt798x_wmac_of_match[] = {
@@ -1306,7 +1304,7 @@ struct platform_driver mt798x_wmac_drive
.of_match_table = mt798x_wmac_of_match,
},
.probe = mt798x_wmac_probe,
- .remove = mt798x_wmac_remove,
+ .remove_new = mt798x_wmac_remove,
};
MODULE_FIRMWARE(MT7986_FIRMWARE_WA);

88
lede/target/linux/generic/backport-6.12/720-v6.13-net-phy-mediatek-ge-soc-Fix-coding-style.patch Normal file
View File

@@ -0,0 +1,88 @@
From 277f96c1f3f71d6e1d3bcf650d7cd84c1442210f Mon Sep 17 00:00:00 2001
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
Date: Thu, 17 Oct 2024 11:22:11 +0800
Subject: [PATCH 01/20] net: phy: mediatek-ge-soc: Fix coding style
This patch fixes spelling errors, re-arrange vars with
reverse Xmas tree and remove unnecessary parens in
mediatek-ge-soc.c.
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/net/phy/mediatek-ge-soc.c | 36 ++++++++++++++++---------------
1 file changed, 19 insertions(+), 17 deletions(-)
--- a/drivers/net/phy/mediatek-ge-soc.c
+++ b/drivers/net/phy/mediatek-ge-soc.c
@@ -408,16 +408,17 @@ static int tx_offset_cal_efuse(struct ph
static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
{
- int i;
- int bias[16] = {};
- const int vals_9461[16] = { 7, 1, 4, 7,
- 7, 1, 4, 7,
- 7, 1, 4, 7,
- 7, 1, 4, 7 };
const int vals_9481[16] = { 10, 6, 6, 10,
10, 6, 6, 10,
10, 6, 6, 10,
10, 6, 6, 10 };
+ const int vals_9461[16] = { 7, 1, 4, 7,
+ 7, 1, 4, 7,
+ 7, 1, 4, 7,
+ 7, 1, 4, 7 };
+ int bias[16] = {};
+ int i;
+
switch (phydev->drv->phy_id) {
case MTK_GPHY_ID_MT7981:
/* We add some calibration to efuse values
@@ -1069,10 +1070,10 @@ static int start_cal(struct phy_device *
static int mt798x_phy_calibration(struct phy_device *phydev)
{
+ struct nvmem_cell *cell;
int ret = 0;
- u32 *buf;
size_t len;
- struct nvmem_cell *cell;
+ u32 *buf;
cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
if (IS_ERR(cell)) {
@@ -1210,14 +1211,15 @@ static int mt798x_phy_led_brightness_set
return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
}
-static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
- BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
- BIT(TRIGGER_NETDEV_LINK) |
- BIT(TRIGGER_NETDEV_LINK_10) |
- BIT(TRIGGER_NETDEV_LINK_100) |
- BIT(TRIGGER_NETDEV_LINK_1000) |
- BIT(TRIGGER_NETDEV_RX) |
- BIT(TRIGGER_NETDEV_TX));
+static const unsigned long supported_triggers =
+ BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
+ BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
+ BIT(TRIGGER_NETDEV_LINK) |
+ BIT(TRIGGER_NETDEV_LINK_10) |
+ BIT(TRIGGER_NETDEV_LINK_100) |
+ BIT(TRIGGER_NETDEV_LINK_1000) |
+ BIT(TRIGGER_NETDEV_RX) |
+ BIT(TRIGGER_NETDEV_TX);
static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
unsigned long rules)
@@ -1415,7 +1417,7 @@ static int mt7988_phy_probe_shared(struc
* LED_C and LED_D respectively. At the same time those pins are used to
* bootstrap configuration of the reference clock source (LED_A),
* DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
- * In practise this is done using a LED and a resistor pulling the pin
+ * In practice this is done using a LED and a resistor pulling the pin
* either to GND or to VIO.
* The detected value at boot time is accessible at run-time using the
* TPBANK0 register located in the gpio base of the pinctrl, in order

271
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@@ -0,0 +1,271 @@
From c0dc1b412f9d840c51c5ee8927bf066e15a59550 Mon Sep 17 00:00:00 2001
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
Date: Thu, 17 Oct 2024 11:22:12 +0800
Subject: [PATCH 02/20] net: phy: mediatek-ge-soc: Shrink line wrapping to 80
characters
This patch shrinks line wrapping to 80 chars. Also, in
tx_amp_fill_result(), use FIELD_PREP() to prettify code.
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/net/phy/mediatek-ge-soc.c | 125 +++++++++++++++++++++---------
1 file changed, 88 insertions(+), 37 deletions(-)
--- a/drivers/net/phy/mediatek-ge-soc.c
+++ b/drivers/net/phy/mediatek-ge-soc.c
@@ -342,7 +342,8 @@ static int cal_cycle(struct phy_device *
ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
MTK_PHY_RG_AD_CAL_CLK, reg_val,
reg_val & MTK_PHY_DA_CAL_CLK, 500,
- ANALOG_INTERNAL_OPERATION_MAX_US, false);
+ ANALOG_INTERNAL_OPERATION_MAX_US,
+ false);
if (ret) {
phydev_err(phydev, "Calibration cycle timeout\n");
return ret;
@@ -441,40 +442,72 @@ static int tx_amp_fill_result(struct phy
}
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
- MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
+ MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
+ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
+ buf[0] + bias[0]));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
- MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]);
+ MTK_PHY_DA_TX_I2MPB_A_TBT_MASK,
+ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TBT_MASK,
+ buf[0] + bias[1]));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
- MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10);
+ MTK_PHY_DA_TX_I2MPB_A_HBT_MASK,
+ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_HBT_MASK,
+ buf[0] + bias[2]));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
- MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]);
+ MTK_PHY_DA_TX_I2MPB_A_TST_MASK,
+ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TST_MASK,
+ buf[0] + bias[3]));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
- MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8);
+ MTK_PHY_DA_TX_I2MPB_B_GBE_MASK,
+ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_GBE_MASK,
+ buf[1] + bias[4]));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
- MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]);
+ MTK_PHY_DA_TX_I2MPB_B_TBT_MASK,
+ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TBT_MASK,
+ buf[1] + bias[5]));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
- MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);
+ MTK_PHY_DA_TX_I2MPB_B_HBT_MASK,
+ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_HBT_MASK,
+ buf[1] + bias[6]));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
- MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]);
+ MTK_PHY_DA_TX_I2MPB_B_TST_MASK,
+ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TST_MASK,
+ buf[1] + bias[7]));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
- MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8);
+ MTK_PHY_DA_TX_I2MPB_C_GBE_MASK,
+ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_GBE_MASK,
+ buf[2] + bias[8]));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
- MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]);
+ MTK_PHY_DA_TX_I2MPB_C_TBT_MASK,
+ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TBT_MASK,
+ buf[2] + bias[9]));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
- MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8);
+ MTK_PHY_DA_TX_I2MPB_C_HBT_MASK,
+ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_HBT_MASK,
+ buf[2] + bias[10]));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
- MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]);
+ MTK_PHY_DA_TX_I2MPB_C_TST_MASK,
+ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TST_MASK,
+ buf[2] + bias[11]));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
- MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8);
+ MTK_PHY_DA_TX_I2MPB_D_GBE_MASK,
+ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_GBE_MASK,
+ buf[3] + bias[12]));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
- MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]);
+ MTK_PHY_DA_TX_I2MPB_D_TBT_MASK,
+ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TBT_MASK,
+ buf[3] + bias[13]));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
- MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8);
+ MTK_PHY_DA_TX_I2MPB_D_HBT_MASK,
+ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_HBT_MASK,
+ buf[3] + bias[14]));
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
- MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]);
+ MTK_PHY_DA_TX_I2MPB_D_TST_MASK,
+ FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TST_MASK,
+ buf[3] + bias[15]));
return 0;
}
@@ -663,7 +696,8 @@ static int tx_vcm_cal_sw(struct phy_devi
goto restore;
/* We calibrate TX-VCM in different logic. Check upper index and then
- * lower index. If this calibration is valid, apply lower index's result.
+ * lower index. If this calibration is valid, apply lower index's
+ * result.
*/
ret = upper_ret - lower_ret;
if (ret == 1) {
@@ -692,7 +726,8 @@ static int tx_vcm_cal_sw(struct phy_devi
} else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
lower_ret == 0) {
ret = 0;
- phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n",
+ phydev_warn(phydev,
+ "TX-VCM SW cal result at high margin 0x%x\n",
upper_idx);
} else {
ret = -EINVAL;
@@ -796,7 +831,8 @@ static void mt7981_phy_finetune(struct p
/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
- MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
+ MTK_PHY_TR_OPEN_LOOP_EN_MASK |
+ MTK_PHY_LPF_X_AVERAGE_MASK,
BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
/* rg_tr_lpf_cnt_val = 512 */
@@ -865,7 +901,8 @@ static void mt7988_phy_finetune(struct p
/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
- MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
+ MTK_PHY_TR_OPEN_LOOP_EN_MASK |
+ MTK_PHY_LPF_X_AVERAGE_MASK,
BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
/* rg_tr_lpf_cnt_val = 1023 */
@@ -977,7 +1014,8 @@ static void mt798x_phy_eee(struct phy_de
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
- __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
+ __phy_modify(phydev, MTK_PHY_LPI_REG_14,
+ MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
__phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
@@ -987,7 +1025,8 @@ static void mt798x_phy_eee(struct phy_de
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
- FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
+ 0xff));
}
static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
@@ -1147,7 +1186,8 @@ static int mt798x_phy_hw_led_on_set(stru
(index ? 16 : 0), &priv->led_state);
if (changed)
return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
- MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
+ MTK_PHY_LED1_ON_CTRL :
+ MTK_PHY_LED0_ON_CTRL,
MTK_PHY_LED_ON_MASK,
on ? MTK_PHY_LED_ON_FORCE_ON : 0);
else
@@ -1157,7 +1197,8 @@ static int mt798x_phy_hw_led_on_set(stru
static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
bool blinking)
{
- unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0);
+ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
+ (index ? 16 : 0);
struct mtk_socphy_priv *priv = phydev->priv;
bool changed;
@@ -1170,8 +1211,10 @@ static int mt798x_phy_hw_led_blink_set(s
(index ? 16 : 0), &priv->led_state);
if (changed)
return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
- MTK_PHY_LED1_BLINK_CTRL : MTK_PHY_LED0_BLINK_CTRL,
- blinking ? MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
+ MTK_PHY_LED1_BLINK_CTRL :
+ MTK_PHY_LED0_BLINK_CTRL,
+ blinking ?
+ MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
else
return 0;
}
@@ -1237,7 +1280,8 @@ static int mt798x_phy_led_hw_is_supporte
static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
unsigned long *rules)
{
- unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0);
+ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
+ (index ? 16 : 0);
unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
struct mtk_socphy_priv *priv = phydev->priv;
@@ -1258,8 +1302,8 @@ static int mt798x_phy_led_hw_control_get
if (blink < 0)
return -EIO;
- if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX |
- MTK_PHY_LED_ON_LINKDOWN)) ||
+ if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX |
+ MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) ||
(blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX)))
set_bit(bit_netdev, &priv->led_state);
else
@@ -1333,17 +1377,23 @@ static int mt798x_phy_led_hw_control_set
if (rules & BIT(TRIGGER_NETDEV_RX)) {
blink |= (on & MTK_PHY_LED_ON_LINK) ?
- (((on & MTK_PHY_LED_ON_LINK10) ? MTK_PHY_LED_BLINK_10RX : 0) |
- ((on & MTK_PHY_LED_ON_LINK100) ? MTK_PHY_LED_BLINK_100RX : 0) |
- ((on & MTK_PHY_LED_ON_LINK1000) ? MTK_PHY_LED_BLINK_1000RX : 0)) :
+ (((on & MTK_PHY_LED_ON_LINK10) ?
+ MTK_PHY_LED_BLINK_10RX : 0) |
+ ((on & MTK_PHY_LED_ON_LINK100) ?
+ MTK_PHY_LED_BLINK_100RX : 0) |
+ ((on & MTK_PHY_LED_ON_LINK1000) ?
+ MTK_PHY_LED_BLINK_1000RX : 0)) :
MTK_PHY_LED_BLINK_RX;
}
if (rules & BIT(TRIGGER_NETDEV_TX)) {
blink |= (on & MTK_PHY_LED_ON_LINK) ?
- (((on & MTK_PHY_LED_ON_LINK10) ? MTK_PHY_LED_BLINK_10TX : 0) |
- ((on & MTK_PHY_LED_ON_LINK100) ? MTK_PHY_LED_BLINK_100TX : 0) |
- ((on & MTK_PHY_LED_ON_LINK1000) ? MTK_PHY_LED_BLINK_1000TX : 0)) :
+ (((on & MTK_PHY_LED_ON_LINK10) ?
+ MTK_PHY_LED_BLINK_10TX : 0) |
+ ((on & MTK_PHY_LED_ON_LINK100) ?
+ MTK_PHY_LED_BLINK_100TX : 0) |
+ ((on & MTK_PHY_LED_ON_LINK1000) ?
+ MTK_PHY_LED_BLINK_1000TX : 0)) :
MTK_PHY_LED_BLINK_TX;
}
@@ -1400,7 +1450,8 @@ static int mt7988_phy_fix_leds_polaritie
/* Only now setup pinctrl to avoid bogus blinking */
pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
if (IS_ERR(pinctrl))
- dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED pinctrl\n");
+ dev_err(&phydev->mdio.bus->dev,
+ "Failed to setup PHY LED pinctrl\n");
return 0;
}

40
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@@ -0,0 +1,40 @@
From bcbbfb4f62c4ba35783cc617997a2e92d91e3940 Mon Sep 17 00:00:00 2001
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
Date: Thu, 17 Oct 2024 11:22:13 +0800
Subject: [PATCH 03/20] net: phy: mediatek-ge-soc: Propagate error code
correctly in cal_cycle()
This patch propagates error code correctly in cal_cycle()
and improve with FIELD_GET().
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/net/phy/mediatek-ge-soc.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
--- a/drivers/net/phy/mediatek-ge-soc.c
+++ b/drivers/net/phy/mediatek-ge-soc.c
@@ -110,7 +110,7 @@
#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
#define MTK_PHY_RG_AD_CAL_COMP 0x17a
-#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8)
+#define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8)
#define MTK_PHY_RG_AD_CAL_CLK 0x17b
#define MTK_PHY_DA_CAL_CLK BIT(0)
@@ -351,8 +351,10 @@ static int cal_cycle(struct phy_device *
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
MTK_PHY_DA_CALIN_FLAG);
- ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
- MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP);
+ if (ret < 0)
+ return ret;
+ ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret);
phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
return ret;

3565
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File diff suppressed because it is too large Load Diff

774
lede/target/linux/generic/backport-6.12/724-v6.13-net-phy-mediatek-Move-LED-helper-functions-into-mtk-.patch Normal file
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@@ -0,0 +1,774 @@
From 71d88c7409b91c853d7f9c933f5e27933d656e5e Mon Sep 17 00:00:00 2001
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
Date: Sat, 9 Nov 2024 00:34:52 +0800
Subject: [PATCH 05/20] net: phy: mediatek: Move LED helper functions into mtk
phy lib
This patch creates mtk-phy-lib.c & mtk-phy.h and integrates mtk-ge-soc.c's
LED helper functions so that we can use those helper functions in other
MTK's ethernet phy driver.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
MAINTAINERS | 2 +
drivers/net/phy/mediatek/Kconfig | 4 +
drivers/net/phy/mediatek/Makefile | 1 +
drivers/net/phy/mediatek/mtk-ge-soc.c | 280 +++----------------------
drivers/net/phy/mediatek/mtk-phy-lib.c | 254 ++++++++++++++++++++++
drivers/net/phy/mediatek/mtk.h | 86 ++++++++
6 files changed, 372 insertions(+), 255 deletions(-)
create mode 100644 drivers/net/phy/mediatek/mtk-phy-lib.c
create mode 100644 drivers/net/phy/mediatek/mtk.h
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14428,7 +14428,9 @@ M: SkyLake Huang <SkyLake.Huang@mediatek
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/phy/mediatek/mtk-ge-soc.c
+F: drivers/net/phy/mediatek/mtk-phy-lib.c
F: drivers/net/phy/mediatek/mtk-ge.c
+F: drivers/net/phy/mediatek/mtk.h
F: drivers/phy/mediatek/phy-mtk-xfi-tphy.c
MEDIATEK I2C CONTROLLER DRIVER
--- a/drivers/net/phy/mediatek/Kconfig
+++ b/drivers/net/phy/mediatek/Kconfig
@@ -1,4 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
+config MTK_NET_PHYLIB
+ tristate
+
config MEDIATEK_GE_PHY
tristate "MediaTek Gigabit Ethernet PHYs"
help
@@ -13,6 +16,7 @@ config MEDIATEK_GE_SOC_PHY
tristate "MediaTek SoC Ethernet PHYs"
depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
depends on NVMEM_MTK_EFUSE
+ select MTK_NET_PHYLIB
help
Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
--- a/drivers/net/phy/mediatek/Makefile
+++ b/drivers/net/phy/mediatek/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_MTK_NET_PHYLIB) += mtk-phy-lib.o
obj-$(CONFIG_MEDIATEK_GE_PHY) += mtk-ge.o
obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mtk-ge-soc.o
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -8,6 +8,8 @@
#include <linux/phy.h>
#include <linux/regmap.h>
+#include "mtk.h"
+
#define MTK_GPHY_ID_MT7981 0x03a29461
#define MTK_GPHY_ID_MT7988 0x03a29481
@@ -210,41 +212,6 @@
#define MTK_PHY_DA_TX_R50_PAIR_D 0x540
/* Registers on MDIO_MMD_VEND2 */
-#define MTK_PHY_LED0_ON_CTRL 0x24
-#define MTK_PHY_LED1_ON_CTRL 0x26
-#define MTK_PHY_LED_ON_MASK GENMASK(6, 0)
-#define MTK_PHY_LED_ON_LINK1000 BIT(0)
-#define MTK_PHY_LED_ON_LINK100 BIT(1)
-#define MTK_PHY_LED_ON_LINK10 BIT(2)
-#define MTK_PHY_LED_ON_LINK (MTK_PHY_LED_ON_LINK10 |\
- MTK_PHY_LED_ON_LINK100 |\
- MTK_PHY_LED_ON_LINK1000)
-#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
-#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
-#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
-#define MTK_PHY_LED_ON_FORCE_ON BIT(6)
-#define MTK_PHY_LED_ON_POLARITY BIT(14)
-#define MTK_PHY_LED_ON_ENABLE BIT(15)
-
-#define MTK_PHY_LED0_BLINK_CTRL 0x25
-#define MTK_PHY_LED1_BLINK_CTRL 0x27
-#define MTK_PHY_LED_BLINK_1000TX BIT(0)
-#define MTK_PHY_LED_BLINK_1000RX BIT(1)
-#define MTK_PHY_LED_BLINK_100TX BIT(2)
-#define MTK_PHY_LED_BLINK_100RX BIT(3)
-#define MTK_PHY_LED_BLINK_10TX BIT(4)
-#define MTK_PHY_LED_BLINK_10RX BIT(5)
-#define MTK_PHY_LED_BLINK_RX (MTK_PHY_LED_BLINK_10RX |\
- MTK_PHY_LED_BLINK_100RX |\
- MTK_PHY_LED_BLINK_1000RX)
-#define MTK_PHY_LED_BLINK_TX (MTK_PHY_LED_BLINK_10TX |\
- MTK_PHY_LED_BLINK_100TX |\
- MTK_PHY_LED_BLINK_1000TX)
-#define MTK_PHY_LED_BLINK_COLLISION BIT(6)
-#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
-#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
-#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9)
-
#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1)
#define MTK_PHY_RG_BG_RASEL 0x115
@@ -299,14 +266,6 @@ enum CAL_MODE {
SW_M
};
-#define MTK_PHY_LED_STATE_FORCE_ON 0
-#define MTK_PHY_LED_STATE_FORCE_BLINK 1
-#define MTK_PHY_LED_STATE_NETDEV 2
-
-struct mtk_socphy_priv {
- unsigned long led_state;
-};
-
struct mtk_socphy_shared {
u32 boottrap;
struct mtk_socphy_priv priv[4];
@@ -1172,76 +1131,23 @@ static int mt798x_phy_config_init(struct
return mt798x_phy_calibration(phydev);
}
-static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
- bool on)
-{
- unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
- struct mtk_socphy_priv *priv = phydev->priv;
- bool changed;
-
- if (on)
- changed = !test_and_set_bit(bit_on, &priv->led_state);
- else
- changed = !!test_and_clear_bit(bit_on, &priv->led_state);
-
- changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
- (index ? 16 : 0), &priv->led_state);
- if (changed)
- return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
- MTK_PHY_LED1_ON_CTRL :
- MTK_PHY_LED0_ON_CTRL,
- MTK_PHY_LED_ON_MASK,
- on ? MTK_PHY_LED_ON_FORCE_ON : 0);
- else
- return 0;
-}
-
-static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
- bool blinking)
-{
- unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
- (index ? 16 : 0);
- struct mtk_socphy_priv *priv = phydev->priv;
- bool changed;
-
- if (blinking)
- changed = !test_and_set_bit(bit_blink, &priv->led_state);
- else
- changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
-
- changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
- (index ? 16 : 0), &priv->led_state);
- if (changed)
- return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
- MTK_PHY_LED1_BLINK_CTRL :
- MTK_PHY_LED0_BLINK_CTRL,
- blinking ?
- MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
- else
- return 0;
-}
-
static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
unsigned long *delay_on,
unsigned long *delay_off)
{
bool blinking = false;
- int err = 0;
-
- if (index > 1)
- return -EINVAL;
+ int err;
- if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
- blinking = true;
- *delay_on = 50;
- *delay_off = 50;
- }
+ err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking);
+ if (err < 0)
+ return err;
- err = mt798x_phy_hw_led_blink_set(phydev, index, blinking);
+ err = mtk_phy_hw_led_blink_set(phydev, index, blinking);
if (err)
return err;
- return mt798x_phy_hw_led_on_set(phydev, index, false);
+ return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK,
+ false);
}
static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
@@ -1249,11 +1155,12 @@ static int mt798x_phy_led_brightness_set
{
int err;
- err = mt798x_phy_hw_led_blink_set(phydev, index, false);
+ err = mtk_phy_hw_led_blink_set(phydev, index, false);
if (err)
return err;
- return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
+ return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK,
+ (value != LED_OFF));
}
static const unsigned long supported_triggers =
@@ -1269,155 +1176,26 @@ static const unsigned long supported_tri
static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
unsigned long rules)
{
- if (index > 1)
- return -EINVAL;
-
- /* All combinations of the supported triggers are allowed */
- if (rules & ~supported_triggers)
- return -EOPNOTSUPP;
-
- return 0;
-};
+ return mtk_phy_led_hw_is_supported(phydev, index, rules,
+ supported_triggers);
+}
static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
unsigned long *rules)
{
- unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
- (index ? 16 : 0);
- unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
- unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
- struct mtk_socphy_priv *priv = phydev->priv;
- int on, blink;
-
- if (index > 1)
- return -EINVAL;
-
- on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
- index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
-
- if (on < 0)
- return -EIO;
-
- blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
- index ? MTK_PHY_LED1_BLINK_CTRL :
- MTK_PHY_LED0_BLINK_CTRL);
- if (blink < 0)
- return -EIO;
-
- if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX |
- MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) ||
- (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX)))
- set_bit(bit_netdev, &priv->led_state);
- else
- clear_bit(bit_netdev, &priv->led_state);
-
- if (on & MTK_PHY_LED_ON_FORCE_ON)
- set_bit(bit_on, &priv->led_state);
- else
- clear_bit(bit_on, &priv->led_state);
-
- if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
- set_bit(bit_blink, &priv->led_state);
- else
- clear_bit(bit_blink, &priv->led_state);
-
- if (!rules)
- return 0;
-
- if (on & MTK_PHY_LED_ON_LINK)
- *rules |= BIT(TRIGGER_NETDEV_LINK);
-
- if (on & MTK_PHY_LED_ON_LINK10)
- *rules |= BIT(TRIGGER_NETDEV_LINK_10);
-
- if (on & MTK_PHY_LED_ON_LINK100)
- *rules |= BIT(TRIGGER_NETDEV_LINK_100);
-
- if (on & MTK_PHY_LED_ON_LINK1000)
- *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
-
- if (on & MTK_PHY_LED_ON_FDX)
- *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
-
- if (on & MTK_PHY_LED_ON_HDX)
- *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
-
- if (blink & MTK_PHY_LED_BLINK_RX)
- *rules |= BIT(TRIGGER_NETDEV_RX);
-
- if (blink & MTK_PHY_LED_BLINK_TX)
- *rules |= BIT(TRIGGER_NETDEV_TX);
-
- return 0;
+ return mtk_phy_led_hw_ctrl_get(phydev, index, rules,
+ MTK_GPHY_LED_ON_SET,
+ MTK_GPHY_LED_RX_BLINK_SET,
+ MTK_GPHY_LED_TX_BLINK_SET);
};
static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
unsigned long rules)
{
- unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
- struct mtk_socphy_priv *priv = phydev->priv;
- u16 on = 0, blink = 0;
- int ret;
-
- if (index > 1)
- return -EINVAL;
-
- if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
- on |= MTK_PHY_LED_ON_FDX;
-
- if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
- on |= MTK_PHY_LED_ON_HDX;
-
- if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
- on |= MTK_PHY_LED_ON_LINK10;
-
- if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
- on |= MTK_PHY_LED_ON_LINK100;
-
- if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
- on |= MTK_PHY_LED_ON_LINK1000;
-
- if (rules & BIT(TRIGGER_NETDEV_RX)) {
- blink |= (on & MTK_PHY_LED_ON_LINK) ?
- (((on & MTK_PHY_LED_ON_LINK10) ?
- MTK_PHY_LED_BLINK_10RX : 0) |
- ((on & MTK_PHY_LED_ON_LINK100) ?
- MTK_PHY_LED_BLINK_100RX : 0) |
- ((on & MTK_PHY_LED_ON_LINK1000) ?
- MTK_PHY_LED_BLINK_1000RX : 0)) :
- MTK_PHY_LED_BLINK_RX;
- }
-
- if (rules & BIT(TRIGGER_NETDEV_TX)) {
- blink |= (on & MTK_PHY_LED_ON_LINK) ?
- (((on & MTK_PHY_LED_ON_LINK10) ?
- MTK_PHY_LED_BLINK_10TX : 0) |
- ((on & MTK_PHY_LED_ON_LINK100) ?
- MTK_PHY_LED_BLINK_100TX : 0) |
- ((on & MTK_PHY_LED_ON_LINK1000) ?
- MTK_PHY_LED_BLINK_1000TX : 0)) :
- MTK_PHY_LED_BLINK_TX;
- }
-
- if (blink || on)
- set_bit(bit_netdev, &priv->led_state);
- else
- clear_bit(bit_netdev, &priv->led_state);
-
- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
- MTK_PHY_LED1_ON_CTRL :
- MTK_PHY_LED0_ON_CTRL,
- MTK_PHY_LED_ON_FDX |
- MTK_PHY_LED_ON_HDX |
- MTK_PHY_LED_ON_LINK,
- on);
-
- if (ret)
- return ret;
-
- return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
- MTK_PHY_LED1_BLINK_CTRL :
- MTK_PHY_LED0_BLINK_CTRL, blink);
+ return mtk_phy_led_hw_ctrl_set(phydev, index, rules,
+ MTK_GPHY_LED_ON_SET,
+ MTK_GPHY_LED_RX_BLINK_SET,
+ MTK_GPHY_LED_TX_BLINK_SET);
};
static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num)
@@ -1492,14 +1270,6 @@ static int mt7988_phy_probe_shared(struc
return 0;
}
-static void mt798x_phy_leds_state_init(struct phy_device *phydev)
-{
- int i;
-
- for (i = 0; i < 2; ++i)
- mt798x_phy_led_hw_control_get(phydev, i, NULL);
-}
-
static int mt7988_phy_probe(struct phy_device *phydev)
{
struct mtk_socphy_shared *shared;
@@ -1525,7 +1295,7 @@ static int mt7988_phy_probe(struct phy_d
phydev->priv = priv;
- mt798x_phy_leds_state_init(phydev);
+ mtk_phy_leds_state_init(phydev);
err = mt7988_phy_fix_leds_polarities(phydev);
if (err)
@@ -1552,7 +1322,7 @@ static int mt7981_phy_probe(struct phy_d
phydev->priv = priv;
- mt798x_phy_leds_state_init(phydev);
+ mtk_phy_leds_state_init(phydev);
return mt798x_phy_calibration(phydev);
}
--- /dev/null
+++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/phy.h>
+#include <linux/module.h>
+
+#include <linux/netdevice.h>
+
+#include "mtk.h"
+
+int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
+ unsigned long rules,
+ unsigned long supported_triggers)
+{
+ if (index > 1)
+ return -EINVAL;
+
+ /* All combinations of the supported triggers are allowed */
+ if (rules & ~supported_triggers)
+ return -EOPNOTSUPP;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtk_phy_led_hw_is_supported);
+
+int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index,
+ unsigned long *rules, u16 on_set,
+ u16 rx_blink_set, u16 tx_blink_set)
+{
+ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
+ (index ? 16 : 0);
+ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
+ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
+ struct mtk_socphy_priv *priv = phydev->priv;
+ int on, blink;
+
+ if (index > 1)
+ return -EINVAL;
+
+ on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
+ index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
+
+ if (on < 0)
+ return -EIO;
+
+ blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
+ index ? MTK_PHY_LED1_BLINK_CTRL :
+ MTK_PHY_LED0_BLINK_CTRL);
+ if (blink < 0)
+ return -EIO;
+
+ if ((on & (on_set | MTK_PHY_LED_ON_FDX |
+ MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) ||
+ (blink & (rx_blink_set | tx_blink_set)))
+ set_bit(bit_netdev, &priv->led_state);
+ else
+ clear_bit(bit_netdev, &priv->led_state);
+
+ if (on & MTK_PHY_LED_ON_FORCE_ON)
+ set_bit(bit_on, &priv->led_state);
+ else
+ clear_bit(bit_on, &priv->led_state);
+
+ if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
+ set_bit(bit_blink, &priv->led_state);
+ else
+ clear_bit(bit_blink, &priv->led_state);
+
+ if (!rules)
+ return 0;
+
+ if (on & on_set)
+ *rules |= BIT(TRIGGER_NETDEV_LINK);
+
+ if (on & MTK_PHY_LED_ON_LINK10)
+ *rules |= BIT(TRIGGER_NETDEV_LINK_10);
+
+ if (on & MTK_PHY_LED_ON_LINK100)
+ *rules |= BIT(TRIGGER_NETDEV_LINK_100);
+
+ if (on & MTK_PHY_LED_ON_LINK1000)
+ *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
+
+ if (on & MTK_PHY_LED_ON_LINK2500)
+ *rules |= BIT(TRIGGER_NETDEV_LINK_2500);
+
+ if (on & MTK_PHY_LED_ON_FDX)
+ *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
+
+ if (on & MTK_PHY_LED_ON_HDX)
+ *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
+
+ if (blink & rx_blink_set)
+ *rules |= BIT(TRIGGER_NETDEV_RX);
+
+ if (blink & tx_blink_set)
+ *rules |= BIT(TRIGGER_NETDEV_TX);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_get);
+
+int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index,
+ unsigned long rules, u16 on_set,
+ u16 rx_blink_set, u16 tx_blink_set)
+{
+ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
+ struct mtk_socphy_priv *priv = phydev->priv;
+ u16 on = 0, blink = 0;
+ int ret;
+
+ if (index > 1)
+ return -EINVAL;
+
+ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
+ on |= MTK_PHY_LED_ON_FDX;
+
+ if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
+ on |= MTK_PHY_LED_ON_HDX;
+
+ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
+ on |= MTK_PHY_LED_ON_LINK10;
+
+ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
+ on |= MTK_PHY_LED_ON_LINK100;
+
+ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
+ on |= MTK_PHY_LED_ON_LINK1000;
+
+ if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK)))
+ on |= MTK_PHY_LED_ON_LINK2500;
+
+ if (rules & BIT(TRIGGER_NETDEV_RX)) {
+ blink |= (on & on_set) ?
+ (((on & MTK_PHY_LED_ON_LINK10) ?
+ MTK_PHY_LED_BLINK_10RX : 0) |
+ ((on & MTK_PHY_LED_ON_LINK100) ?
+ MTK_PHY_LED_BLINK_100RX : 0) |
+ ((on & MTK_PHY_LED_ON_LINK1000) ?
+ MTK_PHY_LED_BLINK_1000RX : 0) |
+ ((on & MTK_PHY_LED_ON_LINK2500) ?
+ MTK_PHY_LED_BLINK_2500RX : 0)) :
+ rx_blink_set;
+ }
+
+ if (rules & BIT(TRIGGER_NETDEV_TX)) {
+ blink |= (on & on_set) ?
+ (((on & MTK_PHY_LED_ON_LINK10) ?
+ MTK_PHY_LED_BLINK_10TX : 0) |
+ ((on & MTK_PHY_LED_ON_LINK100) ?
+ MTK_PHY_LED_BLINK_100TX : 0) |
+ ((on & MTK_PHY_LED_ON_LINK1000) ?
+ MTK_PHY_LED_BLINK_1000TX : 0) |
+ ((on & MTK_PHY_LED_ON_LINK2500) ?
+ MTK_PHY_LED_BLINK_2500TX : 0)) :
+ tx_blink_set;
+ }
+
+ if (blink || on)
+ set_bit(bit_netdev, &priv->led_state);
+ else
+ clear_bit(bit_netdev, &priv->led_state);
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
+ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
+ MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX | on_set,
+ on);
+
+ if (ret)
+ return ret;
+
+ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
+ MTK_PHY_LED1_BLINK_CTRL :
+ MTK_PHY_LED0_BLINK_CTRL, blink);
+}
+EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_set);
+
+int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on,
+ unsigned long *delay_off, bool *blinking)
+{
+ if (index > 1)
+ return -EINVAL;
+
+ if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
+ *blinking = true;
+ *delay_on = 50;
+ *delay_off = 50;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtk_phy_led_num_dly_cfg);
+
+int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
+ u16 led_on_mask, bool on)
+{
+ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
+ struct mtk_socphy_priv *priv = phydev->priv;
+ bool changed;
+
+ if (on)
+ changed = !test_and_set_bit(bit_on, &priv->led_state);
+ else
+ changed = !!test_and_clear_bit(bit_on, &priv->led_state);
+
+ changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
+ (index ? 16 : 0), &priv->led_state);
+ if (changed)
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
+ MTK_PHY_LED1_ON_CTRL :
+ MTK_PHY_LED0_ON_CTRL,
+ led_on_mask,
+ on ? MTK_PHY_LED_ON_FORCE_ON : 0);
+ else
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtk_phy_hw_led_on_set);
+
+int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, bool blinking)
+{
+ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
+ (index ? 16 : 0);
+ struct mtk_socphy_priv *priv = phydev->priv;
+ bool changed;
+
+ if (blinking)
+ changed = !test_and_set_bit(bit_blink, &priv->led_state);
+ else
+ changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
+
+ changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
+ (index ? 16 : 0), &priv->led_state);
+ if (changed)
+ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
+ MTK_PHY_LED1_BLINK_CTRL :
+ MTK_PHY_LED0_BLINK_CTRL,
+ blinking ?
+ MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
+ else
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtk_phy_hw_led_blink_set);
+
+void mtk_phy_leds_state_init(struct phy_device *phydev)
+{
+ int i;
+
+ for (i = 0; i < 2; ++i)
+ phydev->drv->led_hw_control_get(phydev, i, NULL);
+}
+EXPORT_SYMBOL_GPL(mtk_phy_leds_state_init);
+
+MODULE_DESCRIPTION("MediaTek Ethernet PHY driver common");
+MODULE_AUTHOR("Sky Huang <SkyLake.Huang@mediatek.com>");
+MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
+MODULE_LICENSE("GPL");
--- /dev/null
+++ b/drivers/net/phy/mediatek/mtk.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Common definition for Mediatek Ethernet PHYs
+ * Author: SkyLake Huang <SkyLake.Huang@mediatek.com>
+ * Copyright (c) 2024 MediaTek Inc.
+ */
+
+#ifndef _MTK_EPHY_H_
+#define _MTK_EPHY_H_
+
+#define MTK_EXT_PAGE_ACCESS 0x1f
+
+/* Registers on MDIO_MMD_VEND2 */
+#define MTK_PHY_LED0_ON_CTRL 0x24
+#define MTK_PHY_LED1_ON_CTRL 0x26
+#define MTK_GPHY_LED_ON_MASK GENMASK(6, 0)
+#define MTK_2P5GPHY_LED_ON_MASK GENMASK(7, 0)
+#define MTK_PHY_LED_ON_LINK1000 BIT(0)
+#define MTK_PHY_LED_ON_LINK100 BIT(1)
+#define MTK_PHY_LED_ON_LINK10 BIT(2)
+#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
+#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
+#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
+#define MTK_PHY_LED_ON_FORCE_ON BIT(6)
+#define MTK_PHY_LED_ON_LINK2500 BIT(7)
+#define MTK_PHY_LED_ON_POLARITY BIT(14)
+#define MTK_PHY_LED_ON_ENABLE BIT(15)
+
+#define MTK_PHY_LED0_BLINK_CTRL 0x25
+#define MTK_PHY_LED1_BLINK_CTRL 0x27
+#define MTK_PHY_LED_BLINK_1000TX BIT(0)
+#define MTK_PHY_LED_BLINK_1000RX BIT(1)
+#define MTK_PHY_LED_BLINK_100TX BIT(2)
+#define MTK_PHY_LED_BLINK_100RX BIT(3)
+#define MTK_PHY_LED_BLINK_10TX BIT(4)
+#define MTK_PHY_LED_BLINK_10RX BIT(5)
+#define MTK_PHY_LED_BLINK_COLLISION BIT(6)
+#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
+#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
+#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9)
+#define MTK_PHY_LED_BLINK_2500TX BIT(10)
+#define MTK_PHY_LED_BLINK_2500RX BIT(11)
+
+#define MTK_GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK1000 | \
+ MTK_PHY_LED_ON_LINK100 | \
+ MTK_PHY_LED_ON_LINK10)
+#define MTK_GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \
+ MTK_PHY_LED_BLINK_100RX | \
+ MTK_PHY_LED_BLINK_10RX)
+#define MTK_GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \
+ MTK_PHY_LED_BLINK_100RX | \
+ MTK_PHY_LED_BLINK_10RX)
+
+#define MTK_2P5GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK2500 | \
+ MTK_GPHY_LED_ON_SET)
+#define MTK_2P5GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \
+ MTK_GPHY_LED_RX_BLINK_SET)
+#define MTK_2P5GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \
+ MTK_GPHY_LED_TX_BLINK_SET)
+
+#define MTK_PHY_LED_STATE_FORCE_ON 0
+#define MTK_PHY_LED_STATE_FORCE_BLINK 1
+#define MTK_PHY_LED_STATE_NETDEV 2
+
+struct mtk_socphy_priv {
+ unsigned long led_state;
+};
+
+int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
+ unsigned long rules,
+ unsigned long supported_triggers);
+int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index,
+ unsigned long rules, u16 on_set,
+ u16 rx_blink_set, u16 tx_blink_set);
+int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index,
+ unsigned long *rules, u16 on_set,
+ u16 rx_blink_set, u16 tx_blink_set);
+int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on,
+ unsigned long *delay_off, bool *blinking);
+int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
+ u16 led_on_mask, bool on);
+int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
+ bool blinking);
+void mtk_phy_leds_state_init(struct phy_device *phydev);
+
+#endif /* _MTK_EPHY_H_ */

72
lede/target/linux/generic/backport-6.12/725-v6.13-net-phy-mediatek-Improve-readability-of-mtk-phy-lib..patch Normal file
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@@ -0,0 +1,72 @@
From 3efd0595fc7aaae300f5d9f4f0ae86f432c8d2c7 Mon Sep 17 00:00:00 2001
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
Date: Sat, 9 Nov 2024 00:34:53 +0800
Subject: [PATCH 06/20] net: phy: mediatek: Improve readability of
mtk-phy-lib.c's mtk_phy_led_hw_ctrl_set()
This patch removes parens around TRIGGER_NETDEV_RX/TRIGGER_NETDEV_TX in
mtk_phy_led_hw_ctrl_set(), which improves readability.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/mediatek/mtk-phy-lib.c | 44 ++++++++++++++------------
1 file changed, 24 insertions(+), 20 deletions(-)
--- a/drivers/net/phy/mediatek/mtk-phy-lib.c
+++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
@@ -129,29 +129,33 @@ int mtk_phy_led_hw_ctrl_set(struct phy_d
on |= MTK_PHY_LED_ON_LINK2500;
if (rules & BIT(TRIGGER_NETDEV_RX)) {
- blink |= (on & on_set) ?
- (((on & MTK_PHY_LED_ON_LINK10) ?
- MTK_PHY_LED_BLINK_10RX : 0) |
- ((on & MTK_PHY_LED_ON_LINK100) ?
- MTK_PHY_LED_BLINK_100RX : 0) |
- ((on & MTK_PHY_LED_ON_LINK1000) ?
- MTK_PHY_LED_BLINK_1000RX : 0) |
- ((on & MTK_PHY_LED_ON_LINK2500) ?
- MTK_PHY_LED_BLINK_2500RX : 0)) :
- rx_blink_set;
+ if (on & on_set) {
+ if (on & MTK_PHY_LED_ON_LINK10)
+ blink |= MTK_PHY_LED_BLINK_10RX;
+ if (on & MTK_PHY_LED_ON_LINK100)
+ blink |= MTK_PHY_LED_BLINK_100RX;
+ if (on & MTK_PHY_LED_ON_LINK1000)
+ blink |= MTK_PHY_LED_BLINK_1000RX;
+ if (on & MTK_PHY_LED_ON_LINK2500)
+ blink |= MTK_PHY_LED_BLINK_2500RX;
+ } else {
+ blink |= rx_blink_set;
+ }
}
if (rules & BIT(TRIGGER_NETDEV_TX)) {
- blink |= (on & on_set) ?
- (((on & MTK_PHY_LED_ON_LINK10) ?
- MTK_PHY_LED_BLINK_10TX : 0) |
- ((on & MTK_PHY_LED_ON_LINK100) ?
- MTK_PHY_LED_BLINK_100TX : 0) |
- ((on & MTK_PHY_LED_ON_LINK1000) ?
- MTK_PHY_LED_BLINK_1000TX : 0) |
- ((on & MTK_PHY_LED_ON_LINK2500) ?
- MTK_PHY_LED_BLINK_2500TX : 0)) :
- tx_blink_set;
+ if (on & on_set) {
+ if (on & MTK_PHY_LED_ON_LINK10)
+ blink |= MTK_PHY_LED_BLINK_10TX;
+ if (on & MTK_PHY_LED_ON_LINK100)
+ blink |= MTK_PHY_LED_BLINK_100TX;
+ if (on & MTK_PHY_LED_ON_LINK1000)
+ blink |= MTK_PHY_LED_BLINK_1000TX;
+ if (on & MTK_PHY_LED_ON_LINK2500)
+ blink |= MTK_PHY_LED_BLINK_2500TX;
+ } else {
+ blink |= tx_blink_set;
+ }
}
if (blink || on)

153
lede/target/linux/generic/backport-6.12/726-v6.13-net-phy-mediatek-Integrate-read-write-page-helper-fu.patch Normal file
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@@ -0,0 +1,153 @@
From 50a97d716105a5f35aaecca0bdfe8e23cba0e87f Mon Sep 17 00:00:00 2001
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
Date: Sat, 9 Nov 2024 00:34:54 +0800
Subject: [PATCH 07/20] net: phy: mediatek: Integrate read/write page helper
functions
This patch integrates read/write page helper functions as MTK phy lib.
They are basically the same in mtk-ge.c & mtk-ge-soc.c.
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/mediatek/Kconfig | 1 +
drivers/net/phy/mediatek/mtk-ge-soc.c | 18 ++++--------------
drivers/net/phy/mediatek/mtk-ge.c | 20 ++++++--------------
drivers/net/phy/mediatek/mtk-phy-lib.c | 12 ++++++++++++
drivers/net/phy/mediatek/mtk.h | 3 +++
5 files changed, 26 insertions(+), 28 deletions(-)
--- a/drivers/net/phy/mediatek/Kconfig
+++ b/drivers/net/phy/mediatek/Kconfig
@@ -4,6 +4,7 @@ config MTK_NET_PHYLIB
config MEDIATEK_GE_PHY
tristate "MediaTek Gigabit Ethernet PHYs"
+ select MTK_NET_PHYLIB
help
Supports the MediaTek non-built-in Gigabit Ethernet PHYs.
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -271,16 +271,6 @@ struct mtk_socphy_shared {
struct mtk_socphy_priv priv[4];
};
-static int mtk_socphy_read_page(struct phy_device *phydev)
-{
- return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
-}
-
-static int mtk_socphy_write_page(struct phy_device *phydev, int page)
-{
- return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
-}
-
/* One calibration cycle consists of:
* 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
* until AD_CAL_COMP is ready to output calibration result.
@@ -1337,8 +1327,8 @@ static struct phy_driver mtk_socphy_driv
.probe = mt7981_phy_probe,
.suspend = genphy_suspend,
.resume = genphy_resume,
- .read_page = mtk_socphy_read_page,
- .write_page = mtk_socphy_write_page,
+ .read_page = mtk_phy_read_page,
+ .write_page = mtk_phy_write_page,
.led_blink_set = mt798x_phy_led_blink_set,
.led_brightness_set = mt798x_phy_led_brightness_set,
.led_hw_is_supported = mt798x_phy_led_hw_is_supported,
@@ -1354,8 +1344,8 @@ static struct phy_driver mtk_socphy_driv
.probe = mt7988_phy_probe,
.suspend = genphy_suspend,
.resume = genphy_resume,
- .read_page = mtk_socphy_read_page,
- .write_page = mtk_socphy_write_page,
+ .read_page = mtk_phy_read_page,
+ .write_page = mtk_phy_write_page,
.led_blink_set = mt798x_phy_led_blink_set,
.led_brightness_set = mt798x_phy_led_brightness_set,
.led_hw_is_supported = mt798x_phy_led_hw_is_supported,
--- a/drivers/net/phy/mediatek/mtk-ge.c
+++ b/drivers/net/phy/mediatek/mtk-ge.c
@@ -3,6 +3,8 @@
#include <linux/module.h>
#include <linux/phy.h>
+#include "mtk.h"
+
#define MTK_EXT_PAGE_ACCESS 0x1f
#define MTK_PHY_PAGE_STANDARD 0x0000
#define MTK_PHY_PAGE_EXTENDED 0x0001
@@ -11,16 +13,6 @@
#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
-static int mtk_gephy_read_page(struct phy_device *phydev)
-{
- return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
-}
-
-static int mtk_gephy_write_page(struct phy_device *phydev, int page)
-{
- return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
-}
-
static void mtk_gephy_config_init(struct phy_device *phydev)
{
/* Enable HW auto downshift */
@@ -77,8 +69,8 @@ static struct phy_driver mtk_gephy_drive
.handle_interrupt = genphy_handle_interrupt_no_ack,
.suspend = genphy_suspend,
.resume = genphy_resume,
- .read_page = mtk_gephy_read_page,
- .write_page = mtk_gephy_write_page,
+ .read_page = mtk_phy_read_page,
+ .write_page = mtk_phy_write_page,
},
{
PHY_ID_MATCH_EXACT(0x03a29441),
@@ -91,8 +83,8 @@ static struct phy_driver mtk_gephy_drive
.handle_interrupt = genphy_handle_interrupt_no_ack,
.suspend = genphy_suspend,
.resume = genphy_resume,
- .read_page = mtk_gephy_read_page,
- .write_page = mtk_gephy_write_page,
+ .read_page = mtk_phy_read_page,
+ .write_page = mtk_phy_write_page,
},
};
--- a/drivers/net/phy/mediatek/mtk-phy-lib.c
+++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
@@ -6,6 +6,18 @@
#include "mtk.h"
+int mtk_phy_read_page(struct phy_device *phydev)
+{
+ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
+}
+EXPORT_SYMBOL_GPL(mtk_phy_read_page);
+
+int mtk_phy_write_page(struct phy_device *phydev, int page)
+{
+ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
+}
+EXPORT_SYMBOL_GPL(mtk_phy_write_page);
+
int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
unsigned long rules,
unsigned long supported_triggers)
--- a/drivers/net/phy/mediatek/mtk.h
+++ b/drivers/net/phy/mediatek/mtk.h
@@ -66,6 +66,9 @@ struct mtk_socphy_priv {
unsigned long led_state;
};
+int mtk_phy_read_page(struct phy_device *phydev);
+int mtk_phy_write_page(struct phy_device *phydev, int page);
+
int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
unsigned long rules,
unsigned long supported_triggers);

56
lede/target/linux/generic/backport-6.12/727-v6.13-net-phy-mediatek-add-MT7530-MT7531-s-PHY-ID-macros.patch Normal file
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@@ -0,0 +1,56 @@
From e6579df175d5b1baa605c82f8e759542262637cf Mon Sep 17 00:00:00 2001
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
Date: Sat, 9 Nov 2024 00:34:55 +0800
Subject: [PATCH 08/20] net: phy: mediatek: add MT7530 & MT7531's PHY ID macros
This patch adds MT7530 & MT7531's PHY ID macros in mtk-ge.c so that
it follows the same rule of mtk-ge-soc.c.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/phy/mediatek/mtk-ge.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
--- a/drivers/net/phy/mediatek/mtk-ge.c
+++ b/drivers/net/phy/mediatek/mtk-ge.c
@@ -5,6 +5,9 @@
#include "mtk.h"
+#define MTK_GPHY_ID_MT7530 0x03a29412
+#define MTK_GPHY_ID_MT7531 0x03a29441
+
#define MTK_EXT_PAGE_ACCESS 0x1f
#define MTK_PHY_PAGE_STANDARD 0x0000
#define MTK_PHY_PAGE_EXTENDED 0x0001
@@ -59,7 +62,7 @@ static int mt7531_phy_config_init(struct
static struct phy_driver mtk_gephy_driver[] = {
{
- PHY_ID_MATCH_EXACT(0x03a29412),
+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530),
.name = "MediaTek MT7530 PHY",
.config_init = mt7530_phy_config_init,
/* Interrupts are handled by the switch, not the PHY
@@ -73,7 +76,7 @@ static struct phy_driver mtk_gephy_drive
.write_page = mtk_phy_write_page,
},
{
- PHY_ID_MATCH_EXACT(0x03a29441),
+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531),
.name = "MediaTek MT7531 PHY",
.config_init = mt7531_phy_config_init,
/* Interrupts are handled by the switch, not the PHY
@@ -91,8 +94,8 @@ static struct phy_driver mtk_gephy_drive
module_phy_driver(mtk_gephy_driver);
static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
- { PHY_ID_MATCH_EXACT(0x03a29441) },
- { PHY_ID_MATCH_EXACT(0x03a29412) },
+ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530) },
+ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531) },
{ }
};

700
lede/target/linux/generic/backport-6.12/728-v6.14-net-phy-Constify-struct-mdio_device_id.patch Normal file
View File

@@ -0,0 +1,700 @@
From e127f7380aaf2cd1614961d826a4af7ab297d37f Mon Sep 17 00:00:00 2001
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Date: Sun, 12 Jan 2025 15:14:50 +0100
Subject: [PATCH 09/20] net: phy: Constify struct mdio_device_id
'struct mdio_device_id' is not modified in these drivers.
Constifying these structures moves some data to a read-only section, so
increase overall security.
On a x86_64, with allmodconfig, as an example:
Before:
======
text data bss dec hex filename
27014 12792 0 39806 9b7e drivers/net/phy/broadcom.o
After:
=====
text data bss dec hex filename
27206 12600 0 39806 9b7e drivers/net/phy/broadcom.o
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/403c381b7d9156b67ad68ffc44b8eee70c5e86a9.1736691226.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/phy/adin.c | 2 +-
drivers/net/phy/adin1100.c | 2 +-
drivers/net/phy/air_en8811h.c | 2 +-
drivers/net/phy/amd.c | 2 +-
drivers/net/phy/aquantia/aquantia_main.c | 2 +-
drivers/net/phy/ax88796b.c | 2 +-
drivers/net/phy/bcm-cygnus.c | 2 +-
drivers/net/phy/bcm54140.c | 2 +-
drivers/net/phy/bcm63xx.c | 2 +-
drivers/net/phy/bcm7xxx.c | 2 +-
drivers/net/phy/bcm84881.c | 2 +-
drivers/net/phy/broadcom.c | 2 +-
drivers/net/phy/cicada.c | 2 +-
drivers/net/phy/cortina.c | 2 +-
drivers/net/phy/davicom.c | 2 +-
drivers/net/phy/dp83640.c | 2 +-
drivers/net/phy/dp83822.c | 2 +-
drivers/net/phy/dp83848.c | 2 +-
drivers/net/phy/dp83867.c | 2 +-
drivers/net/phy/dp83869.c | 2 +-
drivers/net/phy/dp83tc811.c | 2 +-
drivers/net/phy/dp83td510.c | 2 +-
drivers/net/phy/dp83tg720.c | 2 +-
drivers/net/phy/et1011c.c | 2 +-
drivers/net/phy/icplus.c | 2 +-
drivers/net/phy/intel-xway.c | 2 +-
drivers/net/phy/lxt.c | 2 +-
drivers/net/phy/marvell-88q2xxx.c | 2 +-
drivers/net/phy/marvell-88x2222.c | 2 +-
drivers/net/phy/marvell.c | 2 +-
drivers/net/phy/marvell10g.c | 2 +-
drivers/net/phy/mediatek/mtk-ge-soc.c | 2 +-
drivers/net/phy/mediatek/mtk-ge.c | 2 +-
drivers/net/phy/meson-gxl.c | 2 +-
drivers/net/phy/micrel.c | 2 +-
drivers/net/phy/microchip.c | 2 +-
drivers/net/phy/microchip_t1.c | 2 +-
drivers/net/phy/microchip_t1s.c | 2 +-
drivers/net/phy/mscc/mscc_main.c | 2 +-
drivers/net/phy/mxl-gpy.c | 2 +-
drivers/net/phy/national.c | 2 +-
drivers/net/phy/ncn26000.c | 2 +-
drivers/net/phy/nxp-c45-tja11xx.c | 2 +-
drivers/net/phy/nxp-cbtx.c | 2 +-
drivers/net/phy/nxp-tja11xx.c | 2 +-
drivers/net/phy/qcom/at803x.c | 2 +-
drivers/net/phy/qcom/qca807x.c | 2 +-
drivers/net/phy/qcom/qca808x.c | 2 +-
drivers/net/phy/qcom/qca83xx.c | 2 +-
drivers/net/phy/qsemi.c | 2 +-
drivers/net/phy/rockchip.c | 2 +-
drivers/net/phy/smsc.c | 2 +-
drivers/net/phy/ste10Xp.c | 2 +-
drivers/net/phy/teranetics.c | 2 +-
drivers/net/phy/uPD60620.c | 2 +-
drivers/net/phy/vitesse.c | 2 +-
56 files changed, 56 insertions(+), 56 deletions(-)
--- a/drivers/net/phy/adin.c
+++ b/drivers/net/phy/adin.c
@@ -1040,7 +1040,7 @@ static struct phy_driver adin_driver[] =
module_phy_driver(adin_driver);
-static struct mdio_device_id __maybe_unused adin_tbl[] = {
+static const struct mdio_device_id __maybe_unused adin_tbl[] = {
{ PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200) },
{ PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300) },
{ }
--- a/drivers/net/phy/adin1100.c
+++ b/drivers/net/phy/adin1100.c
@@ -340,7 +340,7 @@ static struct phy_driver adin_driver[] =
module_phy_driver(adin_driver);
-static struct mdio_device_id __maybe_unused adin_tbl[] = {
+static const struct mdio_device_id __maybe_unused adin_tbl[] = {
{ PHY_ID_MATCH_MODEL(PHY_ID_ADIN1100) },
{ PHY_ID_MATCH_MODEL(PHY_ID_ADIN1110) },
{ PHY_ID_MATCH_MODEL(PHY_ID_ADIN2111) },
--- a/drivers/net/phy/air_en8811h.c
+++ b/drivers/net/phy/air_en8811h.c
@@ -1075,7 +1075,7 @@ static struct phy_driver en8811h_driver[
module_phy_driver(en8811h_driver);
-static struct mdio_device_id __maybe_unused en8811h_tbl[] = {
+static const struct mdio_device_id __maybe_unused en8811h_tbl[] = {
{ PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) },
{ }
};
--- a/drivers/net/phy/amd.c
+++ b/drivers/net/phy/amd.c
@@ -111,7 +111,7 @@ static struct phy_driver am79c_drivers[]
module_phy_driver(am79c_drivers);
-static struct mdio_device_id __maybe_unused amd_tbl[] = {
+static const struct mdio_device_id __maybe_unused amd_tbl[] = {
{ PHY_ID_AC101L, 0xfffffff0 },
{ PHY_ID_AM79C874, 0xfffffff0 },
{ }
--- a/drivers/net/phy/aquantia/aquantia_main.c
+++ b/drivers/net/phy/aquantia/aquantia_main.c
@@ -1096,7 +1096,7 @@ static struct phy_driver aqr_driver[] =
module_phy_driver(aqr_driver);
-static struct mdio_device_id __maybe_unused aqr_tbl[] = {
+static const struct mdio_device_id __maybe_unused aqr_tbl[] = {
{ PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
--- a/drivers/net/phy/ax88796b.c
+++ b/drivers/net/phy/ax88796b.c
@@ -121,7 +121,7 @@ static struct phy_driver asix_driver[] =
module_phy_driver(asix_driver);
-static struct mdio_device_id __maybe_unused asix_tbl[] = {
+static const struct mdio_device_id __maybe_unused asix_tbl[] = {
{ PHY_ID_MATCH_EXACT(PHY_ID_ASIX_AX88772A) },
{ PHY_ID_MATCH_EXACT(PHY_ID_ASIX_AX88772C) },
{ PHY_ID_ASIX_AX88796B, 0xfffffff0 },
--- a/drivers/net/phy/bcm-cygnus.c
+++ b/drivers/net/phy/bcm-cygnus.c
@@ -278,7 +278,7 @@ static struct phy_driver bcm_cygnus_phy_
}
};
-static struct mdio_device_id __maybe_unused bcm_cygnus_phy_tbl[] = {
+static const struct mdio_device_id __maybe_unused bcm_cygnus_phy_tbl[] = {
{ PHY_ID_BCM_CYGNUS, 0xfffffff0, },
{ PHY_ID_BCM_OMEGA, 0xfffffff0, },
{ }
--- a/drivers/net/phy/bcm54140.c
+++ b/drivers/net/phy/bcm54140.c
@@ -883,7 +883,7 @@ static struct phy_driver bcm54140_driver
};
module_phy_driver(bcm54140_drivers);
-static struct mdio_device_id __maybe_unused bcm54140_tbl[] = {
+static const struct mdio_device_id __maybe_unused bcm54140_tbl[] = {
{ PHY_ID_BCM54140, BCM54140_PHY_ID_MASK },
{ }
};
--- a/drivers/net/phy/bcm63xx.c
+++ b/drivers/net/phy/bcm63xx.c
@@ -93,7 +93,7 @@ static struct phy_driver bcm63xx_driver[
module_phy_driver(bcm63xx_driver);
-static struct mdio_device_id __maybe_unused bcm63xx_tbl[] = {
+static const struct mdio_device_id __maybe_unused bcm63xx_tbl[] = {
{ 0x00406000, 0xfffffc00 },
{ 0x002bdc00, 0xfffffc00 },
{ }
--- a/drivers/net/phy/bcm7xxx.c
+++ b/drivers/net/phy/bcm7xxx.c
@@ -929,7 +929,7 @@ static struct phy_driver bcm7xxx_driver[
BCM7XXX_16NM_EPHY(PHY_ID_BCM7712, "Broadcom BCM7712"),
};
-static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
+static const struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
{ PHY_ID_BCM72113, 0xfffffff0 },
{ PHY_ID_BCM72116, 0xfffffff0, },
{ PHY_ID_BCM72165, 0xfffffff0, },
--- a/drivers/net/phy/bcm84881.c
+++ b/drivers/net/phy/bcm84881.c
@@ -252,7 +252,7 @@ static struct phy_driver bcm84881_driver
module_phy_driver(bcm84881_drivers);
/* FIXME: module auto-loading for Clause 45 PHYs seems non-functional */
-static struct mdio_device_id __maybe_unused bcm84881_tbl[] = {
+static const struct mdio_device_id __maybe_unused bcm84881_tbl[] = {
{ 0xae025150, 0xfffffff0 },
{ },
};
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -1717,7 +1717,7 @@ static struct phy_driver broadcom_driver
module_phy_driver(broadcom_drivers);
-static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
+static const struct mdio_device_id __maybe_unused broadcom_tbl[] = {
{ PHY_ID_BCM5411, 0xfffffff0 },
{ PHY_ID_BCM5421, 0xfffffff0 },
{ PHY_ID_BCM54210E, 0xfffffff0 },
--- a/drivers/net/phy/cicada.c
+++ b/drivers/net/phy/cicada.c
@@ -145,7 +145,7 @@ static struct phy_driver cis820x_driver[
module_phy_driver(cis820x_driver);
-static struct mdio_device_id __maybe_unused cicada_tbl[] = {
+static const struct mdio_device_id __maybe_unused cicada_tbl[] = {
{ 0x000fc410, 0x000ffff0 },
{ 0x000fc440, 0x000fffc0 },
{ }
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -87,7 +87,7 @@ static struct phy_driver cortina_driver[
module_phy_driver(cortina_driver);
-static struct mdio_device_id __maybe_unused cortina_tbl[] = {
+static const struct mdio_device_id __maybe_unused cortina_tbl[] = {
{ PHY_ID_CS4340, 0xffffffff},
{},
};
--- a/drivers/net/phy/davicom.c
+++ b/drivers/net/phy/davicom.c
@@ -209,7 +209,7 @@ static struct phy_driver dm91xx_driver[]
module_phy_driver(dm91xx_driver);
-static struct mdio_device_id __maybe_unused davicom_tbl[] = {
+static const struct mdio_device_id __maybe_unused davicom_tbl[] = {
{ 0x0181b880, 0x0ffffff0 },
{ 0x0181b8b0, 0x0ffffff0 },
{ 0x0181b8a0, 0x0ffffff0 },
--- a/drivers/net/phy/dp83640.c
+++ b/drivers/net/phy/dp83640.c
@@ -1548,7 +1548,7 @@ MODULE_LICENSE("GPL");
module_init(dp83640_init);
module_exit(dp83640_exit);
-static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
+static const struct mdio_device_id __maybe_unused dp83640_tbl[] = {
{ DP83640_PHY_ID, 0xfffffff0 },
{ }
};
--- a/drivers/net/phy/dp83822.c
+++ b/drivers/net/phy/dp83822.c
@@ -825,7 +825,7 @@ static struct phy_driver dp83822_driver[
};
module_phy_driver(dp83822_driver);
-static struct mdio_device_id __maybe_unused dp83822_tbl[] = {
+static const struct mdio_device_id __maybe_unused dp83822_tbl[] = {
{ DP83822_PHY_ID, 0xfffffff0 },
{ DP83825I_PHY_ID, 0xfffffff0 },
{ DP83826C_PHY_ID, 0xfffffff0 },
--- a/drivers/net/phy/dp83848.c
+++ b/drivers/net/phy/dp83848.c
@@ -123,7 +123,7 @@ static int dp83848_config_init(struct ph
return 0;
}
-static struct mdio_device_id __maybe_unused dp83848_tbl[] = {
+static const struct mdio_device_id __maybe_unused dp83848_tbl[] = {
{ TI_DP83848C_PHY_ID, 0xfffffff0 },
{ NS_DP83848C_PHY_ID, 0xfffffff0 },
{ TI_DP83620_PHY_ID, 0xfffffff0 },
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -1210,7 +1210,7 @@ static struct phy_driver dp83867_driver[
};
module_phy_driver(dp83867_driver);
-static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
+static const struct mdio_device_id __maybe_unused dp83867_tbl[] = {
{ DP83867_PHY_ID, 0xfffffff0 },
{ }
};
--- a/drivers/net/phy/dp83869.c
+++ b/drivers/net/phy/dp83869.c
@@ -928,7 +928,7 @@ static struct phy_driver dp83869_driver[
};
module_phy_driver(dp83869_driver);
-static struct mdio_device_id __maybe_unused dp83869_tbl[] = {
+static const struct mdio_device_id __maybe_unused dp83869_tbl[] = {
{ PHY_ID_MATCH_MODEL(DP83869_PHY_ID) },
{ PHY_ID_MATCH_MODEL(DP83561_PHY_ID) },
{ }
--- a/drivers/net/phy/dp83tc811.c
+++ b/drivers/net/phy/dp83tc811.c
@@ -403,7 +403,7 @@ static struct phy_driver dp83811_driver[
};
module_phy_driver(dp83811_driver);
-static struct mdio_device_id __maybe_unused dp83811_tbl[] = {
+static const struct mdio_device_id __maybe_unused dp83811_tbl[] = {
{ DP83TC811_PHY_ID, 0xfffffff0 },
{ },
};
--- a/drivers/net/phy/dp83td510.c
+++ b/drivers/net/phy/dp83td510.c
@@ -605,7 +605,7 @@ static struct phy_driver dp83td510_drive
} };
module_phy_driver(dp83td510_driver);
-static struct mdio_device_id __maybe_unused dp83td510_tbl[] = {
+static const struct mdio_device_id __maybe_unused dp83td510_tbl[] = {
{ PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID) },
{ }
};
--- a/drivers/net/phy/dp83tg720.c
+++ b/drivers/net/phy/dp83tg720.c
@@ -361,7 +361,7 @@ static struct phy_driver dp83tg720_drive
} };
module_phy_driver(dp83tg720_driver);
-static struct mdio_device_id __maybe_unused dp83tg720_tbl[] = {
+static const struct mdio_device_id __maybe_unused dp83tg720_tbl[] = {
{ PHY_ID_MATCH_MODEL(DP83TG720S_PHY_ID) },
{ }
};
--- a/drivers/net/phy/et1011c.c
+++ b/drivers/net/phy/et1011c.c
@@ -94,7 +94,7 @@ static struct phy_driver et1011c_driver[
module_phy_driver(et1011c_driver);
-static struct mdio_device_id __maybe_unused et1011c_tbl[] = {
+static const struct mdio_device_id __maybe_unused et1011c_tbl[] = {
{ 0x0282f014, 0xfffffff0 },
{ }
};
--- a/drivers/net/phy/icplus.c
+++ b/drivers/net/phy/icplus.c
@@ -624,7 +624,7 @@ static struct phy_driver icplus_driver[]
module_phy_driver(icplus_driver);
-static struct mdio_device_id __maybe_unused icplus_tbl[] = {
+static const struct mdio_device_id __maybe_unused icplus_tbl[] = {
{ PHY_ID_MATCH_MODEL(IP175C_PHY_ID) },
{ PHY_ID_MATCH_MODEL(IP1001_PHY_ID) },
{ PHY_ID_MATCH_EXACT(IP101A_PHY_ID) },
--- a/drivers/net/phy/intel-xway.c
+++ b/drivers/net/phy/intel-xway.c
@@ -456,7 +456,7 @@ static struct phy_driver xway_gphy[] = {
};
module_phy_driver(xway_gphy);
-static struct mdio_device_id __maybe_unused xway_gphy_tbl[] = {
+static const struct mdio_device_id __maybe_unused xway_gphy_tbl[] = {
{ PHY_ID_PHY11G_1_3, 0xffffffff },
{ PHY_ID_PHY22F_1_3, 0xffffffff },
{ PHY_ID_PHY11G_1_4, 0xffffffff },
--- a/drivers/net/phy/lxt.c
+++ b/drivers/net/phy/lxt.c
@@ -348,7 +348,7 @@ static struct phy_driver lxt97x_driver[]
module_phy_driver(lxt97x_driver);
-static struct mdio_device_id __maybe_unused lxt_tbl[] = {
+static const struct mdio_device_id __maybe_unused lxt_tbl[] = {
{ 0x78100000, 0xfffffff0 },
{ 0x001378e0, 0xfffffff0 },
{ 0x00137a10, 0xfffffff0 },
--- a/drivers/net/phy/marvell-88q2xxx.c
+++ b/drivers/net/phy/marvell-88q2xxx.c
@@ -940,7 +940,7 @@ static struct phy_driver mv88q2xxx_drive
module_phy_driver(mv88q2xxx_driver);
-static struct mdio_device_id __maybe_unused mv88q2xxx_tbl[] = {
+static const struct mdio_device_id __maybe_unused mv88q2xxx_tbl[] = {
{ MARVELL_PHY_ID_88Q2110, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88Q2220, MARVELL_PHY_ID_MASK },
{ /*sentinel*/ }
--- a/drivers/net/phy/marvell-88x2222.c
+++ b/drivers/net/phy/marvell-88x2222.c
@@ -613,7 +613,7 @@ static struct phy_driver mv2222_drivers[
};
module_phy_driver(mv2222_drivers);
-static struct mdio_device_id __maybe_unused mv2222_tbl[] = {
+static const struct mdio_device_id __maybe_unused mv2222_tbl[] = {
{ MARVELL_PHY_ID_88X2222, MARVELL_PHY_ID_MASK },
{ }
};
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -4133,7 +4133,7 @@ static struct phy_driver marvell_drivers
module_phy_driver(marvell_drivers);
-static struct mdio_device_id __maybe_unused marvell_tbl[] = {
+static const struct mdio_device_id __maybe_unused marvell_tbl[] = {
{ MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E3082, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -1484,7 +1484,7 @@ static struct phy_driver mv3310_drivers[
module_phy_driver(mv3310_drivers);
-static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
+static const struct mdio_device_id __maybe_unused mv3310_tbl[] = {
{ MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
{ MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
{ },
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -1356,7 +1356,7 @@ static struct phy_driver mtk_socphy_driv
module_phy_driver(mtk_socphy_driver);
-static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
+static const struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
{ }
--- a/drivers/net/phy/mediatek/mtk-ge.c
+++ b/drivers/net/phy/mediatek/mtk-ge.c
@@ -93,7 +93,7 @@ static struct phy_driver mtk_gephy_drive
module_phy_driver(mtk_gephy_driver);
-static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
+static const struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530) },
{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531) },
{ }
--- a/drivers/net/phy/meson-gxl.c
+++ b/drivers/net/phy/meson-gxl.c
@@ -221,7 +221,7 @@ static struct phy_driver meson_gxl_phy[]
},
};
-static struct mdio_device_id __maybe_unused meson_gxl_tbl[] = {
+static const struct mdio_device_id __maybe_unused meson_gxl_tbl[] = {
{ PHY_ID_MATCH_VENDOR(0x01814400) },
{ PHY_ID_MATCH_VENDOR(0x01803301) },
{ }
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -5691,7 +5691,7 @@ MODULE_DESCRIPTION("Micrel PHY driver");
MODULE_AUTHOR("David J. Choi");
MODULE_LICENSE("GPL");
-static struct mdio_device_id __maybe_unused micrel_tbl[] = {
+static const struct mdio_device_id __maybe_unused micrel_tbl[] = {
{ PHY_ID_KSZ9021, 0x000ffffe },
{ PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
{ PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
--- a/drivers/net/phy/microchip.c
+++ b/drivers/net/phy/microchip.c
@@ -508,7 +508,7 @@ static struct phy_driver microchip_phy_d
module_phy_driver(microchip_phy_driver);
-static struct mdio_device_id __maybe_unused microchip_tbl[] = {
+static const struct mdio_device_id __maybe_unused microchip_tbl[] = {
{ 0x0007c132, 0xfffffff2 },
{ PHY_ID_MATCH_MODEL(PHY_ID_LAN937X_TX) },
{ }
--- a/drivers/net/phy/microchip_t1.c
+++ b/drivers/net/phy/microchip_t1.c
@@ -1886,7 +1886,7 @@ static struct phy_driver microchip_t1_ph
module_phy_driver(microchip_t1_phy_driver);
-static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = {
+static const struct mdio_device_id __maybe_unused microchip_t1_tbl[] = {
{ PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX) },
{ PHY_ID_MATCH_MODEL(PHY_ID_LAN937X) },
{ PHY_ID_MATCH_MODEL(PHY_ID_LAN887X) },
--- a/drivers/net/phy/microchip_t1s.c
+++ b/drivers/net/phy/microchip_t1s.c
@@ -323,7 +323,7 @@ static struct phy_driver microchip_t1s_d
module_phy_driver(microchip_t1s_driver);
-static struct mdio_device_id __maybe_unused tbl[] = {
+static const struct mdio_device_id __maybe_unused tbl[] = {
{ PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1) },
{ PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB0) },
{ }
--- a/drivers/net/phy/mscc/mscc_main.c
+++ b/drivers/net/phy/mscc/mscc_main.c
@@ -2700,7 +2700,7 @@ static struct phy_driver vsc85xx_driver[
module_phy_driver(vsc85xx_driver);
-static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
+static const struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
{ PHY_ID_MATCH_VENDOR(PHY_VENDOR_MSCC) },
{ }
};
--- a/drivers/net/phy/mxl-gpy.c
+++ b/drivers/net/phy/mxl-gpy.c
@@ -1047,7 +1047,7 @@ static struct phy_driver gpy_drivers[] =
};
module_phy_driver(gpy_drivers);
-static struct mdio_device_id __maybe_unused gpy_tbl[] = {
+static const struct mdio_device_id __maybe_unused gpy_tbl[] = {
{PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)},
{PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK},
{PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)},
--- a/drivers/net/phy/national.c
+++ b/drivers/net/phy/national.c
@@ -173,7 +173,7 @@ MODULE_DESCRIPTION("NatSemi PHY driver")
MODULE_AUTHOR("Stuart Menefy");
MODULE_LICENSE("GPL");
-static struct mdio_device_id __maybe_unused ns_tbl[] = {
+static const struct mdio_device_id __maybe_unused ns_tbl[] = {
{ DP83865_PHY_ID, 0xfffffff0 },
{ }
};
--- a/drivers/net/phy/ncn26000.c
+++ b/drivers/net/phy/ncn26000.c
@@ -159,7 +159,7 @@ static struct phy_driver ncn26000_driver
module_phy_driver(ncn26000_driver);
-static struct mdio_device_id __maybe_unused ncn26000_tbl[] = {
+static const struct mdio_device_id __maybe_unused ncn26000_tbl[] = {
{ PHY_ID_MATCH_MODEL(PHY_ID_NCN26000) },
{ }
};
--- a/drivers/net/phy/nxp-c45-tja11xx.c
+++ b/drivers/net/phy/nxp-c45-tja11xx.c
@@ -2052,7 +2052,7 @@ static struct phy_driver nxp_c45_driver[
module_phy_driver(nxp_c45_driver);
-static struct mdio_device_id __maybe_unused nxp_c45_tbl[] = {
+static const struct mdio_device_id __maybe_unused nxp_c45_tbl[] = {
{ PHY_ID_MATCH_MODEL(PHY_ID_TJA_1103) },
{ PHY_ID_MATCH_MODEL(PHY_ID_TJA_1120) },
{ /*sentinel*/ },
--- a/drivers/net/phy/nxp-cbtx.c
+++ b/drivers/net/phy/nxp-cbtx.c
@@ -215,7 +215,7 @@ static struct phy_driver cbtx_driver[] =
module_phy_driver(cbtx_driver);
-static struct mdio_device_id __maybe_unused cbtx_tbl[] = {
+static const struct mdio_device_id __maybe_unused cbtx_tbl[] = {
{ PHY_ID_MATCH_MODEL(PHY_ID_CBTX_SJA1110) },
{ },
};
--- a/drivers/net/phy/nxp-tja11xx.c
+++ b/drivers/net/phy/nxp-tja11xx.c
@@ -888,7 +888,7 @@ static struct phy_driver tja11xx_driver[
module_phy_driver(tja11xx_driver);
-static struct mdio_device_id __maybe_unused tja11xx_tbl[] = {
+static const struct mdio_device_id __maybe_unused tja11xx_tbl[] = {
{ PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) },
{ PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) },
{ PHY_ID_MATCH_MODEL(PHY_ID_TJA1102) },
--- a/drivers/net/phy/qcom/at803x.c
+++ b/drivers/net/phy/qcom/at803x.c
@@ -1098,7 +1098,7 @@ static struct phy_driver at803x_driver[]
module_phy_driver(at803x_driver);
-static struct mdio_device_id __maybe_unused atheros_tbl[] = {
+static const struct mdio_device_id __maybe_unused atheros_tbl[] = {
{ ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
{ PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
{ PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
--- a/drivers/net/phy/qcom/qca807x.c
+++ b/drivers/net/phy/qcom/qca807x.c
@@ -828,7 +828,7 @@ static struct phy_driver qca807x_drivers
};
module_phy_driver(qca807x_drivers);
-static struct mdio_device_id __maybe_unused qca807x_tbl[] = {
+static const struct mdio_device_id __maybe_unused qca807x_tbl[] = {
{ PHY_ID_MATCH_EXACT(PHY_ID_QCA8072) },
{ PHY_ID_MATCH_EXACT(PHY_ID_QCA8075) },
{ }
--- a/drivers/net/phy/qcom/qca808x.c
+++ b/drivers/net/phy/qcom/qca808x.c
@@ -655,7 +655,7 @@ static struct phy_driver qca808x_driver[
module_phy_driver(qca808x_driver);
-static struct mdio_device_id __maybe_unused qca808x_tbl[] = {
+static const struct mdio_device_id __maybe_unused qca808x_tbl[] = {
{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
{ }
};
--- a/drivers/net/phy/qcom/qca83xx.c
+++ b/drivers/net/phy/qcom/qca83xx.c
@@ -261,7 +261,7 @@ static struct phy_driver qca83xx_driver[
module_phy_driver(qca83xx_driver);
-static struct mdio_device_id __maybe_unused qca83xx_tbl[] = {
+static const struct mdio_device_id __maybe_unused qca83xx_tbl[] = {
{ PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
{ PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
{ PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
--- a/drivers/net/phy/qsemi.c
+++ b/drivers/net/phy/qsemi.c
@@ -155,7 +155,7 @@ static struct phy_driver qs6612_driver[]
module_phy_driver(qs6612_driver);
-static struct mdio_device_id __maybe_unused qs6612_tbl[] = {
+static const struct mdio_device_id __maybe_unused qs6612_tbl[] = {
{ 0x00181440, 0xfffffff0 },
{ }
};
--- a/drivers/net/phy/rockchip.c
+++ b/drivers/net/phy/rockchip.c
@@ -188,7 +188,7 @@ static struct phy_driver rockchip_phy_dr
module_phy_driver(rockchip_phy_driver);
-static struct mdio_device_id __maybe_unused rockchip_phy_tbl[] = {
+static const struct mdio_device_id __maybe_unused rockchip_phy_tbl[] = {
{ INTERNAL_EPHY_ID, 0xfffffff0 },
{ }
};
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -837,7 +837,7 @@ MODULE_DESCRIPTION("SMSC PHY driver");
MODULE_AUTHOR("Herbert Valerio Riedel");
MODULE_LICENSE("GPL");
-static struct mdio_device_id __maybe_unused smsc_tbl[] = {
+static const struct mdio_device_id __maybe_unused smsc_tbl[] = {
{ 0x0007c0a0, 0xfffffff0 },
{ 0x0007c0b0, 0xfffffff0 },
{ 0x0007c0c0, 0xfffffff0 },
--- a/drivers/net/phy/ste10Xp.c
+++ b/drivers/net/phy/ste10Xp.c
@@ -124,7 +124,7 @@ static struct phy_driver ste10xp_pdriver
module_phy_driver(ste10xp_pdriver);
-static struct mdio_device_id __maybe_unused ste10Xp_tbl[] = {
+static const struct mdio_device_id __maybe_unused ste10Xp_tbl[] = {
{ STE101P_PHY_ID, 0xfffffff0 },
{ STE100P_PHY_ID, 0xffffffff },
{ }
--- a/drivers/net/phy/teranetics.c
+++ b/drivers/net/phy/teranetics.c
@@ -87,7 +87,7 @@ static struct phy_driver teranetics_driv
module_phy_driver(teranetics_driver);
-static struct mdio_device_id __maybe_unused teranetics_tbl[] = {
+static const struct mdio_device_id __maybe_unused teranetics_tbl[] = {
{ PHY_ID_TN2020, 0xffffffff },
{ }
};
--- a/drivers/net/phy/uPD60620.c
+++ b/drivers/net/phy/uPD60620.c
@@ -90,7 +90,7 @@ static struct phy_driver upd60620_driver
module_phy_driver(upd60620_driver);
-static struct mdio_device_id __maybe_unused upd60620_tbl[] = {
+static const struct mdio_device_id __maybe_unused upd60620_tbl[] = {
{ UPD60620_PHY_ID, 0xfffffffe },
{ }
};
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -674,7 +674,7 @@ static struct phy_driver vsc82xx_driver[
module_phy_driver(vsc82xx_driver);
-static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
+static const struct mdio_device_id __maybe_unused vitesse_tbl[] = {
{ PHY_ID_VSC8234, 0x000ffff0 },
{ PHY_ID_VSC8244, 0x000fffc0 },
{ PHY_ID_VSC8572, 0x000ffff0 },

146
lede/target/linux/generic/backport-6.12/729-v6.15-net-phy-mediatek-Change-to-more-meaningful-macros.patch Normal file
View File

@@ -0,0 +1,146 @@
From 7e06c3dbfa5f1e39eba92eb79d854fab2a7ad5fe Mon Sep 17 00:00:00 2001
From: Sky Huang <skylake.huang@mediatek.com>
Date: Thu, 13 Feb 2025 16:05:49 +0800
Subject: [PATCH 10/20] net: phy: mediatek: Change to more meaningful macros
Replace magic number with more meaningful macros in mtk-ge.c.
Also, move some common macros into mtk-phy-lib.c.
Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20250213080553.921434-2-SkyLake.Huang@mediatek.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/phy/mediatek/mtk-ge-soc.c | 1 -
drivers/net/phy/mediatek/mtk-ge.c | 71 +++++++++++++++++++++------
drivers/net/phy/mediatek/mtk.h | 2 +
3 files changed, 57 insertions(+), 17 deletions(-)
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -24,7 +24,6 @@
#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
-#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
#define ANALOG_INTERNAL_OPERATION_MAX_US 20
#define TXRESERVE_MIN 0
--- a/drivers/net/phy/mediatek/mtk-ge.c
+++ b/drivers/net/phy/mediatek/mtk-ge.c
@@ -8,18 +8,38 @@
#define MTK_GPHY_ID_MT7530 0x03a29412
#define MTK_GPHY_ID_MT7531 0x03a29441
-#define MTK_EXT_PAGE_ACCESS 0x1f
-#define MTK_PHY_PAGE_STANDARD 0x0000
-#define MTK_PHY_PAGE_EXTENDED 0x0001
-#define MTK_PHY_PAGE_EXTENDED_2 0x0002
-#define MTK_PHY_PAGE_EXTENDED_3 0x0003
-#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
-#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
+#define MTK_PHY_PAGE_EXTENDED_1 0x0001
+#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14
+#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
+
+#define MTK_PHY_PAGE_EXTENDED_2 0x0002
+#define MTK_PHY_PAGE_EXTENDED_3 0x0003
+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11 0x11
+
+#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
+
+/* Registers on MDIO_MMD_VEND1 */
+#define MTK_PHY_GBE_MODE_TX_DELAY_SEL 0x13
+#define MTK_PHY_TEST_MODE_TX_DELAY_SEL 0x14
+#define MTK_TX_DELAY_PAIR_B_MASK GENMASK(10, 8)
+#define MTK_TX_DELAY_PAIR_D_MASK GENMASK(2, 0)
+
+#define MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL 0xa6
+#define MTK_MCC_NEARECHO_OFFSET_MASK GENMASK(15, 8)
+
+#define MTK_PHY_RXADC_CTRL_RG7 0xc6
+#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
+
+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123 0x123
+#define MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK GENMASK(15, 8)
+#define MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK GENMASK(7, 0)
static void mtk_gephy_config_init(struct phy_device *phydev)
{
/* Enable HW auto downshift */
- phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
+ phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1,
+ MTK_PHY_AUX_CTRL_AND_STATUS,
+ 0, MTK_PHY_ENABLE_DOWNSHIFT);
/* Increase SlvDPSready time */
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
@@ -29,10 +49,20 @@ static void mtk_gephy_config_init(struct
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
/* Adjust 100_mse_threshold */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
-
- /* Disable mcc */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123,
+ MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK |
+ MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK,
+ 0xff) |
+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
+ 0xff));
+
+ /* If echo time is narrower than 0x3, it will be regarded as noise */
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
+ MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL,
+ MTK_MCC_NEARECHO_OFFSET_MASK,
+ FIELD_PREP(MTK_MCC_NEARECHO_OFFSET_MASK, 0x3));
}
static int mt7530_phy_config_init(struct phy_device *phydev)
@@ -40,7 +70,8 @@ static int mt7530_phy_config_init(struct
mtk_gephy_config_init(phydev);
/* Increase post_update_timer */
- phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
+ phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3,
+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11, 0x4b);
return 0;
}
@@ -51,11 +82,19 @@ static int mt7531_phy_config_init(struct
/* PHY link down power saving enable */
phy_set_bits(phydev, 0x17, BIT(4));
- phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
+ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK,
+ FIELD_PREP(MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3));
/* Set TX Pair delay selection */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_GBE_MODE_TX_DELAY_SEL,
+ MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
+ FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
+ FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TEST_MODE_TX_DELAY_SEL,
+ MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
+ FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
+ FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
return 0;
}
--- a/drivers/net/phy/mediatek/mtk.h
+++ b/drivers/net/phy/mediatek/mtk.h
@@ -9,6 +9,8 @@
#define _MTK_EPHY_H_
#define MTK_EXT_PAGE_ACCESS 0x1f
+#define MTK_PHY_PAGE_STANDARD 0x0000
+#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
/* Registers on MDIO_MMD_VEND2 */
#define MTK_PHY_LED0_ON_CTRL 0x24

448
lede/target/linux/generic/backport-6.12/730-v6.15-net-phy-mediatek-Add-token-ring-access-helper-functi.patch Normal file
View File

@@ -0,0 +1,448 @@
From 6e7370079669b0d55c9464bb7c3fb8fb7368b912 Mon Sep 17 00:00:00 2001
From: Sky Huang <skylake.huang@mediatek.com>
Date: Thu, 13 Feb 2025 16:05:50 +0800
Subject: [PATCH 11/20] net: phy: mediatek: Add token ring access helper
functions in mtk-phy-lib
This patch adds TR(token ring) manipulations and adds correct
macro names for those magic numbers. TR is a way to access
proprietary registers on page 52b5. Use these helper functions
so we can see which fields we're going to modify/set/clear.
TR functions with __* prefix mean that the operations inside
aren't wrapped by page select/restore functions.
This patch doesn't really change registers' settings but just
enhances readability and maintainability.
Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20250213080553.921434-3-SkyLake.Huang@mediatek.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/phy/mediatek/mtk-ge-soc.c | 231 +++++++++++++++++--------
drivers/net/phy/mediatek/mtk-ge.c | 11 +-
drivers/net/phy/mediatek/mtk-phy-lib.c | 63 +++++++
drivers/net/phy/mediatek/mtk.h | 5 +
4 files changed, 230 insertions(+), 80 deletions(-)
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -25,6 +25,90 @@
#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
+/* Registers on Token Ring debug nodes */
+/* ch_addr = 0x0, node_addr = 0x7, data_addr = 0x15 */
+/* NormMseLoThresh */
+#define NORMAL_MSE_LO_THRESH_MASK GENMASK(15, 8)
+
+/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
+/* RemAckCntLimitCtrl */
+#define REMOTE_ACK_COUNT_LIMIT_CTRL_MASK GENMASK(2, 1)
+
+/* ch_addr = 0x1, node_addr = 0xd, data_addr = 0x20 */
+/* VcoSlicerThreshBitsHigh */
+#define VCO_SLICER_THRESH_HIGH_MASK GENMASK(23, 0)
+
+/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x0 */
+/* DfeTailEnableVgaThresh1000 */
+#define DFE_TAIL_EANBLE_VGA_TRHESH_1000 GENMASK(5, 1)
+
+/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x1 */
+/* MrvlTrFix100Kp */
+#define MRVL_TR_FIX_100KP_MASK GENMASK(22, 20)
+/* MrvlTrFix100Kf */
+#define MRVL_TR_FIX_100KF_MASK GENMASK(19, 17)
+/* MrvlTrFix1000Kp */
+#define MRVL_TR_FIX_1000KP_MASK GENMASK(16, 14)
+/* MrvlTrFix1000Kf */
+#define MRVL_TR_FIX_1000KF_MASK GENMASK(13, 11)
+
+/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x12 */
+/* VgaDecRate */
+#define VGA_DECIMATION_RATE_MASK GENMASK(8, 5)
+
+/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
+/* SlvDSPreadyTime */
+#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
+/* MasDSPreadyTime */
+#define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7)
+
+/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */
+/* ResetSyncOffset */
+#define RESET_SYNC_OFFSET_MASK GENMASK(11, 8)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x0 */
+/* FfeUpdGainForceVal */
+#define FFE_UPDATE_GAIN_FORCE_VAL_MASK GENMASK(9, 7)
+/* FfeUpdGainForce */
+#define FFE_UPDATE_GAIN_FORCE BIT(6)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */
+/* SS: Steady-state, KP: Proportional Gain */
+/* SSTrKp100 */
+#define SS_TR_KP100_MASK GENMASK(21, 19)
+/* SSTrKf100 */
+#define SS_TR_KF100_MASK GENMASK(18, 16)
+/* SSTrKp1000Mas */
+#define SS_TR_KP1000_MASTER_MASK GENMASK(15, 13)
+/* SSTrKf1000Mas */
+#define SS_TR_KF1000_MASTER_MASK GENMASK(12, 10)
+/* SSTrKp1000Slv */
+#define SS_TR_KP1000_SLAVE_MASK GENMASK(9, 7)
+/* SSTrKf1000Slv */
+#define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */
+/* RegEEE_st2TrKf1000 */
+#define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xf */
+/* RegEEE_slv_waketr_timer_tar */
+#define SLAVE_WAKETR_TIMER_MASK GENMASK(20, 11)
+/* RegEEE_slv_remtx_timer_tar */
+#define SLAVE_REMTX_TIMER_MASK GENMASK(10, 1)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x10 */
+/* RegEEE_slv_wake_int_timer_tar */
+#define SLAVE_WAKEINT_TIMER_MASK GENMASK(10, 1)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x14 */
+/* RegEEE_trfreeze_timer2 */
+#define TR_FREEZE_TIMER2_MASK GENMASK(9, 0)
+
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x1c */
+/* RegEEE100Stg1_tar */
+#define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0)
+
#define ANALOG_INTERNAL_OPERATION_MAX_US 20
#define TXRESERVE_MIN 0
#define TXRESERVE_MAX 7
@@ -700,40 +784,41 @@ restore:
static void mt798x_phy_common_finetune(struct phy_device *phydev)
{
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
- __phy_write(phydev, 0x11, 0xc71);
- __phy_write(phydev, 0x12, 0xc);
- __phy_write(phydev, 0x10, 0x8fae);
+ __mtk_tr_modify(phydev, 0x1, 0xf, 0x17,
+ SLAVE_DSP_READY_TIME_MASK | MASTER_DSP_READY_TIME_MASK,
+ FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) |
+ FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18));
/* EnabRandUpdTrig = 1 */
__phy_write(phydev, 0x11, 0x2f00);
__phy_write(phydev, 0x12, 0xe);
__phy_write(phydev, 0x10, 0x8fb0);
- /* NormMseLoThresh = 85 */
- __phy_write(phydev, 0x11, 0x55a0);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x83aa);
-
- /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
- __phy_write(phydev, 0x11, 0x240);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x9680);
+ __mtk_tr_modify(phydev, 0x0, 0x7, 0x15,
+ NORMAL_MSE_LO_THRESH_MASK,
+ FIELD_PREP(NORMAL_MSE_LO_THRESH_MASK, 0x55));
+
+ __mtk_tr_modify(phydev, 0x2, 0xd, 0x0,
+ FFE_UPDATE_GAIN_FORCE_VAL_MASK,
+ FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) |
+ FFE_UPDATE_GAIN_FORCE);
/* TrFreeze = 0 (mt7988 default) */
__phy_write(phydev, 0x11, 0x0);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x9686);
- /* SSTrKp100 = 5 */
- /* SSTrKf100 = 6 */
- /* SSTrKp1000Mas = 5 */
- /* SSTrKf1000Mas = 6 */
- /* SSTrKp1000Slv = 5 */
- /* SSTrKf1000Slv = 6 */
- __phy_write(phydev, 0x11, 0xbaef);
- __phy_write(phydev, 0x12, 0x2e);
- __phy_write(phydev, 0x10, 0x968c);
+ __mtk_tr_modify(phydev, 0x2, 0xd, 0x6,
+ SS_TR_KP100_MASK | SS_TR_KF100_MASK |
+ SS_TR_KP1000_MASTER_MASK | SS_TR_KF1000_MASTER_MASK |
+ SS_TR_KP1000_SLAVE_MASK | SS_TR_KF1000_SLAVE_MASK,
+ FIELD_PREP(SS_TR_KP100_MASK, 0x5) |
+ FIELD_PREP(SS_TR_KF100_MASK, 0x6) |
+ FIELD_PREP(SS_TR_KP1000_MASTER_MASK, 0x5) |
+ FIELD_PREP(SS_TR_KF1000_MASTER_MASK, 0x6) |
+ FIELD_PREP(SS_TR_KP1000_SLAVE_MASK, 0x5) |
+ FIELD_PREP(SS_TR_KF1000_SLAVE_MASK, 0x6));
+
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
}
@@ -756,27 +841,29 @@ static void mt7981_phy_finetune(struct p
}
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
- /* ResetSyncOffset = 6 */
- __phy_write(phydev, 0x11, 0x600);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x8fc0);
-
- /* VgaDecRate = 1 */
- __phy_write(phydev, 0x11, 0x4c2a);
- __phy_write(phydev, 0x12, 0x3e);
- __phy_write(phydev, 0x10, 0x8fa4);
+ __mtk_tr_modify(phydev, 0x1, 0xf, 0x20,
+ RESET_SYNC_OFFSET_MASK,
+ FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x6));
+
+ __mtk_tr_modify(phydev, 0x1, 0xf, 0x12,
+ VGA_DECIMATION_RATE_MASK,
+ FIELD_PREP(VGA_DECIMATION_RATE_MASK, 0x1));
/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
* MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
*/
- __phy_write(phydev, 0x11, 0xd10a);
- __phy_write(phydev, 0x12, 0x34);
- __phy_write(phydev, 0x10, 0x8f82);
+ __mtk_tr_modify(phydev, 0x1, 0xf, 0x1,
+ MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK |
+ MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK,
+ FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x3) |
+ FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x2) |
+ FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x3) |
+ FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x2));
/* VcoSlicerThreshBitsHigh */
- __phy_write(phydev, 0x11, 0x5555);
- __phy_write(phydev, 0x12, 0x55);
- __phy_write(phydev, 0x10, 0x8ec0);
+ __mtk_tr_modify(phydev, 0x1, 0xd, 0x20,
+ VCO_SLICER_THRESH_HIGH_MASK,
+ FIELD_PREP(VCO_SLICER_THRESH_HIGH_MASK, 0x555555));
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
@@ -828,25 +915,23 @@ static void mt7988_phy_finetune(struct p
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
- /* ResetSyncOffset = 5 */
- __phy_write(phydev, 0x11, 0x500);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x8fc0);
+ __mtk_tr_modify(phydev, 0x1, 0xf, 0x20,
+ RESET_SYNC_OFFSET_MASK,
+ FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x5));
/* VgaDecRate is 1 at default on mt7988 */
- /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
- * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
- */
- __phy_write(phydev, 0x11, 0xb90a);
- __phy_write(phydev, 0x12, 0x6f);
- __phy_write(phydev, 0x10, 0x8f82);
-
- /* RemAckCntLimitCtrl = 1 */
- __phy_write(phydev, 0x11, 0xfbba);
- __phy_write(phydev, 0x12, 0xc3);
- __phy_write(phydev, 0x10, 0x87f8);
-
+ __mtk_tr_modify(phydev, 0x1, 0xf, 0x1,
+ MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK |
+ MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK,
+ FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x6) |
+ FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x7) |
+ FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x6) |
+ FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x7));
+
+ __mtk_tr_modify(phydev, 0x0, 0xf, 0x3c,
+ REMOTE_ACK_COUNT_LIMIT_CTRL_MASK,
+ FIELD_PREP(REMOTE_ACK_COUNT_LIMIT_CTRL_MASK, 0x1));
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
@@ -927,40 +1012,36 @@ static void mt798x_phy_eee(struct phy_de
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x9690);
- /* REG_EEE_st2TrKf1000 = 2 */
- __phy_write(phydev, 0x11, 0x114f);
- __phy_write(phydev, 0x12, 0x2);
- __phy_write(phydev, 0x10, 0x969a);
-
- /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
- __phy_write(phydev, 0x11, 0x3028);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x969e);
-
- /* RegEEE_slv_wake_int_timer_tar = 8 */
- __phy_write(phydev, 0x11, 0x5010);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x96a0);
-
- /* RegEEE_trfreeze_timer2 = 586 */
- __phy_write(phydev, 0x11, 0x24a);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x96a8);
-
- /* RegEEE100Stg1_tar = 16 */
- __phy_write(phydev, 0x11, 0x3210);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x96b8);
+ __mtk_tr_modify(phydev, 0x2, 0xd, 0xd,
+ EEE1000_STAGE2_TR_KF_MASK,
+ FIELD_PREP(EEE1000_STAGE2_TR_KF_MASK, 0x2));
+
+ __mtk_tr_modify(phydev, 0x2, 0xd, 0xf,
+ SLAVE_WAKETR_TIMER_MASK | SLAVE_REMTX_TIMER_MASK,
+ FIELD_PREP(SLAVE_WAKETR_TIMER_MASK, 0x6) |
+ FIELD_PREP(SLAVE_REMTX_TIMER_MASK, 0x14));
+
+ __mtk_tr_modify(phydev, 0x2, 0xd, 0x10,
+ SLAVE_WAKEINT_TIMER_MASK,
+ FIELD_PREP(SLAVE_WAKEINT_TIMER_MASK, 0x8));
+
+ __mtk_tr_modify(phydev, 0x2, 0xd, 0x14,
+ TR_FREEZE_TIMER2_MASK,
+ FIELD_PREP(TR_FREEZE_TIMER2_MASK, 0x24a));
+
+ __mtk_tr_modify(phydev, 0x2, 0xd, 0x1c,
+ EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
+ FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
+ 0x10));
/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
__phy_write(phydev, 0x11, 0x1463);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x96ca);
- /* DfeTailEnableVgaThresh1000 = 27 */
- __phy_write(phydev, 0x11, 0x36);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x8f80);
+ __mtk_tr_modify(phydev, 0x1, 0xf, 0x0,
+ DFE_TAIL_EANBLE_VGA_TRHESH_1000,
+ FIELD_PREP(DFE_TAIL_EANBLE_VGA_TRHESH_1000, 0x1b));
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
--- a/drivers/net/phy/mediatek/mtk-ge.c
+++ b/drivers/net/phy/mediatek/mtk-ge.c
@@ -18,6 +18,10 @@
#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
+/* Registers on Token Ring debug nodes */
+/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
+#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
+
/* Registers on MDIO_MMD_VEND1 */
#define MTK_PHY_GBE_MODE_TX_DELAY_SEL 0x13
#define MTK_PHY_TEST_MODE_TX_DELAY_SEL 0x14
@@ -42,11 +46,8 @@ static void mtk_gephy_config_init(struct
0, MTK_PHY_ENABLE_DOWNSHIFT);
/* Increase SlvDPSready time */
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
- __phy_write(phydev, 0x10, 0xafae);
- __phy_write(phydev, 0x12, 0x2f);
- __phy_write(phydev, 0x10, 0x8fae);
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+ mtk_tr_modify(phydev, 0x1, 0xf, 0x17, SLAVE_DSP_READY_TIME_MASK,
+ FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x5e));
/* Adjust 100_mse_threshold */
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
--- a/drivers/net/phy/mediatek/mtk-phy-lib.c
+++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
@@ -6,6 +6,69 @@
#include "mtk.h"
+/* Difference between functions with mtk_tr* and __mtk_tr* prefixes is
+ * mtk_tr* functions: wrapped by page switching operations
+ * __mtk_tr* functions: no page switching operations
+ */
+
+static void __mtk_tr_access(struct phy_device *phydev, bool read, u8 ch_addr,
+ u8 node_addr, u8 data_addr)
+{
+ u16 tr_cmd = BIT(15); /* bit 14 & 0 are reserved */
+
+ if (read)
+ tr_cmd |= BIT(13);
+
+ tr_cmd |= (((ch_addr & 0x3) << 11) |
+ ((node_addr & 0xf) << 7) |
+ ((data_addr & 0x3f) << 1));
+ dev_dbg(&phydev->mdio.dev, "tr_cmd: 0x%x\n", tr_cmd);
+ __phy_write(phydev, 0x10, tr_cmd);
+}
+
+static void __mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
+ u8 data_addr, u16 *tr_high, u16 *tr_low)
+{
+ __mtk_tr_access(phydev, true, ch_addr, node_addr, data_addr);
+ *tr_low = __phy_read(phydev, 0x11);
+ *tr_high = __phy_read(phydev, 0x12);
+ dev_dbg(&phydev->mdio.dev, "tr_high read: 0x%x, tr_low read: 0x%x\n",
+ *tr_high, *tr_low);
+}
+
+static void __mtk_tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
+ u8 data_addr, u32 tr_data)
+{
+ __phy_write(phydev, 0x11, tr_data & 0xffff);
+ __phy_write(phydev, 0x12, tr_data >> 16);
+ dev_dbg(&phydev->mdio.dev, "tr_high write: 0x%x, tr_low write: 0x%x\n",
+ tr_data >> 16, tr_data & 0xffff);
+ __mtk_tr_access(phydev, false, ch_addr, node_addr, data_addr);
+}
+
+void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
+ u8 data_addr, u32 mask, u32 set)
+{
+ u32 tr_data;
+ u16 tr_high;
+ u16 tr_low;
+
+ __mtk_tr_read(phydev, ch_addr, node_addr, data_addr, &tr_high, &tr_low);
+ tr_data = (tr_high << 16) | tr_low;
+ tr_data = (tr_data & ~mask) | set;
+ __mtk_tr_write(phydev, ch_addr, node_addr, data_addr, tr_data);
+}
+EXPORT_SYMBOL_GPL(__mtk_tr_modify);
+
+void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
+ u8 data_addr, u32 mask, u32 set)
+{
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+ __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, mask, set);
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+}
+EXPORT_SYMBOL_GPL(mtk_tr_modify);
+
int mtk_phy_read_page(struct phy_device *phydev)
{
return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
--- a/drivers/net/phy/mediatek/mtk.h
+++ b/drivers/net/phy/mediatek/mtk.h
@@ -68,6 +68,11 @@ struct mtk_socphy_priv {
unsigned long led_state;
};
+void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
+ u8 data_addr, u32 mask, u32 set);
+void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
+ u8 data_addr, u32 mask, u32 set);
+
int mtk_phy_read_page(struct phy_device *phydev);
int mtk_phy_write_page(struct phy_device *phydev, int page);

73
lede/target/linux/generic/backport-6.12/731-v6.15-net-phy-mediatek-Add-token-ring-set-bit-operation-su.patch Normal file
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@@ -0,0 +1,73 @@
From c7e2fb3421ef5ebbb4c91f44bd735ab10edd755a Mon Sep 17 00:00:00 2001
From: Sky Huang <skylake.huang@mediatek.com>
Date: Thu, 13 Feb 2025 16:05:51 +0800
Subject: [PATCH 12/20] net: phy: mediatek: Add token ring set bit operation
support
Previously in mtk-ge-soc.c, we set some register bits via token
ring, which were implemented in three __phy_write().
Now we can do the same thing via __mtk_tr_set_bits() helper.
Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20250213080553.921434-4-SkyLake.Huang@mediatek.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/phy/mediatek/mtk-ge-soc.c | 10 ++++++----
drivers/net/phy/mediatek/mtk-phy-lib.c | 7 +++++++
drivers/net/phy/mediatek/mtk.h | 2 ++
3 files changed, 15 insertions(+), 4 deletions(-)
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -62,6 +62,10 @@
/* MasDSPreadyTime */
#define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7)
+/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x18 */
+/* EnabRandUpdTrig */
+#define ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER BIT(8)
+
/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */
/* ResetSyncOffset */
#define RESET_SYNC_OFFSET_MASK GENMASK(11, 8)
@@ -789,10 +793,8 @@ static void mt798x_phy_common_finetune(s
FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) |
FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18));
- /* EnabRandUpdTrig = 1 */
- __phy_write(phydev, 0x11, 0x2f00);
- __phy_write(phydev, 0x12, 0xe);
- __phy_write(phydev, 0x10, 0x8fb0);
+ __mtk_tr_set_bits(phydev, 0x1, 0xf, 0x18,
+ ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER);
__mtk_tr_modify(phydev, 0x0, 0x7, 0x15,
NORMAL_MSE_LO_THRESH_MASK,
--- a/drivers/net/phy/mediatek/mtk-phy-lib.c
+++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
@@ -69,6 +69,13 @@ void mtk_tr_modify(struct phy_device *ph
}
EXPORT_SYMBOL_GPL(mtk_tr_modify);
+void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
+ u8 data_addr, u32 set)
+{
+ __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, 0, set);
+}
+EXPORT_SYMBOL_GPL(__mtk_tr_set_bits);
+
int mtk_phy_read_page(struct phy_device *phydev)
{
return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
--- a/drivers/net/phy/mediatek/mtk.h
+++ b/drivers/net/phy/mediatek/mtk.h
@@ -72,6 +72,8 @@ void __mtk_tr_modify(struct phy_device *
u8 data_addr, u32 mask, u32 set);
void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
u8 data_addr, u32 mask, u32 set);
+void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
+ u8 data_addr, u32 set);
int mtk_phy_read_page(struct phy_device *phydev);
int mtk_phy_write_page(struct phy_device *phydev, int page);

122
lede/target/linux/generic/backport-6.12/732-v6.15-net-phy-mediatek-Add-token-ring-clear-bit-operation-.patch Normal file
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@@ -0,0 +1,122 @@
From 7851c73a416b15aff6f9ada9c88affc5f48ff011 Mon Sep 17 00:00:00 2001
From: Sky Huang <skylake.huang@mediatek.com>
Date: Thu, 13 Feb 2025 16:05:52 +0800
Subject: [PATCH 13/20] net: phy: mediatek: Add token ring clear bit operation
support
Similar to __mtk_tr_set_bits() support. Previously in mtk-ge-soc.c,
we clear some register bits via token ring, which were also implemented
in three __phy_write(). Now we can do the same thing via
__mtk_tr_clr_bits() helper.
Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20250213080553.921434-5-SkyLake.Huang@mediatek.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/phy/mediatek/mtk-ge-soc.c | 30 +++++++++++++++-----------
drivers/net/phy/mediatek/mtk-phy-lib.c | 7 ++++++
drivers/net/phy/mediatek/mtk.h | 2 ++
3 files changed, 27 insertions(+), 12 deletions(-)
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -76,6 +76,10 @@
/* FfeUpdGainForce */
#define FFE_UPDATE_GAIN_FORCE BIT(6)
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x3 */
+/* TrFreeze */
+#define TR_FREEZE_MASK GENMASK(11, 0)
+
/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */
/* SS: Steady-state, KP: Proportional Gain */
/* SSTrKp100 */
@@ -91,6 +95,11 @@
/* SSTrKf1000Slv */
#define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4)
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x8 */
+/* clear this bit if wanna select from AFE */
+/* Regsigdet_sel_1000 */
+#define EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE BIT(4)
+
/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */
/* RegEEE_st2TrKf1000 */
#define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11)
@@ -113,6 +122,10 @@
/* RegEEE100Stg1_tar */
#define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0)
+/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x25 */
+/* REGEEE_wake_slv_tr_wait_dfesigdet_en */
+#define WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN BIT(11)
+
#define ANALOG_INTERNAL_OPERATION_MAX_US 20
#define TXRESERVE_MIN 0
#define TXRESERVE_MAX 7
@@ -805,10 +818,7 @@ static void mt798x_phy_common_finetune(s
FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) |
FFE_UPDATE_GAIN_FORCE);
- /* TrFreeze = 0 (mt7988 default) */
- __phy_write(phydev, 0x11, 0x0);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x9686);
+ __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x3, TR_FREEZE_MASK);
__mtk_tr_modify(phydev, 0x2, 0xd, 0x6,
SS_TR_KP100_MASK | SS_TR_KF100_MASK |
@@ -1009,10 +1019,8 @@ static void mt798x_phy_eee(struct phy_de
MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
- /* Regsigdet_sel_1000 = 0 */
- __phy_write(phydev, 0x11, 0xb);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x9690);
+ __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x8,
+ EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE);
__mtk_tr_modify(phydev, 0x2, 0xd, 0xd,
EEE1000_STAGE2_TR_KF_MASK,
@@ -1036,10 +1044,8 @@ static void mt798x_phy_eee(struct phy_de
FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
0x10));
- /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
- __phy_write(phydev, 0x11, 0x1463);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x96ca);
+ __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x25,
+ WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN);
__mtk_tr_modify(phydev, 0x1, 0xf, 0x0,
DFE_TAIL_EANBLE_VGA_TRHESH_1000,
--- a/drivers/net/phy/mediatek/mtk-phy-lib.c
+++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
@@ -76,6 +76,13 @@ void __mtk_tr_set_bits(struct phy_device
}
EXPORT_SYMBOL_GPL(__mtk_tr_set_bits);
+void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
+ u8 data_addr, u32 clr)
+{
+ __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, clr, 0);
+}
+EXPORT_SYMBOL_GPL(__mtk_tr_clr_bits);
+
int mtk_phy_read_page(struct phy_device *phydev)
{
return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
--- a/drivers/net/phy/mediatek/mtk.h
+++ b/drivers/net/phy/mediatek/mtk.h
@@ -74,6 +74,8 @@ void mtk_tr_modify(struct phy_device *ph
u8 data_addr, u32 mask, u32 set);
void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
u8 data_addr, u32 set);
+void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
+ u8 data_addr, u32 clr);
int mtk_phy_read_page(struct phy_device *phydev);
int mtk_phy_write_page(struct phy_device *phydev, int page);

45
lede/target/linux/generic/backport-6.12/733-v6.15-net-phy-mediatek-Move-some-macros-to-phy-lib-for-lat.patch Normal file
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@@ -0,0 +1,45 @@
From bae8c61522c4d5a5250a24dcb57d120ea593fab1 Mon Sep 17 00:00:00 2001
From: Sky Huang <skylake.huang@mediatek.com>
Date: Thu, 13 Feb 2025 16:05:53 +0800
Subject: [PATCH 14/20] net: phy: mediatek: Move some macros to phy-lib for
later use
Move some macros to phy-lib because MediaTek's 2.5G built-in
ethernet PHY will also use them.
Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20250213080553.921434-6-SkyLake.Huang@mediatek.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/phy/mediatek/mtk-ge.c | 4 ----
drivers/net/phy/mediatek/mtk.h | 4 ++++
2 files changed, 4 insertions(+), 4 deletions(-)
--- a/drivers/net/phy/mediatek/mtk-ge.c
+++ b/drivers/net/phy/mediatek/mtk-ge.c
@@ -8,10 +8,6 @@
#define MTK_GPHY_ID_MT7530 0x03a29412
#define MTK_GPHY_ID_MT7531 0x03a29441
-#define MTK_PHY_PAGE_EXTENDED_1 0x0001
-#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14
-#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
-
#define MTK_PHY_PAGE_EXTENDED_2 0x0002
#define MTK_PHY_PAGE_EXTENDED_3 0x0003
#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11 0x11
--- a/drivers/net/phy/mediatek/mtk.h
+++ b/drivers/net/phy/mediatek/mtk.h
@@ -8,7 +8,11 @@
#ifndef _MTK_EPHY_H_
#define _MTK_EPHY_H_
+#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14
+#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
+
#define MTK_EXT_PAGE_ACCESS 0x1f
+#define MTK_PHY_PAGE_EXTENDED_1 0x0001
#define MTK_PHY_PAGE_STANDARD 0x0000
#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5

37
lede/target/linux/generic/backport-6.12/735-v6.16-net-phy-mediatek-permit-to-compile-test-GE-SOC-PHY-d.patch Normal file
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@@ -0,0 +1,37 @@
From e5566162af8b9690e096d2e6089e4ed955a0d13d Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 10 Apr 2025 12:04:03 +0200
Subject: [PATCH] net: phy: mediatek: permit to compile test GE SOC PHY driver
When commit 462a3daad679 ("net: phy: mediatek: fix compile-test
dependencies") fixed the dependency, it should have also introduced
an or on COMPILE_TEST to permit this driver to be compile-tested even if
NVMEM_MTK_EFUSE wasn't selected. The driver makes use of NVMEM API that
are always compiled (return error) so the driver can actually be
compiled even without that config.
Fix and simplify the dependency condition of this kernel config.
Fixes: 462a3daad679 ("net: phy: mediatek: fix compile-test dependencies")
Acked-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Link: https://patch.msgid.link/20250410100410.348-1-ansuelsmth@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/phy/mediatek/Kconfig | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
--- a/drivers/net/phy/mediatek/Kconfig
+++ b/drivers/net/phy/mediatek/Kconfig
@@ -15,8 +15,7 @@ config MEDIATEK_GE_PHY
config MEDIATEK_GE_SOC_PHY
tristate "MediaTek SoC Ethernet PHYs"
- depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
- depends on NVMEM_MTK_EFUSE
+ depends on (ARM64 && ARCH_MEDIATEK && NVMEM_MTK_EFUSE) || COMPILE_TEST
select MTK_NET_PHYLIB
help
Supports MediaTek SoC built-in Gigabit Ethernet PHYs.

129
lede/target/linux/generic/backport-6.12/736-v6.16-net-phy-mediatek-add-Airoha-PHY-ID-to-SoC-driver.patch Normal file
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@@ -0,0 +1,129 @@
From 4590c8bc10951feee3e439bf7fff1b458c2e6fad Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 10 Apr 2025 12:04:04 +0200
Subject: [PATCH 17/20] net: phy: mediatek: add Airoha PHY ID to SoC driver
Airoha AN7581 SoC ship with a Switch based on the MT753x Switch embedded
in other SoC like the MT7581 and the MT7988. Similar to these they
require configuring some pin to enable LED PHYs.
Add support for the PHY ID for the Airoha embedded Switch and define a
simple probe function to toggle these pins. Also fill the LED functions
and add dedicated function to define LED polarity.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://patch.msgid.link/20250410100410.348-2-ansuelsmth@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/phy/mediatek/Kconfig | 4 +-
drivers/net/phy/mediatek/mtk-ge-soc.c | 62 +++++++++++++++++++++++++++
2 files changed, 65 insertions(+), 1 deletion(-)
--- a/drivers/net/phy/mediatek/Kconfig
+++ b/drivers/net/phy/mediatek/Kconfig
@@ -15,7 +15,9 @@ config MEDIATEK_GE_PHY
config MEDIATEK_GE_SOC_PHY
tristate "MediaTek SoC Ethernet PHYs"
- depends on (ARM64 && ARCH_MEDIATEK && NVMEM_MTK_EFUSE) || COMPILE_TEST
+ depends on ARM64 || COMPILE_TEST
+ depends on ARCH_AIROHA || (ARCH_MEDIATEK && NVMEM_MTK_EFUSE) || \
+ COMPILE_TEST
select MTK_NET_PHYLIB
help
Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -10,8 +10,11 @@
#include "mtk.h"
+#define MTK_PHY_MAX_LEDS 2
+
#define MTK_GPHY_ID_MT7981 0x03a29461
#define MTK_GPHY_ID_MT7988 0x03a29481
+#define MTK_GPHY_ID_AN7581 0x03a294c1
#define MTK_EXT_PAGE_ACCESS 0x1f
#define MTK_PHY_PAGE_STANDARD 0x0000
@@ -1405,6 +1408,53 @@ static int mt7981_phy_probe(struct phy_d
return mt798x_phy_calibration(phydev);
}
+static int an7581_phy_probe(struct phy_device *phydev)
+{
+ struct mtk_socphy_priv *priv;
+ struct pinctrl *pinctrl;
+
+ /* Toggle pinctrl to enable PHY LED */
+ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
+ if (IS_ERR(pinctrl))
+ dev_err(&phydev->mdio.bus->dev,
+ "Failed to setup PHY LED pinctrl\n");
+
+ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ phydev->priv = priv;
+
+ return 0;
+}
+
+static int an7581_phy_led_polarity_set(struct phy_device *phydev, int index,
+ unsigned long modes)
+{
+ u32 mode;
+ u16 val;
+
+ if (index >= MTK_PHY_MAX_LEDS)
+ return -EINVAL;
+
+ for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
+ switch (mode) {
+ case PHY_LED_ACTIVE_LOW:
+ val = MTK_PHY_LED_ON_POLARITY;
+ break;
+ case PHY_LED_ACTIVE_HIGH:
+ val = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
+ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
+ MTK_PHY_LED_ON_POLARITY, val);
+}
+
static struct phy_driver mtk_socphy_driver[] = {
{
PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
@@ -1440,6 +1490,17 @@ static struct phy_driver mtk_socphy_driv
.led_hw_control_set = mt798x_phy_led_hw_control_set,
.led_hw_control_get = mt798x_phy_led_hw_control_get,
},
+ {
+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581),
+ .name = "Airoha AN7581 PHY",
+ .probe = an7581_phy_probe,
+ .led_blink_set = mt798x_phy_led_blink_set,
+ .led_brightness_set = mt798x_phy_led_brightness_set,
+ .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
+ .led_hw_control_set = mt798x_phy_led_hw_control_set,
+ .led_hw_control_get = mt798x_phy_led_hw_control_get,
+ .led_polarity_set = an7581_phy_led_polarity_set,
+ },
};
module_phy_driver(mtk_socphy_driver);
@@ -1447,6 +1508,7 @@ module_phy_driver(mtk_socphy_driver);
static const struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
+ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581) },
{ }
};

40
lede/target/linux/generic/backport-6.12/737-v6.16-net-phy-mediatek-init-val-in-.phy_led_polarity_set-f.patch Normal file
View File

@@ -0,0 +1,40 @@
From 34501d047ac0a6cbb13285ba9d15f75c1deb7da7 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Tue, 15 Apr 2025 12:53:05 +0200
Subject: [PATCH 18/20] net: phy: mediatek: init val in .phy_led_polarity_set
for AN7581
Fix smatch warning for uninitialised val in .phy_led_polarity_set for
AN7581 driver.
Correctly init to 0 to set polarity high by default.
Reported-by: Simon Horman <horms@kernel.org>
Fixes: 6a325aed130b ("net: phy: mediatek: add Airoha PHY ID to SoC driver")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://patch.msgid.link/20250415105313.3409-1-ansuelsmth@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/phy/mediatek/mtk-ge-soc.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
@@ -1431,8 +1431,8 @@ static int an7581_phy_probe(struct phy_d
static int an7581_phy_led_polarity_set(struct phy_device *phydev, int index,
unsigned long modes)
{
+ u16 val = 0;
u32 mode;
- u16 val;
if (index >= MTK_PHY_MAX_LEDS)
return -EINVAL;
@@ -1443,7 +1443,6 @@ static int an7581_phy_led_polarity_set(s
val = MTK_PHY_LED_ON_POLARITY;
break;
case PHY_LED_ACTIVE_HIGH:
- val = 0;
break;
default:
return -EINVAL;

4
lede/target/linux/generic/backport-6.12/753-v6.15-net-ethernet-mediatek-add-EEE-support.patch
View File

@@ -43,7 +43,7 @@ Signed-off-by: Qingfang Deng <dqfext@gmail.com>
return phylink_ethtool_set_pauseparam(mac->phylink, pause);
}
+static int mtk_get_eee(struct net_device *dev, struct ethtool_eee *eee)
+static int mtk_get_eee(struct net_device *dev, struct ethtool_keee *eee)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ u32 reg;
@@ -60,7 +60,7 @@ Signed-off-by: Qingfang Deng <dqfext@gmail.com>
+ return 0;
+}
+
+static int mtk_set_eee(struct net_device *dev, struct ethtool_eee *eee)
+static int mtk_set_eee(struct net_device *dev, struct ethtool_keee *eee)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ u32 txidle_thd_ms, reg;

4
lede/target/linux/generic/backport-6.12/781-10-v6.14-net-phy-move-realtek-PHY-driver-to-its-own-subdirect.patch
View File

@@ -24,7 +24,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -358,10 +358,7 @@ config QSEMI_PHY
@@ -343,10 +343,7 @@ config QSEMI_PHY
help
Currently supports the qs6612
@@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
tristate "Renesas PHYs"
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -95,7 +95,7 @@ obj-$(CONFIG_NXP_CBTX_PHY) += nxp-cbtx.o
@@ -94,7 +94,7 @@ obj-$(CONFIG_NXP_CBTX_PHY) += nxp-cbtx.o
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
obj-y += qcom/
obj-$(CONFIG_QSEMI_PHY) += qsemi.o

16
lede/target/linux/generic/files/drivers/net/phy/rtl8261n/phy_rtl826xb_patch.c
View File

@@ -66,7 +66,7 @@ static uint16 _phy_rtl826xb_mmd_convert(uint16 page, uint16 addr)
return reg;
}
int32
static int32
_phy_rtl826xb_patch_wait(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 data, uint32 mask, uint8 patch_mode)
{
int32 ret = 0;
@@ -211,7 +211,7 @@ _phy_rtl826xb_patch_wait(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mm
return RT_ERR_OK;
}
int32
static int32
_phy_rtl826xb_patch_wait_not_equal(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 data, uint32 mask, uint8 patch_mode)
{
int32 ret = 0;
@@ -355,7 +355,7 @@ _phy_rtl826xb_patch_wait_not_equal(uint32 unit, rtk_port_t port, uint32 mmdAddr,
return RT_ERR_OK;
}
int32
static int32
_phy_rtl826xb_patch_top_get(uint32 unit, rtk_port_t port, uint32 topPage, uint32 topReg, uint32 *pData)
{
int32 ret = 0;
@@ -368,7 +368,7 @@ _phy_rtl826xb_patch_top_get(uint32 unit, rtk_port_t port, uint32 topPage, uint32
return RT_ERR_OK;
}
int32
static int32
_phy_rtl826xb_patch_top_set(uint32 unit, rtk_port_t port, uint32 topPage, uint32 topReg, uint32 wData)
{
int32 ret = 0;
@@ -378,7 +378,7 @@ _phy_rtl826xb_patch_top_set(uint32 unit, rtk_port_t port, uint32 topPage, uint32
return RT_ERR_OK;
}
int32
static int32
_phy_rtl826xb_patch_sds_get(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32 sdsReg, uint32 *pData)
{
int32 ret = 0;
@@ -393,7 +393,7 @@ _phy_rtl826xb_patch_sds_get(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32
return _phy_rtl826xb_patch_wait(unit, port, PHY_MMD_VEND1, 0x143, 0, BIT_15, PHY_PATCH_MODE_NORMAL);
}
int32
static int32
_phy_rtl826xb_patch_sds_set(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32 sdsReg, uint32 wData, uint8 patch_mode)
{
int32 ret = 0;
@@ -693,7 +693,7 @@ static int32 _phy_rtl826xb_flow_s(uint32 unit, rtk_port_t port, uint8 portOffset
return RT_ERR_OK;
}
int32 phy_rtl826xb_patch_op(uint32 unit, rtk_port_t port, uint8 portOffset, rtk_hwpatch_t *pPatch_data, uint8 patch_mode)
static int32 phy_rtl826xb_patch_op(uint32 unit, rtk_port_t port, uint8 portOffset, rtk_hwpatch_t *pPatch_data, uint8 patch_mode)
{
int32 ret = RT_ERR_OK;
uint32 rData = 0, wData = 0;
@@ -803,7 +803,7 @@ int32 phy_rtl826xb_patch_op(uint32 unit, rtk_port_t port, uint8 portOffset, rtk_
return ret;
}
int32 phy_rtl826xb_patch_flow(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_flow, uint8 patch_mode)
static int32 phy_rtl826xb_patch_flow(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_flow, uint8 patch_mode)
{
int32 ret = RT_ERR_OK;

1
lede/target/linux/generic/files/drivers/net/phy/rtl8261n/rtk_osal.c
View File

@@ -7,6 +7,7 @@
#include "type.h"
#include "error.h"
#include "rtk_phylib_def.h"
#include "rtk_osal.h"
#include <linux/version.h>
#include <linux/jiffies.h>

2
lede/target/linux/generic/hack-6.12/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
View File

@@ -52,7 +52,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
};
module_phy_driver(aqr_driver);
@@ -1226,6 +1252,8 @@ static struct mdio_device_id __maybe_unu
@@ -1226,6 +1252,8 @@ static const struct mdio_device_id __may
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },

4
lede/target/linux/generic/hack-6.12/735-net-phy-realtek-rtl8261n.patch
View File

@@ -1,6 +1,6 @@
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -434,6 +434,8 @@ config QSEMI_PHY
@@ -419,6 +419,8 @@ config QSEMI_PHY
source "drivers/net/phy/realtek/Kconfig"
@@ -11,7 +11,7 @@
help
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -111,6 +111,7 @@ obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja
@@ -110,6 +110,7 @@ obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja
obj-y += qcom/
obj-$(CONFIG_QSEMI_PHY) += qsemi.o
obj-$(CONFIG_REALTEK_PHY) += realtek/

14
lede/target/linux/generic/hack-6.12/766-net-phy-mediatek-ge-add-LED-configuration-interface.patch
View File

@@ -12,18 +12,18 @@ plans on integrating their own framework for handling these LEDs.
Signed-off-by: David Bauer <mail@david-bauer.net>
---
drivers/net/phy/mediatek-ge.c | 33 +++++++++++++++++++++++++++++++++
drivers/net/phy/mediatek/mtk-ge.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
--- a/drivers/net/phy/mediatek-ge.c
+++ b/drivers/net/phy/mediatek-ge.c
--- a/drivers/net/phy/mediatek/mtk-ge.c
+++ b/drivers/net/phy/mediatek/mtk-ge.c
@@ -1,4 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
+#include <linux/of.h>
#include <linux/bitfield.h>
#include <linux/module.h>
#include <linux/phy.h>
@@ -50,6 +51,36 @@ static int mt7530_phy_config_init(struct
@@ -73,6 +74,36 @@ static int mt7530_phy_config_init(struct
return 0;
}
@@ -60,9 +60,9 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
static int mt7531_phy_config_init(struct phy_device *phydev)
{
mtk_gephy_config_init(phydev);
@@ -62,6 +93,9 @@ static int mt7531_phy_config_init(struct
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
@@ -93,6 +124,9 @@ static int mt7531_phy_config_init(struct
FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
+ /* LED Config*/
+ mt7530_led_config_of(phydev);

2
lede/target/linux/generic/pending-6.12/510-block-add-uImage.FIT-subimage-block-driver.patch
View File

@@ -36,7 +36,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -23666,6 +23666,12 @@ F: Documentation/filesystems/ubifs-authe
@@ -23668,6 +23668,12 @@ F: Documentation/filesystems/ubifs-authe
F: Documentation/filesystems/ubifs.rst
F: fs/ubifs/

2
lede/target/linux/mediatek/Makefile
View File

@@ -9,7 +9,7 @@ SUBTARGETS:=filogic mt7622 mt7623 mt7629
FEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb
KERNEL_PATCHVER:=6.6
KERNEL_TESTING_PATCHVER:=6.1
KERNEL_TESTING_PATCHVER:=6.12
include $(INCLUDE_DIR)/target.mk
DEFAULT_PACKAGES += \

20
lede/target/linux/mediatek/dts/mt7981b-cudy-tr3000-v2-mod.dts Normal file
View File

@@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "mt7981b-cudy-tr3000-v1.dts"
/ {
model = "Cudy TR3000 v2 (U-Boot mod)";
compatible = "cudy,tr3000-v2-mod", "mediatek,mt7981";
};
&spi0 {
flash@0 {
partitions {
partition@5c0000 {
label = "ubi";
reg = <0x5c0000 0xe280000>;
};
};
};
};

276
lede/target/linux/mediatek/dts/mt7981b-huasifei-ws3006.dts Normal file
View File

@@ -0,0 +1,276 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "mt7981.dtsi"
/ {
model = "HUASIFEI WS3006";
compatible = "huasifei,ws3006", "mediatek,mt7981";
aliases {
label-mac-device = &gmac0;
led-boot = &status_led;
led-failsafe = &status_led;
led-running = &status_led;
led-upgrade = &status_led;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
status_led: led-0 {
label = "green:status";
gpios = <&pio 0 GPIO_ACTIVE_LOW>;
};
led-1 {
label = "green:sim1";
gpios = <&pio 6 GPIO_ACTIVE_LOW>;
};
led-2 {
label = "green:sim2";
gpios = <&pio 7 GPIO_ACTIVE_LOW>;
};
led-3 {
label = "green:gbe";
gpios = <&pio 8 GPIO_ACTIVE_LOW>;
};
led-4 {
label = "green:5g";
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
led-5 {
label = "green:wlan";
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
led-6 {
label = "green:4g";
gpios = <&pio 11 GPIO_ACTIVE_LOW>;
};
};
};
&uart0 {
status = "okay";
};
&watchdog {
status = "okay";
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "2500base-x";
phy-handle = <&phy0>;
label = "lan3";
};
};
&mdio_bus {
switch: switch@1f {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
};
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id03a2.9461";
reg = <0>;
phy-mode = "gmii";
nvmem-cells = <&phy_calibration>;
nvmem-cell-names = "phy-cal-data";
};
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <6>;
reset-assert-us = <100000>;
reset-deassert-us = <100000>;
reset-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_flash_pins>;
status = "okay";
spi_nand: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
spi-cal-enable;
spi-cal-mode = "read-data";
spi-cal-datalen = <7>;
spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
spi-cal-addrlen = <5>;
spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
mediatek,nmbm;
mediatek,bmt-max-ratio = <1>;
mediatek,bmt-max-reserved-blocks = <64>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "BL2";
reg = <0x0 0x100000>; /* 1 MiB */
read-only;
};
partition@100000 {
label = "u-boot-env";
reg = <0x100000 0x80000>; /* 0.5 MiB */
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x200000>; /* 2 MiB */
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
eeprom_factory_0: eeprom@0 {
reg = <0x0 0x1000>;
};
};
};
partition@380000 {
label = "FIP";
reg = <0x380000 0x200000>; /* 2 MiB */
};
partition@580000 {
label = "ubi";
reg = <0x580000 0x6e00000>; /* 110 MiB */
};
partition@7380000 {
label = "config";
reg = <0x7380000 0x80000>; /* 0.5 MiB */
};
/* Leave last 12 MiB for NMBM badblock table */
};
};
};
&pio {
spi0_flash_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
};
conf-pd {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
};
};
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "2500base-x";
phy-handle = <&phy1>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&wifi {
status = "okay";
nvmem-cells = <&eeprom_factory_0>;
nvmem-cell-names = "eeprom";
};

34
lede/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-eth1.dtso Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
fragment@0 {
target = <&gmac1>;
__overlay__ {
phy-mode = "2500base-x";
phy-handle = <&phy5>;
};
};
fragment@1 {
target = <&mdio_bus>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
reset-delay-us = <600>;
reset-post-delay-us = <20000>;
phy5: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x";
};
};
};
};

35
lede/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-mxl-2p5g-phy-swp5.dtso Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
fragment@0 {
target = <&sw_p5>;
__overlay__ {
phy-mode = "2500base-x";
phy-handle = <&phy5>;
status = "okay";
};
};
fragment@1 {
target = <&mdio_bus>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
reset-delay-us = <600>;
reset-post-delay-us = <20000>;
phy5: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x";
};
};
};
};

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lede/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7981-rfb-spim-nand.dtso Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/dts-v1/;
/plugin/;
/ {
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
fragment@0 {
target = <&chosen>;
rootdisk-spim-nand = <&ubi_rootdisk>;
};
fragment@1 {
target = <&spi0>;
__overlay__ {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
spi_nand: spi_nand@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <10000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "BL2";
reg = <0x00000 0x0100000>;
read-only;
};
partition@100000 {
label = "u-boot-env";
reg = <0x0100000 0x0080000>;
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x0200000>;
};
partition@380000 {
label = "FIP";
reg = <0x380000 0x0200000>;
};
partition@580000 {
label = "ubi";
reg = <0x580000 0x4000000>;
compatible = "linux,ubi";
volumes {
ubi_rootdisk: ubi-volume-fit {
volname = "fit";
};
};
};
};
};
};
};
fragment@2 {
target = <&wifi>;
__overlay__ {
mediatek,mtd-eeprom = <&factory 0x0>;
status = "okay";
};
};
};

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7981b.dtsi"
/ {
model = "MediaTek MT7981 RFB";
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
aliases {
serial0 = &uart0;
};
chosen: chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/fit0 rootwait";
};
memory {
reg = <0 0x40000000 0 0x20000000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
gpio-keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
};
};
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "gmii";
phy-handle = <&int_gbe_phy>;
};
};
&mdio_bus {
switch: switch@1f {
compatible = "mediatek,mt7531";
reg = <31>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
};
};
&crypto {
status = "okay";
};
&pio {
spi0_flash_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
};
conf-pd {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_flash_pins>;
cs-gpios = <0>, <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
sw_p5: port@5 {
reg = <5>;
label = "lan5";
status = "disabled";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&xhci {
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&reg_5v>;
status = "okay";
};
&uart0 {
status = "okay";
};
&usb_phy {
status = "okay";
};
&watchdog {
status = "okay";
};

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mt7981b.dtsi

498
lede/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "mt7986a.dtsi"
/ {
model = "Bananapi BPI-R3 Mini";
chassis-type = "embedded";
compatible = "bananapi,bpi-r3-mini", "mediatek,mt7986a";
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
led-boot = &led_sys;
led-failsafe = &led_sys;
led-running = &led_sys;
led-upgrade = &led_sys;
};
chosen {
stdout-path = "serial0:115200n8";
};
keys {
compatible = "gpio-keys";
key-reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 7 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led_sys: led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
fan: pwm-fan {
compatible = "pwm-fan";
/* cooling level (0, 1, 2, 3) - pwm inverted */
cooling-levels = <255 128 64 0>;
pwms = <&pwm 0 10000>;
#cooling-cells = <2>;
};
dcin: regulator-12vd {
compatible = "regulator-fixed";
regulator-name = "12vd";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1.8vd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
vin-supply = <&dcin>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3.3vd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
vin-supply = <&dcin>;
};
reg_5v_vbus: regulator-5v-vbus {
compatible = "regulator-fixed";
regulator-name = "5v_vbus1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
vin-supply = <&dcin>;
};
reg_phya: regulator-phya {
compatible = "regulator-fixed";
gpio = <&pio 16 GPIO_ACTIVE_LOW>;
regulator-name = "reg_phya";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_phyb: regulator-phyb {
compatible = "regulator-fixed";
gpio = <&pio 17 GPIO_ACTIVE_LOW>;
regulator-name = "reg_phyb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_keyb: regulator-vcc-keyb {
compatible = "regulator-fixed";
gpio = <&pio 20 GPIO_ACTIVE_LOW>;
regulator-name = "vcc_keyb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&reg_3p3v>;
};
gpio-export {
compatible = "gpio-export";
lte-gnss {
gpio-export,name = "lte_gnss";
gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
};
lte-perst {
gpio-export,name = "lte_perst";
gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
};
lte-wwan {
gpio-export,name = "lte_wwan";
gpios = <&pio 13 GPIO_ACTIVE_HIGH>;
};
lte-power {
gpio-export,name = "lte_power";
gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
};
lte-reset {
gpio-export,name = "lte_reset";
gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
};
lte-coex {
gpio-export,name = "lte_coex";
gpios = <&pio 32 GPIO_ACTIVE_HIGH>;
};
};
};
&cpu_thermal {
cooling-maps {
map-cpu-active-high {
/* active: set fan to cooling level 3 */
cooling-device = <&fan 3 3>;
trip = <&cpu_trip_active_high>;
};
map-cpu-active-med {
/* active: set fan to cooling level 2 */
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_active_med>;
};
map-cpu-active-low {
/* active: set fan to cooling level 1 */
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_low>;
};
};
};
&crypto {
status = "okay";
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
phy-handle = <&phy14>;
phy-supply = <&reg_phya>;
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "2500base-x";
phy-handle = <&phy15>;
phy-supply = <&reg_phyb>;
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
&mdio {
phy14: phy@14 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <14>;
reset-assert-us = <10000>;
reset-deassert-us = <20000>;
reset-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
interrupt-parent = <&pio>;
interrupts = <48 IRQ_TYPE_EDGE_FALLING>;
airoha,pnswap-rx;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_AMBER>;
default-state = "keep";
};
led@1 {
reg = <1>;
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_GREEN>;
default-state = "keep";
};
};
};
phy15: phy@15 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <15>;
reset-assert-us = <10000>;
reset-deassert-us = <20000>;
reset-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
interrupt-parent = <&pio>;
interrupts = <46 IRQ_TYPE_EDGE_FALLING>;
airoha,pnswap-rx;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_AMBER>;
default-state = "keep";
};
led@1 {
reg = <1>;
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_GREEN>;
default-state = "keep";
};
};
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <8>;
size = <256>;
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
status = "okay";
};
&mmc0 {
bus-width = <8>;
cap-mmc-highspeed;
hs400-ds-delay = <0x14014>;
max-frequency = <200000000>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
non-removable;
no-sd;
no-sdio;
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pio {
i2c0_pins: i2c0-pins {
mux {
function = "i2c";
groups = "i2c";
};
};
mdio_pins: mdio-pins {
mux {
function = "eth";
groups = "mdc_mdio";
};
};
spi_flash_pins: spi-flash-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
drive-strength = <8>;
mediatek,pull-up-adv = <0>; /* bias-disable */
};
conf-pd {
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
drive-strength = <8>;
mediatek,pull-down-adv = <0>; /* bias-disable */
};
};
mmc0_pins_default: mmc0-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
mmc0_pins_uhs: mmc0-uhs-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
pcie_pins: pcie-pins {
mux {
function = "pcie";
groups = "pcie_clk", "pcie_wake", "pcie_pereset";
};
};
pwm_pins: pwm-pins {
mux {
function = "pwm";
groups = "pwm0", "pwm1_0";
};
};
uart1_pins: uart1-pins {
mux {
function = "uart";
groups = "uart1";
};
};
wf_led_pins: wf-led-pins {
mux {
function = "led";
groups = "wifi_led";
};
};
wf_dbdc_pins: wf-dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins>;
status = "okay";
};
&ssusb {
vusb33-supply = <&vcc_keyb>;
vbus-supply = <&reg_5v_vbus>;
status = "okay";
};
&trng {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&usb_phy {
status = "okay";
};
&watchdog {
status = "okay";
};
&wifi {
pinctrl-names = "dbdc";
pinctrl-0 = <&wf_dbdc_pins>, <&wf_led_pins>;
status = "okay";
};

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lede/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3mini-emmc.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "mt7986a-bananapi-bpi-r3-mini.dts"
/ {
model = "Bananapi BPI-R3 Mini (eMMC)";
chosen {
bootargs = "console=ttyS0,115200n8 root=PARTLABEL=rootfs rootwait";
};
};

52
lede/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3mini-nand.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "mt7986a-bananapi-bpi-r3-mini.dts"
/ {
model = "Bananapi BPI-R3 Mini (NAND)";
};
&spi0 {
flash@0 {
compatible = "spi-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <52000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bl2";
reg = <0x0000000 0x0100000>;
};
partition@100000 {
label = "u-boot-env";
reg = <0x0100000 0x0080000>;
};
partition@180000 {
label = "factory";
reg = <0x0180000 0x0200000>;
};
partition@380000 {
label = "fip";
reg = <0x0380000 0x0200000>;
};
partition@580000 {
label = "ubi";
reg = <0x0580000 0x7a80000>;
};
};
};
};

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lede/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
#include "mt7986a-rfb.dtsi"
/ {
compatible = "mediatek,mt7986a-rfb-snand";
};
&spi0 {
status = "okay";
spi_nand: spi_nand@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <10000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "BL2";
reg = <0x00000 0x0100000>;
read-only;
};
partition@100000 {
label = "u-boot-env";
reg = <0x0100000 0x0080000>;
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x0200000>;
};
partition@380000 {
label = "FIP";
reg = <0x380000 0x0200000>;
};
partition@580000 {
label = "ubi";
reg = <0x580000 0x4000000>;
};
};
};
};
&wifi {
mediatek,mtd-eeprom = <&factory 0>;
};

51
lede/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
#include "mt7986a-rfb.dtsi"
/ {
compatible = "mediatek,mt7986a-rfb-snor";
};
&spi0 {
status = "okay";
spi_nor: spi_nor@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@00000 {
label = "BL2";
reg = <0x00000 0x0040000>;
};
partition@40000 {
label = "u-boot-env";
reg = <0x40000 0x0010000>;
};
factory: partition@50000 {
label = "Factory";
reg = <0x50000 0x00B0000>;
};
partition@100000 {
label = "FIP";
reg = <0x100000 0x0080000>;
};
partition@180000 {
label = "firmware";
reg = <0x180000 0xE00000>;
};
};
};
};
&wifi {
mediatek,mtd-eeprom = <&factory 0>;
};

389
lede/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
/dts-v1/;
#include "mt7986a.dtsi"
/ {
model = "MediaTek MT7986a RFB";
compatible = "mediatek,mt7986a-rfb";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
reg = <0 0x40000000 0 0x40000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "2500base-x";
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
};
&mdio {
phy5: phy@5 {
compatible = "ethernet-phy-id67c9.de0a";
reg = <5>;
reset-gpios = <&pio 6 1>;
reset-deassert-us = <20000>;
};
phy6: phy@6 {
compatible = "ethernet-phy-id67c9.de0a";
reg = <6>;
};
switch: switch@1f {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 5 0>;
};
};
&crypto {
status = "okay";
};
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x14014>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pio {
mmc0_pins_default: mmc0-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
mmc0_pins_uhs: mmc0-uhs-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
pcie_pins: pcie-pins {
mux {
function = "pcie";
groups = "pcie_clk", "pcie_wake", "pcie_pereset";
};
};
spic_pins_g2: spic-pins-29-to-32 {
mux {
function = "spi";
groups = "spi1_2";
};
};
spi_flash_pins: spi-flash-pins-33-to-38 {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
drive-strength = <8>;
mediatek,pull-up-adv = <0>; /* bias-disable */
};
conf-pd {
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
drive-strength = <8>;
mediatek,pull-down-adv = <0>; /* bias-disable */
};
};
uart1_pins: uart1-pins {
mux {
function = "uart";
groups = "uart1";
};
};
uart2_pins: uart2-pins {
mux {
function = "uart";
groups = "uart2";
};
};
wf_2g_5g_pins: wf_2g_5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_dbdc_pins: wf_dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi_flash_pins>;
cs-gpios = <0>, <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic_pins_g2>;
status = "okay";
proslic_spi: proslic_spi@0 {
compatible = "silabs,proslic_spi";
reg = <0>;
spi-max-frequency = <10000000>;
spi-cpha = <1>;
spi-cpol = <1>;
channel_count = <1>;
debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
reset_gpio = <&pio 7 0>;
ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
};
};
&gmac1 {
phy-mode = "2500base-x";
phy-connection-type = "2500base-x";
phy-handle = <&phy6>;
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@5 {
reg = <5>;
label = "lan6";
phy-mode = "2500base-x";
phy-handle = <&phy5>;
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&ssusb {
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&reg_5v>;
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&usb_phy {
status = "okay";
};

25
lede/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-poe.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 MediaTek Inc.
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
#include "mt7988a-bananapi-bpi-r4.dtsi"
/ {
model = "Bananapi BPI-R4 2.5GE PoE";
compatible = "bananapi,bpi-r4-poe",
"mediatek,mt7988a";
};
&gmac1 {
phy-mode = "internal";
phy-connection-type = "internal";
phy = <&int_2p5g_phy>;
status = "okay";
};
&int_2p5g_phy {
pinctrl-names = "i2p5gbe-led";
pinctrl-0 = <&i2p5gbe_led0_pins>;
};

99
lede/target/linux/mediatek/files-6.12/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-wifi-mt7996a.dtso Normal file
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@@ -0,0 +1,99 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
fragment@0 {
target-path = "/";
__overlay__ {
wifi_12v: regulator-wifi-12v {
compatible = "regulator-fixed";
regulator-name = "wifi";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpios = <&pio 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
};
};
fragment@1 {
target = <&i2c_wifi>;
__overlay__ {
// 5G WIFI MAC Address EEPROM
wifi_eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
address-bits = <8>;
page-size = <8>;
size = <256>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_5g: macaddr@0 {
reg = <0x0 0x6>;
};
};
};
// 6G WIFI MAC Address EEPROM
wifi_eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
address-bits = <8>;
page-size = <8>;
size = <256>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_6g: macaddr@0 {
reg = <0x0 0x6>;
};
};
};
};
};
fragment@2 {
target = <&pcie0>;
__overlay__ {
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_5g>;
};
};
};
};
fragment@3 {
target = <&pcie1>;
__overlay__ {
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_6g>;
};
};
};
};
};

278
lede/target/linux/mediatek/files-6.12/drivers/mfd/airoha-an8855.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* MFD driver for Airoha AN8855 Switch
*/
#include <linux/mfd/airoha-an8855-mfd.h>
#include <linux/mfd/core.h>
#include <linux/mdio.h>
#include <linux/module.h>
#include <linux/phy.h>
#include <linux/regmap.h>
static const struct mfd_cell an8855_mfd_devs[] = {
{
.name = "an8855-efuse",
.of_compatible = "airoha,an8855-efuse",
}, {
.name = "an8855-switch",
.of_compatible = "airoha,an8855-switch",
}, {
.name = "an8855-mdio",
.of_compatible = "airoha,an8855-mdio",
}
};
int an8855_mii_set_page(struct an8855_mfd_priv *priv, u8 phy_id,
u8 page) __must_hold(&priv->bus->mdio_lock)
{
struct mii_bus *bus = priv->bus;
int ret;
ret = __mdiobus_write(bus, phy_id, AN8855_PHY_SELECT_PAGE, page);
if (ret < 0)
dev_err_ratelimited(&bus->dev,
"failed to set an8855 mii page\n");
/* Cache current page if next mii read/write is for switch */
priv->current_page = page;
return ret < 0 ? ret : 0;
}
EXPORT_SYMBOL_GPL(an8855_mii_set_page);
static int an8855_mii_read32(struct mii_bus *bus, u8 phy_id, u32 reg,
u32 *val) __must_hold(&bus->mdio_lock)
{
int lo, hi, ret;
ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,
AN8855_PBUS_MODE_ADDR_FIXED);
if (ret < 0)
goto err;
ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_HIGH,
upper_16_bits(reg));
if (ret < 0)
goto err;
ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_LOW,
lower_16_bits(reg));
if (ret < 0)
goto err;
hi = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_HIGH);
if (hi < 0) {
ret = hi;
goto err;
}
lo = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_LOW);
if (lo < 0) {
ret = lo;
goto err;
}
*val = ((u16)hi << 16) | ((u16)lo & 0xffff);
return 0;
err:
dev_err_ratelimited(&bus->dev,
"failed to read an8855 register\n");
return ret;
}
static int an8855_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
{
struct an8855_mfd_priv *priv = ctx;
struct mii_bus *bus = priv->bus;
u16 addr = priv->switch_addr;
int ret;
mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
if (ret < 0)
goto exit;
ret = an8855_mii_read32(bus, addr, reg, val);
exit:
mutex_unlock(&bus->mdio_lock);
return ret < 0 ? ret : 0;
}
static int an8855_mii_write32(struct mii_bus *bus, u8 phy_id, u32 reg,
u32 val) __must_hold(&bus->mdio_lock)
{
int ret;
ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,
AN8855_PBUS_MODE_ADDR_FIXED);
if (ret < 0)
goto err;
ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_HIGH,
upper_16_bits(reg));
if (ret < 0)
goto err;
ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_LOW,
lower_16_bits(reg));
if (ret < 0)
goto err;
ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_HIGH,
upper_16_bits(val));
if (ret < 0)
goto err;
ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_LOW,
lower_16_bits(val));
if (ret < 0)
goto err;
return 0;
err:
dev_err_ratelimited(&bus->dev,
"failed to write an8855 register\n");
return ret;
}
static int
an8855_regmap_write(void *ctx, uint32_t reg, uint32_t val)
{
struct an8855_mfd_priv *priv = ctx;
struct mii_bus *bus = priv->bus;
u16 addr = priv->switch_addr;
int ret;
mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
if (ret < 0)
goto exit;
ret = an8855_mii_write32(bus, addr, reg, val);
exit:
mutex_unlock(&bus->mdio_lock);
return ret < 0 ? ret : 0;
}
static int an8855_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask,
uint32_t write_val)
{
struct an8855_mfd_priv *priv = ctx;
struct mii_bus *bus = priv->bus;
u16 addr = priv->switch_addr;
u32 val;
int ret;
mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
if (ret < 0)
goto exit;
ret = an8855_mii_read32(bus, addr, reg, &val);
if (ret < 0)
goto exit;
val &= ~mask;
val |= write_val;
ret = an8855_mii_write32(bus, addr, reg, val);
exit:
mutex_unlock(&bus->mdio_lock);
return ret < 0 ? ret : 0;
}
static const struct regmap_range an8855_readable_ranges[] = {
regmap_reg_range(0x10000000, 0x10000fff), /* SCU */
regmap_reg_range(0x10001000, 0x10001fff), /* RBUS */
regmap_reg_range(0x10002000, 0x10002fff), /* MCU */
regmap_reg_range(0x10005000, 0x10005fff), /* SYS SCU */
regmap_reg_range(0x10007000, 0x10007fff), /* I2C Slave */
regmap_reg_range(0x10008000, 0x10008fff), /* I2C Master */
regmap_reg_range(0x10009000, 0x10009fff), /* PDMA */
regmap_reg_range(0x1000a100, 0x1000a2ff), /* General Purpose Timer */
regmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */
regmap_reg_range(0x1000a300, 0x1000a3ff), /* GPIO */
regmap_reg_range(0x1000a400, 0x1000a5ff), /* EFUSE */
regmap_reg_range(0x1000c000, 0x1000cfff), /* GDMP CSR */
regmap_reg_range(0x10010000, 0x1001ffff), /* GDMP SRAM */
regmap_reg_range(0x10200000, 0x10203fff), /* Switch - ARL Global */
regmap_reg_range(0x10204000, 0x10207fff), /* Switch - BMU */
regmap_reg_range(0x10208000, 0x1020bfff), /* Switch - ARL Port */
regmap_reg_range(0x1020c000, 0x1020cfff), /* Switch - SCH */
regmap_reg_range(0x10210000, 0x10213fff), /* Switch - MAC */
regmap_reg_range(0x10214000, 0x10217fff), /* Switch - MIB */
regmap_reg_range(0x10218000, 0x1021bfff), /* Switch - Port Control */
regmap_reg_range(0x1021c000, 0x1021ffff), /* Switch - TOP */
regmap_reg_range(0x10220000, 0x1022ffff), /* SerDes */
regmap_reg_range(0x10286000, 0x10286fff), /* RG Batcher */
regmap_reg_range(0x1028c000, 0x1028ffff), /* ETHER_SYS */
regmap_reg_range(0x30000000, 0x37ffffff), /* I2C EEPROM */
regmap_reg_range(0x38000000, 0x3fffffff), /* BOOT_ROM */
regmap_reg_range(0xa0000000, 0xbfffffff), /* GPHY */
};
static const struct regmap_access_table an8855_readable_table = {
.yes_ranges = an8855_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(an8855_readable_ranges),
};
static const struct regmap_config an8855_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = 0xbfffffff,
.reg_read = an8855_regmap_read,
.reg_write = an8855_regmap_write,
.reg_update_bits = an8855_regmap_update_bits,
.disable_locking = true,
.rd_table = &an8855_readable_table,
};
static int an8855_mfd_probe(struct mdio_device *mdiodev)
{
struct an8855_mfd_priv *priv;
struct regmap *regmap;
priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->bus = mdiodev->bus;
priv->dev = &mdiodev->dev;
priv->switch_addr = mdiodev->addr;
/* no DMA for mdiobus, mute warning for DMA mask not set */
priv->dev->dma_mask = &priv->dev->coherent_dma_mask;
regmap = devm_regmap_init(priv->dev, NULL, priv,
&an8855_regmap_config);
if (IS_ERR(regmap))
dev_err_probe(priv->dev, PTR_ERR(priv->dev),
"regmap initialization failed\n");
dev_set_drvdata(&mdiodev->dev, priv);
return devm_mfd_add_devices(priv->dev, PLATFORM_DEVID_AUTO, an8855_mfd_devs,
ARRAY_SIZE(an8855_mfd_devs), NULL, 0,
NULL);
}
static const struct of_device_id an8855_mfd_of_match[] = {
{ .compatible = "airoha,an8855-mfd" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, an8855_mfd_of_match);
static struct mdio_driver an8855_mfd_driver = {
.probe = an8855_mfd_probe,
.mdiodrv.driver = {
.name = "an8855",
.of_match_table = an8855_mfd_of_match,
},
};
mdio_module_driver(an8855_mfd_driver);
MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
MODULE_DESCRIPTION("Driver for Airoha AN8855 MFD");
MODULE_LICENSE("GPL");

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2023 Min Yao <min.yao@airoha.com>
* Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
*/
#ifndef __AN8855_H
#define __AN8855_H
#include <linux/bitfield.h>
#define AN8855_NUM_PORTS 6
#define AN8855_CPU_PORT 5
#define AN8855_NUM_FDB_RECORDS 2048
#define AN8855_GPHY_SMI_ADDR_DEFAULT 1
#define AN8855_PORT_VID_DEFAULT 0
#define MTK_TAG_LEN 4
#define AN8855_MAX_MTU (15360 - ETH_HLEN - ETH_FCS_LEN - MTK_TAG_LEN)
#define AN8855_L2_AGING_MS_CONSTANT 1024
#define AN8855_PHY_FLAGS_EN_CALIBRATION BIT(0)
/* AN8855_SCU 0x10000000 */
#define AN8855_RG_GPIO_LED_MODE 0x10000054
#define AN8855_RG_GPIO_LED_SEL(i) (0x10000000 + (0x0058 + ((i) * 4)))
#define AN8855_RG_INTB_MODE 0x10000080
#define AN8855_RG_RGMII_TXCK_C 0x100001d0
#define AN8855_PKG_SEL 0x10000094
#define AN8855_PAG_SEL_AN8855H 0x2
/* Register for hw trap status */
#define AN8855_HWTRAP 0x1000009c
#define AN8855_RG_GPIO_L_INV 0x10000010
#define AN8855_RG_GPIO_CTRL 0x1000a300
#define AN8855_RG_GPIO_DATA 0x1000a304
#define AN8855_RG_GPIO_OE 0x1000a314
#define AN8855_CREV 0x10005000
#define AN8855_ID 0x8855
/* Register for system reset */
#define AN8855_RST_CTRL 0x100050c0
#define AN8855_SYS_CTRL_SYS_RST BIT(31)
#define AN8855_INT_MASK 0x100050f0
#define AN8855_INT_SYS BIT(15)
#define AN8855_RG_CLK_CPU_ICG 0x10005034
#define AN8855_MCU_ENABLE BIT(3)
#define AN8855_RG_TIMER_CTL 0x1000a100
#define AN8855_WDOG_ENABLE BIT(25)
#define AN8855_RG_GDMP_RAM 0x10010000
/* Registers to mac forward control for unknown frames */
#define AN8855_MFC 0x10200010
#define AN8855_CPU_EN BIT(15)
#define AN8855_CPU_PORT_IDX GENMASK(12, 8)
#define AN8855_PAC 0x10200024
#define AN8855_TAG_PAE_MANG_FR BIT(30)
#define AN8855_TAG_PAE_BPDU_FR BIT(28)
#define AN8855_TAG_PAE_EG_TAG GENMASK(27, 25)
#define AN8855_TAG_PAE_LKY_VLAN BIT(24)
#define AN8855_TAG_PAE_PRI_HIGH BIT(23)
#define AN8855_TAG_PAE_MIR GENMASK(20, 19)
#define AN8855_TAG_PAE_PORT_FW GENMASK(18, 16)
#define AN8855_PAE_MANG_FR BIT(14)
#define AN8855_PAE_BPDU_FR BIT(12)
#define AN8855_PAE_EG_TAG GENMASK(11, 9)
#define AN8855_PAE_LKY_VLAN BIT(8)
#define AN8855_PAE_PRI_HIGH BIT(7)
#define AN8855_PAE_MIR GENMASK(4, 3)
#define AN8855_PAE_PORT_FW GENMASK(2, 0)
#define AN8855_RGAC1 0x10200028
#define AN8855_R02_MANG_FR BIT(30)
#define AN8855_R02_BPDU_FR BIT(28)
#define AN8855_R02_EG_TAG GENMASK(27, 25)
#define AN8855_R02_LKY_VLAN BIT(24)
#define AN8855_R02_PRI_HIGH BIT(23)
#define AN8855_R02_MIR GENMASK(20, 19)
#define AN8855_R02_PORT_FW GENMASK(18, 16)
#define AN8855_R01_MANG_FR BIT(14)
#define AN8855_R01_BPDU_FR BIT(12)
#define AN8855_R01_EG_TAG GENMASK(11, 9)
#define AN8855_R01_LKY_VLAN BIT(8)
#define AN8855_R01_PRI_HIGH BIT(7)
#define AN8855_R01_MIR GENMASK(4, 3)
#define AN8855_R01_PORT_FW GENMASK(2, 0)
#define AN8855_RGAC2 0x1020002c
#define AN8855_R0E_MANG_FR BIT(30)
#define AN8855_R0E_BPDU_FR BIT(28)
#define AN8855_R0E_EG_TAG GENMASK(27, 25)
#define AN8855_R0E_LKY_VLAN BIT(24)
#define AN8855_R0E_PRI_HIGH BIT(23)
#define AN8855_R0E_MIR GENMASK(20, 19)
#define AN8855_R0E_PORT_FW GENMASK(18, 16)
#define AN8855_R03_MANG_FR BIT(14)
#define AN8855_R03_BPDU_FR BIT(12)
#define AN8855_R03_EG_TAG GENMASK(11, 9)
#define AN8855_R03_LKY_VLAN BIT(8)
#define AN8855_R03_PRI_HIGH BIT(7)
#define AN8855_R03_MIR GENMASK(4, 3)
#define AN8855_R03_PORT_FW GENMASK(2, 0)
#define AN8855_AAC 0x102000a0
#define AN8855_MAC_AUTO_FLUSH BIT(28)
/* Control Address Table Age time.
* (AN8855_AGE_CNT + 1) * ( AN8855_AGE_UNIT + 1 ) * AN8855_L2_AGING_MS_CONSTANT
*/
#define AN8855_AGE_CNT GENMASK(20, 12)
/* Value in seconds. Value is always incremented of 1 */
#define AN8855_AGE_UNIT GENMASK(10, 0)
/* Registers for ARL Unknown Unicast Forward control */
#define AN8855_UNUF 0x102000b4
/* Registers for ARL Unknown Multicast Forward control */
#define AN8855_UNMF 0x102000b8
/* Registers for ARL Broadcast forward control */
#define AN8855_BCF 0x102000bc
/* Registers for port address age disable */
#define AN8855_AGDIS 0x102000c0
/* Registers for mirror port control */
#define AN8855_MIR 0x102000cc
#define AN8855_MIRROR_EN BIT(7)
#define AN8855_MIRROR_PORT GENMASK(4, 0)
/* Registers for BPDU and PAE frame control*/
#define AN8855_BPC 0x102000d0
#define AN8855_BPDU_MANG_FR BIT(14)
#define AN8855_BPDU_BPDU_FR BIT(12)
#define AN8855_BPDU_EG_TAG GENMASK(11, 9)
#define AN8855_BPDU_LKY_VLAN BIT(8)
#define AN8855_BPDU_PRI_HIGH BIT(7)
#define AN8855_BPDU_MIR GENMASK(4, 3)
#define AN8855_BPDU_PORT_FW GENMASK(2, 0)
/* Registers for IP Unknown Multicast Forward control */
#define AN8855_UNIPMF 0x102000dc
enum an8855_bpdu_port_fw {
AN8855_BPDU_FOLLOW_MFC = 0,
AN8855_BPDU_CPU_EXCLUDE = 4,
AN8855_BPDU_CPU_INCLUDE = 5,
AN8855_BPDU_CPU_ONLY = 6,
AN8855_BPDU_DROP = 7,
};
/* Register for address table control */
#define AN8855_ATC 0x10200300
#define AN8855_ATC_BUSY BIT(31)
#define AN8855_ATC_HASH GENMASK(24, 16)
#define AN8855_ATC_HIT GENMASK(15, 12)
#define AN8855_ATC_MAT_MASK GENMASK(11, 7)
#define AN8855_ATC_MAT(x) FIELD_PREP(AN8855_ATC_MAT_MASK, x)
#define AN8855_ATC_SAT GENMASK(5, 4)
#define AN8855_ATC_CMD GENMASK(2, 0)
enum an8855_fdb_mat_cmds {
AND8855_FDB_MAT_ALL = 0,
AND8855_FDB_MAT_MAC, /* All MAC address */
AND8855_FDB_MAT_DYNAMIC_MAC, /* All Dynamic MAC address */
AND8855_FDB_MAT_STATIC_MAC, /* All Static Mac Address */
AND8855_FDB_MAT_DIP, /* All DIP/GA address */
AND8855_FDB_MAT_DIP_IPV4, /* All DIP/GA IPv4 address */
AND8855_FDB_MAT_DIP_IPV6, /* All DIP/GA IPv6 address */
AND8855_FDB_MAT_DIP_SIP, /* All DIP_SIP address */
AND8855_FDB_MAT_DIP_SIP_IPV4, /* All DIP_SIP IPv4 address */
AND8855_FDB_MAT_DIP_SIP_IPV6, /* All DIP_SIP IPv6 address */
AND8855_FDB_MAT_MAC_CVID, /* All MAC address with CVID */
AND8855_FDB_MAT_MAC_FID, /* All MAC address with Filter ID */
AND8855_FDB_MAT_MAC_PORT, /* All MAC address with port */
AND8855_FDB_MAT_DIP_SIP_DIP_IPV4, /* All DIP_SIP address with DIP_IPV4 */
AND8855_FDB_MAT_DIP_SIP_SIP_IPV4, /* All DIP_SIP address with SIP_IPV4 */
AND8855_FDB_MAT_DIP_SIP_DIP_IPV6, /* All DIP_SIP address with DIP_IPV6 */
AND8855_FDB_MAT_DIP_SIP_SIP_IPV6, /* All DIP_SIP address with SIP_IPV6 */
/* All MAC address with MAC type (dynamic or static) with CVID */
AND8855_FDB_MAT_MAC_TYPE_CVID,
/* All MAC address with MAC type (dynamic or static) with Filter ID */
AND8855_FDB_MAT_MAC_TYPE_FID,
/* All MAC address with MAC type (dynamic or static) with port */
AND8855_FDB_MAT_MAC_TYPE_PORT,
};
enum an8855_fdb_cmds {
AN8855_FDB_READ = 0,
AN8855_FDB_WRITE = 1,
AN8855_FDB_FLUSH = 2,
AN8855_FDB_START = 4,
AN8855_FDB_NEXT = 5,
};
/* Registers for address table access */
#define AN8855_ATA1 0x10200304
#define AN8855_ATA1_MAC0 GENMASK(31, 24)
#define AN8855_ATA1_MAC1 GENMASK(23, 16)
#define AN8855_ATA1_MAC2 GENMASK(15, 8)
#define AN8855_ATA1_MAC3 GENMASK(7, 0)
#define AN8855_ATA2 0x10200308
#define AN8855_ATA2_MAC4 GENMASK(31, 24)
#define AN8855_ATA2_MAC5 GENMASK(23, 16)
#define AN8855_ATA2_UNAUTH BIT(10)
#define AN8855_ATA2_TYPE BIT(9) /* 1: dynamic, 0: static */
#define AN8855_ATA2_AGE GENMASK(8, 0)
/* Register for address table write data */
#define AN8855_ATWD 0x10200324
#define AN8855_ATWD_FID GENMASK(31, 28)
#define AN8855_ATWD_VID GENMASK(27, 16)
#define AN8855_ATWD_IVL BIT(15)
#define AN8855_ATWD_EG_TAG GENMASK(14, 12)
#define AN8855_ATWD_SA_MIR GENMASK(9, 8)
#define AN8855_ATWD_SA_FWD GENMASK(7, 5)
#define AN8855_ATWD_UPRI GENMASK(4, 2)
#define AN8855_ATWD_LEAKY BIT(1)
#define AN8855_ATWD_VLD BIT(0) /* vid LOAD */
#define AN8855_ATWD2 0x10200328
#define AN8855_ATWD2_PORT GENMASK(7, 0)
/* Registers for table search read address */
#define AN8855_ATRDS 0x10200330
#define AN8855_ATRD_SEL GENMASK(1, 0)
#define AN8855_ATRD0 0x10200334
#define AN8855_ATRD0_FID GENMASK(28, 25)
#define AN8855_ATRD0_VID GENMASK(21, 10)
#define AN8855_ATRD0_IVL BIT(9)
#define AN8855_ATRD0_TYPE GENMASK(4, 3)
#define AN8855_ATRD0_ARP GENMASK(2, 1)
#define AN8855_ATRD0_LIVE BIT(0)
#define AN8855_ATRD1 0x10200338
#define AN8855_ATRD1_MAC4 GENMASK(31, 24)
#define AN8855_ATRD1_MAC5 GENMASK(23, 16)
#define AN8855_ATRD1_AGING GENMASK(11, 3)
#define AN8855_ATRD2 0x1020033c
#define AN8855_ATRD2_MAC0 GENMASK(31, 24)
#define AN8855_ATRD2_MAC1 GENMASK(23, 16)
#define AN8855_ATRD2_MAC2 GENMASK(15, 8)
#define AN8855_ATRD2_MAC3 GENMASK(7, 0)
#define AN8855_ATRD3 0x10200340
#define AN8855_ATRD3_PORTMASK GENMASK(7, 0)
enum an8855_fdb_type {
AN8855_MAC_TB_TY_MAC = 0,
AN8855_MAC_TB_TY_DIP = 1,
AN8855_MAC_TB_TY_DIP_SIP = 2,
};
/* Register for vlan table control */
#define AN8855_VTCR 0x10200600
#define AN8855_VTCR_BUSY BIT(31)
#define AN8855_VTCR_FUNC GENMASK(15, 12)
#define AN8855_VTCR_VID GENMASK(11, 0)
enum an8855_vlan_cmd {
/* Read/Write the specified VID entry from VAWD register based
* on VID.
*/
AN8855_VTCR_RD_VID = 0,
AN8855_VTCR_WR_VID = 1,
};
/* Register for setup vlan write data */
#define AN8855_VAWD0 0x10200604
/* VLAN Member Control */
#define AN8855_VA0_PORT GENMASK(31, 26)
/* Egress Tag Control */
#define AN8855_VA0_ETAG GENMASK(23, 12)
#define AN8855_VA0_ETAG_PORT GENMASK(13, 12)
#define AN8855_VA0_ETAG_PORT_SHIFT(port) ((port) * 2)
#define AN8855_VA0_ETAG_PORT_MASK(port) (AN8855_VA0_ETAG_PORT << \
AN8855_VA0_ETAG_PORT_SHIFT(port))
#define AN8855_VA0_ETAG_PORT_VAL(port, val) (FIELD_PREP(AN8855_VA0_ETAG_PORT, (val)) << \
AN8855_VA0_ETAG_PORT_SHIFT(port))
#define AN8855_VA0_EG_CON BIT(11)
#define AN8855_VA0_VTAG_EN BIT(10) /* Per VLAN Egress Tag Control */
#define AN8855_VA0_IVL_MAC BIT(5) /* Independent VLAN Learning */
#define AN8855_VA0_FID GENMASK(4, 1)
#define AN8855_VA0_VLAN_VALID BIT(0) /* VLAN Entry Valid */
#define AN8855_VAWD1 0x10200608
#define AN8855_VA1_PORT_STAG BIT(1)
enum an8855_fid {
AN8855_FID_STANDALONE = 0,
AN8855_FID_BRIDGED = 1,
};
/* Same register field of VAWD0 */
#define AN8855_VARD0 0x10200618
enum an8855_vlan_egress_attr {
AN8855_VLAN_EGRESS_UNTAG = 0,
AN8855_VLAN_EGRESS_TAG = 2,
AN8855_VLAN_EGRESS_STACK = 3,
};
/* Register for port STP state control */
#define AN8855_SSP_P(x) (0x10208000 + ((x) * 0x200))
/* Up to 16 FID supported, each with the same mask */
#define AN8855_FID_PST GENMASK(1, 0)
#define AN8855_FID_PST_SHIFT(fid) (2 * (fid))
#define AN8855_FID_PST_MASK(fid) (AN8855_FID_PST << \
AN8855_FID_PST_SHIFT(fid))
#define AN8855_FID_PST_VAL(fid, val) (FIELD_PREP(AN8855_FID_PST, (val)) << \
AN8855_FID_PST_SHIFT(fid))
enum an8855_stp_state {
AN8855_STP_DISABLED = 0,
AN8855_STP_BLOCKING = 1,
AN8855_STP_LISTENING = AN8855_STP_BLOCKING,
AN8855_STP_LEARNING = 2,
AN8855_STP_FORWARDING = 3
};
/* Register for port control */
#define AN8855_PCR_P(x) (0x10208004 + ((x) * 0x200))
#define AN8855_EG_TAG GENMASK(29, 28)
#define AN8855_PORT_PRI GENMASK(26, 24)
#define AN8855_PORT_TX_MIR BIT(20)
#define AN8855_PORT_RX_MIR BIT(16)
#define AN8855_PORT_VLAN GENMASK(1, 0)
enum an8855_port_mode {
/* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
AN8855_PORT_MATRIX_MODE = 0,
/* Fallback Mode: Forward received frames with ingress ports that do
* not belong to the VLAN member. Frames whose VID is not listed on
* the VLAN table are forwarded by the PCR_MATRIX members.
*/
AN8855_PORT_FALLBACK_MODE = 1,
/* Check Mode: Forward received frames whose ingress do not
* belong to the VLAN member. Discard frames if VID ismiddes on the
* VLAN table.
*/
AN8855_PORT_CHECK_MODE = 2,
/* Security Mode: Discard any frame due to ingress membership
* violation or VID missed on the VLAN table.
*/
AN8855_PORT_SECURITY_MODE = 3,
};
/* Register for port security control */
#define AN8855_PSC_P(x) (0x1020800c + ((x) * 0x200))
#define AN8855_SA_DIS BIT(4)
/* Register for port vlan control */
#define AN8855_PVC_P(x) (0x10208010 + ((x) * 0x200))
#define AN8855_PORT_SPEC_REPLACE_MODE BIT(11)
#define AN8855_PVC_EG_TAG GENMASK(10, 8)
#define AN8855_VLAN_ATTR GENMASK(7, 6)
#define AN8855_PORT_SPEC_TAG BIT(5)
#define AN8855_ACC_FRM GENMASK(1, 0)
enum an8855_vlan_port_eg_tag {
AN8855_VLAN_EG_DISABLED = 0,
AN8855_VLAN_EG_CONSISTENT = 1,
AN8855_VLAN_EG_UNTAGGED = 4,
AN8855_VLAN_EG_SWAP = 5,
AN8855_VLAN_EG_TAGGED = 6,
AN8855_VLAN_EG_STACK = 7,
};
enum an8855_vlan_port_attr {
AN8855_VLAN_USER = 0,
AN8855_VLAN_STACK = 1,
AN8855_VLAN_TRANSPARENT = 3,
};
enum an8855_vlan_port_acc_frm {
AN8855_VLAN_ACC_ALL = 0,
AN8855_VLAN_ACC_TAGGED = 1,
AN8855_VLAN_ACC_UNTAGGED = 2,
};
#define AN8855_PPBV1_P(x) (0x10208014 + ((x) * 0x200))
#define AN8855_PPBV_G0_PORT_VID GENMASK(11, 0)
#define AN8855_PORTMATRIX_P(x) (0x10208044 + ((x) * 0x200))
#define AN8855_PORTMATRIX GENMASK(5, 0)
/* Port matrix without the CPU port that should never be removed */
#define AN8855_USER_PORTMATRIX GENMASK(4, 0)
/* Register for port PVID */
#define AN8855_PVID_P(x) (0x10208048 + ((x) * 0x200))
#define AN8855_G0_PORT_VID GENMASK(11, 0)
/* Register for port MAC control register */
#define AN8855_PMCR_P(x) (0x10210000 + ((x) * 0x200))
#define AN8855_PMCR_FORCE_MODE BIT(31)
#define AN8855_PMCR_FORCE_SPEED GENMASK(30, 28)
#define AN8855_PMCR_FORCE_SPEED_5000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x4)
#define AN8855_PMCR_FORCE_SPEED_2500 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x3)
#define AN8855_PMCR_FORCE_SPEED_1000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x2)
#define AN8855_PMCR_FORCE_SPEED_100 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1)
#define AN8855_PMCR_FORCE_SPEED_10 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1)
#define AN8855_PMCR_FORCE_FDX BIT(25)
#define AN8855_PMCR_FORCE_LNK BIT(24)
#define AN8855_PMCR_IFG_XMIT GENMASK(21, 20)
#define AN8855_PMCR_EXT_PHY BIT(19)
#define AN8855_PMCR_MAC_MODE BIT(18)
#define AN8855_PMCR_TX_EN BIT(16)
#define AN8855_PMCR_RX_EN BIT(15)
#define AN8855_PMCR_BACKOFF_EN BIT(12)
#define AN8855_PMCR_BACKPR_EN BIT(11)
#define AN8855_PMCR_FORCE_EEE5G BIT(9)
#define AN8855_PMCR_FORCE_EEE2P5G BIT(8)
#define AN8855_PMCR_FORCE_EEE1G BIT(7)
#define AN8855_PMCR_FORCE_EEE100 BIT(6)
#define AN8855_PMCR_TX_FC_EN BIT(5)
#define AN8855_PMCR_RX_FC_EN BIT(4)
#define AN8855_PMSR_P(x) (0x10210010 + (x) * 0x200)
#define AN8855_PMSR_SPEED GENMASK(30, 28)
#define AN8855_PMSR_SPEED_5000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x4)
#define AN8855_PMSR_SPEED_2500 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x3)
#define AN8855_PMSR_SPEED_1000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x2)
#define AN8855_PMSR_SPEED_100 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x1)
#define AN8855_PMSR_SPEED_10 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x0)
#define AN8855_PMSR_DPX BIT(25)
#define AN8855_PMSR_LNK BIT(24)
#define AN8855_PMSR_EEE1G BIT(7)
#define AN8855_PMSR_EEE100M BIT(6)
#define AN8855_PMSR_RX_FC BIT(5)
#define AN8855_PMSR_TX_FC BIT(4)
#define AN8855_PMEEECR_P(x) (0x10210004 + (x) * 0x200)
#define AN8855_LPI_MODE_EN BIT(31)
#define AN8855_WAKEUP_TIME_2500 GENMASK(23, 16)
#define AN8855_WAKEUP_TIME_1000 GENMASK(15, 8)
#define AN8855_WAKEUP_TIME_100 GENMASK(7, 0)
#define AN8855_PMEEECR2_P(x) (0x10210008 + (x) * 0x200)
#define AN8855_WAKEUP_TIME_5000 GENMASK(7, 0)
#define AN8855_GMACCR 0x10213e00
#define AN8855_MAX_RX_JUMBO GENMASK(7, 4)
/* 2K for 0x0, 0x1, 0x2 */
#define AN8855_MAX_RX_JUMBO_2K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x0)
#define AN8855_MAX_RX_JUMBO_3K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x3)
#define AN8855_MAX_RX_JUMBO_4K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x4)
#define AN8855_MAX_RX_JUMBO_5K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x5)
#define AN8855_MAX_RX_JUMBO_6K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x6)
#define AN8855_MAX_RX_JUMBO_7K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x7)
#define AN8855_MAX_RX_JUMBO_8K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x8)
#define AN8855_MAX_RX_JUMBO_9K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x9)
#define AN8855_MAX_RX_JUMBO_12K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xa)
#define AN8855_MAX_RX_JUMBO_15K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xb)
#define AN8855_MAX_RX_JUMBO_16K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xc)
#define AN8855_MAX_RX_PKT_LEN GENMASK(1, 0)
#define AN8855_MAX_RX_PKT_1518_1522 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x0)
#define AN8855_MAX_RX_PKT_1536 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x1)
#define AN8855_MAX_RX_PKT_1552 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x2)
#define AN8855_MAX_RX_PKT_JUMBO FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x3)
#define AN8855_CKGCR 0x10213e1c
#define AN8855_LPI_TXIDLE_THD_MASK GENMASK(31, 14)
#define AN8855_CKG_LNKDN_PORT_STOP BIT(1)
#define AN8855_CKG_LNKDN_GLB_STOP BIT(0)
/* Register for MIB */
#define AN8855_PORT_MIB_COUNTER(x) (0x10214000 + (x) * 0x200)
/* Each define is an offset of AN8855_PORT_MIB_COUNTER */
#define AN8855_PORT_MIB_TX_DROP 0x00
#define AN8855_PORT_MIB_TX_CRC_ERR 0x04
#define AN8855_PORT_MIB_TX_UNICAST 0x08
#define AN8855_PORT_MIB_TX_MULTICAST 0x0c
#define AN8855_PORT_MIB_TX_BROADCAST 0x10
#define AN8855_PORT_MIB_TX_COLLISION 0x14
#define AN8855_PORT_MIB_TX_SINGLE_COLLISION 0x18
#define AN8855_PORT_MIB_TX_MULTIPLE_COLLISION 0x1c
#define AN8855_PORT_MIB_TX_DEFERRED 0x20
#define AN8855_PORT_MIB_TX_LATE_COLLISION 0x24
#define AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION 0x28
#define AN8855_PORT_MIB_TX_PAUSE 0x2c
#define AN8855_PORT_MIB_TX_PKT_SZ_64 0x30
#define AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127 0x34
#define AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255 0x38
#define AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511 0x3
#define AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023 0x40
#define AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518 0x44
#define AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX 0x48
#define AN8855_PORT_MIB_TX_BYTES 0x4c /* 64 bytes */
#define AN8855_PORT_MIB_TX_OVERSIZE_DROP 0x54
#define AN8855_PORT_MIB_TX_BAD_PKT_BYTES 0x58 /* 64 bytes */
#define AN8855_PORT_MIB_RX_DROP 0x80
#define AN8855_PORT_MIB_RX_FILTERING 0x84
#define AN8855_PORT_MIB_RX_UNICAST 0x88
#define AN8855_PORT_MIB_RX_MULTICAST 0x8c
#define AN8855_PORT_MIB_RX_BROADCAST 0x90
#define AN8855_PORT_MIB_RX_ALIGN_ERR 0x94
#define AN8855_PORT_MIB_RX_CRC_ERR 0x98
#define AN8855_PORT_MIB_RX_UNDER_SIZE_ERR 0x9c
#define AN8855_PORT_MIB_RX_FRAG_ERR 0xa0
#define AN8855_PORT_MIB_RX_OVER_SZ_ERR 0xa4
#define AN8855_PORT_MIB_RX_JABBER_ERR 0xa8
#define AN8855_PORT_MIB_RX_PAUSE 0xac
#define AN8855_PORT_MIB_RX_PKT_SZ_64 0xb0
#define AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127 0xb4
#define AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255 0xb8
#define AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511 0xbc
#define AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023 0xc0
#define AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518 0xc4
#define AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX 0xc8
#define AN8855_PORT_MIB_RX_BYTES 0xcc /* 64 bytes */
#define AN8855_PORT_MIB_RX_CTRL_DROP 0xd4
#define AN8855_PORT_MIB_RX_INGRESS_DROP 0xd8
#define AN8855_PORT_MIB_RX_ARL_DROP 0xdc
#define AN8855_PORT_MIB_FLOW_CONTROL_DROP 0xe0
#define AN8855_PORT_MIB_WRED_DROP 0xe4
#define AN8855_PORT_MIB_MIRROR_DROP 0xe8
#define AN8855_PORT_MIB_RX_BAD_PKT_BYTES 0xec /* 64 bytes */
#define AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP 0xf4
#define AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP 0xf8
#define AN8855_PORT_MIB_PORT_CONTROL_DROP 0xfc
#define AN8855_MIB_CCR 0x10213e30
#define AN8855_CCR_MIB_ENABLE BIT(31)
#define AN8855_CCR_RX_OCT_CNT_GOOD BIT(7)
#define AN8855_CCR_RX_OCT_CNT_BAD BIT(6)
#define AN8855_CCR_TX_OCT_CNT_GOOD BIT(5)
#define AN8855_CCR_TX_OCT_CNT_BAD BIT(4)
#define AN8855_CCR_RX_OCT_CNT_GOOD_2 BIT(3)
#define AN8855_CCR_RX_OCT_CNT_BAD_2 BIT(2)
#define AN8855_CCR_TX_OCT_CNT_GOOD_2 BIT(1)
#define AN8855_CCR_TX_OCT_CNT_BAD_2 BIT(0)
#define AN8855_CCR_MIB_ACTIVATE (AN8855_CCR_MIB_ENABLE | \
AN8855_CCR_RX_OCT_CNT_GOOD | \
AN8855_CCR_RX_OCT_CNT_BAD | \
AN8855_CCR_TX_OCT_CNT_GOOD | \
AN8855_CCR_TX_OCT_CNT_BAD | \
AN8855_CCR_RX_OCT_CNT_BAD_2 | \
AN8855_CCR_TX_OCT_CNT_BAD_2)
#define AN8855_MIB_CLR 0x10213e34
#define AN8855_MIB_PORT6_CLR BIT(6)
#define AN8855_MIB_PORT5_CLR BIT(5)
#define AN8855_MIB_PORT4_CLR BIT(4)
#define AN8855_MIB_PORT3_CLR BIT(3)
#define AN8855_MIB_PORT2_CLR BIT(2)
#define AN8855_MIB_PORT1_CLR BIT(1)
#define AN8855_MIB_PORT0_CLR BIT(0)
/* HSGMII/SGMII Configuration register */
/* AN8855_HSGMII_AN_CSR_BASE 0x10220000 */
#define AN8855_SGMII_REG_AN0 0x10220000
/* AN8855_SGMII_AN_ENABLE BMCR_ANENABLE */
/* AN8855_SGMII_AN_RESTART BMCR_ANRESTART */
#define AN8855_SGMII_REG_AN_13 0x10220034
#define AN8855_SGMII_REMOTE_FAULT_DIS BIT(8)
#define AN8855_SGMII_IF_MODE GENMASK(5, 0)
#define AN8855_SGMII_REG_AN_FORCE_CL37 0x10220060
#define AN8855_RG_FORCE_AN_DONE BIT(0)
/* AN8855_HSGMII_CSR_PCS_BASE 0x10220000 */
#define AN8855_RG_HSGMII_PCS_CTROL_1 0x10220a00
#define AN8855_RG_TBI_10B_MODE BIT(30)
#define AN8855_RG_AN_SGMII_MODE_FORCE 0x10220a24
#define AN8855_RG_FORCE_CUR_SGMII_MODE GENMASK(5, 4)
#define AN8855_RG_FORCE_CUR_SGMII_SEL BIT(0)
/* AN8855_MULTI_SGMII_CSR_BASE 0x10224000 */
#define AN8855_SGMII_STS_CTRL_0 0x10224018
#define AN8855_RG_LINK_MODE_P0 GENMASK(5, 4)
#define AN8855_RG_LINK_MODE_P0_SPEED_2500 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x3)
#define AN8855_RG_LINK_MODE_P0_SPEED_1000 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x2)
#define AN8855_RG_LINK_MODE_P0_SPEED_100 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x1)
#define AN8855_RG_LINK_MODE_P0_SPEED_10 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x0)
#define AN8855_RG_FORCE_SPD_MODE_P0 BIT(2)
#define AN8855_MSG_RX_CTRL_0 0x10224100
#define AN8855_MSG_RX_LIK_STS_0 0x10224514
#define AN8855_RG_DPX_STS_P3 BIT(24)
#define AN8855_RG_DPX_STS_P2 BIT(16)
#define AN8855_RG_EEE1G_STS_P1 BIT(12)
#define AN8855_RG_DPX_STS_P1 BIT(8)
#define AN8855_RG_TXFC_STS_P0 BIT(2)
#define AN8855_RG_RXFC_STS_P0 BIT(1)
#define AN8855_RG_DPX_STS_P0 BIT(0)
#define AN8855_MSG_RX_LIK_STS_2 0x1022451c
#define AN8855_RG_RXFC_AN_BYPASS_P3 BIT(11)
#define AN8855_RG_RXFC_AN_BYPASS_P2 BIT(10)
#define AN8855_RG_RXFC_AN_BYPASS_P1 BIT(9)
#define AN8855_RG_TXFC_AN_BYPASS_P3 BIT(7)
#define AN8855_RG_TXFC_AN_BYPASS_P2 BIT(6)
#define AN8855_RG_TXFC_AN_BYPASS_P1 BIT(5)
#define AN8855_RG_DPX_AN_BYPASS_P3 BIT(3)
#define AN8855_RG_DPX_AN_BYPASS_P2 BIT(2)
#define AN8855_RG_DPX_AN_BYPASS_P1 BIT(1)
#define AN8855_RG_DPX_AN_BYPASS_P0 BIT(0)
#define AN8855_PHY_RX_FORCE_CTRL_0 0x10224520
#define AN8855_RG_FORCE_TXC_SEL BIT(4)
/* AN8855_XFI_CSR_PCS_BASE 0x10225000 */
#define AN8855_RG_USXGMII_AN_CONTROL_0 0x10225bf8
/* AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000 */
#define AN8855_RG_RATE_ADAPT_CTRL_0 0x10226000
#define AN8855_RG_RATE_ADAPT_RX_BYPASS BIT(27)
#define AN8855_RG_RATE_ADAPT_TX_BYPASS BIT(26)
#define AN8855_RG_RATE_ADAPT_RX_EN BIT(4)
#define AN8855_RG_RATE_ADAPT_TX_EN BIT(0)
#define AN8855_RATE_ADP_P0_CTRL_0 0x10226100
#define AN8855_RG_P0_DIS_MII_MODE BIT(31)
#define AN8855_RG_P0_MII_MODE BIT(28)
#define AN8855_RG_P0_MII_RA_RX_EN BIT(3)
#define AN8855_RG_P0_MII_RA_TX_EN BIT(2)
#define AN8855_RG_P0_MII_RA_RX_MODE BIT(1)
#define AN8855_RG_P0_MII_RA_TX_MODE BIT(0)
#define AN8855_MII_RA_AN_ENABLE 0x10226300
#define AN8855_RG_P0_RA_AN_EN BIT(0)
/* AN8855_QP_DIG_CSR_BASE 0x1022a000 */
#define AN8855_QP_CK_RST_CTRL_4 0x1022a310
#define AN8855_QP_DIG_MODE_CTRL_0 0x1022a324
#define AN8855_RG_SGMII_MODE GENMASK(5, 4)
#define AN8855_RG_SGMII_AN_EN BIT(0)
#define AN8855_QP_DIG_MODE_CTRL_1 0x1022a330
#define AN8855_RG_TPHY_SPEED GENMASK(3, 2)
/* AN8855_SERDES_WRAPPER_BASE 0x1022c000 */
#define AN8855_USGMII_CTRL_0 0x1022c000
/* AN8855_QP_PMA_TOP_BASE 0x1022e000 */
#define AN8855_PON_RXFEDIG_CTRL_0 0x1022e100
#define AN8855_RG_QP_EQ_RX500M_CK_SEL BIT(12)
#define AN8855_PON_RXFEDIG_CTRL_9 0x1022e124
#define AN8855_RG_QP_EQ_LEQOSC_DLYCNT GENMASK(2, 0)
#define AN8855_SS_LCPLL_PWCTL_SETTING_2 0x1022e208
#define AN8855_RG_NCPO_ANA_MSB GENMASK(17, 16)
#define AN8855_SS_LCPLL_TDC_FLT_2 0x1022e230
#define AN8855_RG_LCPLL_NCPO_VALUE GENMASK(30, 0)
#define AN8855_SS_LCPLL_TDC_FLT_5 0x1022e23c
#define AN8855_RG_LCPLL_NCPO_CHG BIT(24)
#define AN8855_SS_LCPLL_TDC_PCW_1 0x1022e248
#define AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0)
#define AN8855_INTF_CTRL_8 0x1022e320
#define AN8855_INTF_CTRL_9 0x1022e324
#define AN8855_INTF_CTRL_10 0x1022e328
#define AN8855_RG_DA_QP_TX_FIR_C2_SEL BIT(29)
#define AN8855_RG_DA_QP_TX_FIR_C2_FORCE GENMASK(28, 24)
#define AN8855_RG_DA_QP_TX_FIR_C1_SEL BIT(21)
#define AN8855_RG_DA_QP_TX_FIR_C1_FORCE GENMASK(20, 16)
#define AN8855_INTF_CTRL_11 0x1022e32c
#define AN8855_RG_DA_QP_TX_FIR_C0B_SEL BIT(6)
#define AN8855_RG_DA_QP_TX_FIR_C0B_FORCE GENMASK(5, 0)
#define AN8855_PLL_CTRL_0 0x1022e400
#define AN8855_RG_PHYA_AUTO_INIT BIT(0)
#define AN8855_PLL_CTRL_2 0x1022e408
#define AN8855_RG_DA_QP_PLL_SDM_IFM_INTF BIT(30)
#define AN8855_RG_DA_QP_PLL_RICO_SEL_INTF BIT(29)
#define AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF BIT(28)
#define AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF BIT(27)
#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF BIT(26)
#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF GENMASK(25, 24)
#define AN8855_RG_DA_QP_PLL_PCK_SEL_INTF BIT(22)
#define AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF GENMASK(21, 20)
#define AN8855_RG_DA_QP_PLL_IR_INTF GENMASK(19, 16)
#define AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF BIT(14)
#define AN8855_RG_DA_QP_PLL_FBKSEL_INTF GENMASK(13, 12)
#define AN8855_RG_DA_QP_PLL_BR_INTF GENMASK(10, 8)
#define AN8855_RG_DA_QP_PLL_BPD_INTF GENMASK(7, 6)
#define AN8855_RG_DA_QP_PLL_BPA_INTF GENMASK(4, 2)
#define AN8855_RG_DA_QP_PLL_BC_INTF GENMASK(1, 0)
#define AN8855_PLL_CTRL_3 0x1022e40c
#define AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF GENMASK(31, 16)
#define AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF GENMASK(15, 0)
#define AN8855_PLL_CTRL_4 0x1022e410
#define AN8855_RG_DA_QP_PLL_SDM_HREN_INTF GENMASK(4, 3)
#define AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF BIT(2)
#define AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF GENMASK(1, 0)
#define AN8855_PLL_CK_CTRL_0 0x1022e414
#define AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF BIT(9)
#define AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF BIT(8)
#define AN8855_RX_DLY_0 0x1022e614
#define AN8855_RG_QP_RX_SAOSC_EN_H_DLY GENMASK(13, 8)
#define AN8855_RG_QP_RX_PI_CAL_EN_H_DLY GENMASK(7, 0)
#define AN8855_RX_CTRL_2 0x1022e630
#define AN8855_RG_QP_RX_EQ_EN_H_DLY GENMASK(28, 16)
#define AN8855_RX_CTRL_5 0x1022e63c
#define AN8855_RG_FREDET_CHK_CYCLE GENMASK(29, 10)
#define AN8855_RX_CTRL_6 0x1022e640
#define AN8855_RG_FREDET_GOLDEN_CYCLE GENMASK(19, 0)
#define AN8855_RX_CTRL_7 0x1022e644
#define AN8855_RG_FREDET_TOLERATE_CYCLE GENMASK(19, 0)
#define AN8855_RX_CTRL_8 0x1022e648
#define AN8855_RG_DA_QP_SAOSC_DONE_TIME GENMASK(27, 16)
#define AN8855_RG_DA_QP_LEQOS_EN_TIME GENMASK(14, 0)
#define AN8855_RX_CTRL_26 0x1022e690
#define AN8855_RG_QP_EQ_RETRAIN_ONLY_EN BIT(26)
#define AN8855_RG_LINK_NE_EN BIT(24)
#define AN8855_RG_LINK_ERRO_EN BIT(23)
#define AN8855_RX_CTRL_42 0x1022e6d0
#define AN8855_RG_QP_EQ_EN_DLY GENMASK(12, 0)
/* AN8855_QP_ANA_CSR_BASE 0x1022f000 */
#define AN8855_RG_QP_RX_DAC_EN 0x1022f000
#define AN8855_RG_QP_SIGDET_HF GENMASK(17, 16)
#define AN8855_RG_QP_RXAFE_RESERVE 0x1022f004
#define AN8855_RG_QP_CDR_PD_10B_EN BIT(11)
#define AN8855_RG_QP_CDR_LPF_BOT_LIM 0x1022f008
#define AN8855_RG_QP_CDR_LPF_KP_GAIN GENMASK(26, 24)
#define AN8855_RG_QP_CDR_LPF_KI_GAIN GENMASK(22, 20)
#define AN8855_RG_QP_CDR_LPF_MJV_LIM 0x1022f00c
#define AN8855_RG_QP_CDR_LPF_RATIO GENMASK(5, 4)
#define AN8855_RG_QP_CDR_LPF_SETVALUE 0x1022f014
#define AN8855_RG_QP_CDR_PR_BUF_IN_SR GENMASK(31, 29)
#define AN8855_RG_QP_CDR_PR_BETA_SEL GENMASK(28, 25)
#define AN8855_RG_QP_CDR_PR_CKREF_DIV1 0x1022f018
#define AN8855_RG_QP_CDR_PR_KBAND_DIV GENMASK(26, 24)
#define AN8855_RG_QP_CDR_PR_DAC_BAND GENMASK(12, 8)
#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE 0x1022f01c
#define AN8855_RG_QP_CDR_PR_XFICK_EN BIT(30)
#define AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE BIT(6)
#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK GENMASK(5, 0)
#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF 0x1022f020
#define AN8855_RG_QP_CDR_PHYCK_SEL GENMASK(17, 16)
#define AN8855_RG_QP_CDR_PHYCK_RSTB BIT(13)
#define AN8855_RG_QP_CDR_PHYCK_DIV GENMASK(12, 6)
#define AN8855_RG_QP_TX_MODE 0x1022f028
#define AN8855_RG_QP_TX_RESERVE GENMASK(31, 16)
#define AN8855_RG_QP_TX_MODE_16B_EN BIT(0)
#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL 0x1022f03c
#define AN8855_RG_QP_PLL_SDM_ORD 0x1022f040
#define AN8855_RG_QP_PLL_SSC_PHASE_INI BIT(4)
#define AN8855_RG_QP_PLL_SSC_TRI_EN BIT(3)
/* AN8855_ETHER_SYS_BASE 0x1028c800 */
#define AN8855_RG_GPHY_AFE_PWD 0x1028c840
#define AN8855_RG_GPHY_SMI_ADDR 0x1028c848
#define MIB_DESC(_s, _o, _n) \
{ \
.size = (_s), \
.offset = (_o), \
.name = (_n), \
}
struct an8855_mib_desc {
unsigned int size;
unsigned int offset;
const char *name;
};
struct an8855_fdb {
u16 vid;
u8 port_mask;
u16 aging;
u8 mac[6];
bool noarp;
u8 live;
u8 type;
u8 fid;
u8 ivl;
};
struct an8855_priv {
struct device *dev;
struct dsa_switch *ds;
struct regmap *regmap;
struct gpio_desc *reset_gpio;
/* Protect ATU or VLAN table access */
struct mutex reg_mutex;
struct phylink_pcs pcs;
u8 mirror_rx;
u8 mirror_tx;
u8 port_isolated_map;
bool phy_require_calib;
};
#endif /* __AN8855_H */

113
lede/target/linux/mediatek/files-6.12/drivers/net/mdio/mdio-an8855.c Normal file
View File

@@ -0,0 +1,113 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* MDIO passthrough driver for Airoha AN8855 Switch
*/
#include <linux/mfd/airoha-an8855-mfd.h>
#include <linux/module.h>
#include <linux/of_mdio.h>
#include <linux/platform_device.h>
static int an855_phy_restore_page(struct an8855_mfd_priv *priv,
int phy) __must_hold(&priv->bus->mdio_lock)
{
/* Check PHY page only for addr shared with switch */
if (phy != priv->switch_addr)
return 0;
/* Don't restore page if it's not set to switch page */
if (priv->current_page != FIELD_GET(AN8855_PHY_PAGE,
AN8855_PHY_PAGE_EXTENDED_4))
return 0;
/* Restore page to 0, PHY might change page right after but that
* will be ignored as it won't be a switch page.
*/
return an8855_mii_set_page(priv, phy, AN8855_PHY_PAGE_STANDARD);
}
static int an8855_phy_read(struct mii_bus *bus, int phy, int regnum)
{
struct an8855_mfd_priv *priv = bus->priv;
struct mii_bus *real_bus = priv->bus;
int ret;
mutex_lock_nested(&real_bus->mdio_lock, MDIO_MUTEX_NESTED);
ret = an855_phy_restore_page(priv, phy);
if (ret)
goto exit;
ret = __mdiobus_read(real_bus, phy, regnum);
exit:
mutex_unlock(&real_bus->mdio_lock);
return ret;
}
static int an8855_phy_write(struct mii_bus *bus, int phy, int regnum, u16 val)
{
struct an8855_mfd_priv *priv = bus->priv;
struct mii_bus *real_bus = priv->bus;
int ret;
mutex_lock_nested(&real_bus->mdio_lock, MDIO_MUTEX_NESTED);
ret = an855_phy_restore_page(priv, phy);
if (ret)
goto exit;
ret = __mdiobus_write(real_bus, phy, regnum, val);
exit:
mutex_unlock(&real_bus->mdio_lock);
return ret;
}
static int an8855_mdio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct an8855_mfd_priv *priv;
struct mii_bus *bus;
int ret;
/* Get priv of MFD */
priv = dev_get_drvdata(dev->parent);
bus = devm_mdiobus_alloc(dev);
if (!bus)
return -ENOMEM;
bus->priv = priv;
bus->name = KBUILD_MODNAME "-mii";
snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d",
priv->switch_addr);
bus->parent = dev;
bus->read = an8855_phy_read;
bus->write = an8855_phy_write;
ret = devm_of_mdiobus_register(dev, bus, dev->of_node);
if (ret)
return dev_err_probe(dev, ret, "failed to register MDIO bus\n");
return ret;
}
static const struct of_device_id an8855_mdio_of_match[] = {
{ .compatible = "airoha,an8855-mdio", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, an8855_mdio_of_match);
static struct platform_driver an8855_mdio_driver = {
.probe = an8855_mdio_probe,
.driver = {
.name = "an8855-mdio",
.of_match_table = an8855_mdio_of_match,
},
};
module_platform_driver(an8855_mdio_driver);
MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
MODULE_DESCRIPTION("Driver for AN8855 MDIO passthrough");
MODULE_LICENSE("GPL");

267
lede/target/linux/mediatek/files-6.12/drivers/net/phy/air_an8855.c Normal file
View File

@@ -0,0 +1,267 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
*/
#include <linux/bitfield.h>
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/phy.h>
#define AN8855_PHY_SELECT_PAGE 0x1f
#define AN8855_PHY_PAGE GENMASK(2, 0)
#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)
#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)
/* MII Registers Page 1 */
#define AN8855_PHY_EXT_REG_14 0x14
#define AN8855_PHY_EN_DOWN_SHIFT BIT(4)
/* R50 Calibration regs in MDIO_MMD_VEND1 */
#define AN8855_PHY_R500HM_RSEL_TX_AB 0x174
#define AN8855_PHY_R50OHM_RSEL_TX_A_EN BIT(15)
#define AN8855_PHY_R50OHM_RSEL_TX_A GENMASK(14, 8)
#define AN8855_PHY_R50OHM_RSEL_TX_B_EN BIT(7)
#define AN8855_PHY_R50OHM_RSEL_TX_B GENMASK(6, 0)
#define AN8855_PHY_R500HM_RSEL_TX_CD 0x175
#define AN8855_PHY_R50OHM_RSEL_TX_C_EN BIT(15)
#define AN8855_PHY_R50OHM_RSEL_TX_C GENMASK(14, 8)
#define AN8855_PHY_R50OHM_RSEL_TX_D_EN BIT(7)
#define AN8855_PHY_R50OHM_RSEL_TX_D GENMASK(6, 0)
#define AN8855_SWITCH_EFUSE_R50O GENMASK(30, 24)
/* PHY TX PAIR DELAY SELECT Register */
#define AN8855_PHY_TX_PAIR_DLY_SEL_GBE 0x013
#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_A_GBE GENMASK(14, 12)
#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_B_GBE GENMASK(10, 8)
#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_C_GBE GENMASK(6, 4)
#define AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_D_GBE GENMASK(2, 0)
/* PHY ADC Register */
#define AN8855_PHY_RXADC_CTRL 0x0d8
#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_A BIT(12)
#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_B BIT(8)
#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_C BIT(4)
#define AN8855_PHY_RG_AD_SAMNPLE_PHSEL_D BIT(0)
#define AN8855_PHY_RXADC_REV_0 0x0d9
#define AN8855_PHY_RG_AD_RESERVE0_A GENMASK(15, 8)
#define AN8855_PHY_RG_AD_RESERVE0_B GENMASK(7, 0)
#define AN8855_PHY_RXADC_REV_1 0x0da
#define AN8855_PHY_RG_AD_RESERVE0_C GENMASK(15, 8)
#define AN8855_PHY_RG_AD_RESERVE0_D GENMASK(7, 0)
#define AN8855_PHY_ID 0xc0ff0410
#define AN8855_PHY_FLAGS_EN_CALIBRATION BIT(0)
struct air_an8855_priv {
u8 calibration_data[4];
};
static const u8 dsa_r50ohm_table[] = {
127, 127, 127, 127, 127, 127, 127, 127, 127, 127,
127, 127, 127, 127, 127, 127, 127, 126, 122, 117,
112, 109, 104, 101, 97, 94, 90, 88, 84, 80,
78, 74, 72, 68, 66, 64, 61, 58, 56, 53,
51, 48, 47, 44, 42, 40, 38, 36, 34, 32,
31, 28, 27, 24, 24, 22, 20, 18, 16, 16,
14, 12, 11, 9
};
static int en8855_get_r50ohm_val(struct device *dev, const char *calib_name,
u8 *dest)
{
u32 shift_sel, val;
int ret;
int i;
ret = nvmem_cell_read_u32(dev, calib_name, &val);
if (ret)
return ret;
shift_sel = FIELD_GET(AN8855_SWITCH_EFUSE_R50O, val);
for (i = 0; i < ARRAY_SIZE(dsa_r50ohm_table); i++)
if (dsa_r50ohm_table[i] == shift_sel)
break;
if (i < 8 || i >= ARRAY_SIZE(dsa_r50ohm_table))
*dest = dsa_r50ohm_table[25];
else
*dest = dsa_r50ohm_table[i - 8];
return 0;
}
static int an8855_probe(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
struct device_node *node = dev->of_node;
struct air_an8855_priv *priv;
/* If we don't have a node, skip calib */
if (!node)
return 0;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
phydev->priv = priv;
return 0;
}
static int an8855_get_downshift(struct phy_device *phydev, u8 *data)
{
int val;
val = phy_read_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, AN8855_PHY_EXT_REG_14);
if (val < 0)
return val;
*data = val & AN8855_PHY_EN_DOWN_SHIFT ? DOWNSHIFT_DEV_DEFAULT_COUNT :
DOWNSHIFT_DEV_DISABLE;
return 0;
}
static int an8855_set_downshift(struct phy_device *phydev, u8 cnt)
{
u16 ds = cnt != DOWNSHIFT_DEV_DISABLE ? AN8855_PHY_EN_DOWN_SHIFT : 0;
return phy_modify_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1,
AN8855_PHY_EXT_REG_14, AN8855_PHY_EN_DOWN_SHIFT,
ds);
}
static int an8855_config_init(struct phy_device *phydev)
{
struct air_an8855_priv *priv = phydev->priv;
struct device *dev = &phydev->mdio.dev;
int ret;
/* Enable HW auto downshift */
ret = an8855_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT);
if (ret)
return ret;
/* Apply calibration values, if needed.
* AN8855_PHY_FLAGS_EN_CALIBRATION signal this.
*/
if (priv && phydev->dev_flags & AN8855_PHY_FLAGS_EN_CALIBRATION) {
u8 *calibration_data = priv->calibration_data;
ret = en8855_get_r50ohm_val(dev, "tx_a", &calibration_data[0]);
if (ret)
return ret;
ret = en8855_get_r50ohm_val(dev, "tx_b", &calibration_data[1]);
if (ret)
return ret;
ret = en8855_get_r50ohm_val(dev, "tx_c", &calibration_data[2]);
if (ret)
return ret;
ret = en8855_get_r50ohm_val(dev, "tx_d", &calibration_data[3]);
if (ret)
return ret;
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R500HM_RSEL_TX_AB,
AN8855_PHY_R50OHM_RSEL_TX_A | AN8855_PHY_R50OHM_RSEL_TX_B,
FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_A, calibration_data[0]) |
FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_B, calibration_data[1]));
if (ret)
return ret;
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R500HM_RSEL_TX_CD,
AN8855_PHY_R50OHM_RSEL_TX_C | AN8855_PHY_R50OHM_RSEL_TX_D,
FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_C, calibration_data[2]) |
FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_D, calibration_data[3]));
if (ret)
return ret;
}
/* Apply values to reduce signal noise */
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_TX_PAIR_DLY_SEL_GBE,
FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_A_GBE, 0x4) |
FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELKAY_SEL_C_GBE, 0x4));
if (ret)
return ret;
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_CTRL,
AN8855_PHY_RG_AD_SAMNPLE_PHSEL_A |
AN8855_PHY_RG_AD_SAMNPLE_PHSEL_C);
if (ret)
return ret;
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_0,
FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_A, 0x1));
if (ret)
return ret;
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_1,
FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_C, 0x1));
if (ret)
return ret;
return 0;
}
static int an8855_get_tunable(struct phy_device *phydev,
struct ethtool_tunable *tuna, void *data)
{
switch (tuna->id) {
case ETHTOOL_PHY_DOWNSHIFT:
return an8855_get_downshift(phydev, data);
default:
return -EOPNOTSUPP;
}
}
static int an8855_set_tunable(struct phy_device *phydev,
struct ethtool_tunable *tuna, const void *data)
{
switch (tuna->id) {
case ETHTOOL_PHY_DOWNSHIFT:
return an8855_set_downshift(phydev, *(const u8 *)data);
default:
return -EOPNOTSUPP;
}
}
static int an8855_read_page(struct phy_device *phydev)
{
return __phy_read(phydev, AN8855_PHY_SELECT_PAGE);
}
static int an8855_write_page(struct phy_device *phydev, int page)
{
return __phy_write(phydev, AN8855_PHY_SELECT_PAGE, page);
}
static struct phy_driver an8855_driver[] = {
{
PHY_ID_MATCH_EXACT(AN8855_PHY_ID),
.name = "Airoha AN8855 internal PHY",
/* PHY_GBIT_FEATURES */
.flags = PHY_IS_INTERNAL,
.probe = an8855_probe,
.config_init = an8855_config_init,
.soft_reset = genphy_soft_reset,
.get_tunable = an8855_get_tunable,
.set_tunable = an8855_set_tunable,
.suspend = genphy_suspend,
.resume = genphy_resume,
.read_page = an8855_read_page,
.write_page = an8855_write_page,
}, };
module_phy_driver(an8855_driver);
static struct mdio_device_id __maybe_unused an8855_tbl[] = {
{ PHY_ID_MATCH_EXACT(AN8855_PHY_ID) },
{ }
};
MODULE_DEVICE_TABLE(mdio, an8855_tbl);
MODULE_DESCRIPTION("Airoha AN8855 PHY driver");
MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
MODULE_LICENSE("GPL");

63
lede/target/linux/mediatek/files-6.12/drivers/nvmem/an8855-efuse.c Normal file
View File

@@ -0,0 +1,63 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Airoha AN8855 Switch EFUSE Driver
*/
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/nvmem-provider.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#define AN8855_EFUSE_CELL 50
#define AN8855_EFUSE_DATA0 0x1000a500
#define AN8855_EFUSE_R50O GENMASK(30, 24)
static int an8855_efuse_read(void *context, unsigned int offset,
void *val, size_t bytes)
{
struct regmap *regmap = context;
return regmap_bulk_read(regmap, AN8855_EFUSE_DATA0 + offset,
val, bytes / sizeof(u32));
}
static int an8855_efuse_probe(struct platform_device *pdev)
{
struct nvmem_config an8855_nvmem_config = {
.name = "an8855-efuse",
.size = AN8855_EFUSE_CELL * sizeof(u32),
.stride = sizeof(u32),
.word_size = sizeof(u32),
.reg_read = an8855_efuse_read,
};
struct device *dev = &pdev->dev;
struct nvmem_device *nvmem;
/* Assign NVMEM priv to MFD regmap */
an8855_nvmem_config.priv = dev_get_regmap(dev->parent, NULL);
an8855_nvmem_config.dev = dev;
nvmem = devm_nvmem_register(dev, &an8855_nvmem_config);
return PTR_ERR_OR_ZERO(nvmem);
}
static const struct of_device_id an8855_efuse_of_match[] = {
{ .compatible = "airoha,an8855-efuse", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, an8855_efuse_of_match);
static struct platform_driver an8855_efuse_driver = {
.probe = an8855_efuse_probe,
.driver = {
.name = "an8855-efuse",
.of_match_table = an8855_efuse_of_match,
},
};
module_platform_driver(an8855_efuse_driver);
MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
MODULE_DESCRIPTION("Driver for AN8855 Switch EFUSE");
MODULE_LICENSE("GPL");

41
lede/target/linux/mediatek/files-6.12/include/linux/mfd/airoha-an8855-mfd.h Normal file
View File

@@ -0,0 +1,41 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* MFD driver for Airoha AN8855 Switch
*/
#ifndef _LINUX_INCLUDE_MFD_AIROHA_AN8855_MFD_H
#define _LINUX_INCLUDE_MFD_AIROHA_AN8855_MFD_H
#include <linux/bitfield.h>
/* MII Registers */
#define AN8855_PHY_SELECT_PAGE 0x1f
#define AN8855_PHY_PAGE GENMASK(2, 0)
#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)
#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)
#define AN8855_PHY_PAGE_EXTENDED_4 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x4)
/* MII Registers Page 4 */
#define AN8855_PBUS_MODE 0x10
#define AN8855_PBUS_MODE_ADDR_FIXED 0x0
#define AN8855_PBUS_MODE_ADDR_INCR BIT(15)
#define AN8855_PBUS_WR_ADDR_HIGH 0x11
#define AN8855_PBUS_WR_ADDR_LOW 0x12
#define AN8855_PBUS_WR_DATA_HIGH 0x13
#define AN8855_PBUS_WR_DATA_LOW 0x14
#define AN8855_PBUS_RD_ADDR_HIGH 0x15
#define AN8855_PBUS_RD_ADDR_LOW 0x16
#define AN8855_PBUS_RD_DATA_HIGH 0x17
#define AN8855_PBUS_RD_DATA_LOW 0x18
struct an8855_mfd_priv {
struct device *dev;
struct mii_bus *bus;
unsigned int switch_addr;
u16 current_page;
};
int an8855_mii_set_page(struct an8855_mfd_priv *priv, u8 phy_id,
u8 page);
#endif

8
lede/target/linux/mediatek/filogic/base-files/etc/board.d/02_network
View File

@@ -61,6 +61,9 @@ mediatek_setup_interfaces()
hf,m7986r1*)
ucidef_set_interfaces_lan_wan "lan2 lan3 lan4" "lan1 usb0"
;;
huasifei,ws3006*)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan"
;;
mediatek,mt7986a-rfb|\
mediatek,mt7986b-rfb)
ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" eth1
@@ -128,6 +131,11 @@ mediatek_setup_macs()
lan_mac=$(macaddr_add "$wan_mac" 1)
label_mac=$wan_mac
;;
huasifei,ws3006)
wifi_mac=$(mtd_get_mac_binary Factory 0x4)
lan_mac=$(macaddr_add "$wifi_mac" 1)
wan_mac=$(macaddr_add "$wifi_mac" 2)
;;
imou,lc-hx3001)
lan_mac=$(mtd_get_mac_ascii u-boot-env mac)
wan_mac=$(macaddr_add "$lan_mac" 2)

5
lede/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
View File

@@ -61,6 +61,11 @@ case "$board" in
[ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
;;
huasifei,ws3006)
addr=$(mtd_get_mac_binary_ubi Factory 0x04)
[ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress
;;
imou,lc-hx3001)
addr=$(mtd_get_mac_ascii u-boot-env mac)
[ "$PHYNBR" = "0" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress

532
lede/target/linux/mediatek/filogic/config-6.12 Normal file
View File

@@ -0,0 +1,532 @@
CONFIG_64BIT=y
# CONFIG_AHCI_MTK is not set
CONFIG_AIROHA_EN8801SC_PHY=y
CONFIG_AIR_AN8855_PHY=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_FORCE_MAX_ORDER=10
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PKEY_BITS=3
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_WANTS_EXECMEM_LATE=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PLATFORM_DEVICES=y
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_VA_BITS_39=y
# CONFIG_ARM64_VA_BITS_52 is not set
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_MEDIATEK_CPUFREQ=y
CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=y
CONFIG_ARM_PMU=y
CONFIG_ARM_PMUV3=y
CONFIG_ARM_PSCI_FW=y
CONFIG_ATA=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_NOTIFIERS=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_BUFFER_HEAD=y
CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE_OVERRIDE=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_MEDIATEK=y
# CONFIG_COMMON_CLK_MT2712 is not set
# CONFIG_COMMON_CLK_MT6779 is not set
# CONFIG_COMMON_CLK_MT6795 is not set
# CONFIG_COMMON_CLK_MT6797 is not set
# CONFIG_COMMON_CLK_MT7622 is not set
CONFIG_COMMON_CLK_MT7981=y
CONFIG_COMMON_CLK_MT7981_ETHSYS=y
CONFIG_COMMON_CLK_MT7986=y
CONFIG_COMMON_CLK_MT7986_ETHSYS=y
CONFIG_COMMON_CLK_MT7988=y
# CONFIG_COMMON_CLK_MT8173 is not set
# CONFIG_COMMON_CLK_MT8183 is not set
# CONFIG_COMMON_CLK_MT8186 is not set
# CONFIG_COMMON_CLK_MT8195 is not set
# CONFIG_COMMON_CLK_MT8365 is not set
# CONFIG_COMMON_CLK_MT8516 is not set
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
# CONFIG_COMPAT_32BIT_TIME is not set
# CONFIG_COMPRESSED_INSTALL is not set
CONFIG_CONFIGFS_FS=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_CPU_FREQ=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MITIGATIONS=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_THERMAL=y
CONFIG_CRC16=y
CONFIG_CRC_CCITT=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32
CONFIG_CRYPTO_JITTERENTROPY_OSR=1
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y
CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_MISC=y
CONFIG_DEVFREQ_GOV_PASSIVE=y
# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
# CONFIG_DEVFREQ_GOV_USERSPACE is not set
# CONFIG_DEVFREQ_THERMAL is not set
CONFIG_DMADEVICES=y
CONFIG_DMATEST=y
CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_ENGINE_RAID=y
CONFIG_DMA_NEED_SYNC=y
CONFIG_DMA_OF=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EINT_MTK=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_EXT4_FS=y
CONFIG_F2FS_FS=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FRAME_POINTER=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FUNCTION_ALIGNMENT=4
CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_DEVICES=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GLOB=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
CONFIG_GRO_CELLS=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
# CONFIG_HISILICON_ERRATUM_162100801 is not set
CONFIG_HWMON=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MTK=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MT65XX=y
CONFIG_ICPLUS_PHY=y
# CONFIG_IDPF is not set
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_MSI_LIB=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
CONFIG_JUMP_LABEL=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_SMARTRG_LED=y
CONFIG_LEDS_TRIGGER_PATTERN=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LRU_GEN_WALKS_MMU=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAXLINEAR_GPHY=y
CONFIG_MDIO_AN8855=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MEDIATEK_2P5GE_PHY=y
CONFIG_MEDIATEK_GE_PHY=y
CONFIG_MEDIATEK_GE_SOC_PHY=y
CONFIG_MEDIATEK_WATCHDOG=y
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
CONFIG_MFD_AIROHA_AN8855=y
CONFIG_MFD_CORE=y
CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_MTK=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_MEDIATEK=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_MTK=y
CONFIG_MTD_NAND_MTK_BMT=y
CONFIG_MTD_PARSER_TRX=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_NVMEM=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_VIRT_CONCAT=y
# CONFIG_MTK_CMDQ is not set
CONFIG_MTK_CPUX_TIMER=y
# CONFIG_MTK_CQDMA is not set
CONFIG_MTK_HSDMA=y
CONFIG_MTK_INFRACFG=y
CONFIG_MTK_LVTS_THERMAL=y
CONFIG_MTK_LVTS_THERMAL_DEBUGFS=y
CONFIG_MTK_NET_PHYLIB=y
CONFIG_MTK_PMIC_WRAP=y
CONFIG_MTK_REGULATOR_COUPLER=y
CONFIG_MTK_SCPSYS=y
CONFIG_MTK_SCPSYS_PM_DOMAINS=y
# CONFIG_MTK_SOCINFO is not set
CONFIG_MTK_SOC_THERMAL=y
# CONFIG_MTK_SVS is not set
CONFIG_MTK_THERMAL=y
CONFIG_MTK_TIMER=y
# CONFIG_MTK_UART_APDMA is not set
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_LENGTH=y
# CONFIG_NET_AIROHA is not set
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_AN8855=y
CONFIG_NET_DSA_MT7530=y
CONFIG_NET_DSA_MT7530_MDIO=y
CONFIG_NET_DSA_MT7530_MMIO=y
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_EGRESS=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_INGRESS=y
CONFIG_NET_MEDIATEK_SOC=y
CONFIG_NET_MEDIATEK_SOC_WED=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_VENDOR_MEDIATEK=y
CONFIG_NET_XGRESS=y
CONFIG_NLS=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
CONFIG_NVMEM_AN8855_EFUSE=y
CONFIG_NVMEM_BLOCK=y
CONFIG_NVMEM_LAYOUTS=y
CONFIG_NVMEM_LAYOUT_ADTRAN=y
CONFIG_NVMEM_MTK_EFUSE=y
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_RESOLVE=y
CONFIG_PADATA=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEASPM=y
# CONFIG_PCIEASPM_DEFAULT is not set
CONFIG_PCIEASPM_PERFORMANCE=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
# CONFIG_PCIE_MEDIATEK is not set
CONFIG_PCIE_MEDIATEK_GEN3=y
CONFIG_PCIE_PME=y
CONFIG_PCI_DEBUG=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCS_MTK_LYNXI=y
CONFIG_PCS_MTK_USXGMII=y
CONFIG_PERF_EVENTS=y
CONFIG_PER_VMA_LOCK=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYLIB=y
CONFIG_PHYLIB_LEDS=y
CONFIG_PHYLINK=y
CONFIG_PHYS_ADDR_T_64BIT=y
# CONFIG_PHY_MTK_DP is not set
# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set
# CONFIG_PHY_MTK_PCIE is not set
CONFIG_PHY_MTK_TPHY=y
# CONFIG_PHY_MTK_UFS is not set
CONFIG_PHY_MTK_XFI_TPHY=y
CONFIG_PHY_MTK_XSPHY=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_MT2712 is not set
# CONFIG_PINCTRL_MT6765 is not set
# CONFIG_PINCTRL_MT6795 is not set
# CONFIG_PINCTRL_MT6797 is not set
# CONFIG_PINCTRL_MT7622 is not set
CONFIG_PINCTRL_MT7981=y
CONFIG_PINCTRL_MT7986=y
CONFIG_PINCTRL_MT7988=y
# CONFIG_PINCTRL_MT8173 is not set
# CONFIG_PINCTRL_MT8183 is not set
# CONFIG_PINCTRL_MT8186 is not set
# CONFIG_PINCTRL_MT8188 is not set
# CONFIG_PINCTRL_MT8516 is not set
CONFIG_PINCTRL_MTK_MOORE=y
CONFIG_PINCTRL_MTK_V2=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_PM_OPP=y
CONFIG_POLYNOMIAL=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_SUPPLY=y
CONFIG_PRINTK_TIME=y
CONFIG_PSTORE=y
CONFIG_PSTORE_COMPRESS=y
CONFIG_PSTORE_CONSOLE=y
CONFIG_PSTORE_PMSG=y
CONFIG_PSTORE_RAM=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PWM=y
CONFIG_PWM_MEDIATEK=y
# CONFIG_PWM_MTK_DISP is not set
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
# CONFIG_RAVE_SP_CORE is not set
CONFIG_REALTEK_PHY=y
CONFIG_REALTEK_PHY_HWMON=y
CONFIG_REED_SOLOMON=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_MT6380=y
CONFIG_REGULATOR_RT5190A=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_TI_SYSCON=y
CONFIG_RFS_ACCEL=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_MT7622=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTL8261N_PHY=y
# CONFIG_RTL8367S_GSW is not set
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SCHED_MC=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SGL_ALLOC=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOC_BUS=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_DYNAMIC=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_MT65XX=y
# CONFIG_SPI_MTK_NOR is not set
CONFIG_SPI_MTK_SNFI=y
CONFIG_SPLIT_PMD_PTLOCKS=y
CONFIG_SPLIT_PTE_PTLOCKS=y
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
CONFIG_SWIOTLB=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
# CONFIG_TEST_FPU is not set
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_BANG_BANG=y
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
# CONFIG_UCLAMP_TASK is not set
CONFIG_UIMAGE_FIT_BLK=y
# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
CONFIG_USB_SUPPORT=y
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_VDSO_GETRANDOM=y
CONFIG_VMAP_STACK=y
CONFIG_WATCHDOG_CORE=y
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
CONFIG_WATCHDOG_SYSFS=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZONE_DMA32=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

60
lede/target/linux/mediatek/image/filogic.mk
View File

@@ -363,21 +363,6 @@ define Device/cmcc_xr30-nand
endef
TARGET_DEVICES += cmcc_xr30-nand
define Device/cudy_tr3000-mod
DEVICE_VENDOR := Cudy
DEVICE_MODEL := TR3000
DEVICE_VARIANT := (U-Boot mod)
DEVICE_DTS := mt7981b-cudy-tr3000-mod
DEVICE_DTS_DIR := ../dts
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
KERNEL_IN_UBI := 1
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
DEVICE_PACKAGES := kmod-usb3 kmod-mt7981-firmware mt7981-wo-firmware
endef
TARGET_DEVICES += cudy_tr3000-mod
define Device/cudy_tr3000-v1
DEVICE_VENDOR := Cudy
DEVICE_MODEL := TR3000
@@ -395,6 +380,36 @@ define Device/cudy_tr3000-v1
endef
TARGET_DEVICES += cudy_tr3000-v1
define Device/cudy_tr3000-mod
DEVICE_VENDOR := Cudy
DEVICE_MODEL := TR3000
DEVICE_VARIANT := v1 (U-Boot mod)
DEVICE_DTS := mt7981b-cudy-tr3000-mod
DEVICE_DTS_DIR := ../dts
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
KERNEL_IN_UBI := 1
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
DEVICE_PACKAGES := kmod-usb3 kmod-mt7981-firmware mt7981-wo-firmware
endef
TARGET_DEVICES += cudy_tr3000-mod
define Device/cudy_tr3000-v2-mod
DEVICE_VENDOR := Cudy
DEVICE_MODEL := TR3000
DEVICE_VARIANT := v2 256MB (U-Boot mod)
DEVICE_DTS := mt7981b-cudy-tr3000-v2-mod
DEVICE_DTS_DIR := ../dts
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
KERNEL_IN_UBI := 1
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
DEVICE_PACKAGES := kmod-usb3 kmod-mt7981-firmware mt7981-wo-firmware
endef
TARGET_DEVICES += cudy_tr3000-v2-mod
define Device/fzs_5gcpe-p3
DEVICE_VENDOR := FZS
DEVICE_MODEL := 5GCPE P3
@@ -503,6 +518,21 @@ define Device/huasifei_wh3000-emmc
endef
TARGET_DEVICES += huasifei_wh3000-emmc
define Device/huasifei_ws3006
DEVICE_VENDOR := Huasifei
DEVICE_MODEL := WS3006
DEVICE_DTS := mt7981b-huasifei-ws3006
DEVICE_DTS_DIR := ../dts
DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGE_SIZE := 112640k
KERNEL_IN_UBI := 1
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
endef
TARGET_DEVICES += huasifei_ws3006
define Device/hf_m7986r1-emmc
DEVICE_VENDOR := HF
DEVICE_MODEL := M7986R1 (eMMC)

516
lede/target/linux/mediatek/mt7622/config-6.12 Normal file
View File

@@ -0,0 +1,516 @@
CONFIG_64BIT=y
# CONFIG_AHCI_MTK is not set
# CONFIG_AIROHA_EN8801SC_PHY is not set
# CONFIG_AIR_AN8855_PHY is not set
CONFIG_AQUANTIA_PHY=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_FORCE_MAX_ORDER=10
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PKEY_BITS=3
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_WANTS_EXECMEM_LATE=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PLATFORM_DEVICES=y
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_VA_BITS_39=y
# CONFIG_ARM64_VA_BITS_52 is not set
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_MEDIATEK_CPUFREQ=y
CONFIG_ARM_PMU=y
CONFIG_ARM_PMUV3=y
CONFIG_ARM_PSCI_FW=y
CONFIG_ATA=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_NOTIFIERS=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_BUFFER_HEAD=y
CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLONE_BACKWARDS=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_MEDIATEK=y
CONFIG_COMMON_CLK_MT2712=y
# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set
# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set
# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set
# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set
# CONFIG_COMMON_CLK_MT2712_MMSYS is not set
# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set
# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set
# CONFIG_COMMON_CLK_MT6779 is not set
# CONFIG_COMMON_CLK_MT6795 is not set
# CONFIG_COMMON_CLK_MT6797 is not set
CONFIG_COMMON_CLK_MT7622=y
CONFIG_COMMON_CLK_MT7622_AUDSYS=y
CONFIG_COMMON_CLK_MT7622_ETHSYS=y
CONFIG_COMMON_CLK_MT7622_HIFSYS=y
# CONFIG_COMMON_CLK_MT7981 is not set
# CONFIG_COMMON_CLK_MT7986 is not set
# CONFIG_COMMON_CLK_MT7988 is not set
# CONFIG_COMMON_CLK_MT8173 is not set
# CONFIG_COMMON_CLK_MT8183 is not set
# CONFIG_COMMON_CLK_MT8186 is not set
# CONFIG_COMMON_CLK_MT8195 is not set
# CONFIG_COMMON_CLK_MT8365 is not set
# CONFIG_COMMON_CLK_MT8516 is not set
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
# CONFIG_COMPRESSED_INSTALL is not set
CONFIG_CONFIGFS_FS=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MITIGATIONS=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_THERMAL=y
CONFIG_CRC16=y
CONFIG_CRC_CCITT=y
CONFIG_CRC_ITU_T=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_ECC=y
CONFIG_CRYPTO_ECDH=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32
CONFIG_CRYPTO_JITTERENTROPY_OSR=1
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y
CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_MISC=y
CONFIG_DMADEVICES=y
CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_NEED_SYNC=y
CONFIG_DMA_OF=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EINT_MTK=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_EXT4_FS=y
CONFIG_F2FS_FS=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FRAME_POINTER=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FUNCTION_ALIGNMENT=4
CONFIG_FUNCTION_ALIGNMENT_4B=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_DEVICES=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GLOB=y
CONFIG_GPIO_CDEV=y
CONFIG_GRO_CELLS=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
# CONFIG_HISILICON_ERRATUM_162100801 is not set
CONFIG_HWMON=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MTK=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MT65XX=y
CONFIG_ICPLUS_PHY=y
# CONFIG_IDPF is not set
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INTEL_XWAY_PHY=y
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_MSI_LIB=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
CONFIG_JUMP_LABEL=y
CONFIG_LEDS_SMARTRG_LED=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LRU_GEN_WALKS_MMU=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAXLINEAR_GPHY=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
# CONFIG_MEDIATEK_2P5GE_PHY is not set
CONFIG_MEDIATEK_GE_PHY=y
# CONFIG_MEDIATEK_GE_SOC_PHY is not set
CONFIG_MEDIATEK_WATCHDOG=y
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
# CONFIG_MFD_AIROHA_AN8855 is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_MTK=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_MEDIATEK=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_MTK=y
CONFIG_MTD_NAND_MTK_BMT=y
CONFIG_MTD_PARSER_TRX=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_NVMEM=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
# CONFIG_MTK_CMDQ is not set
CONFIG_MTK_CPUX_TIMER=y
# CONFIG_MTK_CQDMA is not set
CONFIG_MTK_HSDMA=y
CONFIG_MTK_INFRACFG=y
# CONFIG_MTK_LVTS_THERMAL is not set
CONFIG_MTK_NET_PHYLIB=y
CONFIG_MTK_PMIC_WRAP=y
CONFIG_MTK_REGULATOR_COUPLER=y
CONFIG_MTK_SCPSYS=y
CONFIG_MTK_SCPSYS_PM_DOMAINS=y
CONFIG_MTK_SOCINFO=y
CONFIG_MTK_SOC_THERMAL=y
# CONFIG_MTK_SVS is not set
CONFIG_MTK_THERMAL=y
CONFIG_MTK_TIMER=y
# CONFIG_MTK_UART_APDMA is not set
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_LENGTH=y
# CONFIG_NET_AIROHA is not set
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MT7530=y
CONFIG_NET_DSA_MT7530_MDIO=y
# CONFIG_NET_DSA_MT7530_MMIO is not set
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_EGRESS=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_INGRESS=y
CONFIG_NET_MEDIATEK_SOC=y
CONFIG_NET_MEDIATEK_SOC_WED=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_VENDOR_MEDIATEK=y
CONFIG_NET_XGRESS=y
CONFIG_NLS=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=2
CONFIG_NVMEM=y
CONFIG_NVMEM_BLOCK=y
CONFIG_NVMEM_LAYOUTS=y
CONFIG_NVMEM_LAYOUT_ADTRAN=y
CONFIG_NVMEM_MTK_EFUSE=y
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_RESOLVE=y
CONFIG_PADATA=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEASPM=y
# CONFIG_PCIEASPM_DEFAULT is not set
CONFIG_PCIEASPM_PERFORMANCE=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_MEDIATEK=y
CONFIG_PCIE_PME=y
CONFIG_PCI_DEBUG=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCS_MTK_LYNXI=y
CONFIG_PERF_EVENTS=y
CONFIG_PER_VMA_LOCK=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYLIB=y
CONFIG_PHYLIB_LEDS=y
CONFIG_PHYLINK=y
CONFIG_PHYS_ADDR_T_64BIT=y
# CONFIG_PHY_MTK_DP is not set
# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set
# CONFIG_PHY_MTK_PCIE is not set
CONFIG_PHY_MTK_TPHY=y
# CONFIG_PHY_MTK_UFS is not set
# CONFIG_PHY_MTK_XSPHY is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_MT2712 is not set
# CONFIG_PINCTRL_MT6765 is not set
# CONFIG_PINCTRL_MT6795 is not set
# CONFIG_PINCTRL_MT6797 is not set
CONFIG_PINCTRL_MT7622=y
# CONFIG_PINCTRL_MT7981 is not set
# CONFIG_PINCTRL_MT7986 is not set
# CONFIG_PINCTRL_MT7988 is not set
# CONFIG_PINCTRL_MT8173 is not set
# CONFIG_PINCTRL_MT8183 is not set
# CONFIG_PINCTRL_MT8186 is not set
# CONFIG_PINCTRL_MT8188 is not set
# CONFIG_PINCTRL_MT8516 is not set
CONFIG_PINCTRL_MTK_MOORE=y
CONFIG_PINCTRL_MTK_V2=y
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_PM_OPP=y
CONFIG_POLYNOMIAL=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_SUPPLY=y
CONFIG_PRINTK_TIME=y
CONFIG_PSTORE=y
CONFIG_PSTORE_COMPRESS=y
CONFIG_PSTORE_CONSOLE=y
CONFIG_PSTORE_PMSG=y
CONFIG_PSTORE_RAM=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PWM=y
CONFIG_PWM_MEDIATEK=y
# CONFIG_PWM_MTK_DISP is not set
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
# CONFIG_RAVE_SP_CORE is not set
CONFIG_REALTEK_PHY=y
CONFIG_REALTEK_PHY_HWMON=y
CONFIG_REED_SOLOMON=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_MT6380=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RFS_ACCEL=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_MT7622=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTL8367S_GSW=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SCHED_MC=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SGL_ALLOC=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOC_BUS=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_DYNAMIC=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_MT65XX=y
CONFIG_SPI_MTK_NOR=y
CONFIG_SPI_MTK_SNFI=y
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
CONFIG_SWCONFIG=y
CONFIG_SWIOTLB=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
# CONFIG_TEST_FPU is not set
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_EMULATION=y
CONFIG_THERMAL_GOV_BANG_BANG=y
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
# CONFIG_UCLAMP_TASK is not set
CONFIG_UIMAGE_FIT_BLK=y
# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
CONFIG_USB_SUPPORT=y
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_VDSO_GETRANDOM=y
CONFIG_VMAP_STACK=y
CONFIG_WATCHDOG_CORE=y
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
CONFIG_WATCHDOG_SYSFS=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZONE_DMA32=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

670
lede/target/linux/mediatek/mt7623/config-6.12 Normal file
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@@ -0,0 +1,670 @@
# CONFIG_AIO is not set
# CONFIG_AIROHA_EN8801SC_PHY is not set
# CONFIG_AIR_AN8855_PHY is not set
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
# CONFIG_ARM_ATAG_DTB_COMPAT is not set
CONFIG_ARM_CPU_SUSPEND=y
# CONFIG_ARM_CPU_TOPOLOGY is not set
# CONFIG_ARM_DEBUG_WX is not set
CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8
CONFIG_ARM_DMA_USE_IOMMU=y
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_GROUP_RELOCS=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
# CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set
CONFIG_ARM_MEDIATEK_CPUFREQ=y
CONFIG_ARM_PAN=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
# CONFIG_ARM_SMMU is not set
CONFIG_ARM_THUMB=y
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
CONFIG_ATAGS=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GPIO=y
# CONFIG_BACKLIGHT_KTD2801 is not set
CONFIG_BACKLIGHT_LED=y
# CONFIG_BACKLIGHT_LM3509 is not set
# CONFIG_BACKLIGHT_MP3309C is not set
CONFIG_BACKLIGHT_PWM=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BOUNCE=y
CONFIG_BUFFER_HEAD=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2"
CONFIG_CMDLINE_FROM_BOOTLOADER=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_CMDLINE_PARTITION=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_MEDIATEK=y
CONFIG_COMMON_CLK_MT2701=y
CONFIG_COMMON_CLK_MT2701_AUDSYS=y
CONFIG_COMMON_CLK_MT2701_BDPSYS=y
CONFIG_COMMON_CLK_MT2701_ETHSYS=y
CONFIG_COMMON_CLK_MT2701_G3DSYS=y
CONFIG_COMMON_CLK_MT2701_HIFSYS=y
CONFIG_COMMON_CLK_MT2701_IMGSYS=y
CONFIG_COMMON_CLK_MT2701_MMSYS=y
CONFIG_COMMON_CLK_MT2701_VDECSYS=y
# CONFIG_COMMON_CLK_MT6795 is not set
# CONFIG_COMMON_CLK_MT7622 is not set
# CONFIG_COMMON_CLK_MT7629 is not set
# CONFIG_COMMON_CLK_MT7981 is not set
# CONFIG_COMMON_CLK_MT7986 is not set
# CONFIG_COMMON_CLK_MT7988 is not set
# CONFIG_COMMON_CLK_MT8135 is not set
# CONFIG_COMMON_CLK_MT8365 is not set
# CONFIG_COMMON_CLK_MT8516 is not set
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONFIGFS_FS=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_COREDUMP=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MITIGATIONS=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_GENIV=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32
CONFIG_CRYPTO_JITTERENTROPY_OSR=1
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_ALIGN_RODATA=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_GPIO=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
CONFIG_DEBUG_MISC=y
CONFIG_DEBUG_MT6589_UART0=y
# CONFIG_DEBUG_MT8127_UART0 is not set
# CONFIG_DEBUG_MT8135_UART3 is not set
CONFIG_DEBUG_PREEMPT=y
CONFIG_DEBUG_UART_8250=y
CONFIG_DEBUG_UART_8250_SHIFT=2
CONFIG_DEBUG_UART_PHYS=0x11004000
CONFIG_DEBUG_UART_VIRT=0xf1004000
# CONFIG_DEVFREQ_GOV_PASSIVE is not set
# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
# CONFIG_DEVFREQ_GOV_USERSPACE is not set
# CONFIG_DEVFREQ_THERMAL is not set
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_NEED_SYNC=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS_HELPERS=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DRM=y
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_BRIDGE_CONNECTOR=y
CONFIG_DRM_DISPLAY_CONNECTOR=y
# CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set
# CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER=y
CONFIG_DRM_DISPLAY_HELPER=y
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
CONFIG_DRM_GEM_DMA_HELPER=y
CONFIG_DRM_GEM_SHMEM_HELPER=y
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_LIMA=y
CONFIG_DRM_LVDS_CODEC=y
CONFIG_DRM_MEDIATEK=y
# CONFIG_DRM_MEDIATEK_DP is not set
CONFIG_DRM_MEDIATEK_HDMI=y
CONFIG_DRM_MIPI_DSI=y
CONFIG_DRM_PANEL=y
# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set
# CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 is not set
CONFIG_DRM_PANEL_BRIDGE=y
# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set
# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set
# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set
# CONFIG_DRM_PANEL_LG_SW43408 is not set
# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y
# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set
# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set
# CONFIG_DRM_PANIC is not set
# CONFIG_DRM_PANTHOR is not set
CONFIG_DRM_SCHED=y
CONFIG_DRM_SIMPLE_BRIDGE=y
# CONFIG_DRM_WERROR is not set
# CONFIG_DRM_XE is not set
CONFIG_DTC=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_EARLY_PRINTK=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EINT_MTK=y
CONFIG_ELF_CORE=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_EXT4_FS=y
CONFIG_EXTCON=y
CONFIG_F2FS_FS=y
CONFIG_FB=y
CONFIG_FB_CORE=y
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_DEVICE=y
CONFIG_FB_DMAMEM_HELPERS=y
CONFIG_FB_DMAMEM_HELPERS_DEFERRED=y
CONFIG_FB_SYSMEM_FOPS=y
CONFIG_FB_SYSMEM_HELPERS=y
CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_IMAGEBLIT=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FONT_8x16=y
CONFIG_FONT_8x8=y
CONFIG_FONT_SUPPORT=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_FREEZER=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FUNCTION_ALIGNMENT=0
CONFIG_FWNODE_MDIO=y
CONFIG_FW_CACHE=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_DEVICES=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GLOB=y
CONFIG_GPIO_CDEV=y
CONFIG_GRO_CELLS=y
# CONFIG_HARDEN_BRANCH_HISTORY is not set
# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HDMI=y
CONFIG_HID=y
CONFIG_HID_SUPPORT=y
CONFIG_HIGHMEM=y
CONFIG_HIGHPTE=y
CONFIG_HOTPLUG_CORE_SYNC=y
CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HWMON=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MTK=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MT65XX=y
CONFIG_ICPLUS_PHY=y
# CONFIG_IDPF is not set
CONFIG_IIO=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_KEYBOARD=y
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_IOMMUFD is not set
CONFIG_IOMMU_API=y
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
CONFIG_IOMMU_SUPPORT=y
CONFIG_IRQCHIP=y
CONFIG_IRQSTACKS=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
CONFIG_KALLSYMS=y
CONFIG_KCMP=y
CONFIG_KEYBOARD_MTK_PMIC=y
CONFIG_KMAP_LOCAL=y
CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=y
CONFIG_LEDS_MT6323=y
# CONFIG_LEDS_QCOM_LPG is not set
# CONFIG_LEDS_SMARTRG_LED is not set
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LOGO=y
CONFIG_LOGO_LINUX_CLUT224=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
# CONFIG_MACH_MT2701 is not set
# CONFIG_MACH_MT6589 is not set
# CONFIG_MACH_MT6592 is not set
CONFIG_MACH_MT7623=y
# CONFIG_MACH_MT7629 is not set
# CONFIG_MACH_MT8127 is not set
# CONFIG_MACH_MT8135 is not set
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAILBOX=y
# CONFIG_MAILBOX_TEST is not set
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_GPIO=y
CONFIG_MEDIATEK_GE_PHY=y
# CONFIG_MEDIATEK_MT6359_AUXADC is not set
CONFIG_MEDIATEK_MT6577_AUXADC=y
CONFIG_MEDIATEK_WATCHDOG=y
CONFIG_MEMORY=y
# CONFIG_MFD_AIROHA_AN8855 is not set
CONFIG_MFD_CORE=y
# CONFIG_MFD_HI6421_SPMI is not set
CONFIG_MFD_MT6397=y
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_MTK=y
CONFIG_MMC_SDHCI=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_CMDLINE_PARTS=y
# CONFIG_MTD_NAND_ECC_MEDIATEK is not set
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_UIMAGE_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
# CONFIG_MTK_ADSP_MBOX is not set
CONFIG_MTK_CMDQ=y
CONFIG_MTK_CMDQ_MBOX=y
CONFIG_MTK_CPUX_TIMER=y
CONFIG_MTK_CQDMA=y
# CONFIG_MTK_HSDMA is not set
CONFIG_MTK_INFRACFG=y
CONFIG_MTK_IOMMU=y
CONFIG_MTK_IOMMU_V1=y
# CONFIG_MTK_LVTS_THERMAL is not set
CONFIG_MTK_MMSYS=y
CONFIG_MTK_NET_PHYLIB=y
CONFIG_MTK_PMIC_WRAP=y
CONFIG_MTK_REGULATOR_COUPLER=y
CONFIG_MTK_SCPSYS=y
CONFIG_MTK_SCPSYS_PM_DOMAINS=y
CONFIG_MTK_SMI=y
CONFIG_MTK_SOCINFO=y
CONFIG_MTK_SOC_THERMAL=y
# CONFIG_MTK_SVS is not set
CONFIG_MTK_THERMAL=y
CONFIG_MTK_TIMER=y
# CONFIG_MTK_UART_APDMA is not set
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_SRCU_NMI_SAFE=y
CONFIG_NEON=y
# CONFIG_NET_AIROHA is not set
CONFIG_NET_DEVLINK=y
CONFIG_NET_DEVMEM=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MT7530=y
CONFIG_NET_DSA_MT7530_MDIO=y
# CONFIG_NET_DSA_MT7530_MMIO is not set
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_EGRESS=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_INGRESS=y
CONFIG_NET_MEDIATEK_SOC=y
CONFIG_NET_MEDIATEK_SOC_WED=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_VENDOR_MEDIATEK=y
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_NET_XGRESS=y
CONFIG_NLS=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
CONFIG_NVMEM_LAYOUTS=y
# CONFIG_NVMEM_LAYOUT_ADTRAN is not set
CONFIG_NVMEM_MTK_EFUSE=y
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IOMMU=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_RESOLVE=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_MEDIATEK=y
CONFIG_PCIE_PME=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCS_MTK_LYNXI=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PER_VMA_LOCK=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLIB_LEDS=y
CONFIG_PHYLINK=y
# CONFIG_PHY_MTK_DP is not set
CONFIG_PHY_MTK_HDMI=y
# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set
CONFIG_PHY_MTK_MIPI_DSI=y
# CONFIG_PHY_MTK_PCIE is not set
CONFIG_PHY_MTK_TPHY=y
# CONFIG_PHY_MTK_UFS is not set
# CONFIG_PHY_MTK_XSPHY is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MT2701=y
# CONFIG_PINCTRL_MT6397 is not set
CONFIG_PINCTRL_MT7623=y
CONFIG_PINCTRL_MTK=y
CONFIG_PINCTRL_MTK_MOORE=y
CONFIG_PINCTRL_MTK_V2=y
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_DEVFREQ=y
# CONFIG_PM_DEVFREQ_EVENT is not set
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
CONFIG_PM_OPP=y
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_MT6323 is not set
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_SUPPLY_HWMON=y
CONFIG_PREEMPT=y
CONFIG_PREEMPTION=y
CONFIG_PREEMPT_BUILD=y
CONFIG_PREEMPT_COUNT=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_RCU=y
CONFIG_PRINTK_TIME=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PWM=y
CONFIG_PWM_MEDIATEK=y
# CONFIG_PWM_MTK_DISP is not set
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_MT6323=y
# CONFIG_REGULATOR_MT6331 is not set
# CONFIG_REGULATOR_MT6332 is not set
# CONFIG_REGULATOR_MT6357 is not set
# CONFIG_REGULATOR_MT6358 is not set
# CONFIG_REGULATOR_MT6380 is not set
# CONFIG_REGULATOR_MT6397 is not set
# CONFIG_REGULATOR_QCOM_LABIBB is not set
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
CONFIG_RESET_CONTROLLER=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_DRV_MT6397 is not set
# CONFIG_RTC_DRV_MT7622 is not set
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
# CONFIG_RTL8367S_GSW is not set
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SERIAL_8250_DMA is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
# CONFIG_SMP_ON_UP is not set
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOC_BUS=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_DYNAMIC=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_MT65XX=y
# CONFIG_SPI_MTK_NOR is not set
CONFIG_SPLIT_PTE_PTLOCKS=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
# CONFIG_SPMI_MTK_PMIF is not set
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYNC_FILE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_OF=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TOUCHSCREEN_EDT_FT5X06=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_UIMAGE_FIT_BLK=y
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_F_ACM=y
CONFIG_USB_F_ECM=y
CONFIG_USB_F_MASS_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GPIO_VBUS=y
CONFIG_USB_G_MULTI=y
CONFIG_USB_G_MULTI_CDC=y
# CONFIG_USB_G_MULTI_RNDIS is not set
CONFIG_USB_HID=y
CONFIG_USB_HIDDEV=y
CONFIG_USB_INVENTRA_DMA=y
CONFIG_USB_LIBCOMPOSITE=y
CONFIG_USB_MUSB_DUAL_ROLE=y
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_MEDIATEK=y
CONFIG_USB_OTG=y
CONFIG_USB_PHY=y
CONFIG_USB_ROLE_SWITCH=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_U_ETHER=y
CONFIG_USB_U_SERIAL=y
CONFIG_USE_OF=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_VIDEO=y
CONFIG_VIDEOMODE_HELPERS=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

366
lede/target/linux/mediatek/mt7629/config-6.12 Normal file
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@@ -0,0 +1,366 @@
# CONFIG_AIROHA_EN8801SC_PHY is not set
# CONFIG_AIR_AN8855_PHY is not set
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
# CONFIG_ARM_DEBUG_WX is not set
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_GROUP_RELOCS=y
CONFIG_ARM_HEAVY_MB=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_PAN=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_ATAGS=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_CACHE_L2X0=y
CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_CHR_DEV_SCH=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
CONFIG_CMDLINE_FROM_BOOTLOADER=y
CONFIG_CMDLINE_OVERRIDE=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_MEDIATEK=y
# CONFIG_COMMON_CLK_MT2701 is not set
# CONFIG_COMMON_CLK_MT6795 is not set
# CONFIG_COMMON_CLK_MT7622 is not set
CONFIG_COMMON_CLK_MT7629=y
CONFIG_COMMON_CLK_MT7629_ETHSYS=y
CONFIG_COMMON_CLK_MT7629_HIFSYS=y
# CONFIG_COMMON_CLK_MT7981 is not set
# CONFIG_COMMON_CLK_MT7986 is not set
# CONFIG_COMMON_CLK_MT7988 is not set
# CONFIG_COMMON_CLK_MT8135 is not set
# CONFIG_COMMON_CLK_MT8365 is not set
# CONFIG_COMMON_CLK_MT8516 is not set
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MITIGATIONS=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_DEBUG_MISC=y
CONFIG_DEFAULT_HOSTNAME="(mt7629)"
CONFIG_DMA_NEED_SYNC=y
CONFIG_DMA_OPS_HELPERS=y
CONFIG_DTC=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EINT_MTK=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FS_IOMAP=y
CONFIG_FUNCTION_ALIGNMENT=0
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_DEVICES=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GPIO_CDEV=y
CONFIG_GRO_CELLS=y
# CONFIG_HARDEN_BRANCH_HISTORY is not set
# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HOTPLUG_CORE_SYNC=y
CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MTK=y
CONFIG_HZ_FIXED=0
# CONFIG_IDPF is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQSTACKS=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_IRQ_WORK=y
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
# CONFIG_MACH_MT2701 is not set
# CONFIG_MACH_MT6589 is not set
# CONFIG_MACH_MT6592 is not set
# CONFIG_MACH_MT7623 is not set
CONFIG_MACH_MT7629=y
# CONFIG_MACH_MT8127 is not set
# CONFIG_MACH_MT8135 is not set
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MEDIATEK_GE_PHY=y
CONFIG_MEDIATEK_WATCHDOG=y
# CONFIG_MFD_AIROHA_AN8855 is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_MEDIATEK=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_MTK_BMT=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
# CONFIG_MTK_CMDQ is not set
CONFIG_MTK_CPUX_TIMER=y
CONFIG_MTK_INFRACFG=y
CONFIG_MTK_NET_PHYLIB=y
# CONFIG_MTK_PMIC_WRAP is not set
CONFIG_MTK_SCPSYS=y
CONFIG_MTK_SCPSYS_PM_DOMAINS=y
CONFIG_MTK_TIMER=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SRCU_NMI_SAFE=y
CONFIG_NETFILTER=y
CONFIG_NETFILTER_BPF_LINK=y
# CONFIG_NET_AIROHA is not set
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MT7530=y
CONFIG_NET_DSA_MT7530_MDIO=y
# CONFIG_NET_DSA_MT7530_MMIO is not set
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_EGRESS=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_INGRESS=y
CONFIG_NET_MEDIATEK_SOC=y
CONFIG_NET_MEDIATEK_SOC_WED=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_VENDOR_MEDIATEK=y
CONFIG_NET_XGRESS=y
CONFIG_NLS=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=2
CONFIG_NVMEM=y
CONFIG_NVMEM_LAYOUTS=y
# CONFIG_NVMEM_LAYOUT_ADTRAN is not set
# CONFIG_NVMEM_MTK_EFUSE is not set
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_MEDIATEK=y
CONFIG_PCIE_PME=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCS_MTK_LYNXI=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PER_VMA_LOCK=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLIB_LEDS=y
CONFIG_PHYLINK=y
# CONFIG_PHY_MTK_DP is not set
# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set
# CONFIG_PHY_MTK_PCIE is not set
CONFIG_PHY_MTK_TPHY=y
# CONFIG_PHY_MTK_UFS is not set
# CONFIG_PHY_MTK_XSPHY is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MT7629=y
CONFIG_PINCTRL_MTK_MOORE=y
CONFIG_PINCTRL_MTK_V2=y
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PWM=y
CONFIG_PWM_MEDIATEK=y
# CONFIG_PWM_MTK_DISP is not set
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
# CONFIG_RTL8367S_GSW is not set
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SGL_ALLOC=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_MT65XX=y
CONFIG_SPI_MTK_NOR=y
CONFIG_SPI_MTK_SNFI=y
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
CONFIG_STACKTRACE=y
# CONFIG_SWAP is not set
CONFIG_SWCONFIG=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_MTK=y
# CONFIG_USB_XHCI_PLATFORM is not set
CONFIG_USE_OF=y
# CONFIG_VFP is not set
CONFIG_WATCHDOG_CORE=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

151
lede/target/linux/mediatek/patches-6.12/010-v6.14-pinctrl-mediatek-add-support-for-MTK_PULL_PD_TYPE.patch Normal file
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@@ -0,0 +1,151 @@
From 1673d720b7e2862a5ff1994922558b7427f8a56b Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Tue, 17 Dec 2024 09:54:26 +0100
Subject: [PATCH 1/2] pinctrl: mediatek: add support for MTK_PULL_PD_TYPE
The MediaTek MT7988 SoC got some pins which only got configurable
pull-down but unlike previous designs there is no pull-up option.
Add new type MTK_PULL_PD_TYPE to support configuring such pins.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/20241217085435.9586-2-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
.../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 73 ++++++++++++++++---
.../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 +
2 files changed, 63 insertions(+), 11 deletions(-)
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -573,7 +573,7 @@ EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_r
*/
static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
- u32 pullup, u32 arg)
+ u32 pullup, u32 arg, bool pd_only)
{
int err, pu, pd;
@@ -587,18 +587,34 @@ static int mtk_pinconf_bias_set_pu_pd(st
pu = 0;
pd = 1;
} else {
- err = -EINVAL;
- goto out;
+ return -EINVAL;
}
- err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu);
- if (err)
- goto out;
+ if (!pd_only) {
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu);
+ if (err)
+ return err;
+ }
- err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
+ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
+}
+
+static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 pullup, u32 arg)
+{
+ int err, pd;
+
+ if (arg != MTK_DISABLE && arg != MTK_ENABLE)
+ return -EINVAL;
+
+ if (arg == MTK_DISABLE || pullup)
+ pd = 0;
+ else if (!pullup)
+ pd = 1;
+
+ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
-out:
- return err;
}
static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
@@ -737,7 +753,7 @@ static int mtk_pinconf_bias_set_pu_pd_rs
return err;
}
- return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable);
+ return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable, false);
}
int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
@@ -758,8 +774,14 @@ int mtk_pinconf_bias_set_combo(struct mt
return 0;
}
+ if (try_all_type & MTK_PULL_PD_TYPE) {
+ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, true);
+ if (!err)
+ return err;
+ }
+
if (try_all_type & MTK_PULL_PU_PD_TYPE) {
- err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
+ err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, false);
if (!err)
return 0;
}
@@ -878,6 +900,29 @@ out:
return err;
}
+static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw,
+ const struct mtk_pin_desc *desc,
+ u32 *pullup, u32 *enable)
+{
+ int err, pd;
+
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
+ if (err)
+ goto out;
+
+ if (pd == 0) {
+ *pullup = 0;
+ *enable = MTK_DISABLE;
+ } else if (pd == 1) {
+ *pullup = 0;
+ *enable = MTK_ENABLE;
+ } else
+ err = -EINVAL;
+
+out:
+ return err;
+}
+
static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
u32 *pullup, u32 *enable)
@@ -947,6 +992,12 @@ int mtk_pinconf_bias_get_combo(struct mt
return 0;
}
+ if (try_all_type & MTK_PULL_PD_TYPE) {
+ err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable);
+ if (!err)
+ return err;
+ }
+
if (try_all_type & MTK_PULL_PU_PD_TYPE) {
err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
if (!err)
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
@@ -24,6 +24,7 @@
* turned on/off itself. But it can't be selected pull up/down
*/
#define MTK_PULL_RSEL_TYPE BIT(3)
+#define MTK_PULL_PD_TYPE BIT(4)
/* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by
* MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE.
*/

1610
lede/target/linux/mediatek/patches-6.12/011-v6.14-pinctrl-mediatek-add-MT7988-pinctrl-driver.patch Normal file
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File diff suppressed because it is too large Load Diff

41
lede/target/linux/mediatek/patches-6.12/012-v6.14-pinctrl-mediatek-Drop-mtk_pinconf_bias_set_pd.patch Normal file
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@@ -0,0 +1,41 @@
From 0e18b099672160698dfbd7c3c82e03e011c907e6 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Wed, 8 Jan 2025 22:52:44 +0100
Subject: [PATCH] pinctrl: mediatek: Drop mtk_pinconf_bias_set_pd()
This function is unused and causing compile errors, delete it.
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Link: https://lore.kernel.org/linux-next/20250106164630.4447cd0d@canb.auug.org.au/
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
.../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 18 ------------------
1 file changed, 18 deletions(-)
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -599,24 +599,6 @@ static int mtk_pinconf_bias_set_pu_pd(st
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
}
-static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw,
- const struct mtk_pin_desc *desc,
- u32 pullup, u32 arg)
-{
- int err, pd;
-
- if (arg != MTK_DISABLE && arg != MTK_ENABLE)
- return -EINVAL;
-
- if (arg == MTK_DISABLE || pullup)
- pd = 0;
- else if (!pullup)
- pd = 1;
-
- return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
-
-}
-
static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc,
u32 pullup, u32 arg)

71
lede/target/linux/mediatek/patches-6.12/020-v6.13-arm64-dts-mediatek-mt7988-add-UART-controllers.patch Normal file
View File

@@ -0,0 +1,71 @@
From 52e2ca3be4b6d451fef0a2cd337157dd021b830f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
Date: Wed, 5 Jun 2024 10:54:33 +0200
Subject: [PATCH 01/32] arm64: dts: mediatek: mt7988: add UART controllers
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
MT7988 has three on-SoC UART controllers that support M16C450 and
M16550A modes.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240605085433.26513-2-zajec5@gmail.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 35 ++++++++++++++++++++++-
1 file changed, 34 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -86,7 +86,7 @@
#clock-cells = <1>;
};
- clock-controller@1001b000 {
+ topckgen: clock-controller@1001b000 {
compatible = "mediatek,mt7988-topckgen", "syscon";
reg = <0 0x1001b000 0 0x1000>;
#clock-cells = <1>;
@@ -124,6 +124,39 @@
status = "disabled";
};
+ serial@11000000 {
+ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11000000 0 0x100>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uart", "wakeup";
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_52M_UART0_CK>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ serial@11000100 {
+ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11000100 0 0x100>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uart", "wakeup";
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_52M_UART1_CK>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ serial@11000200 {
+ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11000200 0 0x100>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uart", "wakeup";
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_52M_UART2_CK>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
i2c@11003000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11003000 0 0x1000>,

35
lede/target/linux/mediatek/patches-6.12/021-v6.13-arm64-dts-mediatek-mt7988-add-efuse-block.patch Normal file
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@@ -0,0 +1,35 @@
From 390529e00d5586eb6d7f4c33c23dee7f43ac14e7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
Date: Thu, 13 Jun 2024 21:59:33 +0200
Subject: [PATCH 02/32] arm64: dts: mediatek: mt7988: add efuse block
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
MT7988 (AKA MediaTek Filogic 880) uses efuse for storing calibration
data.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20240613195933.31089-2-zajec5@gmail.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -234,6 +234,13 @@
#clock-cells = <1>;
};
+ efuse@11f50000 {
+ compatible = "mediatek,mt7988-efuse", "mediatek,efuse";
+ reg = <0 0x11f50000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
clock-controller@15000000 {
compatible = "mediatek,mt7988-ethsys", "syscon";
reg = <0 0x15000000 0 0x1000>;

85
lede/target/linux/mediatek/patches-6.12/022-v6.14-arm64-dts-mediatek-mt7988-Add-pinctrl-support.patch Normal file
View File

@@ -0,0 +1,85 @@
From a01cc71a8c55e7fc12cb37109953ad9c58a12d4f Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 09:54:29 +0100
Subject: [PATCH 03/32] arm64: dts: mediatek: mt7988: Add pinctrl support
Add mt7988a pinctrl node.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217085435.9586-5-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 54 +++++++++++++++++++++++
1 file changed, 54 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -3,6 +3,7 @@
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
/ {
compatible = "mediatek,mt7988a";
@@ -105,6 +106,59 @@
#clock-cells = <1>;
};
+ pio: pinctrl@1001f000 {
+ compatible = "mediatek,mt7988-pinctrl";
+ reg = <0 0x1001f000 0 0x1000>,
+ <0 0x11c10000 0 0x1000>,
+ <0 0x11d00000 0 0x1000>,
+ <0 0x11d20000 0 0x1000>,
+ <0 0x11e00000 0 0x1000>,
+ <0 0x11f00000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "gpio", "iocfg_tr",
+ "iocfg_br", "iocfg_rb",
+ "iocfg_lb", "iocfg_tl", "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 84>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+
+ pcie0_pins: pcie0-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
+ "pcie_wake_n0_0";
+ };
+ };
+
+ pcie1_pins: pcie1-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
+ "pcie_wake_n1_0";
+ };
+ };
+
+ pcie2_pins: pcie2-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
+ "pcie_wake_n2_0";
+ };
+ };
+
+ pcie3_pins: pcie3-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
+ "pcie_wake_n3_0";
+ };
+ };
+ };
+
pwm@10048000 {
compatible = "mediatek,mt7988-pwm";
reg = <0 0x10048000 0 0x1000>;

37
lede/target/linux/mediatek/patches-6.12/023-v6.14-arm64-dts-mediatek-mt7988-Add-reserved-memory.patch Normal file
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@@ -0,0 +1,37 @@
From b3bb498ff23f5bcaa95614e0f8c9176690af8acb Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:15 +0100
Subject: [PATCH 04/32] arm64: dts: mediatek: mt7988: Add reserved memory
Add memory range handled by ATF to not be touched by linux kernel.
ATF is SoC specific and not board-specific so add it to mt7988.dtsi.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-2-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -62,6 +62,18 @@
method = "smc";
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
+ secmon@43000000 {
+ reg = <0 0x43000000 0 0x50000>;
+ no-map;
+ };
+ };
+
soc {
compatible = "simple-bus";
ranges;

52
lede/target/linux/mediatek/patches-6.12/024-v6.14-arm64-dts-mediatek-mt7988-Add-mmc-support.patch Normal file
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@@ -0,0 +1,52 @@
From de6ba1a3ef621762394e841888de3e0ed127e20a Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:16 +0100
Subject: [PATCH 05/32] arm64: dts: mediatek: mt7988: Add mmc support
Add devicetree node for MMC controller.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-3-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -112,7 +112,7 @@
#reset-cells = <1>;
};
- clock-controller@1001e000 {
+ apmixedsys: clock-controller@1001e000 {
compatible = "mediatek,mt7988-apmixedsys";
reg = <0 0x1001e000 0 0x1000>;
#clock-cells = <1>;
@@ -293,6 +293,25 @@
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
};
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt7988-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11D60000 0 0x1000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_MSDC400>,
+ <&infracfg CLK_INFRA_MSDC2_HCK>,
+ <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
+ <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
+ assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
+ <&topckgen CLK_TOP_EMMC_400M_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
+ <&apmixedsys CLK_APMIXED_MSDCPLL>;
+ clock-names = "source", "hclk", "axi_cg", "ahb_cg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
clock-controller@11f40000 {
compatible = "mediatek,mt7988-xfi-pll";
reg = <0 0x11f40000 0 0x1000>;

62
lede/target/linux/mediatek/patches-6.12/025-v6.14-arm64-dts-mediatek-mt7988-Add-lvts-node.patch Normal file
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@@ -0,0 +1,62 @@
From f07e0e093c42736df56f4830179c19f48f8b0725 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:17 +0100
Subject: [PATCH 06/32] arm64: dts: mediatek: mt7988: Add lvts node
Add Low Voltage Thermal Sensor (LVTS) node for mt7988 SoC.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-4-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt65xx.h>
+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
/ {
compatible = "mediatek,mt7988a";
@@ -97,6 +98,7 @@
compatible = "mediatek,mt7988-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
topckgen: clock-controller@1001b000 {
@@ -265,6 +267,17 @@
status = "disabled";
};
+ lvts: lvts@1100a000 {
+ compatible = "mediatek,mt7988-lvts-ap";
+ #thermal-sensor-cells = <1>;
+ reg = <0 0x1100a000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
+ nvmem-cells = <&lvts_calibration>;
+ nvmem-cell-names = "lvts-calib-data-1";
+ };
+
usb@11190000 {
compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
reg = <0 0x11190000 0 0x2e00>,
@@ -324,6 +337,10 @@
reg = <0 0x11f50000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ lvts_calibration: calib@918 {
+ reg = <0x918 0x28>;
+ };
};
clock-controller@15000000 {

39
lede/target/linux/mediatek/patches-6.12/026-v6.14-arm64-dts-mediatek-mt7988-Add-thermal-zone.patch Normal file
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@@ -0,0 +1,39 @@
From 122ed9fc41b948d79ac357f95f5438a4bd6786b8 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:18 +0100
Subject: [PATCH 07/32] arm64: dts: mediatek: mt7988: Add thermal-zone
Add basic thermal-zone node.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-5-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -358,6 +358,21 @@
};
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+ thermal-sensors = <&lvts 0>;
+ trips {
+ cpu_trip_crit: crit {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;

31
lede/target/linux/mediatek/patches-6.12/027-v6.14-arm64-dts-mediatek-mt7988-Add-mcu-sys-node-for-cpu.patch Normal file
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@@ -0,0 +1,31 @@
From 7fa08d530548ed57752703e9f011eeeb809ef9b0 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:20 +0100
Subject: [PATCH 08/32] arm64: dts: mediatek: mt7988: Add mcu-sys node for cpu
In preparation for adding support for CPU DVFS and clock tables for it,
add the MCUSYS clock controller node.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-7-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -192,6 +192,12 @@
status = "disabled";
};
+ mcusys: mcusys@100e0000 {
+ compatible = "mediatek,mt7988-mcusys", "syscon";
+ reg = <0 0x100e0000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
serial@11000000 {
compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
reg = <0 0x11000000 0 0x100>;

84
lede/target/linux/mediatek/patches-6.12/028-v6.14-arm64-dts-mediatek-mt7988-Add-CPU-OPP-table-for-cloc.patch Normal file
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@@ -0,0 +1,84 @@
From b10331c8faa1208c61fb98d9b65da2828e239113 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:21 +0100
Subject: [PATCH 09/32] arm64: dts: mediatek: mt7988: Add CPU OPP table for
clock scaling
Add operating points defining frequency/voltages of cpu cores.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-8-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 38 +++++++++++++++++++++++
1 file changed, 38 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -21,6 +21,10 @@
reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+ <&topckgen CLK_TOP_XTAL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu@1 {
@@ -28,6 +32,10 @@
reg = <0x1>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+ <&topckgen CLK_TOP_XTAL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu@2 {
@@ -35,6 +43,10 @@
reg = <0x2>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+ <&topckgen CLK_TOP_XTAL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu@3 {
@@ -42,6 +54,32 @@
reg = <0x3>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+ <&topckgen CLK_TOP_XTAL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <850000>;
+ };
+ opp-1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-microvolt = <850000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <850000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <900000>;
+ };
};
};

34
lede/target/linux/mediatek/patches-6.12/029-v6.14-arm64-dts-mediatek-mt7988-Disable-usb-controllers-by.patch Normal file
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@@ -0,0 +1,34 @@
From 39bb12c26f556046e55f3638e2e4184bfbfd0564 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:22 +0100
Subject: [PATCH 10/32] arm64: dts: mediatek: mt7988: Disable usb controllers
by default
The controllers should be enabled at board level if used.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-9-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -334,6 +334,7 @@
<&infracfg CLK_INFRA_133M_USB_HCK>,
<&infracfg CLK_INFRA_USB_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+ status = "disabled";
};
usb@11200000 {
@@ -348,6 +349,7 @@
<&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>,
<&infracfg CLK_INFRA_USB_XHCI_CK_P1>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+ status = "disabled";
};
mmc0: mmc@11230000 {

59
lede/target/linux/mediatek/patches-6.12/030-v6.14-arm64-dts-mediatek-mt7988-Add-t-phy-for-ssusb1.patch Normal file
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@@ -0,0 +1,59 @@
From 46d056b6c2376d3ef866f9ab5212879c97588892 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:23 +0100
Subject: [PATCH 11/32] arm64: dts: mediatek: mt7988: Add t-phy for ssusb1
USB controller needs phys for working properly.
On mt7988 ssusb0 uses a xs-phy, ssusb uses t-phy.
For now add the t-phy for ssusb1. We can reuse the mt7986 compatible
here.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-10-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 25 +++++++++++++++++++++++
1 file changed, 25 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -349,6 +349,8 @@
<&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>,
<&infracfg CLK_INFRA_USB_XHCI_CK_P1>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+ phys = <&tphyu2port0 PHY_TYPE_USB2>,
+ <&tphyu3port0 PHY_TYPE_USB3>;
status = "disabled";
};
@@ -371,6 +373,29 @@
status = "disabled";
};
+ t-phy@11c50000 {
+ compatible = "mediatek,mt7986-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ tphyu2port0: usb-phy@11c50000 {
+ reg = <0 0x11c50000 0 0x700>;
+ clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+
+ tphyu3port0: usb-phy@11c50700 {
+ reg = <0 0x11c50700 0 0x900>;
+ clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
clock-controller@11f40000 {
compatible = "mediatek,mt7988-xfi-pll";
reg = <0 0x11f40000 0 0x1000>;

176
lede/target/linux/mediatek/patches-6.12/031-v6.14-arm64-dts-mediatek-mt7988-Add-pcie-nodes.patch Normal file
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@@ -0,0 +1,176 @@
From aac2eb27ee500ca2828fe0fd1895ec6f9ef83787 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:24 +0100
Subject: [PATCH 12/32] arm64: dts: mediatek: mt7988: Add pcie nodes
Add pcie controllers for mt7988. Reuse mt7986 compatible.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-11-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 152 ++++++++++++++++++++++
1 file changed, 152 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -373,6 +373,158 @@
status = "disabled";
};
+ pcie@11280000 {
+ compatible = "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x11280000 0 0x2000>;
+ reg-names = "pcie-mac";
+ linux,pci-domain = <3>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0x00 0x20000000 0x00
+ 0x20000000 0x00 0x00200000>,
+ <0x82000000 0x00 0x20200000 0x00
+ 0x20200000 0x00 0x07e00000>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_pins>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc2 0>,
+ <0 0 0 2 &pcie_intc2 1>,
+ <0 0 0 3 &pcie_intc2 2>,
+ <0 0 0 4 &pcie_intc2 3>;
+ pcie_intc2: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie@11290000 {
+ compatible = "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x11290000 0 0x2000>;
+ reg-names = "pcie-mac";
+ linux,pci-domain = <2>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0x00 0x28000000 0x00
+ 0x28000000 0x00 0x00200000>,
+ <0x82000000 0x00 0x28200000 0x00
+ 0x28200000 0x00 0x07e00000>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3_pins>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc3 0>,
+ <0 0 0 2 &pcie_intc3 1>,
+ <0 0 0 3 &pcie_intc3 2>,
+ <0 0 0 4 &pcie_intc3 3>;
+ pcie_intc3: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie@11300000 {
+ compatible = "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x11300000 0 0x2000>;
+ reg-names = "pcie-mac";
+ linux,pci-domain = <0>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0x00 0x30000000 0x00
+ 0x30000000 0x00 0x00200000>,
+ <0x82000000 0x00 0x30200000 0x00
+ 0x30200000 0x00 0x07e00000>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_pins>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie@11310000 {
+ compatible = "mediatek,mt7986-pcie",
+ "mediatek,mt8192-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0 0x11310000 0 0x2000>;
+ reg-names = "pcie-mac";
+ linux,pci-domain = <1>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0x00 0x38000000 0x00
+ 0x38000000 0x00 0x00200000>,
+ <0x82000000 0x00 0x38200000 0x00
+ 0x38200000 0x00 0x07e00000>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
+ <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m",
+ "top_133m";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
t-phy@11c50000 {
compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v2";

211
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@@ -0,0 +1,211 @@
From 6b116c43782a153bcde18bd54d3220d81b476859 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 09:54:30 +0100
Subject: [PATCH 13/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add pinctrl
subnodes for bpi-r4
Add board specific pinctrl configurations on Bananapi R4.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217085435.9586-6-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 189 ++++++++++++++++++
1 file changed, 189 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -9,3 +9,192 @@
model = "Banana Pi BPI-R4";
chassis-type = "embedded";
};
+
+&pio {
+ mdio0_pins: mdio0-pins {
+ mux {
+ function = "eth";
+ groups = "mdc_mdio0";
+ };
+
+ conf {
+ pins = "SMI_0_MDC", "SMI_0_MDIO";
+ drive-strength = <8>;
+ };
+ };
+
+ i2c0_pins: i2c0-g0-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c0_1";
+ };
+ };
+
+ i2c1_pins: i2c1-g0-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c1_0";
+ };
+ };
+
+ i2c1_sfp_pins: i2c1-sfp-g0-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c1_sfp";
+ };
+ };
+
+ i2c2_0_pins: i2c2-g0-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c2_0";
+ };
+ };
+
+ i2c2_1_pins: i2c2-g1-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c2_1";
+ };
+ };
+
+ gbe0_led0_pins: gbe0-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe0_led0";
+ };
+ };
+
+ gbe1_led0_pins: gbe1-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe1_led0";
+ };
+ };
+
+ gbe2_led0_pins: gbe2-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe2_led0";
+ };
+ };
+
+ gbe3_led0_pins: gbe3-led0-pins {
+ mux {
+ function = "led";
+ groups = "gbe3_led0";
+ };
+ };
+
+ gbe0_led1_pins: gbe0-led1-pins {
+ mux {
+ function = "led";
+ groups = "gbe0_led1";
+ };
+ };
+
+ gbe1_led1_pins: gbe1-led1-pins {
+ mux {
+ function = "led";
+ groups = "gbe1_led1";
+ };
+ };
+
+ gbe2_led1_pins: gbe2-led1-pins {
+ mux {
+ function = "led";
+ groups = "gbe2_led1";
+ };
+ };
+
+ gbe3_led1_pins: gbe3-led1-pins {
+ mux {
+ function = "led";
+ groups = "gbe3_led1";
+ };
+ };
+
+ i2p5gbe_led0_pins: 2p5gbe-led0-pins {
+ mux {
+ function = "led";
+ groups = "2p5gbe_led0";
+ };
+ };
+
+ i2p5gbe_led1_pins: 2p5gbe-led1-pins {
+ mux {
+ function = "led";
+ groups = "2p5gbe_led1";
+ };
+ };
+
+ mmc0_pins_emmc_45: mmc0-emmc-45-pins {
+ mux {
+ function = "flash";
+ groups = "emmc_45";
+ };
+ };
+
+ mmc0_pins_emmc_51: mmc0-emmc-51-pins {
+ mux {
+ function = "flash";
+ groups = "emmc_51";
+ };
+ };
+
+ mmc0_pins_sdcard: mmc0-sdcard-pins {
+ mux {
+ function = "flash";
+ groups = "sdcard";
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ mux {
+ function = "uart";
+ groups = "uart0";
+ };
+ };
+
+ snfi_pins: snfi-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ spi0_pins: spi0-pins {
+ mux {
+ function = "spi";
+ groups = "spi0";
+ };
+ };
+
+ spi0_flash_pins: spi0-flash-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+
+ spi1_pins: spi1-pins {
+ mux {
+ function = "spi";
+ groups = "spi1";
+ };
+ };
+
+ spi2_pins: spi2-pins {
+ mux {
+ function = "spi";
+ groups = "spi2";
+ };
+ };
+
+ spi2_flash_pins: spi2-flash-pins {
+ mux {
+ function = "spi";
+ groups = "spi2", "spi2_wp_hold";
+ };
+ };
+};

25
lede/target/linux/mediatek/patches-6.12/033-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-watchdog.patch Normal file
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@@ -0,0 +1,25 @@
From 6b6f2f1ee88b8b5763f4112babbc9fc45a94999a Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:25 +0100
Subject: [PATCH 14/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable watchdog
Enable the watchdog on Bananapi R4 board.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-12-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -198,3 +198,7 @@
};
};
};
+
+&watchdog {
+ status = "okay";
+};

48
lede/target/linux/mediatek/patches-6.12/034-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-fixed-regulato.patch Normal file
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@@ -0,0 +1,48 @@
From 72b0a6f181c5ca417405e594c80d724baee54813 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:26 +0100
Subject: [PATCH 15/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add fixed
regulators for 1v8 and 3v3
Add regulator nodes used for mmc to Bananapi R4 board.
This board has 1 MMC controller used for SDMMC and eMMC where only one can
be used at one time, selected by hardware switches. SD uses 3v3 for both
supplies and emmc uses both regulators.
So defining both regulators in board dts and referencing them in the dt
overlay.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-13-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -8,6 +8,24 @@
compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
model = "Banana Pi BPI-R4";
chassis-type = "embedded";
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
&pio {

54
lede/target/linux/mediatek/patches-6.12/035-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-thermal-config.patch Normal file
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@@ -0,0 +1,54 @@
From 67511ea667d3c4da827588fd460772562d7b054e Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:28 +0100
Subject: [PATCH 16/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add thermal
configuration
Add additional thermal trips to Bananapi R4 board.
SoC only contains the critical trip.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-15-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -28,6 +28,34 @@
};
};
+&cpu_thermal {
+ trips {
+ cpu_trip_hot: hot {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpu_trip_active_high: active-high {
+ temperature = <115000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_active_med: active-med {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_active_low: active-low {
+ temperature = <40000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+};
+
&pio {
mdio0_pins: mdio0-pins {
mux {

41
lede/target/linux/mediatek/patches-6.12/036-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-serial0-deb.patch Normal file
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@@ -0,0 +1,41 @@
From a9df5ed2333b01546b4f906e2f6fd21dd5b146aa Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:29 +0100
Subject: [PATCH 17/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable serial0
debug uart
Enable the debug uart on Bananapi R4 board.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-16-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -245,6 +245,10 @@
};
};
+&serial0 {
+ status = "okay";
+};
+
&watchdog {
status = "okay";
};
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -236,7 +236,7 @@
#clock-cells = <1>;
};
- serial@11000000 {
+ serial0: serial@11000000 {
compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
reg = <0 0x11000000 0 0x100>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;

29
lede/target/linux/mediatek/patches-6.12/037-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-default-UART-s.patch Normal file
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@@ -0,0 +1,29 @@
From 3dfb0dcb194e3f32ed931747131be08bfc429522 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:30 +0100
Subject: [PATCH 18/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add default UART
stdout
Add chosen node on Bananapi R4 board with stdout and default bootargs.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-17-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -9,6 +9,10 @@
model = "Banana Pi BPI-R4";
chassis-type = "embedded";
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";

72
lede/target/linux/mediatek/patches-6.12/038-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-I2C-control.patch Normal file
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@@ -0,0 +1,72 @@
From 90d4eb65db14a3f2e776d2a8b1dc832e70198328 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:31 +0100
Subject: [PATCH 19/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable I2C
controllers
Enable the I2C0, I2C2 controllers found on the BananaPi R4 board.
Both controllers are not accessible from user and having fixed spare
devices. I2C0 have a pmic connected, I2C2 is used with I2C-multiplexer
for e.g. SFP cages.
The missing I2C1 is connected to GPIO header which can have either GPIO
mode or I2C mode.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-18-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 12 ++++++++++++
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 +++---
2 files changed, 15 insertions(+), 3 deletions(-)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -60,6 +60,18 @@
};
};
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_1_pins>;
+ status = "okay";
+};
+
&pio {
mdio0_pins: mdio0-pins {
mux {
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -269,7 +269,7 @@
status = "disabled";
};
- i2c@11003000 {
+ i2c0: i2c@11003000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11003000 0 0x1000>,
<0 0x10217080 0 0x80>;
@@ -283,7 +283,7 @@
status = "disabled";
};
- i2c@11004000 {
+ i2c1: i2c@11004000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11004000 0 0x1000>,
<0 0x10217100 0 0x80>;
@@ -297,7 +297,7 @@
status = "disabled";
};
- i2c@11005000 {
+ i2c2: i2c@11005000 {
compatible = "mediatek,mt7981-i2c";
reg = <0 0x11005000 0 0x1000>,
<0 0x10217180 0 0x80>;

74
lede/target/linux/mediatek/patches-6.12/039-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Add-PCA9545-I2C-Mu.patch Normal file
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@@ -0,0 +1,74 @@
From dde7d741329616025e4cfa350eb3935b495ae140 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:32 +0100
Subject: [PATCH 20/32] arm64: dts: mediatek: mt7988a-bpi-r4: Add PCA9545 I2C
Mux
Bananapi R4 uses an i2c multiplexer for SFP slots, rtc and eeprom.
Add its node to the right i2c controller.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-19-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 41 +++++++++++++++++++
1 file changed, 41 insertions(+)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -2,6 +2,8 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+
#include "mt7988a.dtsi"
/ {
@@ -70,6 +72,45 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c2_1_pins>;
status = "okay";
+
+ pca9545: i2c-mux@70 {
+ compatible = "nxp,pca9545";
+ reg = <0x70>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ };
+
+ eeprom@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ size = <256>;
+ };
+
+ };
+
+ i2c_sfp1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_sfp2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ };
};
&pio {

41
lede/target/linux/mediatek/patches-6.12/040-v6.14-arm64-dts-mediatek-mt7988a-bpi-r4-Enable-t-phy-for-s.patch Normal file
View File

@@ -0,0 +1,41 @@
From dfe00be85da20d9823d39775c92139c569a7960d Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 17 Dec 2024 10:12:33 +0100
Subject: [PATCH 21/32] arm64: dts: mediatek: mt7988a-bpi-r4: Enable t-phy for
ssusb1
Bananapi R4 uses t-phy for usb. Enable its node at board level.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241217091238.16032-20-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -306,6 +306,10 @@
status = "okay";
};
+&tphy {
+ status = "okay";
+};
+
&watchdog {
status = "okay";
};
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -525,7 +525,7 @@
};
};
- t-phy@11c50000 {
+ tphy: t-phy@11c50000 {
compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v2";
#address-cells = <2>;

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