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53 lines
1.9 KiB
Diff
53 lines
1.9 KiB
Diff
From de6ba1a3ef621762394e841888de3e0ed127e20a Mon Sep 17 00:00:00 2001
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From: Frank Wunderlich <frank-w@public-files.de>
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Date: Tue, 17 Dec 2024 10:12:16 +0100
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Subject: [PATCH 05/32] arm64: dts: mediatek: mt7988: Add mmc support
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Add devicetree node for MMC controller.
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Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Link: https://lore.kernel.org/r/20241217091238.16032-3-linux@fw-web.de
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Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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---
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arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 21 ++++++++++++++++++++-
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1 file changed, 20 insertions(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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@@ -112,7 +112,7 @@
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#reset-cells = <1>;
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};
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- clock-controller@1001e000 {
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+ apmixedsys: clock-controller@1001e000 {
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compatible = "mediatek,mt7988-apmixedsys";
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reg = <0 0x1001e000 0 0x1000>;
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#clock-cells = <1>;
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@@ -293,6 +293,25 @@
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clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
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};
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+ mmc0: mmc@11230000 {
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+ compatible = "mediatek,mt7988-mmc";
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+ reg = <0 0x11230000 0 0x1000>,
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+ <0 0x11D60000 0 0x1000>;
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+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&infracfg CLK_INFRA_MSDC400>,
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+ <&infracfg CLK_INFRA_MSDC2_HCK>,
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+ <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
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+ <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
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+ assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
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+ <&topckgen CLK_TOP_EMMC_400M_SEL>;
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+ assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
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+ <&apmixedsys CLK_APMIXED_MSDCPLL>;
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+ clock-names = "source", "hclk", "axi_cg", "ahb_cg";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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clock-controller@11f40000 {
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compatible = "mediatek,mt7988-xfi-pll";
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reg = <0 0x11f40000 0 0x1000>;
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