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[vdpu34x]: Add clock gating by default
Change-Id: Idede84f638db679ac06af7bcdf526a9a3b7225bb Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
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@@ -587,6 +587,10 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal
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common->dec_cabac_err_en_lowbits.cabac_err_en_lowbits = 0xffffdfff;
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common->dec_cabac_err_en_highbits.cabac_err_en_highbits = 0x3ffbf9ff;
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common->dec_block_gating_en.swreg_block_gating_e = 0xffff;
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common->dec_block_gating_en.block_gating_en_l2 = 0xf;
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common->dec_block_gating_en.reg_cfg_gating_en = 1;
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common->dec_imp_en.dec_clkgate_e = 1;
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common->dec_imp_en.dec_e_strmd_clkgate_dis = 0;
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common->dec_imp_en.dec_timeout_e = 1;
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@@ -869,6 +869,10 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
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hw_regs->common.dec_cabac_err_en_lowbits.cabac_err_en_lowbits = 0xffffdfff;
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hw_regs->common.dec_cabac_err_en_highbits.cabac_err_en_highbits = 0x3ffbf9ff;
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hw_regs->common.dec_block_gating_en.swreg_block_gating_e = 0xffff;
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hw_regs->common.dec_block_gating_en.block_gating_en_l2 = 0xf;
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hw_regs->common.dec_block_gating_en.reg_cfg_gating_en = 1;
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valid_ref = hw_regs->common_addr.decout_base.decout_base;
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hw_regs->common_addr.error_ref_base.error_ref_base = valid_ref;
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for (i = 0; i < (RK_S32)MPP_ARRAY_ELEMS(dxva_cxt->pp.RefPicList); i++) {
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