package/mpp
1
0
Fork 0
mirror of https://github.com/nyanmisaka/mpp.git synced 2025-10-30 04:02:07 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

fix[vdpu_34x]: disable cabac err check for rk3588

Browse Source 
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: Id162fcbe405b67fc70031fcded4b359f595c7e46
This commit is contained in:
Yandong Lin
2022-11-10 16:58:31 +08:00
committed by Herman Chen
parent 8e10b8aad2
commit 60986ca3cf
3 changed files with 27 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
mpp/hal/rkdec/avs2d/hal_avs2d_rkv.c
View File

@@ -251,11 +251,16 @@ static MPP_RET init_common_regs(Vdpu34xAvs2dRegSet *regs)
common->reg021.error_deb_en = 0;
common->reg021.error_intra_mode = 0;
common->reg024.cabac_err_en_lowbits = 0xffffffdf;
common->reg025.cabac_err_en_highbits = 0x3dffffff;
if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3588) {
common->reg024.cabac_err_en_lowbits = 0;
common->reg025.cabac_err_en_highbits = 0;
common->reg026.swreg_block_gating_e = 0xfffef;
} else {
common->reg024.cabac_err_en_lowbits = 0xffffffdf;
common->reg025.cabac_err_en_highbits = 0x3dffffff;
common->reg026.swreg_block_gating_e = 0xfffff;
}
common->reg026.swreg_block_gating_e =
(mpp_get_soc_type() == ROCKCHIP_SOC_RK3588) ? 0xfffef : 0xfffff;
common->reg026.reg_cfg_gating_en = 1;
common->reg032_timeout_threshold = 0x3fffff;

13
mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c
View File

@@ -683,10 +683,15 @@ static MPP_RET init_common_regs(Vdpu34xH264dRegSet *regs)
common->reg021.inter_error_prc_mode = 0;
common->reg021.error_intra_mode = 1;
common->reg024.cabac_err_en_lowbits = 0xffffffff;
common->reg025.cabac_err_en_highbits = 0x3ff3ffff;
common->reg026.swreg_block_gating_e =
(mpp_get_soc_type() == ROCKCHIP_SOC_RK3588) ? 0xfffef : 0xfffff;
if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3588) {
common->reg024.cabac_err_en_lowbits = 0;
common->reg025.cabac_err_en_highbits = 0;
common->reg026.swreg_block_gating_e = 0xfffef;
} else {
common->reg024.cabac_err_en_lowbits = 0xffffffff;
common->reg025.cabac_err_en_highbits = 0x3ff3ffff;
common->reg026.swreg_block_gating_e = 0xfffff;
}
common->reg026.reg_cfg_gating_en = 1;
common->reg032_timeout_threshold = 0x3ffff;

13
mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
View File

@@ -1036,13 +1036,18 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
? 0 : 1;
hw_regs->common.reg012.colmv_compress_en = 1;
hw_regs->common.reg024.cabac_err_en_lowbits = 0xffffdfff;
hw_regs->common.reg025.cabac_err_en_highbits = 0x3ffbf9ff;
if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3588) {
hw_regs->common.reg026.swreg_block_gating_e = 0xfffef;
hw_regs->common.reg024.cabac_err_en_lowbits = 0;
hw_regs->common.reg025.cabac_err_en_highbits = 0;
} else {
hw_regs->common.reg024.cabac_err_en_lowbits = 0xffffdfff;
hw_regs->common.reg025.cabac_err_en_highbits = 0x3ffbf9ff;
hw_regs->common.reg026.swreg_block_gating_e = 0xfffff;
}
hw_regs->common.reg011.dec_clkgate_e = 1;
hw_regs->common.reg011.dec_e_strmd_clkgate_dis = 0;
hw_regs->common.reg026.swreg_block_gating_e =
(mpp_get_soc_type() == ROCKCHIP_SOC_RK3588) ? 0xfffef : 0xfffff;
hw_regs->common.reg026.reg_cfg_gating_en = 1;
hw_regs->common.reg032_timeout_threshold = 0x3ffff;