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feat[vepu_511]: Add rv1126b 265e/264e/jpge support

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Change-Id: Ie6baf5a0820ecfe9adbb49dd4d267fc2c51d5c2a
Signed-off-by: Yanjun Liao <yanjun.liao@rock-chips.com>
This commit is contained in:
Yanjun Liao
2024-12-03 17:11:54 +08:00
committed by Herman Chen
parent 27ab1e4abd
commit 43a191ede7
22 changed files with 12355 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
mpp/codec/enc/h265/h265e_api.c
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@@ -89,7 +89,9 @@ static MPP_RET h265e_init(void *ctx, EncImplCfg *ctrlCfg)
h265->const_intra_pred = 0; /* constraint intra prediction flag */
soc_type = mpp_get_soc_type();
if (soc_type == ROCKCHIP_SOC_RK3528 || soc_type == ROCKCHIP_SOC_RK3576)
if (soc_type == ROCKCHIP_SOC_RK3528 ||
soc_type == ROCKCHIP_SOC_RK3576 ||
soc_type == ROCKCHIP_SOC_RV1126B)
h265->max_cu_size = 32;
else
h265->max_cu_size = 64;

4
mpp/codec/enc/h265/h265e_ps.c
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@@ -194,6 +194,7 @@ MPP_RET h265e_set_sps(H265eCtx *ctx, H265eSps *sps, H265eVps *vps)
RK_S32 minCUSize, log2MinCUSize;
RK_S32 tuQTMinLog2Size = 2, tuQTMaxLog2Size;
MppEncCpbInfo *cpb_info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
RockchipSocType soc_type;
RK_U32 *tmp = &sps->zscan2raster[0];
memset(convertToBit, -1, sizeof(convertToBit));
@@ -208,7 +209,8 @@ MPP_RET h265e_set_sps(H265eCtx *ctx, H265eSps *sps, H265eVps *vps)
minCUDepth = (codec->max_cu_size >> (maxCUDepth - 1));
tuQTMaxLog2Size = convertToBit[codec->max_cu_size] + 2 - 1;
if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3576) {
soc_type = mpp_get_soc_type();
if (soc_type == ROCKCHIP_SOC_RK3576 || soc_type == ROCKCHIP_SOC_RV1126B) {
tuQTMaxLog2Size = tuQTMaxLog2Size + 1;
}

2
mpp/codec/enc/h265/h265e_syntax.c
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@@ -154,7 +154,7 @@ static void fill_slice_parameters( const H265eCtx *h,
sp->ref_pic_lst_mdf_l0 = slice->ref_pic_list_modification_flag_l0;
sp->num_refidx_l1_act = 0;
sp->num_refidx_l0_act = 1;
sp->num_refidx_l0_act = 0;
sp->num_refidx_act_ovrd = (((RK_U32)slice->m_numRefIdx[0] != slice->m_pps->m_numRefIdxL0DefaultActive)
|| (slice->m_sliceType == B_SLICE &&

4
mpp/hal/common/h264/hal_h264e_api_v2.c
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@@ -34,6 +34,7 @@
#include "hal_h264e_vepu580.h"
#include "hal_h264e_vepu540c.h"
#include "hal_h264e_vepu510.h"
#include "hal_h264e_vepu511.h"
typedef struct HalH264eCtx_t {
const MppEncHalApi *api;
@@ -65,6 +66,9 @@ static MPP_RET hal_h264e_init(void *hal, MppEncHalCfg *cfg)
case HWID_VEPU510 : {
api = &hal_h264e_vepu510;
} break;
case HWID_VEPU511 : {
api = &hal_h264e_vepu511;
} break;
default : {
api = &hal_h264e_vepu541;
} break;

4
mpp/hal/common/h265/hal_h265e_api_v2.c
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@@ -31,6 +31,7 @@
#include "hal_h265e_vepu580.h"
#include "hal_h265e_vepu540c.h"
#include "hal_h265e_vepu510.h"
#include "hal_h265e_vepu511.h"
typedef struct HalH265eV2Ctx_t {
const MppEncHalApi *api;
@@ -60,6 +61,9 @@ static MPP_RET hal_h265ev2_init(void *hal, MppEncHalCfg *cfg)
case HWID_VEPU510 : {
api = &hal_h265e_vepu510;
} break;
case HWID_VEPU511 : {
api = &hal_h265e_vepu511;
} break;
default : {
api = &hal_h265e_vepu541;
} break;

13
mpp/hal/common/jpeg/hal_jpege_api_v2.c
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@@ -32,6 +32,7 @@
#include "hal_jpege_vepu2_v2.h"
#include "hal_jpege_vepu540c.h"
#include "hal_jpege_vpu720.h"
#include "hal_jpege_vepu511.h"
typedef struct HaljpegeCtx_t {
const MppEncHalApi *api;
@@ -50,9 +51,15 @@ static MPP_RET hal_jpege_init(void *hal, MppEncHalCfg *cfg)
mpp_env_get_u32("hal_jpege_debug", &hal_jpege_debug, 0);
if ((vcodec_type & HAVE_RKVENC) &&
(HWID_VEPU540C == mpp_get_client_hw_id(VPU_CLIENT_RKVENC))) {
api = &hal_jpege_vepu540c;
if (vcodec_type & HAVE_RKVENC) {
if (HWID_VEPU540C == mpp_get_client_hw_id(VPU_CLIENT_RKVENC))
api = &hal_jpege_vepu540c;
else if (HWID_VEPU511 == mpp_get_client_hw_id(VPU_CLIENT_RKVENC))
api = &hal_jpege_vepu511;
else {
mpp_err("vcodec type %08x can not find JPEG encoder device\n", vcodec_type);
ret = MPP_NOK;
}
} else if (vcodec_type & (HAVE_VEPU2 | HAVE_VEPU2_JPEG)) {
api = &hal_jpege_vepu2;
} else if (vcodec_type & HAVE_VEPU1) {

1
mpp/hal/rkenc/common/CMakeLists.txt
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@@ -8,6 +8,7 @@ add_library(hal_vepu541_common STATIC
vepu540c_common.c
vepu580_tune.c
vepu510_common.c
vepu511_common.c
)
target_link_libraries(hal_vepu541_common mpp_base)

155
mpp/hal/rkenc/common/vepu511_common.c Normal file
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@@ -0,0 +1,155 @@
/* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
#define MODULE_TAG "vepu511_common"
#include <string.h>
#include "mpp_log.h"
#include "mpp_common.h"
#include "vepu511_common.h"
#include "jpege_syntax.h"
#include "vepu541_common.h"
#include "hal_enc_task.h"
#include "mpp_frame_impl.h"
#include "mpp_packet.h"
#include "mpp_debug.h"
#include "mpp_mem.h"
MPP_RET vepu511_set_osd(Vepu511OsdCfg * cfg, Vepu511Osd *osd_reg)
{
Vepu511Osd *regs = osd_reg;
MppEncOSDData3 *osd_ptr = cfg->osd_data3;
Vepu511OsdRegion *osd_regions = &regs->osd_regions[0];
MppEncOSDRegion3 *region = osd_ptr->region;
RK_U32 i = 0;
if (NULL == osd_regions) {
mpp_err_f("invalid reg_regions %p\n", osd_regions);
}
memset(osd_regions, 0, sizeof(Vepu511OsdRegion) * 8);
if (osd_ptr->num_region > 8) {
mpp_err_f("do NOT support more than 8 regions invalid num %d\n",
osd_ptr->num_region);
mpp_assert(osd_ptr->num_region <= 8);
return MPP_NOK;
}
for (i = 0; i < osd_ptr->num_region; i++, region++) {
Vepu511OsdRegion *reg = &osd_reg->osd_regions[i];
VepuFmtCfg fmt_cfg;
MppFrameFormat fmt = region->fmt;
vepu541_set_fmt(&fmt_cfg, fmt);
reg->cfg0.osd_en = region->enable;
reg->cfg0.osd_range_trns_en = region->range_trns_en;
reg->cfg0.osd_range_trns_sel = region->range_trns_sel;
reg->cfg0.osd_fmt = fmt_cfg.format;
reg->cfg0.osd_rbuv_swap = region->rbuv_swap;
reg->cfg1.osd_lt_xcrd = region->lt_x;
reg->cfg1.osd_lt_ycrd = region->lt_y;
reg->cfg2.osd_rb_xcrd = region->rb_x;
reg->cfg2.osd_rb_ycrd = region->rb_y;
reg->cfg1.osd_endn = region->osd_endn;
reg->cfg5.osd_stride = region->stride;
reg->cfg5.osd_ch_ds_mode = region->ch_ds_mode;
reg->cfg0.osd_alpha_swap = region->alpha_cfg.alpha_swap;
reg->cfg0.osd_fg_alpha = region->alpha_cfg.fg_alpha;
reg->cfg0.osd_fg_alpha_sel = region->alpha_cfg.fg_alpha_sel;
reg->cfg0.osd_qp_adj_en = region->qp_cfg.qp_adj_en;
reg->cfg8.osd_qp_adj_sel = region->qp_cfg.qp_adj_sel;
reg->cfg8.osd_qp = region->qp_cfg.qp;
reg->cfg8.osd_qp_max = region->qp_cfg.qp_max;
reg->cfg8.osd_qp_min = region->qp_cfg.qp_min;
reg->cfg8.osd_qp_prj = region->qp_cfg.qp_prj;
if (region->osd_buf.buf)
reg->osd_st_addr = mpp_buffer_get_fd(region->osd_buf.buf);
}
regs->osd_whi_cfg0.osd_csc_yr = 77;
regs->osd_whi_cfg0.osd_csc_yg = 150;
regs->osd_whi_cfg0.osd_csc_yb = 29;
regs->osd_whi_cfg1.osd_csc_ur = -43;
regs->osd_whi_cfg1.osd_csc_ug = -85;
regs->osd_whi_cfg1.osd_csc_ub = 128;
regs->osd_whi_cfg2.osd_csc_vr = 128;
regs->osd_whi_cfg2.osd_csc_vg = -107;
regs->osd_whi_cfg2.osd_csc_vb = -21;
regs->osd_whi_cfg3.osd_csc_ofst_y = 0;
regs->osd_whi_cfg3.osd_csc_ofst_u = 128;
regs->osd_whi_cfg3.osd_csc_ofst_v = 128;
return MPP_OK;
}
MPP_RET vepu511_set_roi(Vepu511RoiCfg *roi_reg_base, MppEncROICfg * roi, RK_S32 w, RK_S32 h)
{
MppEncROIRegion *region = roi->regions;
Vepu511RoiCfg *roi_cfg = (Vepu511RoiCfg *)roi_reg_base;
Vepu511RoiRegion *reg_regions = &roi_cfg->regions[0];
MPP_RET ret = MPP_NOK;
RK_S32 i = 0;
memset(reg_regions, 0, sizeof(Vepu511RoiRegion) * 8);
if (NULL == roi_cfg || NULL == roi) {
mpp_err_f("invalid buf %p roi %p\n", roi_cfg, roi);
goto DONE;
}
if (roi->number > VEPU511_MAX_ROI_NUM) {
mpp_err_f("invalid region number %d\n", roi->number);
goto DONE;
}
/* check region config */
ret = MPP_OK;
for (i = 0; i < (RK_S32) roi->number; i++, region++) {
if (region->x + region->w > w || region->y + region->h > h)
ret = MPP_NOK;
if (region->intra > 1 || region->qp_area_idx >= VEPU511_MAX_ROI_NUM ||
region->area_map_en > 1 || region->abs_qp_en > 1)
ret = MPP_NOK;
if ((region->abs_qp_en && region->quality > 51) ||
(!region->abs_qp_en && (region->quality > 51 || region->quality < -51)))
ret = MPP_NOK;
if (ret) {
mpp_err_f("region %d invalid param:\n", i);
mpp_err_f("position [%d:%d:%d:%d] vs [%d:%d]\n",
region->x, region->y, region->w, region->h, w, h);
mpp_err_f("force intra %d qp area index %d\n",
region->intra, region->qp_area_idx);
mpp_err_f("abs qp mode %d value %d\n",
region->abs_qp_en, region->quality);
goto DONE;
}
reg_regions->roi_pos_lt.roi_lt_x = MPP_ALIGN(region->x, 16) >> 4;
reg_regions->roi_pos_lt.roi_lt_y = MPP_ALIGN(region->y, 16) >> 4;
reg_regions->roi_pos_rb.roi_rb_x = MPP_ALIGN(region->x + region->w, 16) >> 4;
reg_regions->roi_pos_rb.roi_rb_y = MPP_ALIGN(region->y + region->h, 16) >> 4;
reg_regions->roi_base.roi_qp_value = region->quality;
reg_regions->roi_base.roi_qp_adj_mode = region->abs_qp_en;
reg_regions->roi_base.roi_en = 1;
reg_regions->roi_base.roi_pri = 0x1f;
if (region->intra) {
reg_regions->reg1063.roi0_mdc0_hevc.mdc_intra16 = 1;
reg_regions->roi_mdc_hevc.mdc_intra32 = 1;
}
reg_regions++;
}
DONE:
return ret;
}

3052
mpp/hal/rkenc/common/vepu511_common.h Normal file
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File diff suppressed because it is too large Load Diff

1
mpp/hal/rkenc/common/vepu5xx.h
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@@ -20,5 +20,6 @@
#define HWID_VEPU58X (0x50603312)
#define HWID_VEPU540C (0x50603313)
#define HWID_VEPU510 (0x506f2314)
#define HWID_VEPU511 (0x50602715)
#endif /* __VEPU5XX_H__ */

1
mpp/hal/rkenc/h264e/CMakeLists.txt
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@@ -16,6 +16,7 @@ set(HAL_H264E_SRC
hal_h264e_vepu580.c
hal_h264e_vepu540c.c
hal_h264e_vepu510.c
hal_h264e_vepu511.c
)
add_library(hal_h264e_rkv STATIC

2511
mpp/hal/rkenc/h264e/hal_h264e_vepu511.c Normal file
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File diff suppressed because it is too large Load Diff

13
mpp/hal/rkenc/h264e/hal_h264e_vepu511.h Normal file
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@@ -0,0 +1,13 @@
/* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
#ifndef __HAL_H264E_VEPU511_H__
#define __HAL_H264E_VEPU511_H__
#include "mpp_enc_hal.h"
extern const MppEncHalApi hal_h264e_vepu511;
#endif /* __HAL_H264E_VEPU511_H__ */

1204
mpp/hal/rkenc/h264e/hal_h264e_vepu511_reg.h Normal file
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File diff suppressed because it is too large Load Diff

2
mpp/hal/rkenc/h265e/CMakeLists.txt
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@@ -10,6 +10,7 @@ set(HAL_H265E_HDR
hal_h265e_vepu541_reg.h
hal_h265e_vepu580_reg.h
hal_h265e_vepu510_reg.h
hal_h265e_vepu511_reg.h
)
# hal h265 encoder sourse
@@ -18,6 +19,7 @@ set(HAL_H265E_SRC
hal_h265e_vepu580.c
hal_h265e_vepu540c.c
hal_h265e_vepu510.c
hal_h265e_vepu511.c
)
add_library(hal_h265e_vepu541 STATIC

2721
mpp/hal/rkenc/h265e/hal_h265e_vepu511.c Normal file
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File diff suppressed because it is too large Load Diff

13
mpp/hal/rkenc/h265e/hal_h265e_vepu511.h Normal file
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@@ -0,0 +1,13 @@
/* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
#ifndef __HAL_H265E_VEPU511_H__
#define __HAL_H265E_VEPU511_H__
#include "mpp_enc_hal.h"
extern const MppEncHalApi hal_h265e_vepu511;
#endif /* __HAL_H265E_VEPU511_H__ */

1575
mpp/hal/rkenc/h265e/hal_h265e_vepu511_reg.h Normal file
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File diff suppressed because it is too large Load Diff

2
mpp/hal/rkenc/jpege/CMakeLists.txt
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@@ -6,6 +6,7 @@ include_directories(../common/)
# hal jpeg header
set(HAL_JPEGE_HDR
hal_jpege_vepu540c_reg.h
hal_jpege_vepu511_reg.h
hal_jpege_vpu720_reg.h
hal_jpege_vpu720.h
)
@@ -13,6 +14,7 @@ set(HAL_JPEGE_HDR
# hal jpeg encoder sourse
set(HAL_JPEGE_SRC
hal_jpege_vepu540c.c
hal_jpege_vepu511.c
hal_jpege_vpu720.c
)

680
mpp/hal/rkenc/jpege/hal_jpege_vepu511.c Normal file
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@@ -0,0 +1,680 @@
/* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
#define MODULE_TAG "hal_jpege_v511"
#include <linux/string.h>
#include <string.h>
#include <math.h>
#include <limits.h>
#include "mpp_env.h"
#include "mpp_mem.h"
#include "mpp_soc.h"
#include "mpp_common.h"
#include "mpp_frame_impl.h"
#include "hal_jpege_debug.h"
#include "jpege_syntax.h"
#include "hal_bufs.h"
#include "rkv_enc_def.h"
#include "vepu541_common.h"
#include "vepu511_common.h"
#include "hal_jpege_vepu511.h"
#include "hal_jpege_vepu511_reg.h"
#include "hal_jpege_hdr.h"
typedef struct JpegeV511HalContext_t {
MppEncHalApi api;
MppDev dev;
void *regs;
void *reg_out;
void *dump_files;
RK_S32 frame_type;
RK_S32 last_frame_type;
/* @frame_cnt starts from ZERO */
RK_U32 frame_cnt;
void *roi_data;
MppEncCfgSet *cfg;
Vepu511OsdCfg osd_cfg;
RK_U32 enc_mode;
RK_U32 frame_size;
RK_S32 max_buf_cnt;
RK_S32 hdr_status;
void *input_fmt;
RK_U8 *src_buf;
RK_U8 *dst_buf;
RK_S32 buf_size;
RK_U32 frame_num;
RK_S32 fbc_header_len;
RK_U32 title_num;
JpegeBits bits;
JpegeSyntax syntax;
} JpegeV511HalContext;
MPP_RET hal_jpege_vepu511_init(void *hal, MppEncHalCfg *cfg)
{
MPP_RET ret = MPP_OK;
JpegeV511HalContext *ctx = (JpegeV511HalContext *)hal;
mpp_env_get_u32("hal_jpege_debug", &hal_jpege_debug, 0);
hal_jpege_enter();
ctx->reg_out = mpp_calloc(JpegV511Status, 1);
ctx->regs = mpp_calloc(JpegV511RegSet, 1);
ctx->input_fmt = mpp_calloc(VepuFmtCfg, 1);
ctx->cfg = cfg->cfg;
ctx->frame_cnt = 0;
ctx->enc_mode = 1;
cfg->type = VPU_CLIENT_RKVENC;
ret = mpp_dev_init(&cfg->dev, cfg->type);
if (ret) {
mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
return ret;
}
ctx->dev = cfg->dev;
jpege_bits_init(&ctx->bits);
mpp_assert(ctx->bits);
hal_jpege_leave();
return ret;
}
MPP_RET hal_jpege_vepu511_deinit(void *hal)
{
JpegeV511HalContext *ctx = (JpegeV511HalContext *)hal;
hal_jpege_enter();
jpege_bits_deinit(ctx->bits);
MPP_FREE(ctx->regs);
MPP_FREE(ctx->reg_out);
MPP_FREE(ctx->input_fmt);
if (ctx->dev) {
mpp_dev_deinit(ctx->dev);
ctx->dev = NULL;
}
hal_jpege_leave();
return MPP_OK;
}
static MPP_RET hal_jpege_vepu511_prepare(void *hal)
{
JpegeV511HalContext *ctx = (JpegeV511HalContext *)hal;
hal_jpege_dbg_func("enter %p\n", hal);
VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
vepu541_set_fmt(fmt, ctx->cfg->prep.format);
hal_jpege_dbg_func("leave %p\n", hal);
return MPP_OK;
}
static MPP_RET vepu511_jpeg_set_patch_info(MppDev dev, JpegeSyntax *syn,
Vepu541Fmt input_fmt,
HalEncTask *task)
{
RK_U32 hor_stride = syn->hor_stride;
RK_U32 ver_stride = syn->ver_stride ? syn->ver_stride : syn->height;
RK_U32 frame_size = hor_stride * ver_stride;
RK_U32 u_offset = 0, v_offset = 0;
MPP_RET ret = MPP_OK;
if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(task->frame))) {
u_offset = mpp_frame_get_fbc_offset(task->frame);
v_offset = u_offset;
} else {
switch (input_fmt) {
case VEPU541_FMT_YUV420P: {
u_offset = frame_size;
v_offset = frame_size * 5 / 4;
} break;
case VEPU541_FMT_YUV420SP:
case VEPU541_FMT_YUV422SP: {
u_offset = frame_size;
v_offset = frame_size;
} break;
case VEPU541_FMT_YUV422P: {
u_offset = frame_size;
v_offset = frame_size * 3 / 2;
} break;
case VEPU540_FMT_YUV400 :
case VEPU541_FMT_YUYV422:
case VEPU541_FMT_UYVY422: {
u_offset = 0;
v_offset = 0;
} break;
case VEPU580_FMT_YUV444SP : {
u_offset = frame_size;
v_offset = frame_size;
} break;
case VEPU580_FMT_YUV444P : {
u_offset = frame_size;
v_offset = frame_size * 2;
} break;
case VEPU541_FMT_BGR565:
case VEPU541_FMT_BGR888:
case VEPU541_FMT_BGRA8888: {
u_offset = 0;
v_offset = 0;
} break;
default: {
mpp_err("unknown color space: %d\n", input_fmt);
u_offset = frame_size;
v_offset = frame_size * 5 / 4;
}
}
}
/* input cb addr */
if (u_offset)
mpp_dev_set_reg_offset(dev, 265, u_offset);
/* input cr addr */
if (v_offset)
mpp_dev_set_reg_offset(dev, 266, v_offset);
return ret;
}
MPP_RET vepu511_set_jpeg_reg(Vepu511JpegCfg *cfg)
{
HalEncTask *task = ( HalEncTask *)cfg->enc_task;
JpegeSyntax *syn = (JpegeSyntax *)task->syntax.data;
Vepu511JpegReg *regs = (Vepu511JpegReg *)cfg->jpeg_reg_base;
VepuFmtCfg *fmt = (VepuFmtCfg *)cfg->input_fmt;
RK_U32 pic_width_align8, pic_height_align8;
RK_S32 stridey = 0;
RK_S32 stridec = 0;
pic_width_align8 = (syn->width + 7) & (~7);
pic_height_align8 = (syn->height + 7) & (~7);
regs->adr_src0 = mpp_buffer_get_fd(task->input);
regs->adr_src1 = regs->adr_src0;
regs->adr_src2 = regs->adr_src0;
vepu511_jpeg_set_patch_info(cfg->dev, syn, (Vepu541Fmt) fmt->format, task);
regs->adr_bsbt = mpp_buffer_get_fd(task->output);
regs->adr_bsbb = regs->adr_bsbt;
regs->adr_bsbs = regs->adr_bsbt;
regs->adr_bsbr = regs->adr_bsbt;
mpp_dev_set_reg_offset(cfg->dev, 258, mpp_packet_get_length(task->packet));
mpp_dev_set_reg_offset(cfg->dev, 256, mpp_buffer_get_size(task->output));
regs->enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1;
regs->src_fill.pic_wfill = (syn->width & 0x7)
? (8 - (syn->width & 0x7)) : 0;
regs->enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1;
regs->src_fill.pic_hfill = (syn->height & 0x7)
? (8 - (syn->height & 0x7)) : 0;
regs->src_fmt.src_cfmt = fmt->format;
regs->src_fmt.alpha_swap = fmt->alpha_swap;
regs->src_fmt.rbuv_swap = fmt->rbuv_swap;
regs->src_fmt.src_range_trns_en = 0;
regs->src_fmt.src_range_trns_sel = 0;
regs->src_fmt.chroma_ds_mode = 0;
regs->src_proc.src_mirr = syn->mirroring > 0;
regs->src_proc.src_rot = syn->rotation;
if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(task->frame))) {
regs->src_proc.rkfbcd_en = 1;
stridey = mpp_frame_get_fbc_hdr_stride(task->frame);
if (!stridey)
stridey = MPP_ALIGN(syn->hor_stride, 16) >> 2;
} else if (syn->hor_stride) {
stridey = syn->hor_stride;
} else {
if (regs->src_fmt.src_cfmt == VEPU541_FMT_BGRA8888 )
stridey = syn->width * 4;
else if (regs->src_fmt.src_cfmt == VEPU541_FMT_BGR888 ||
regs->src_fmt.src_cfmt == VEPU580_FMT_YUV444P ||
regs->src_fmt.src_cfmt == VEPU580_FMT_YUV444SP)
stridey = syn->width * 3;
else if (regs->src_fmt.src_cfmt == VEPU541_FMT_BGR565 ||
regs->src_fmt.src_cfmt == VEPU541_FMT_YUYV422 ||
regs->src_fmt.src_cfmt == VEPU541_FMT_UYVY422)
stridey = syn->width * 2;
}
stridec = (regs->src_fmt.src_cfmt == VEPU541_FMT_YUV422SP ||
regs->src_fmt.src_cfmt == VEPU541_FMT_YUV420SP ||
regs->src_fmt.src_cfmt == VEPU580_FMT_YUV444P) ?
stridey : stridey / 2;
if (regs->src_fmt.src_cfmt == VEPU580_FMT_YUV444SP)
stridec = stridey * 2;
if (regs->src_fmt.src_cfmt < VEPU541_FMT_NONE) {
regs->src_udfy.csc_wgt_r2y = 66;
regs->src_udfy.csc_wgt_g2y = 129;
regs->src_udfy.csc_wgt_b2y = 25;
regs->src_udfu.csc_wgt_r2u = -38;
regs->src_udfu.csc_wgt_g2u = -74;
regs->src_udfu.csc_wgt_b2u = 112;
regs->src_udfv.csc_wgt_r2v = 112;
regs->src_udfv.csc_wgt_g2v = -94;
regs->src_udfv.csc_wgt_b2v = -18;
regs->src_udfo.csc_ofst_y = 16;
regs->src_udfo.csc_ofst_u = 128;
regs->src_udfo.csc_ofst_v = 128;
}
regs->src_strd0.src_strd0 = stridey;
regs->src_strd1.src_strd1 = stridec;
regs->pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
regs->pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
regs->y_cfg.bias_y = 0;
regs->u_cfg.bias_u = 0;
regs->v_cfg.bias_v = 0;
regs->base_cfg.ri = syn->restart_ri;
regs->base_cfg.out_mode = 0;
regs->base_cfg.start_rst_m = 0;
regs->base_cfg.pic_last_ecs = 1;
regs->base_cfg.stnd = 1;
regs->uvc_cfg.uvc_partition0_len = 0;
regs->uvc_cfg.uvc_partition_len = 0;
regs->uvc_cfg.uvc_skip_len = 0;
return MPP_OK;
}
static MPP_RET hal_jpege_vepu510_set_roi(void *roi_reg_base, MppEncROICfg * roi,
RK_S32 w, RK_S32 h)
{
MppEncROIRegion *region = roi->regions;
Vepu511JpegReg *roi_reg = (Vepu511JpegReg *)roi_reg_base;
Vepu511JpegRoiRegion *reg_regions = &roi_reg->roi_regions[0];
RK_S32 i;
MPP_RET ret = MPP_NOK;
if (NULL == reg_regions) {
mpp_err_f("invalid reg_regions %p\n", reg_regions);
goto DONE;
}
memset(reg_regions, 0, sizeof(Vepu511RoiRegion) * 8);
if (NULL == roi) {
mpp_err_f("invalid buf %p roi %p\n", roi);
goto DONE;
}
if (roi->number > MPP_MAX_JPEG_ROI_NUM) {
mpp_err_f("invalid region number %d\n", roi->number);
goto DONE;
}
mpp_log_f("set roi vepu511: roi->number %d\n", roi->number);
/* check region config */
ret = MPP_OK;
for (i = 0; i < (RK_S32) roi->number; i++, region++) {
if (region->x + region->w > w || region->y + region->h > h)
ret = MPP_NOK;
if (region->intra > 1
|| region->qp_area_idx >= MPP_MAX_JPEG_ROI_NUM
|| region->area_map_en > 1 || region->abs_qp_en > 1)
ret = MPP_NOK;
if ((region->abs_qp_en && region->quality > 51) ||
(!region->abs_qp_en
&& (region->quality > 51 || region->quality < -51)))
ret = MPP_NOK;
if (ret) {
mpp_err_f("region %d invalid param:\n", i);
mpp_err_f("position [%d:%d:%d:%d] vs [%d:%d]\n",
region->x, region->y, region->w, region->h, w,
h);
mpp_err_f("force intra %d qp area index %d\n",
region->intra, region->qp_area_idx);
mpp_err_f("abs qp mode %d value %d\n",
region->abs_qp_en, region->quality);
goto DONE;
}
reg_regions->roi_cfg0.roi0_rdoq_en = 1;
reg_regions->roi_cfg0.roi0_rdoq_level = region->quality;
reg_regions->roi_cfg0.roi0_rdoq_start_x = MPP_ALIGN(region->x, 16) >> 3;
reg_regions->roi_cfg0.roi0_rdoq_start_y = MPP_ALIGN(region->y, 16) >> 3;
reg_regions->roi_cfg1.roi0_rdoq_width_m1 = (MPP_ALIGN(region->w, 16) >> 3) - 1;
reg_regions->roi_cfg1.roi0_rdoq_height_m1 = (MPP_ALIGN(region->h, 16) >> 3) - 1;
reg_regions++;
}
DONE:
return ret;
}
MPP_RET hal_jpege_vepu511_gen_regs(void *hal, HalEncTask *task)
{
JpegeV511HalContext *ctx = (JpegeV511HalContext *)hal;
JpegV511RegSet *regs = ctx->regs;
Vepu511ControlCfg *reg_ctl = &regs->reg_ctl;
JpegVepu511Base *reg_base = &regs->reg_base;
JpegeBits bits = ctx->bits;
const RK_U8 *qtable[2] = {NULL};
size_t length = mpp_packet_get_length(task->packet);
RK_U8 *buf = mpp_buffer_get_ptr(task->output);
size_t size = mpp_buffer_get_size(task->output);
JpegeSyntax *syntax = &ctx->syntax;
VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
Vepu511JpegCfg cfg;
RK_S32 bitpos;
hal_jpege_enter();
cfg.enc_task = task;
cfg.jpeg_reg_base = &reg_base->jpegReg;
cfg.dev = ctx->dev;
cfg.input_fmt = ctx->input_fmt;
memset(regs, 0, sizeof(JpegV511RegSet));
/* write header to output buffer */
jpege_bits_setup(bits, buf, (RK_U32)size);
/* seek length bytes data */
jpege_seek_bits(bits, length << 3);
/* NOTE: write header will update qtable */
write_jpeg_header(bits, syntax, qtable);
bitpos = jpege_bits_get_bitpos(bits);
task->length = (bitpos + 7) >> 3;
mpp_buffer_sync_partial_end(task->output, 0, task->length);
mpp_packet_set_length(task->packet, task->length);
reg_ctl->enc_strt.lkt_num = 0;
reg_ctl->enc_strt.vepu_cmd = ctx->enc_mode;
reg_ctl->enc_clr.safe_clr = 0x0;
reg_ctl->enc_clr.force_clr = 0x0;
reg_ctl->int_en.enc_done_en = 1;
reg_ctl->int_en.lkt_node_done_en = 1;
reg_ctl->int_en.sclr_done_en = 1;
reg_ctl->int_en.vslc_done_en = 1;
reg_ctl->int_en.vbsf_oflw_en = 1;
reg_ctl->int_en.jbuf_lens_en = 1;
reg_ctl->int_en.enc_err_en = 1;
reg_ctl->int_en.vsrc_err_en = 1;
reg_ctl->int_en.wdg_en = 1;
reg_ctl->int_en.lkt_err_int_en = 0;
reg_ctl->int_en.lkt_err_stop_en = 0;
reg_ctl->int_en.lkt_force_stop_en = 0;
reg_ctl->int_en.jslc_done_en = 0;
reg_ctl->int_en.jbsf_oflw_en = 0;
reg_ctl->int_en.dvbm_err_en = 0;
reg_ctl->dtrns_map.jpeg_bus_edin = 0x7;
reg_ctl->dtrns_map.src_bus_edin = 0x0;
reg_ctl->dtrns_map.meiw_bus_edin = 0x0;
reg_ctl->dtrns_map.bsw_bus_edin = 0x0;
reg_ctl->dtrns_map.lktr_bus_edin = 0x0;
reg_ctl->dtrns_map.roir_bus_edin = 0x0;
reg_ctl->dtrns_map.lktw_bus_edin = 0x0;
reg_ctl->dtrns_map.rec_nfbc_bus_edin = 0x0;
reg_ctl->dtrns_cfg.jsrc_bus_edin = fmt->src_endian;
reg_base->common.enc_pic.enc_stnd = 2; // disable h264 or hevc
reg_ctl->dtrns_cfg.axi_brsp_cke = 0x0;
reg_ctl->enc_wdg.vs_load_thd = 0x1fffff;
reg_base->common.enc_pic.jpeg_slen_fifo = 0;
vepu511_set_jpeg_reg(&cfg);
if (ctx->roi_data) {
mpp_log_f("set roi data2\n");
hal_jpege_vepu510_set_roi(&regs->reg_base.jpegReg, ctx->roi_data,
ctx->cfg->prep.width, ctx->cfg->prep.height);
}
if (ctx->osd_cfg.osd_data3 || ctx->osd_cfg.osd_data)
vepu511_set_osd(&ctx->osd_cfg, &regs->reg_osd.osd_jpeg_cfg);
{
RK_U16 *tbl = &regs->jpeg_table.qua_tab0[0];
RK_U32 i, j;
for ( i = 0; i < 8; i++) {
for ( j = 0; j < 8; j++) {
tbl[i * 8 + j] = 0x8000 / qtable[0][j * 8 + i];
}
}
tbl += 64;
for ( i = 0; i < 8; i++) {
for ( j = 0; j < 8; j++) {
tbl[i * 8 + j] = 0x8000 / qtable[1][j * 8 + i];
}
}
tbl += 64;
for ( i = 0; i < 8; i++) {
for ( j = 0; j < 8; j++) {
tbl[i * 8 + j] = 0x8000 / qtable[1][j * 8 + i];
}
}
}
ctx->frame_num++;
hal_jpege_leave();
return MPP_OK;
}
MPP_RET hal_jpege_vepu511_start(void *hal, HalEncTask *enc_task)
{
MPP_RET ret = MPP_OK;
JpegeV511HalContext *ctx = (JpegeV511HalContext *)hal;
JpegV511RegSet *hw_regs = ctx->regs;
JpegV511Status *reg_out = ctx->reg_out;
MppDevRegWrCfg cfg;
MppDevRegRdCfg cfg1;
hal_jpege_enter();
if (enc_task->flags.err) {
mpp_err_f("enc_task->flags.err %08x, return e arly",
enc_task->flags.err);
return MPP_NOK;
}
cfg.reg = (RK_U32*)&hw_regs->reg_ctl;
cfg.size = sizeof(Vepu511ControlCfg);
cfg.offset = VEPU511_CTL_OFFSET;
ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
if (ret) {
mpp_err_f("set register write failed %d\n", ret);
return ret;
}
cfg.reg = &hw_regs->jpeg_table;
cfg.size = sizeof(JpegVepu511Tab);
cfg.offset = VEPU511_JPEGTAB_OFFSET;
ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
if (ret) {
mpp_err_f("set register write failed %d\n", ret);
return ret;
}
cfg.reg = &hw_regs->reg_base;
cfg.size = sizeof(JpegVepu511Base);
cfg.offset = VEPU511_FRAME_OFFSET;
ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
if (ret) {
mpp_err_f("set register write failed %d\n", ret);
return ret;
}
cfg.reg = &hw_regs->reg_osd;
cfg.size = sizeof(Vepu511OsdRegs);
cfg.offset = VEPU511_OSD_OFFSET;
ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
if (ret) {
mpp_err_f("set register write failed %d\n", ret);
return ret;
}
cfg1.reg = &reg_out->hw_status;
cfg1.size = sizeof(RK_U32);
cfg1.offset = VEPU511_REG_BASE_HW_STATUS;
ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
if (ret) {
mpp_err_f("set register read failed %d\n", ret);
return ret;
}
cfg1.reg = &reg_out->st;
cfg1.size = sizeof(JpegV511Status) - 4;
cfg1.offset = VEPU511_STATUS_OFFSET;
ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
if (ret) {
mpp_err_f("set register read failed %d\n", ret);
return ret;
}
ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
if (ret) {
mpp_err_f("send cmd failed %d\n", ret);
}
hal_jpege_leave();
return ret;
}
static MPP_RET hal_jpege_vepu511_status_check(void *hal)
{
JpegeV511HalContext *ctx = (JpegeV511HalContext *)hal;
JpegV511Status *elem = (JpegV511Status *)ctx->reg_out;
RK_U32 hw_status = elem->hw_status;
if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH)
mpp_err_f("RKV_ENC_INT_LINKTABLE_FINISH");
if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH)
mpp_err_f("RKV_ENC_INT_ONE_SLICE_FINISH");
if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH)
mpp_err_f("RKV_ENC_INT_SAFE_CLEAR_FINISH");
if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW)
mpp_err_f("RKV_ENC_INT_BIT_STREAM_OVERFLOW");
if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL)
mpp_err_f("RKV_ENC_INT_BUS_WRITE_FULL");
if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR)
mpp_err_f("RKV_ENC_INT_BUS_WRITE_ERROR");
if (hw_status & RKV_ENC_INT_BUS_READ_ERROR)
mpp_err_f("RKV_ENC_INT_BUS_READ_ERROR");
if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR)
mpp_err_f("RKV_ENC_INT_TIMEOUT_ERROR");
return MPP_OK;
}
MPP_RET hal_jpege_vepu511_wait(void *hal, HalEncTask *task)
{
MPP_RET ret = MPP_OK;
JpegeV511HalContext *ctx = (JpegeV511HalContext *)hal;
HalEncTask *enc_task = task;
JpegV511Status *elem = (JpegV511Status *)ctx->reg_out;
hal_jpege_enter();
if (enc_task->flags.err) {
mpp_err_f("enc_task->flags.err %08x, return early",
enc_task->flags.err);
return MPP_NOK;
}
ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
if (ret) {
mpp_err_f("poll cmd failed %d\n", ret);
ret = MPP_ERR_VPUHW;
} else {
hal_jpege_vepu511_status_check(hal);
task->hw_length += elem->st.jpeg_head_bits_l32;
}
hal_jpege_leave();
return ret;
}
MPP_RET hal_jpege_vepu511_get_task(void *hal, HalEncTask *task)
{
JpegeV511HalContext *ctx = (JpegeV511HalContext *)hal;
MppFrame frame = task->frame;
EncFrmStatus *frm_status = &task->rc_task->frm;
JpegeSyntax *syntax = (JpegeSyntax *)task->syntax.data;
hal_jpege_enter();
memcpy(&ctx->syntax, syntax, sizeof(ctx->syntax));
ctx->last_frame_type = ctx->frame_type;
if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
MppMeta meta = mpp_frame_get_meta(frame);
mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
mpp_meta_get_ptr(meta, KEY_OSD_DATA3, (void **)&ctx->osd_cfg.osd_data3);
}
hal_jpege_leave();
return MPP_OK;
}
MPP_RET hal_jpege_vepu511_ret_task(void *hal, HalEncTask *task)
{
(void)hal;
EncRcTaskInfo *rc_info = &task->rc_task->info;
hal_jpege_enter();
task->length += task->hw_length;
// setup bit length for rate control
rc_info->bit_real = task->hw_length * 8;
rc_info->quality_real = rc_info->quality_target;
hal_jpege_leave();
return MPP_OK;
}
const MppEncHalApi hal_jpege_vepu511 = {
.name = "hal_jpege_v511",
.coding = MPP_VIDEO_CodingMJPEG,
.ctx_size = sizeof(JpegeV511HalContext),
.flag = 0,
.init = hal_jpege_vepu511_init,
.deinit = hal_jpege_vepu511_deinit,
.prepare = hal_jpege_vepu511_prepare,
.get_task = hal_jpege_vepu511_get_task,
.gen_regs = hal_jpege_vepu511_gen_regs,
.start = hal_jpege_vepu511_start,
.wait = hal_jpege_vepu511_wait,
.part_start = NULL,
.part_wait = NULL,
.ret_task = hal_jpege_vepu511_ret_task,
};

15
mpp/hal/rkenc/jpege/hal_jpege_vepu511.h Normal file
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@@ -0,0 +1,15 @@
/* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
#ifndef __HAL_JPEGE_VEPU511_H__
#define __HAL_JPEGE_VEPU511_H__
#include "mpp_enc_hal.h"
extern const MppEncHalApi hal_jpege_vepu511;
#define MPP_MAX_JPEG_ROI_NUM 16
#define MPP_MAX_JPEG_ROI_LEVEL 63
#endif /* __HAL_JPEGE_VEPU511_H__ */

384
mpp/hal/rkenc/jpege/hal_jpege_vepu511_reg.h Normal file
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@@ -0,0 +1,384 @@
/* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
#ifndef __HAL_JPEGE_VEPU511_REG_H__
#define __HAL_JPEGE_VEPU511_REG_H__
#include "rk_type.h"
#include "vepu511_common.h"
typedef struct Vepu511JpegRoiRegion_t {
struct {
RK_U32 roi0_rdoq_start_x : 11;
RK_U32 roi0_rdoq_start_y : 11;
RK_U32 reserved : 3;
RK_U32 roi0_rdoq_level : 6;
RK_U32 roi0_rdoq_en : 1;
} roi_cfg0;
struct {
RK_U32 roi0_rdoq_width_m1 : 11;
RK_U32 roi0_rdoq_height_m1 : 11;
/* the below 10 bits only for roi0 */
RK_U32 reserved : 3;
RK_U32 frm_rdoq_level : 6;
RK_U32 frm_rdoq_en : 1;
} roi_cfg1;
} Vepu511JpegRoiRegion;
/* 0x00000400 reg256 - 0x0000050c reg323*/
typedef struct Vepu511JpegReg_t {
/* 0x00000400 reg256 */
RK_U32 adr_bsbt;
/* 0x00000404 reg257 */
RK_U32 adr_bsbb;
/* 0x00000408 reg258 */
RK_U32 adr_bsbs;
/* 0x0000040c reg259 */
RK_U32 adr_bsbr;
/* 0x00000410 reg260 */
RK_U32 adr_vsy_b;
/* 0x00000414 reg261 */
RK_U32 adr_vsc_b;
/* 0x00000418 reg262 */
RK_U32 adr_vsy_t;
/* 0x0000041c reg263 */
RK_U32 adr_vsc_t;
/* 0x00000420 reg264 */
RK_U32 adr_src0;
/* 0x00000424 reg265 */
RK_U32 adr_src1;
/* 0x00000428 reg266 */
RK_U32 adr_src2;
/* 0x0000042c reg267 */
RK_U32 bsp_size;
/* 0x430 - 0x43c */
RK_U32 reserved268_271[4];
/* 0x00000440 reg272 */
struct {
RK_U32 pic_wd8_m1 : 11;
RK_U32 reserved : 1;
RK_U32 pp0_vnum_m1 : 4;
RK_U32 pic_hd8_m1 : 11;
RK_U32 reserved1 : 1;
RK_U32 pp0_jnum_m1 : 4;
} enc_rsl;
/* 0x00000444 reg273 */
struct {
RK_U32 pic_wfill : 6;
RK_U32 reserved : 10;
RK_U32 pic_hfill : 6;
RK_U32 reserved1 : 10;
} src_fill;
/* 0x00000448 reg274 */
struct {
RK_U32 alpha_swap : 1;
RK_U32 rbuv_swap : 1;
RK_U32 src_cfmt : 4;
RK_U32 reserved : 2;
RK_U32 src_range_trns_en : 1;
RK_U32 src_range_trns_sel : 1;
RK_U32 chroma_ds_mode : 1;
RK_U32 reserved1 : 21;
} src_fmt;
/* 0x0000044c reg275 */
struct {
RK_U32 csc_wgt_b2y : 9;
RK_U32 csc_wgt_g2y : 9;
RK_U32 csc_wgt_r2y : 9;
RK_U32 reserved : 5;
} src_udfy;
/* 0x00000450 reg276 */
struct {
RK_U32 csc_wgt_b2u : 9;
RK_U32 csc_wgt_g2u : 9;
RK_U32 csc_wgt_r2u : 9;
RK_U32 reserved : 5;
} src_udfu;
/* 0x00000454 reg277 */
struct {
RK_U32 csc_wgt_b2v : 9;
RK_U32 csc_wgt_g2v : 9;
RK_U32 csc_wgt_r2v : 9;
RK_U32 reserved : 5;
} src_udfv;
/* 0x00000458 reg278 */
struct {
RK_U32 csc_ofst_v : 8;
RK_U32 csc_ofst_u : 8;
RK_U32 csc_ofst_y : 5;
RK_U32 reserved : 11;
} src_udfo;
/* 0x0000045c reg279 */
struct {
RK_U32 cr_force_value : 8;
RK_U32 cb_force_value : 8;
RK_U32 chroma_force_en : 1;
RK_U32 reserved : 9;
RK_U32 src_mirr : 1;
RK_U32 src_rot : 2;
RK_U32 reserved1 : 1;
RK_U32 rkfbcd_en : 1;
RK_U32 reserved2 : 1;
} src_proc;
/* 0x00000460 reg280 */
struct {
RK_U32 pic_ofst_x : 14;
RK_U32 reserved : 2;
RK_U32 pic_ofst_y : 14;
RK_U32 reserved1 : 2;
} pic_ofst;
/* 0x00000464 reg281 */
struct {
RK_U32 src_strd0 : 21;
RK_U32 reserved : 11;
} src_strd0;
/* 0x00000468 reg282 */
struct {
RK_U32 src_strd1 : 16;
RK_U32 reserved : 16;
} src_strd1;
/* 0x0000046c reg283 */
struct {
RK_U32 pp_corner_filter_strength : 2;
RK_U32 reserved : 2;
RK_U32 pp_edge_filter_strength : 2;
RK_U32 reserved1 : 2;
RK_U32 pp_internal_filter_strength : 2;
RK_U32 reserved2 : 22;
} src_flt_cfg;
/* 0x00000470 reg284 */
struct {
RK_U32 bias_y : 15;
RK_U32 reserved : 17;
} y_cfg;
/* 0x00000474 reg285 */
struct {
RK_U32 bias_u : 15;
RK_U32 reserved : 17;
} u_cfg;
/* 0x00000478 reg286 */
struct {
RK_U32 bias_v : 15;
RK_U32 reserved : 17;
} v_cfg;
/* 0x0000047c reg287 */
struct {
RK_U32 ri : 25;
RK_U32 out_mode : 1;
RK_U32 start_rst_m : 3;
RK_U32 pic_last_ecs : 1;
RK_U32 reserved : 1;
RK_U32 stnd : 1;
} base_cfg;
/* 0x00000480 reg288 */
struct {
RK_U32 uvc_partition0_len : 12;
RK_U32 uvc_partition_len : 12;
RK_U32 uvc_skip_len : 6;
RK_U32 reserved : 2;
} uvc_cfg;
/* 0x00000484 reg289 */
struct {
RK_U32 reserved : 4;
RK_U32 eslf_badr : 28;
} adr_eslf;
/* 0x00000488 reg290 */
struct {
RK_U32 eslf_rptr : 10;
RK_U32 eslf_wptr : 10;
RK_U32 eslf_blen : 10;
RK_U32 eslf_updt : 2;
} eslf_buf;
/* 0x48c */
RK_U32 reserved_291;
/* 0x00000490 reg292 - 0x0000050c reg323*/
Vepu511JpegRoiRegion roi_regions[16];
} Vepu511JpegReg;
/* 0x00002ca0 reg2856 - - 0x00002e1c reg2951 */
typedef struct JpegVepu511Tab_t {
RK_U16 qua_tab0[64];
RK_U16 qua_tab1[64];
RK_U16 qua_tab2[64];
} JpegVepu511Tab;
typedef struct Vepu511JpegOsdCfg_t {
/* 0x00003138 reg3150 */
struct {
RK_U32 osd_en : 1;
RK_U32 reserved : 4;
RK_U32 osd_qp_adj_en : 1;
RK_U32 osd_range_trns_en : 1;
RK_U32 osd_range_trns_sel : 1;
RK_U32 osd_fmt : 4;
RK_U32 osd_alpha_swap : 1;
RK_U32 osd_rbuv_swap : 1;
RK_U32 reserved1 : 8;
RK_U32 osd_fg_alpha : 8;
RK_U32 osd_fg_alpha_sel : 2;
} osd_cfg0;
/* 0x0000313c reg3151 */
struct {
RK_U32 osd_lt_xcrd : 14;
RK_U32 osd_lt_ycrd : 14;
RK_U32 osd_endn : 4;
} osd_cfg1;
/* 0x00003140 reg3152 */
struct {
RK_U32 osd_rb_xcrd : 14;
RK_U32 osd_rb_ycrd : 14;
RK_U32 reserved : 4;
} osd_cfg2;
/* 0x00003144 reg3153 */
RK_U32 osd_st_addr;
/* 0x3148 */
RK_U32 reserved_3154;
/* 0x0000314c reg3155 */
struct {
RK_U32 osd_stride : 17;
RK_U32 reserved : 8;
RK_U32 osd_ch_ds_mode : 1;
RK_U32 reserved1 : 6;
} osd_cfg5;
/* 0x00003150 reg3156 */
struct {
RK_U32 osd_v_b_lut0 : 8;
RK_U32 osd_u_g_lut0 : 8;
RK_U32 osd_y_r_lut0 : 8;
RK_U32 osd_v_b_lut1 : 8;
} osd_cfg6;
/* 0x00003154 reg3157 */
struct {
RK_U32 osd0_u_g_lut1 : 8;
RK_U32 osd0_y_r_lut1 : 8;
RK_U32 osd0_alpha_lut0 : 8;
RK_U32 osd0_alpha_lut1 : 8;
} osd_cfg7;
/* 0x3158 */
RK_U32 reserved_3158;
} JpegVepu511Osd_cfg;
/* 0x00003138 reg3150 - - 0x00003264 reg3225 */
typedef struct Vepu511JpegOsd_t {
JpegVepu511Osd_cfg osd_cfg[8];
/* 0x00003258 reg3222 */
struct {
RK_U32 osd_csc_yr : 9;
RK_U32 osd_csc_yg : 9;
RK_U32 osd_csc_yb : 9;
RK_U32 reserved : 5;
} osd_whi_cfg0;
/* 0x0000325c reg3223 */
struct {
RK_U32 osd_csc_ur : 9;
RK_U32 osd_csc_ug : 9;
RK_U32 osd_csc_ub : 9;
RK_U32 reserved : 5;
} osd_whi_cfg1;
/* 0x00003260 reg3224 */
struct {
RK_U32 osd_csc_vr : 9;
RK_U32 osd_csc_vg : 9;
RK_U32 osd_csc_vb : 9;
RK_U32 reserved : 5;
} osd_whi_cfg2;
/* 0x00003264 reg3225 */
struct {
RK_U32 osd_csc_ofst_y : 8;
RK_U32 osd_csc_ofst_u : 8;
RK_U32 osd_csc_ofst_v : 8;
RK_U32 reserved : 8;
} osd_whi_cfg3;
} JpegVepu511Osd;
/* class: buffer/video syntax */
/* 0x00000270 reg156 - 0x0000050c reg323 */
typedef struct JpegVepu511Base_t {
/* 0x00000270 reg156 - 0x0000039c reg231 */
Vepu511FrmCommon common;
/* 0x000003a0 reg232 - 0x000003f4 reg253*/
RK_U32 reserved232_253[22];
/* 0x000003f8 reg254 */
struct {
RK_U32 slice_sta_x : 9;
RK_U32 reserved1 : 7;
RK_U32 slice_sta_y : 10;
RK_U32 reserved2 : 5;
RK_U32 slice_enc_ena : 1;
} slice_enc_cfg0;
/* 0x000003fc reg255 */
struct {
RK_U32 slice_end_x : 9;
RK_U32 reserved : 7;
RK_U32 slice_end_y : 10;
RK_U32 reserved1 : 6;
} slice_enc_cfg1;
/* 0x00000400 reg256 - 0x0000050c reg323 */
Vepu511JpegReg jpegReg;
} JpegVepu511Base;
typedef struct JpegV511RegSet_t {
Vepu511ControlCfg reg_ctl;
JpegVepu511Base reg_base;
JpegVepu511Tab jpeg_table;
Vepu511OsdRegs reg_osd;
Vepu511Dbg reg_dbg;
} JpegV511RegSet;
typedef struct JpegV511Status_t {
RK_U32 hw_status;
Vepu511Status st;
} JpegV511Status;
#endif