diff --git a/mpp/codec/enc/h265/h265e_api.c b/mpp/codec/enc/h265/h265e_api.c
index 4e9a5ea1..259391ce 100644
--- a/mpp/codec/enc/h265/h265e_api.c
+++ b/mpp/codec/enc/h265/h265e_api.c
@@ -89,7 +89,9 @@ static MPP_RET h265e_init(void *ctx, EncImplCfg *ctrlCfg)
     h265->const_intra_pred = 0;           /* constraint intra prediction flag */
 
     soc_type = mpp_get_soc_type();
-    if (soc_type == ROCKCHIP_SOC_RK3528 || soc_type == ROCKCHIP_SOC_RK3576)
+    if (soc_type == ROCKCHIP_SOC_RK3528 ||
+        soc_type == ROCKCHIP_SOC_RK3576 ||
+        soc_type == ROCKCHIP_SOC_RV1126B)
         h265->max_cu_size = 32;
     else
         h265->max_cu_size = 64;
diff --git a/mpp/codec/enc/h265/h265e_ps.c b/mpp/codec/enc/h265/h265e_ps.c
index 4ae942fc..f92db241 100644
--- a/mpp/codec/enc/h265/h265e_ps.c
+++ b/mpp/codec/enc/h265/h265e_ps.c
@@ -194,6 +194,7 @@ MPP_RET h265e_set_sps(H265eCtx *ctx, H265eSps *sps, H265eVps *vps)
     RK_S32 minCUSize, log2MinCUSize;
     RK_S32 tuQTMinLog2Size = 2, tuQTMaxLog2Size;
     MppEncCpbInfo *cpb_info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
+    RockchipSocType soc_type;
     RK_U32 *tmp = &sps->zscan2raster[0];
 
     memset(convertToBit, -1, sizeof(convertToBit));
@@ -208,7 +209,8 @@ MPP_RET h265e_set_sps(H265eCtx *ctx, H265eSps *sps, H265eVps *vps)
     minCUDepth = (codec->max_cu_size >> (maxCUDepth - 1));
 
     tuQTMaxLog2Size = convertToBit[codec->max_cu_size] + 2 - 1;
-    if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3576) {
+    soc_type = mpp_get_soc_type();
+    if (soc_type == ROCKCHIP_SOC_RK3576 || soc_type == ROCKCHIP_SOC_RV1126B) {
         tuQTMaxLog2Size = tuQTMaxLog2Size + 1;
     }
 
diff --git a/mpp/codec/enc/h265/h265e_syntax.c b/mpp/codec/enc/h265/h265e_syntax.c
index c4e1fd7b..381a83f4 100644
--- a/mpp/codec/enc/h265/h265e_syntax.c
+++ b/mpp/codec/enc/h265/h265e_syntax.c
@@ -154,7 +154,7 @@ static void fill_slice_parameters( const H265eCtx *h,
     sp->ref_pic_lst_mdf_l0  = slice->ref_pic_list_modification_flag_l0;
 
     sp->num_refidx_l1_act   = 0;
-    sp->num_refidx_l0_act   = 1;
+    sp->num_refidx_l0_act   = 0;
 
     sp->num_refidx_act_ovrd = (((RK_U32)slice->m_numRefIdx[0] != slice->m_pps->m_numRefIdxL0DefaultActive)
                                || (slice->m_sliceType == B_SLICE &&
diff --git a/mpp/hal/common/h264/hal_h264e_api_v2.c b/mpp/hal/common/h264/hal_h264e_api_v2.c
index 5d56ca8d..de543394 100644
--- a/mpp/hal/common/h264/hal_h264e_api_v2.c
+++ b/mpp/hal/common/h264/hal_h264e_api_v2.c
@@ -34,6 +34,7 @@
 #include "hal_h264e_vepu580.h"
 #include "hal_h264e_vepu540c.h"
 #include "hal_h264e_vepu510.h"
+#include "hal_h264e_vepu511.h"
 
 typedef struct HalH264eCtx_t {
     const MppEncHalApi  *api;
@@ -65,6 +66,9 @@ static MPP_RET hal_h264e_init(void *hal, MppEncHalCfg *cfg)
         case HWID_VEPU510 : {
             api = &hal_h264e_vepu510;
         } break;
+        case HWID_VEPU511 : {
+            api = &hal_h264e_vepu511;
+        } break;
         default : {
             api = &hal_h264e_vepu541;
         } break;
diff --git a/mpp/hal/common/h265/hal_h265e_api_v2.c b/mpp/hal/common/h265/hal_h265e_api_v2.c
index c7a62bbd..bdaccd7b 100644
--- a/mpp/hal/common/h265/hal_h265e_api_v2.c
+++ b/mpp/hal/common/h265/hal_h265e_api_v2.c
@@ -31,6 +31,7 @@
 #include "hal_h265e_vepu580.h"
 #include "hal_h265e_vepu540c.h"
 #include "hal_h265e_vepu510.h"
+#include "hal_h265e_vepu511.h"
 
 typedef struct HalH265eV2Ctx_t {
     const MppEncHalApi  *api;
@@ -60,6 +61,9 @@ static MPP_RET hal_h265ev2_init(void *hal, MppEncHalCfg *cfg)
         case HWID_VEPU510 : {
             api = &hal_h265e_vepu510;
         } break;
+        case HWID_VEPU511 : {
+            api = &hal_h265e_vepu511;
+        } break;
         default : {
             api = &hal_h265e_vepu541;
         } break;
diff --git a/mpp/hal/common/jpeg/hal_jpege_api_v2.c b/mpp/hal/common/jpeg/hal_jpege_api_v2.c
index d943f9af..7607fb90 100644
--- a/mpp/hal/common/jpeg/hal_jpege_api_v2.c
+++ b/mpp/hal/common/jpeg/hal_jpege_api_v2.c
@@ -32,6 +32,7 @@
 #include "hal_jpege_vepu2_v2.h"
 #include "hal_jpege_vepu540c.h"
 #include "hal_jpege_vpu720.h"
+#include "hal_jpege_vepu511.h"
 
 typedef struct HaljpegeCtx_t {
     const MppEncHalApi  *api;
@@ -50,9 +51,15 @@ static MPP_RET hal_jpege_init(void *hal, MppEncHalCfg *cfg)
 
     mpp_env_get_u32("hal_jpege_debug", &hal_jpege_debug, 0);
 
-    if ((vcodec_type & HAVE_RKVENC) &&
-        (HWID_VEPU540C == mpp_get_client_hw_id(VPU_CLIENT_RKVENC))) {
-        api = &hal_jpege_vepu540c;
+    if (vcodec_type & HAVE_RKVENC) {
+        if (HWID_VEPU540C == mpp_get_client_hw_id(VPU_CLIENT_RKVENC))
+            api = &hal_jpege_vepu540c;
+        else if (HWID_VEPU511 == mpp_get_client_hw_id(VPU_CLIENT_RKVENC))
+            api = &hal_jpege_vepu511;
+        else {
+            mpp_err("vcodec type %08x can not find JPEG encoder device\n", vcodec_type);
+            ret = MPP_NOK;
+        }
     } else if (vcodec_type & (HAVE_VEPU2 | HAVE_VEPU2_JPEG)) {
         api = &hal_jpege_vepu2;
     } else if (vcodec_type & HAVE_VEPU1) {
diff --git a/mpp/hal/rkenc/common/CMakeLists.txt b/mpp/hal/rkenc/common/CMakeLists.txt
index 65e8ebb2..0c4b9c3f 100644
--- a/mpp/hal/rkenc/common/CMakeLists.txt
+++ b/mpp/hal/rkenc/common/CMakeLists.txt
@@ -8,6 +8,7 @@ add_library(hal_vepu541_common STATIC
             vepu540c_common.c
             vepu580_tune.c
             vepu510_common.c
+            vepu511_common.c
             )
 
 target_link_libraries(hal_vepu541_common mpp_base)
diff --git a/mpp/hal/rkenc/common/vepu511_common.c b/mpp/hal/rkenc/common/vepu511_common.c
new file mode 100644
index 00000000..f81e9953
--- /dev/null
+++ b/mpp/hal/rkenc/common/vepu511_common.c
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG  "vepu511_common"
+
+#include <string.h>
+#include "mpp_log.h"
+#include "mpp_common.h"
+#include "vepu511_common.h"
+#include "jpege_syntax.h"
+#include "vepu541_common.h"
+#include "hal_enc_task.h"
+#include "mpp_frame_impl.h"
+#include "mpp_packet.h"
+#include "mpp_debug.h"
+#include "mpp_mem.h"
+
+MPP_RET vepu511_set_osd(Vepu511OsdCfg * cfg, Vepu511Osd *osd_reg)
+{
+    Vepu511Osd *regs = osd_reg;
+    MppEncOSDData3 *osd_ptr = cfg->osd_data3;
+    Vepu511OsdRegion *osd_regions = &regs->osd_regions[0];
+    MppEncOSDRegion3 *region = osd_ptr->region;
+    RK_U32 i = 0;
+
+    if (NULL == osd_regions) {
+        mpp_err_f("invalid reg_regions %p\n", osd_regions);
+    }
+
+    memset(osd_regions, 0, sizeof(Vepu511OsdRegion) * 8);
+    if (osd_ptr->num_region > 8) {
+        mpp_err_f("do NOT support more than 8 regions invalid num %d\n",
+                  osd_ptr->num_region);
+        mpp_assert(osd_ptr->num_region <= 8);
+        return MPP_NOK;
+    }
+
+    for (i = 0; i < osd_ptr->num_region; i++, region++) {
+        Vepu511OsdRegion *reg = &osd_reg->osd_regions[i];
+        VepuFmtCfg fmt_cfg;
+        MppFrameFormat fmt = region->fmt;
+
+        vepu541_set_fmt(&fmt_cfg, fmt);
+        reg->cfg0.osd_en = region->enable;
+        reg->cfg0.osd_range_trns_en = region->range_trns_en;
+        reg->cfg0.osd_range_trns_sel = region->range_trns_sel;
+        reg->cfg0.osd_fmt = fmt_cfg.format;
+        reg->cfg0.osd_rbuv_swap = region->rbuv_swap;
+        reg->cfg1.osd_lt_xcrd = region->lt_x;
+        reg->cfg1.osd_lt_ycrd = region->lt_y;
+        reg->cfg2.osd_rb_xcrd = region->rb_x;
+        reg->cfg2.osd_rb_ycrd = region->rb_y;
+
+        reg->cfg1.osd_endn = region->osd_endn;
+        reg->cfg5.osd_stride = region->stride;
+        reg->cfg5.osd_ch_ds_mode = region->ch_ds_mode;
+        reg->cfg0.osd_alpha_swap = region->alpha_cfg.alpha_swap;
+        reg->cfg0.osd_fg_alpha = region->alpha_cfg.fg_alpha;
+        reg->cfg0.osd_fg_alpha_sel = region->alpha_cfg.fg_alpha_sel;
+        reg->cfg0.osd_qp_adj_en = region->qp_cfg.qp_adj_en;
+        reg->cfg8.osd_qp_adj_sel = region->qp_cfg.qp_adj_sel;
+        reg->cfg8.osd_qp = region->qp_cfg.qp;
+        reg->cfg8.osd_qp_max = region->qp_cfg.qp_max;
+        reg->cfg8.osd_qp_min = region->qp_cfg.qp_min;
+        reg->cfg8.osd_qp_prj = region->qp_cfg.qp_prj;
+
+        if (region->osd_buf.buf)
+            reg->osd_st_addr = mpp_buffer_get_fd(region->osd_buf.buf);
+    }
+
+    regs->osd_whi_cfg0.osd_csc_yr = 77;
+    regs->osd_whi_cfg0.osd_csc_yg = 150;
+    regs->osd_whi_cfg0.osd_csc_yb = 29;
+
+    regs->osd_whi_cfg1.osd_csc_ur = -43;
+    regs->osd_whi_cfg1.osd_csc_ug = -85;
+    regs->osd_whi_cfg1.osd_csc_ub = 128;
+
+    regs->osd_whi_cfg2.osd_csc_vr = 128;
+    regs->osd_whi_cfg2.osd_csc_vg = -107;
+    regs->osd_whi_cfg2.osd_csc_vb = -21;
+
+    regs->osd_whi_cfg3.osd_csc_ofst_y = 0;
+    regs->osd_whi_cfg3.osd_csc_ofst_u = 128;
+    regs->osd_whi_cfg3.osd_csc_ofst_v = 128;
+
+    return MPP_OK;
+}
+
+MPP_RET vepu511_set_roi(Vepu511RoiCfg *roi_reg_base, MppEncROICfg * roi, RK_S32 w, RK_S32 h)
+{
+    MppEncROIRegion *region = roi->regions;
+    Vepu511RoiCfg  *roi_cfg = (Vepu511RoiCfg *)roi_reg_base;
+    Vepu511RoiRegion *reg_regions = &roi_cfg->regions[0];
+    MPP_RET ret = MPP_NOK;
+    RK_S32 i = 0;
+
+    memset(reg_regions, 0, sizeof(Vepu511RoiRegion) * 8);
+    if (NULL == roi_cfg || NULL == roi) {
+        mpp_err_f("invalid buf %p roi %p\n", roi_cfg, roi);
+        goto DONE;
+    }
+
+    if (roi->number > VEPU511_MAX_ROI_NUM) {
+        mpp_err_f("invalid region number %d\n", roi->number);
+        goto DONE;
+    }
+
+    /* check region config */
+    ret = MPP_OK;
+    for (i = 0; i < (RK_S32) roi->number; i++, region++) {
+        if (region->x + region->w > w || region->y + region->h > h)
+            ret = MPP_NOK;
+
+        if (region->intra > 1 || region->qp_area_idx >= VEPU511_MAX_ROI_NUM ||
+            region->area_map_en > 1 || region->abs_qp_en > 1)
+            ret = MPP_NOK;
+
+        if ((region->abs_qp_en && region->quality > 51) ||
+            (!region->abs_qp_en && (region->quality > 51 || region->quality < -51)))
+            ret = MPP_NOK;
+
+        if (ret) {
+            mpp_err_f("region %d invalid param:\n", i);
+            mpp_err_f("position [%d:%d:%d:%d] vs [%d:%d]\n",
+                      region->x, region->y, region->w, region->h, w, h);
+            mpp_err_f("force intra %d qp area index %d\n",
+                      region->intra, region->qp_area_idx);
+            mpp_err_f("abs qp mode %d value %d\n",
+                      region->abs_qp_en, region->quality);
+            goto DONE;
+        }
+
+        reg_regions->roi_pos_lt.roi_lt_x = MPP_ALIGN(region->x, 16) >> 4;
+        reg_regions->roi_pos_lt.roi_lt_y = MPP_ALIGN(region->y, 16) >> 4;
+        reg_regions->roi_pos_rb.roi_rb_x = MPP_ALIGN(region->x + region->w, 16) >> 4;
+        reg_regions->roi_pos_rb.roi_rb_y = MPP_ALIGN(region->y + region->h, 16) >> 4;
+        reg_regions->roi_base.roi_qp_value = region->quality;
+        reg_regions->roi_base.roi_qp_adj_mode = region->abs_qp_en;
+        reg_regions->roi_base.roi_en = 1;
+        reg_regions->roi_base.roi_pri = 0x1f;
+        if (region->intra) {
+            reg_regions->reg1063.roi0_mdc0_hevc.mdc_intra16 = 1;
+            reg_regions->roi_mdc_hevc.mdc_intra32 = 1;
+        }
+        reg_regions++;
+    }
+
+DONE:
+    return ret;
+}
+
+
diff --git a/mpp/hal/rkenc/common/vepu511_common.h b/mpp/hal/rkenc/common/vepu511_common.h
new file mode 100644
index 00000000..48dad83e
--- /dev/null
+++ b/mpp/hal/rkenc/common/vepu511_common.h
@@ -0,0 +1,3052 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __VEPU511_COMMON_H__
+#define __VEPU511_COMMON_H__
+
+#include "rk_venc_cmd.h"
+#include "mpp_device.h"
+
+#define VEPU511_CTL_OFFSET           (0 * sizeof(RK_U32))       /* 0x00000000 reg0    - 0x00000120 reg72 */
+#define VEPU511_FRAME_OFFSET         (156 * sizeof(RK_U32))     /* 0x00000270 reg156  - 0x00000538 reg334 */
+#define VEPU511_RC_ROI_OFFSET        (1024 * sizeof(RK_U32))    /* 0x00001000 reg1024 - 0x00001160 reg1112 */
+#define VEPU511_PARAM_OFFSET         (1472 * sizeof(RK_U32))    /* 0x00001700 reg1472 - 0x000019cc reg1651 */
+#define VEPU511_SQI_OFFSET           (2048 * sizeof(RK_U32))    /* 0x00002000 reg2048 - 0x0000216c reg2139 */
+#define VEPU511_SCL_OFFSET           (2176 * sizeof(RK_U32))    /* 0x00002200 reg2176 - 0x00002c9c reg2855 */
+#define VEPU511_JPEGTAB_OFFSET       (2856 * sizeof(RK_U32))    /* 0x00002ca0 reg2856 - 0x00002e1c reg2951 */
+#define VEPU511_OSD_OFFSET           (3072 * sizeof(RK_U32))    /* 0x00003000 reg3072 - 0x00003264 reg3225 */
+#define VEPU511_STATUS_OFFSET        (4096 * sizeof(RK_U32))    /* 0x00004000 reg4096 - 0x0000424c reg4243 */
+#define VEPU511_DBG_OFFSET           (5120 * sizeof(RK_U32))    /* 0x00005000 reg5120 - 0x0000523c reg5263 */
+#define VEPU511_REG_BASE_HW_STATUS   (0x2c)
+
+#define VEPU511_MAX_ROI_NUM          8
+#define VEPU511_SLICE_FIFO_LEN       8
+
+typedef enum qbias_ofst_e {
+    IFRAME_THD0 = 0,
+    IFRAME_THD1,
+    IFRAME_THD2,
+    IFRAME_BIAS0,
+    IFRAME_BIAS1,
+    IFRAME_BIAS2,
+    IFRAME_BIAS3,
+    PFRAME_THD0,
+    PFRAME_THD1,
+    PFRAME_THD2,
+    PFRAME_IBLK_BIAS0,
+    PFRAME_IBLK_BIAS1,
+    PFRAME_IBLK_BIAS2,
+    PFRAME_IBLK_BIAS3,
+    PFRAME_PBLK_BIAS0,
+    PFRAME_PBLK_BIAS1,
+    PFRAME_PBLK_BIAS2,
+    PFRAME_PBLK_BIAS3
+} QbiasOfst;
+
+typedef struct Vepu511Online_t {
+    /* 0x00000270 reg156 */
+    struct {
+        RK_U32 reserved     : 4;
+        RK_U32 adr_vsy_t    : 28;
+    } adr_vsy_t;
+
+    /* 0x00000274 reg157 */
+    struct {
+        RK_U32 reserved     : 4;
+        RK_U32 adr_vsc_t    : 28;
+    } adr_vsc_t;
+
+    /* 0x00000278 reg158 */
+    struct {
+        RK_U32 reserved     : 4;
+        RK_U32 adr_vsy_b    : 28;
+    } adr_vsy_b;
+
+    /* 0x0000027c reg159 */
+    struct {
+        RK_U32 reserved     : 4;
+        RK_U32 adr_vsc_b    : 28;
+    } adr_vsc_b;
+} vepu511_online;
+
+typedef struct RdoB32SkipPar_t {
+    /* 0x00002060 reg2072 */
+    struct {
+        RK_U32 madp_thd0                : 12;
+        RK_U32 reserved                 : 4;
+        RK_U32 madp_thd1                : 12;
+        RK_U32 reserved1                : 1;
+        RK_U32 flckr_frame_qp_en        : 1;
+        RK_U32 flckr_lgt_chng_en        : 1;
+        RK_U32 flckr_en                 : 1;
+    } atf_thd0;
+
+    /* 0x00002064 reg2073 */
+    struct {
+        RK_U32 madp_thd2      : 12;
+        RK_U32 reserved       : 4;
+        RK_U32 madp_thd3      : 12;
+        RK_U32 reserved1      : 4;
+    } atf_thd1;
+
+    /* 0x00002068 reg2074 */
+    struct {
+        RK_U32 wgt0    : 8;
+        RK_U32 wgt1    : 8;
+        RK_U32 wgt2    : 8;
+        RK_U32 wgt3    : 8;
+    } atf_wgt0;
+
+    /* 0x206c */
+    RK_U32 reserved_2075;
+} rdo_b32_skip_par;
+
+typedef struct RdoSkipPar_t {
+    struct {
+        RK_U32 madp_thd0    : 12;
+        RK_U32 reserved     : 4;
+        RK_U32 madp_thd1    : 12;
+        RK_U32 reserved1    : 4;
+    } atf_thd0;
+
+    /* 0x00002064 reg2073 */
+    struct {
+        RK_U32 madp_thd2    : 12;
+        RK_U32 reserved     : 4;
+        RK_U32 madp_thd3    : 12;
+        RK_U32 reserved1    : 4;
+    } atf_thd1;
+
+    /* 0x00002068 reg2074 */
+    struct {
+        RK_U32 wgt0    : 8;
+        RK_U32 wgt1    : 8;
+        RK_U32 wgt2    : 8;
+        RK_U32 wgt3    : 8;
+    } atf_wgt0;
+
+    /* 0x0000206c reg2075 */
+    struct {
+        RK_U32 wgt4         : 8;
+        RK_U32 reserved     : 24;
+    } atf_wgt1;
+} rdo_skip_par;
+
+typedef struct RdoB32NoSkipPar_t {
+    /* 0x00002080 reg2080 */
+    struct {
+        RK_U32 madp_thd0    : 12;
+        RK_U32 reserved     : 4;
+        RK_U32 madp_thd1    : 12;
+        RK_U32 reserved1    : 4;
+    } atf_thd0;
+
+    /* 0x00002084 reg2081 */
+    struct {
+        RK_U32 madp_thd2            : 12;
+        RK_U32 reserved             : 4;
+        RK_U32 atf_bypass_pri_flag  : 1;
+        RK_U32 reserved1            : 15;
+    } atf_thd1;
+
+
+    /* 0x00002088 reg2082 */
+    struct {
+        RK_U32 wgt0     : 8;
+        RK_U32 wgt1     : 8;
+        RK_U32 wgt2     : 8;
+        RK_U32 reserved : 8;
+    } atf_wgt;
+} rdo_b32_noskip_par;
+
+typedef struct RdoNoSkipPar_t {
+    /* 0x00002080 reg2080 */
+    struct {
+        RK_U32 madp_thd0    : 12;
+        RK_U32 reserved     : 4;
+        RK_U32 madp_thd1    : 12;
+        RK_U32 reserved1    : 4;
+    } ratf_thd0;
+
+    /* 0x00002084 reg2081 */
+    struct {
+        RK_U32 madp_thd2    : 12;
+        RK_U32 reserved     : 20;
+    } ratf_thd1;
+
+    /* 0x00002088 reg2082 */
+    struct {
+        RK_U32 wgt0    : 8;
+        RK_U32 wgt1    : 8;
+        RK_U32 wgt2    : 8;
+        RK_U32 wgt3    : 8;
+    } atf_wgt;
+} rdo_noskip_par;
+
+typedef struct Vepu511RoiRegion_t {
+    struct {
+        RK_U32 roi_lt_x    : 10;
+        RK_U32 reserved    : 6;
+        RK_U32 roi_lt_y    : 10;
+        RK_U32 reserved1   : 6;
+    } roi_pos_lt;
+
+    struct {
+        RK_U32 roi_rb_x    : 10;
+        RK_U32 reserved    : 6;
+        RK_U32 roi_rb_y    : 10;
+        RK_U32 reserved1   : 6;
+    } roi_pos_rb;
+
+    struct {
+        RK_U32 roi_qp_value       : 7;
+        RK_U32 roi_qp_adj_mode    : 1;
+        RK_U32 roi_pri            : 5;
+        RK_U32 roi_en             : 1;
+        RK_U32 reserved           : 18;
+    } roi_base;
+
+    /* 0x0000109c reg1063 */
+    union {
+        struct {
+            RK_U32 mdc_intra16         : 4;
+            RK_U32 mdc_inter16         : 4;
+            RK_U32 mdc_split16         : 4;
+            RK_U32 mdc_res_intra16     : 4;
+            RK_U32 mdc_res_inter16     : 4;
+            RK_U32 mdc_res_zeromv16    : 4;
+            RK_U32 mdc_dpth_hevc       : 1;
+            RK_U32 reserved            : 7;
+        } roi0_mdc0_hevc;
+
+        struct {
+            RK_U32 roi0_mdc_intra16    : 4;
+            RK_U32 roi0_mdc_inter16    : 4;
+            RK_U32 roi0_mdc_skip16     : 4;
+            RK_U32 reserved            : 20;
+        } roi0_mdc0_h264;
+    } reg1063;
+
+    /* 0x000010a0 reg1064 */
+    struct {
+        RK_U32 mdc_intra32         : 4;
+        RK_U32 mdc_inter32         : 4;
+        RK_U32 mdc_split32         : 4;
+        RK_U32 mdc_res_intra32     : 4;
+        RK_U32 mdc_res_inter32     : 4;
+        RK_U32 mdc_res_zeromv32    : 4;
+        RK_U32 reserved            : 8;
+    } roi_mdc_hevc;
+} Vepu511RoiRegion;
+
+typedef struct Vepu511RoiCfg_t {
+    /* 0x00001080 reg1056 */
+    union {
+        struct {
+            RK_U32 fmdc_adju_intra16         : 4;
+            RK_U32 fmdc_adju_inter16         : 4;
+            RK_U32 fmdc_adju_split16         : 4;
+            RK_U32 fmdc_adju_res_intra16     : 4;
+            RK_U32 fmdc_adju_res_inter16     : 4;
+            RK_U32 fmdc_adju_res_zeromv16    : 4;
+            RK_U32 fmdc_adju_pri             : 5;
+            RK_U32 reserved                  : 3;
+        } fmdc_adj0_hevc;
+
+        struct {
+            RK_U32 fmdc_adju_intra16    : 4;
+            RK_U32 fmdc_adju_inter16    : 4;
+            RK_U32 fmdc_adju_skip16     : 4;
+            RK_U32 reserved             : 12;
+            RK_U32 fmdc_adj_pri         : 5;
+            RK_U32 reserved1            : 3;
+        } fmdc_adj0_h264;
+    } reg1056;
+
+    /* 0x00001084 reg1057 */
+    struct {
+        RK_U32 fmdc_adju_intra32         : 4;
+        RK_U32 fmdc_adju_inter32         : 4;
+        RK_U32 fmdc_adju_split32         : 4;
+        RK_U32 fmdc_adju_res_intra32     : 4;
+        RK_U32 fmdc_adju_res_inter32     : 4;
+        RK_U32 fmdc_adju_res_zeromv32    : 4;
+        RK_U32 fmdc_adju_split8          : 4;
+        RK_U32 fmdc_adju_lt_ref32        : 4;
+    } fmdc_adj1_hevc;
+
+    RK_U32 reserved_1058;
+
+    /* 0x0000108c reg1059 */
+    struct {
+        RK_U32 bmap_en               : 1;
+        RK_U32 bmap_pri              : 5;
+        RK_U32 bmap_qpmin            : 6;
+        RK_U32 bmap_qpmax            : 6;
+        RK_U32 bmap_mdc_dpth         : 1;
+        RK_U32 reserved              : 13;
+    } bmap_cfg;
+
+    /* 0x00001090 reg1060 - 0x0000112c reg1099 */
+    Vepu511RoiRegion regions[8];
+} Vepu511RoiCfg;
+
+/* class: control/link */
+/* 0x00000000 reg0 - 0x00000120 reg72 */
+typedef struct Vepu511ControlCfg_t {
+    /* 0x00000000 reg0 */
+    struct {
+        RK_U32 sub_ver      : 8;
+        RK_U32 h264_cap     : 1;
+        RK_U32 hevc_cap     : 1;
+        RK_U32 reserved     : 2;
+        RK_U32 res_cap      : 4;
+        RK_U32 osd_cap      : 2;
+        RK_U32 filtr_cap    : 2;
+        RK_U32 bfrm_cap     : 1;
+        RK_U32 fbc_cap      : 2;
+        RK_U32 reserved1    : 1;
+        RK_U32 ip_id        : 8;
+    } version;
+
+    /* 0x00000004 - 0x0000000c */
+    RK_U32 reserved1_3[3];
+
+    /* 0x00000010 reg4 */
+    struct {
+        RK_U32 lkt_num     : 8;
+        RK_U32 vepu_cmd    : 3;
+        RK_U32 reserved    : 21;
+    } enc_strt;
+
+    /* 0x00000014 reg5 */
+    struct {
+        RK_U32 safe_clr     : 1;
+        RK_U32 force_clr    : 1;
+        RK_U32 reserved     : 30;
+    } enc_clr;
+
+    /* 0x00000018 reg6 */
+    struct {
+        RK_U32 vswm_lcnt_soft    : 14;
+        RK_U32 vswm_fcnt_soft    : 8;
+        RK_U32 reserved          : 2;
+        RK_U32 dvbm_ack_soft     : 1;
+        RK_U32 dvbm_ack_sel      : 1;
+        RK_U32 dvbm_inf_sel      : 1;
+        RK_U32 reserved1         : 5;
+    } vs_ldly;
+
+    /* 0x0000001c */
+    RK_U32 reserved_7;
+
+    /* 0x00000020 reg8 */
+    struct {
+        RK_U32 enc_done_en          : 1;
+        RK_U32 lkt_node_done_en     : 1;
+        RK_U32 sclr_done_en         : 1;
+        RK_U32 vslc_done_en         : 1;
+        RK_U32 vbsf_oflw_en         : 1;
+        RK_U32 vbuf_lens_en         : 1;
+        RK_U32 enc_err_en           : 1;
+        RK_U32 vsrc_err_en          : 1;
+        RK_U32 wdg_en               : 1;
+        RK_U32 lkt_err_int_en       : 1;
+        RK_U32 lkt_err_stop_en      : 1;
+        RK_U32 lkt_force_stop_en    : 1;
+        RK_U32 jslc_done_en         : 1;
+        RK_U32 jbsf_oflw_en         : 1;
+        RK_U32 jbuf_lens_en         : 1;
+        RK_U32 dvbm_err_en          : 1;
+        RK_U32 reserved             : 16;
+    } int_en;
+
+    /* 0x00000024 reg9 */
+    struct {
+        RK_U32 enc_done_msk          : 1;
+        RK_U32 lkt_node_done_msk     : 1;
+        RK_U32 sclr_done_msk         : 1;
+        RK_U32 vslc_done_msk         : 1;
+        RK_U32 vbsf_oflw_msk         : 1;
+        RK_U32 vbuf_lens_msk         : 1;
+        RK_U32 enc_err_msk           : 1;
+        RK_U32 vsrc_err_msk          : 1;
+        RK_U32 wdg_msk               : 1;
+        RK_U32 lkt_err_int_msk       : 1;
+        RK_U32 lkt_err_stop_msk      : 1;
+        RK_U32 lkt_force_stop_msk    : 1;
+        RK_U32 jslc_done_msk         : 1;
+        RK_U32 jbsf_oflw_msk         : 1;
+        RK_U32 jbuf_lens_msk         : 1;
+        RK_U32 dvbm_err_msk          : 1;
+        RK_U32 reserved              : 16;
+    } int_msk;
+
+    /* 0x00000028 reg10 */
+    struct {
+        RK_U32 enc_done_clr          : 1;
+        RK_U32 lkt_node_done_clr     : 1;
+        RK_U32 sclr_done_clr         : 1;
+        RK_U32 vslc_done_clr         : 1;
+        RK_U32 vbsf_oflw_clr         : 1;
+        RK_U32 vbuf_lens_clr         : 1;
+        RK_U32 enc_err_clr           : 1;
+        RK_U32 vsrc_err_clr          : 1;
+        RK_U32 wdg_clr               : 1;
+        RK_U32 lkt_err_int_clr       : 1;
+        RK_U32 lkt_err_stop_clr      : 1;
+        RK_U32 lkt_force_stop_clr    : 1;
+        RK_U32 jslc_done_clr         : 1;
+        RK_U32 jbsf_oflw_clr         : 1;
+        RK_U32 jbuf_lens_clr         : 1;
+        RK_U32 dvbm_err_clr          : 1;
+        RK_U32 reserved              : 16;
+    } int_clr;
+
+    /* 0x0000002c reg11 */
+    struct {
+        RK_U32 enc_done_sta          : 1;
+        RK_U32 lkt_node_done_sta     : 1;
+        RK_U32 sclr_done_sta         : 1;
+        RK_U32 vslc_done_sta         : 1;
+        RK_U32 vbsf_oflw_sta         : 1;
+        RK_U32 vbuf_lens_sta         : 1;
+        RK_U32 enc_err_sta           : 1;
+        RK_U32 vsrc_err_sta          : 1;
+        RK_U32 wdg_sta               : 1;
+        RK_U32 lkt_err_int_sta       : 1;
+        RK_U32 lkt_err_stop_sta      : 1;
+        RK_U32 lkt_force_stop_sta    : 1;
+        RK_U32 jslc_done_sta         : 1;
+        RK_U32 jbsf_oflw_sta         : 1;
+        RK_U32 jbuf_lens_sta         : 1;
+        RK_U32 dvbm_err_sta          : 1;
+        RK_U32 reserved              : 16;
+    } int_sta;
+
+    /* 0x00000030 reg12 */
+    struct {
+        RK_U32 jpeg_bus_edin        : 4;
+        RK_U32 src_bus_edin         : 4;
+        RK_U32 meiw_bus_edin        : 4;
+        RK_U32 bsw_bus_edin         : 4;
+        RK_U32 lktr_bus_edin        : 4;
+        RK_U32 roir_bus_edin        : 4;
+        RK_U32 lktw_bus_edin        : 4;
+        RK_U32 rec_nfbc_bus_edin    : 4;
+    } dtrns_map;
+
+    /* 0x00000034 reg13 */
+    struct {
+        RK_U32 jsrc_bus_edin    : 4;
+        RK_U32 reserved         : 12;
+        RK_U32 axi_brsp_cke     : 10;
+        RK_U32 reserved1        : 6;
+    } dtrns_cfg;
+
+    /* 0x00000038 reg14 */
+    struct {
+        RK_U32 vs_load_thd    : 24;
+        RK_U32 reserved       : 8;
+    } enc_wdg;
+
+    /* 0x0000003c reg15 */
+    struct {
+        RK_U32 hurry_en      : 1;
+        RK_U32 hurry_low     : 3;
+        RK_U32 hurry_mid     : 3;
+        RK_U32 hurry_high    : 3;
+        RK_U32 reserved      : 6;
+        RK_U32 qos_period    : 16;
+    } qos_cfg;
+
+    /* 0x00000040 reg16 */
+    struct {
+        RK_U32 qos_ar_dprt    : 4;
+        RK_U32 qos_ar_lprt    : 4;
+        RK_U32 qos_ar_mprt    : 4;
+        RK_U32 qos_ar_hprt    : 4;
+        RK_U32 qos_aw_dprt    : 4;
+        RK_U32 qos_aw_lprt    : 4;
+        RK_U32 qos_aw_mprt    : 4;
+        RK_U32 qos_aw_hprt    : 4;
+    } qos_prty;
+
+    /* 0x00000044 reg17 */
+    RK_U32 hurry_thd_low;
+
+    /* 0x00000048 reg18 */
+    RK_U32 hurry_thd_mid;
+
+    /* 0x0000004c reg19 */
+    RK_U32 hurry_thd_high;
+
+    /* 0x00000050 reg20 */
+    RK_U32 reserved_20;
+
+    /* 0x00000054 reg21 */
+    struct {
+        RK_U32 cke              : 1;
+        RK_U32 resetn_hw_en     : 1;
+        RK_U32 rfpr_err_e       : 1;
+        RK_U32 sram_ckg_en      : 1;
+        RK_U32 link_err_stop    : 1;
+        RK_U32 reserved         : 27;
+    } opt_strg;
+
+    /* 0x00000058 reg22 */
+    union {
+        struct {
+            RK_U32 tq8_ckg           : 1;
+            RK_U32 tq4_ckg           : 1;
+            RK_U32 bits_ckg_8x8      : 1;
+            RK_U32 bits_ckg_4x4_1    : 1;
+            RK_U32 bits_ckg_4x4_0    : 1;
+            RK_U32 inter_mode_ckg    : 1;
+            RK_U32 inter_ctrl_ckg    : 1;
+            RK_U32 inter_pred_ckg    : 1;
+            RK_U32 intra8_ckg        : 1;
+            RK_U32 intra4_ckg        : 1;
+            RK_U32 reserved          : 22;
+        } rdo_ckg_h264;
+
+        struct {
+            RK_U32 recon32_ckg       : 1;
+            RK_U32 iqit32_ckg        : 1;
+            RK_U32 q32_ckg           : 1;
+            RK_U32 t32_ckg           : 1;
+            RK_U32 cabac32_ckg       : 1;
+            RK_U32 recon16_ckg       : 1;
+            RK_U32 iqit16_ckg        : 1;
+            RK_U32 q16_ckg           : 1;
+            RK_U32 t16_ckg           : 1;
+            RK_U32 cabac16_ckg       : 1;
+            RK_U32 recon8_ckg        : 1;
+            RK_U32 iqit8_ckg         : 1;
+            RK_U32 q8_ckg            : 1;
+            RK_U32 t8_ckg            : 1;
+            RK_U32 cabac8_ckg        : 1;
+            RK_U32 recon4_ckg        : 1;
+            RK_U32 iqit4_ckg         : 1;
+            RK_U32 q4_ckg            : 1;
+            RK_U32 t4_ckg            : 1;
+            RK_U32 cabac4_ckg        : 1;
+            RK_U32 intra32_ckg       : 1;
+            RK_U32 intra16_ckg       : 1;
+            RK_U32 intra8_ckg        : 1;
+            RK_U32 intra4_ckg        : 1;
+            RK_U32 inter_pred_ckg    : 1;
+            RK_U32 reserved          : 7;
+        } rdo_ckg_hevc;
+    } reg0022;
+
+    /* 0x0000005c reg23 */
+    struct {
+        RK_U32 core_id     : 2;
+        RK_U32 reserved    : 30;
+    } core_id;
+
+    /* 0x00000060 reg24 */
+    struct {
+        RK_U32 dvbm_en           : 1;
+        RK_U32 src_badr_sel      : 1;
+        RK_U32 ptr_gbck          : 1;
+        RK_U32 dvbm_vpu_fskp     : 1;
+        RK_U32 dvbm_isp_cnct     : 1;
+        RK_U32 dvbm_vepu_cnct    : 1;
+        RK_U32 vepu_expt_type    : 2;
+        RK_U32 vinf_dly_cycle    : 8;
+        RK_U32 ybuf_full_mgn     : 8;
+        RK_U32 ybuf_oflw_mgn     : 8;
+    } dvbm_cfg;
+
+    /* 0x64 */
+    RK_U32 reserved_25;
+
+    /* 0x00000068 reg26 */
+    struct {
+        RK_U32 reserved         : 4;
+        RK_U32 src_y_adr_str    : 28;
+    } dvbm_y_sadr;
+
+    /* 0x0000006c reg27 */
+    struct {
+        RK_U32 reserved         : 4;
+        RK_U32 src_c_adr_str    : 28;
+    } dvbm_c_sadr;
+
+    /* 0x00000070 reg28 */
+    struct {
+        RK_U32 reserved      : 4;
+        RK_U32 dvbm_y_top    : 28;
+    } dvbm_y_top;
+
+    /* 0x00000074 reg29 */
+    struct {
+        RK_U32 reserved      : 4;
+        RK_U32 dvbm_c_top    : 28;
+    } dvbm_c_top;
+
+    /* 0x00000078 reg30 */
+    struct {
+        RK_U32 reserved       : 4;
+        RK_U32 dvbm_y_botm    : 28;
+    } dvbm_y_botm;
+
+    /* 0x0000007c reg31 */
+    struct {
+        RK_U32 reserved       : 4;
+        RK_U32 dvbm_c_botm    : 28;
+    } dvbm_c_botm;
+
+    /* 0x00000080 reg32 */
+    struct {
+        RK_U32 dvbm_y_line_strd0    : 17;
+        RK_U32 reserved             : 15;
+    } dvbm_y_lstd0;
+
+    /* 0x84 */
+    RK_U32 reserved_33;
+
+    /* 0x00000088 reg34 */
+    struct {
+        RK_U32 reserved            : 4;
+        RK_U32 dvbm_y_frm_strd0    : 28;
+    } dvbm_y_fstd0;
+
+    /* 0x0000008c reg35 */
+    struct {
+        RK_U32 reserved            : 4;
+        RK_U32 dvbm_c_frm_strd0    : 28;
+    } dvbm_c_fstd0;
+
+    /* 0x00000090 reg36 */
+    struct {
+        RK_U32 dvbm_y_line_strd1    : 17;
+        RK_U32 reserved             : 15;
+    } dvbm_y_lstd1;
+
+    /* 0x94 */
+    RK_U32 reserved_37;
+
+    /* 0x00000098 reg38 */
+    struct {
+        RK_U32 reserved            : 4;
+        RK_U32 dvbm_y_frm_strd1    : 28;
+    } dvbm_y_fstd1;
+
+    /* 0x0000009c reg39 */
+    struct {
+        RK_U32 reserved            : 4;
+        RK_U32 dvbm_c_frm_strd1    : 28;
+    } dvbm_c_fstd1;
+
+    /* 0xa0 - 0xfc */
+    RK_U32 reserved40_63[24];
+
+    /* 0x00000100 reg64 */
+    struct {
+        RK_U32 node_core_id     : 2;
+        RK_U32 node_int         : 1;
+        RK_U32 reserved         : 1;
+        RK_U32 task_id          : 12;
+        RK_U32 bsw_cntd         : 1;
+        RK_U32 bsw_cntd_jpeg    : 1;
+        RK_U32 reserved1        : 14;
+    } lkt_node_cfg;
+
+    /* 0x00000104 reg65 */
+    struct {
+        RK_U32 pcfg_rd_en       : 1;
+        RK_U32 reserved         : 3;
+        RK_U32 lkt_addr_pcfg    : 28;
+    } lkt_addr_pcfg;
+
+    /* 0x00000108 reg66 */
+    struct {
+        RK_U32 rc_cfg_rd_en       : 1;
+        RK_U32 reserved           : 3;
+        RK_U32 lkt_addr_rc_cfg    : 28;
+    } lkt_addr_rc_cfg;
+
+    /* 0x0000010c reg67 */
+    struct {
+        RK_U32 par_cfg_rd_en       : 1;
+        RK_U32 reserved            : 3;
+        RK_U32 lkt_addr_par_cfg    : 28;
+    } lkt_addr_par_cfg;
+
+    /* 0x00000110 reg68 */
+    struct {
+        RK_U32 sqi_cfg_rd_en       : 1;
+        RK_U32 reserved            : 3;
+        RK_U32 lkt_addr_sqi_cfg    : 28;
+    } lkt_addr_sqi_cfg;
+
+    /* 0x00000114 reg69 */
+    struct {
+        RK_U32 scal_cfg_rd_en       : 1;
+        RK_U32 reserved             : 3;
+        RK_U32 lkt_addr_scal_cfg    : 28;
+    } lkt_addr_scal_cfg;
+
+    /* 0x00000118 reg70 */
+    struct {
+        RK_U32 pp_cfg_rd_en       : 1;
+        RK_U32 reserved           : 3;
+        RK_U32 lkt_addr_pp_cfg    : 28;
+    } lkt_addr_osd_cfg;
+
+    /* 0x0000011c reg71 */
+    struct {
+        RK_U32 st_rd_en       : 1;
+        RK_U32 st_wr_en       : 1;
+        RK_U32 reserved       : 2;
+        RK_U32 lkt_addr_st    : 28;
+    } lkt_addr_st;
+
+    /* 0x00000120 reg72 */
+    struct {
+        RK_U32 nxt_node_vld    : 1;
+        RK_U32 reserved        : 3;
+        RK_U32 lkt_addr_nxt    : 28;
+    } lkt_addr_nxt;
+} Vepu511ControlCfg;
+
+/* 0x00000270 reg156  - 0x0000039c reg231 */
+typedef struct Vepu511FrmCommon_t {
+    /* 0x00000270 reg156 - 0x0000027c reg159 */
+    vepu511_online online_addr;
+
+    /* 0x00000280 reg160 */
+    RK_U32 adr_src0;
+
+    /* 0x00000284 reg161 */
+    RK_U32 adr_src1;
+
+    /* 0x00000288 reg162 */
+    RK_U32 adr_src2;
+
+    /* 0x0000028c reg163 */
+    RK_U32 rfpw_h_addr;
+
+    /* 0x00000290 reg164 */
+    RK_U32 rfpw_b_addr;
+
+    /* 0x00000294 reg165 */
+    RK_U32 rfpr_h_addr;
+
+    /* 0x00000298 reg166 */
+    RK_U32 rfpr_b_addr;
+
+    /* 0x0000029c reg167 */
+    RK_U32 colmvw_addr;
+
+    /* 0x000002a0 reg168 */
+    RK_U32 colmvr_addr;
+
+    /* 0x000002a4 reg169 */
+    RK_U32 dspw_addr;
+
+    /* 0x000002a8 reg170 */
+    RK_U32 dspr_addr;
+
+    /* 0x000002ac reg171 */
+    RK_U32 meiw_addr;
+
+    /* 0x000002b0 reg172 */
+    RK_U32 bsbt_addr;
+
+    /* 0x000002b4 reg173 */
+    RK_U32 bsbb_addr;
+
+    /* 0x000002b8 reg174 */
+    RK_U32 adr_bsbs;
+
+    /* 0x000002bc reg175 */
+    RK_U32 bsbr_addr;
+
+    /* 0x000002c0 reg176 */
+    RK_U32 lpfw_addr;
+
+    /* 0x000002c4 reg177 */
+    RK_U32 lpfr_addr;
+
+    /* 0x000002c8 reg178 */
+    RK_U32 ebuft_addr;
+
+    /* 0x000002cc reg179 */
+    RK_U32 ebufb_addr;
+
+    /* 0x000002d0 reg180 */
+    RK_U32 rfpt_h_addr;
+
+    /* 0x000002d4 reg181 */
+    RK_U32 rfpb_h_addr;
+
+    /* 0x000002d8 reg182 */
+    RK_U32 rfpt_b_addr;
+
+    /* 0x000002dc reg183 */
+    RK_U32 adr_rfpb_b;
+
+    /* 0x000002e0 reg184 */
+    RK_U32 adr_smear_rd;
+
+    /* 0x000002e4 reg185 */
+    RK_U32 adr_smear_wr;
+
+    /* 0x000002e8 reg186 */
+    RK_U32 adr_roir;
+
+    /* 0x000002ec reg187 */
+    RK_U32 eslf_badr;
+
+    /* 0x000002f0 reg188 */
+    RK_U32 rfp1r_h_addr;
+
+    /* 0x000002f4 reg189 */
+    RK_U32 rfp1r_b_addr;
+
+    /* 0x000002f8 reg190 */
+    RK_U32 dsp1r_addr;
+
+    /* 0x2fc */
+    RK_U32 reserved_191;
+
+    /* 0x00000300 reg192 */
+    struct {
+        RK_U32 enc_stnd                : 2;
+        RK_U32 cur_frm_ref             : 1;
+        RK_U32 mei_stor                : 1;
+        RK_U32 bs_scp                  : 1;
+        RK_U32 reserved                : 3;
+        RK_U32 pic_qp                  : 6;
+        RK_U32 num_pic_tot_cur_hevc    : 5;
+        RK_U32 log2_ctu_num_hevc       : 5;
+        RK_U32 rfpr_compress_mode      : 1;
+        RK_U32 reserved1               : 2;
+        RK_U32 eslf_out_e_jpeg         : 1;
+        RK_U32 jpeg_slen_fifo          : 1;
+        RK_U32 eslf_out_e              : 1;
+        RK_U32 slen_fifo               : 1;
+        RK_U32 rec_fbc_dis             : 1;
+    } enc_pic;
+
+    /* 0x00000304 reg193 */
+    struct {
+        RK_U32 dchs_txid    : 2;
+        RK_U32 dchs_rxid    : 2;
+        RK_U32 dchs_txe     : 1;
+        RK_U32 dchs_rxe     : 1;
+        RK_U32 reserved     : 2;
+        RK_U32 dchs_dly     : 8;
+        RK_U32 dchs_ofst    : 10;
+        RK_U32 reserved1    : 6;
+    } dual_core;
+
+    /* 0x00000308 reg194 */
+    struct {
+        RK_U32 frame_id        : 8;
+        RK_U32 frm_id_match    : 1;
+        RK_U32 reserved        : 3;
+        RK_U32 source_id       : 1;
+        RK_U32 src_id_match    : 1;
+        RK_U32 reserved1       : 2;
+        RK_U32 ch_id           : 2;
+        RK_U32 vrsp_rtn_en     : 1;
+        RK_U32 vinf_req_en     : 1;
+        RK_U32 reserved2       : 12;
+    } enc_id;
+
+    /* 0x0000030c reg195 */
+    RK_U32 bsp_size;
+
+    /* 0x00000310 reg196 */
+    struct {
+        RK_U32 pic_wd8_m1    : 11;
+        RK_U32 reserved      : 5;
+        RK_U32 pic_hd8_m1    : 11;
+        RK_U32 reserved1     : 5;
+    } enc_rsl;
+
+    /* 0x00000314 reg197 */
+    struct {
+        RK_U32 pic_wfill    : 6;
+        RK_U32 reserved     : 10;
+        RK_U32 pic_hfill    : 6;
+        RK_U32 reserved1    : 10;
+    } src_fill;
+
+    /* 0x00000318 reg198 */
+    struct {
+        RK_U32 alpha_swap            : 1;
+        RK_U32 rbuv_swap             : 1;
+        RK_U32 src_cfmt              : 4;
+        RK_U32 src_rcne              : 1;
+        RK_U32 out_fmt               : 1;
+        RK_U32 src_range_trns_en     : 1;
+        RK_U32 src_range_trns_sel    : 1;
+        RK_U32 chroma_ds_mode        : 1;
+        RK_U32 reserved              : 21;
+    } src_fmt;
+
+    /* 0x0000031c reg199 */
+    struct {
+        RK_U32 csc_wgt_b2y    : 9;
+        RK_U32 csc_wgt_g2y    : 9;
+        RK_U32 csc_wgt_r2y    : 9;
+        RK_U32 reserved       : 5;
+    } src_udfy;
+
+    /* 0x00000320 reg200 */
+    struct {
+        RK_U32 csc_wgt_b2u    : 9;
+        RK_U32 csc_wgt_g2u    : 9;
+        RK_U32 csc_wgt_r2u    : 9;
+        RK_U32 reserved       : 5;
+    } src_udfu;
+
+    /* 0x00000324 reg201 */
+    struct {
+        RK_U32 csc_wgt_b2v    : 9;
+        RK_U32 csc_wgt_g2v    : 9;
+        RK_U32 csc_wgt_r2v    : 9;
+        RK_U32 reserved       : 5;
+    } src_udfv;
+
+    /* 0x00000328 reg202 */
+    struct {
+        RK_U32 csc_ofst_v    : 8;
+        RK_U32 csc_ofst_u    : 8;
+        RK_U32 csc_ofst_y    : 5;
+        RK_U32 reserved      : 11;
+    } src_udfo;
+
+    /* 0x0000032c reg203 */
+    struct {
+        RK_U32 cr_force_value     : 8;
+        RK_U32 cb_force_value     : 8;
+        RK_U32 chroma_force_en    : 1;
+        RK_U32 reserved           : 9;
+        RK_U32 src_mirr           : 1;
+        RK_U32 src_rot            : 2;
+        RK_U32 tile4x4_en         : 1;
+        RK_U32 rkfbcd_en          : 1;
+        RK_U32 reserved1          : 1;
+    } src_proc;
+
+    /* 0x00000330 reg204 */
+    struct {
+        RK_U32 pic_ofst_x    : 14;
+        RK_U32 reserved      : 2;
+        RK_U32 pic_ofst_y    : 14;
+        RK_U32 reserved1     : 2;
+    } pic_ofst;
+
+    /* 0x00000334 reg205 */
+    struct {
+        RK_U32 src_strd0    : 21;
+        RK_U32 reserved     : 11;
+    } src_strd0;
+
+    /* 0x00000338 reg206 */
+    struct {
+        RK_U32 src_strd1    : 16;
+        RK_U32 reserved     : 16;
+    } src_strd1;
+
+    /* 0x0000033c reg207 */
+    struct {
+        RK_U32 pp_corner_filter_strength      : 2;
+        RK_U32 reserved                       : 2;
+        RK_U32 pp_edge_filter_strength        : 2;
+        RK_U32 reserved1                      : 2;
+        RK_U32 pp_internal_filter_strength    : 2;
+        RK_U32 reserved2                      : 22;
+    } src_flt_cfg;
+
+    /* 0x340 - 0x34c */
+    RK_U32 reserved208_211[4];
+
+    /* 0x00000350 reg212 */
+    struct {
+        RK_U32 rc_en         : 1;
+        RK_U32 aq_en         : 1;
+        RK_U32 reserved      : 10;
+        RK_U32 rc_ctu_num    : 20;
+    } rc_cfg;
+
+    /* 0x00000354 reg213 */
+    struct {
+        RK_U32 reserved       : 16;
+        RK_U32 rc_qp_range    : 4;
+        RK_U32 rc_max_qp      : 6;
+        RK_U32 rc_min_qp      : 6;
+    } rc_qp;
+
+    /* 0x00000358 reg214 */
+    struct {
+        RK_U32 ctu_ebit    : 20;
+        RK_U32 reserved    : 12;
+    } rc_tgt;
+
+    /* 0x0000035c reg215 */
+    struct {
+        RK_U32 eslf_rptr    : 10;
+        RK_U32 eslf_wptr    : 10;
+        RK_U32 eslf_blen    : 10;
+        RK_U32 eslf_updt    : 2;
+    } eslf_buf;
+
+    /* 0x00000360 reg216 */
+    struct {
+        RK_U32 sli_splt          : 1;
+        RK_U32 sli_splt_mode     : 1;
+        RK_U32 sli_splt_cpst     : 1;
+        RK_U32 reserved          : 12;
+        RK_U32 sli_flsh          : 1;
+        RK_U32 sli_max_num_m1    : 15;
+        RK_U32 reserved1         : 1;
+    } sli_splt;
+
+    /* 0x00000364 reg217 */
+    struct {
+        RK_U32 sli_splt_byte    : 20;
+        RK_U32 reserved         : 12;
+    } sli_byte;
+
+    /* 0x00000368 reg218 */
+    struct {
+        RK_U32 sli_splt_cnum_m1    : 20;
+        RK_U32 reserved            : 12;
+    } sli_cnum;
+
+    /* 0x0000036c reg219 */
+    struct {
+        RK_U32 uvc_partition0_len    : 12;
+        RK_U32 uvc_partition_len     : 12;
+        RK_U32 uvc_skip_len          : 6;
+        RK_U32 reserved              : 2;
+    } vbs_pad;
+
+    /* 0x00000370 reg220 */
+    struct {
+        RK_U32 cime_srch_dwnh    : 4;
+        RK_U32 cime_srch_uph     : 4;
+        RK_U32 cime_srch_rgtw    : 4;
+        RK_U32 cime_srch_lftw    : 4;
+        RK_U32 dlt_frm_num       : 16;
+    } me_rnge;
+
+    /* 0x00000374 reg221 */
+    struct {
+        RK_U32 srgn_max_num      : 7;
+        RK_U32 cime_dist_thre    : 13;
+        RK_U32 rme_srch_h        : 2;
+        RK_U32 rme_srch_v        : 2;
+        RK_U32 rme_dis           : 3;
+        RK_U32 reserved          : 1;
+        RK_U32 fme_dis           : 3;
+        RK_U32 reserved1         : 1;
+    } me_cfg;
+
+    /* 0x00000378 reg222 */
+    struct {
+        RK_U32 cime_zero_thre     : 13;
+        RK_U32 reserved           : 15;
+        RK_U32 fme_prefsu_en      : 2;
+        RK_U32 colmv_stor_hevc    : 1;
+        RK_U32 colmv_load_hevc    : 1;
+    } me_cach;
+
+    /* 0x0000037c reg223 */
+    struct {
+        RK_U32 ref_num                    : 1;
+        RK_U32 thre_zero_sad_dep0_cme     : 6;
+        RK_U32 thre_zero_sad_dep1_cme     : 6;
+        RK_U32 thre_zero_diff_dep1_cme    : 3;
+        RK_U32 thre_zero_num_dep1_cme     : 3;
+        RK_U32 thre_num_hit_dep1_cme      : 2;
+        RK_U32 reserved                   : 7;
+        RK_U32 rfpw_mode                  : 1;
+        RK_U32 rfpr_mode                  : 1;
+        RK_U32 rfp1r_mode                 : 1;
+        RK_U32 reserved1                  : 1;
+    } me_ref_comb;
+
+    /* 0x380 - 0x39c */
+    RK_U32 reserved224_231[8];
+
+} Vepu511FrmCommon;
+
+/* 0x520 reg328 - 0x538 reg334 */
+typedef struct Vepu511PpFrameCfg_t {
+    /* 0x00000520 reg328 */
+    RK_U32 adr_md_vpp;
+
+    /* 0x00000524 reg329 */
+    RK_U32 adr_od_vpp;
+
+    /* 0x00000528 reg330 */
+    RK_U32 adr_ref_mdw;
+
+    /* 0x0000052c reg331 */
+    RK_U32 adr_ref_mdr;
+
+    /* 0x00000530 reg332 */
+    struct {
+        RK_U32 sto_stride_md          : 8;
+        RK_U32 sto_stride_od          : 8;
+        RK_U32 cur_frm_en_md          : 1;
+        RK_U32 ref_frm_en_md          : 1;
+        RK_U32 switch_sad_md          : 2;
+        RK_U32 night_mode_en_md       : 1;
+        RK_U32 flycatkin_flt_en_md    : 1;
+        RK_U32 en_od                  : 1;
+        RK_U32 background_en_od       : 1;
+        RK_U32 sad_comp_en_od         : 1;
+        RK_U32 reserved               : 6;
+        RK_U32 vepu_pp_en             : 1;
+    } vpp_base_cfg;
+
+    /* 0x00000534 reg333 */
+    struct {
+        RK_U32 thres_sad_md          : 12;
+        RK_U32 thres_move_md         : 3;
+        RK_U32 reserved              : 1;
+        RK_U32 thres_dust_move_md    : 4;
+        RK_U32 thres_dust_blk_md     : 3;
+        RK_U32 reserved1             : 1;
+        RK_U32 thres_dust_chng_md    : 8;
+    } thd_md_vpp;
+
+    /* 0x00000538 reg334 */
+    struct {
+        RK_U32 thres_complex_od        : 12;
+        RK_U32 thres_complex_cnt_od    : 3;
+        RK_U32 thres_sad_od            : 14;
+        RK_U32 reserved                : 3;
+    } thd_od_vpp;
+} Vepu511PpFrameCfg;
+
+/* class: rc/roi/aq/klut */
+/* 0x00001000 reg1024 - 0x00001160 reg1112 */
+typedef struct Vepu511RcRoi_t {
+    /* 0x00001000 reg1024 */
+    struct {
+        RK_U32 qp_adj0     : 5;
+        RK_U32 qp_adj1     : 5;
+        RK_U32 qp_adj2     : 5;
+        RK_U32 qp_adj3     : 5;
+        RK_U32 qp_adj4     : 5;
+        RK_U32 reserved    : 7;
+    } rc_adj0;
+
+    /* 0x00001004 reg1025 */
+    struct {
+        RK_U32 qp_adj5     : 5;
+        RK_U32 qp_adj6     : 5;
+        RK_U32 qp_adj7     : 5;
+        RK_U32 qp_adj8     : 5;
+        RK_U32 reserved    : 12;
+    } rc_adj1;
+
+    /* 0x00001008 reg1026 - 0x00001028 reg1034 */
+    RK_U32 rc_dthd_0_8[9];
+
+    /* 0x102c */
+    RK_U32 reserved_1035;
+
+    /* 0x00001030 reg1036 */
+    struct {
+        RK_U32 qpmin_area0    : 6;
+        RK_U32 qpmax_area0    : 6;
+        RK_U32 qpmin_area1    : 6;
+        RK_U32 qpmax_area1    : 6;
+        RK_U32 qpmin_area2    : 6;
+        RK_U32 reserved       : 2;
+    } roi_qthd0;
+
+    /* 0x00001034 reg1037 */
+    struct {
+        RK_U32 qpmax_area2    : 6;
+        RK_U32 qpmin_area3    : 6;
+        RK_U32 qpmax_area3    : 6;
+        RK_U32 qpmin_area4    : 6;
+        RK_U32 qpmax_area4    : 6;
+        RK_U32 reserved       : 2;
+    } roi_qthd1;
+
+    /* 0x00001038 reg1038 */
+    struct {
+        RK_U32 qpmin_area5    : 6;
+        RK_U32 qpmax_area5    : 6;
+        RK_U32 qpmin_area6    : 6;
+        RK_U32 qpmax_area6    : 6;
+        RK_U32 qpmin_area7    : 6;
+        RK_U32 reserved       : 2;
+    } roi_qthd2;
+
+    /* 0x0000103c reg1039 */
+    struct {
+        RK_U32 qpmax_area7    : 6;
+        RK_U32 reserved       : 26;
+    } roi_qthd3;
+
+    /* 0x00001040 reg1040 */
+    RK_U32 reserved_1040;
+
+    /* 0x00001044 reg1041 */
+    struct {
+        RK_U32 aq_tthd0    : 8;
+        RK_U32 aq_tthd1    : 8;
+        RK_U32 aq_tthd2    : 8;
+        RK_U32 aq_tthd3    : 8;
+    } aq_tthd0;
+
+    /* 0x00001048 reg1042 */
+    struct {
+        RK_U32 aq_tthd4    : 8;
+        RK_U32 aq_tthd5    : 8;
+        RK_U32 aq_tthd6    : 8;
+        RK_U32 aq_tthd7    : 8;
+    } aq_tthd1;
+
+    /* 0x0000104c reg1043 */
+    struct {
+        RK_U32 aq_tthd8     : 8;
+        RK_U32 aq_tthd9     : 8;
+        RK_U32 aq_tthd10    : 8;
+        RK_U32 aq_tthd11    : 8;
+    } aq_tthd2;
+
+    /* 0x00001050 reg1044 */
+    struct {
+        RK_U32 aq_tthd12    : 8;
+        RK_U32 aq_tthd13    : 8;
+        RK_U32 aq_tthd14    : 8;
+        RK_U32 aq_tthd15    : 8;
+    } aq_tthd3;
+
+    /* 0x00001054 reg1045 */
+    struct {
+        RK_S32 aq_stp_s0     : 5;
+        RK_S32 aq_stp_0t1    : 5;
+        RK_S32 aq_stp_1t2    : 5;
+        RK_S32 aq_stp_2t3    : 5;
+        RK_S32 aq_stp_3t4    : 5;
+        RK_S32 aq_stp_4t5    : 5;
+        RK_S32 reserved      : 2;
+    } aq_stp0;
+
+    /* 0x00001058 reg1046 */
+    struct {
+        RK_S32 aq_stp_5t6      : 5;
+        RK_S32 aq_stp_6t7      : 5;
+        RK_S32 aq_stp_7t8      : 5;
+        RK_S32 aq_stp_8t9      : 5;
+        RK_S32 aq_stp_9t10     : 5;
+        RK_S32 aq_stp_10t11    : 5;
+        RK_S32 reserved        : 2;
+    } aq_stp1;
+
+    /* 0x0000105c reg1047 */
+    struct {
+        RK_S32 aq_stp_11t12    : 5;
+        RK_S32 aq_stp_12t13    : 5;
+        RK_S32 aq_stp_13t14    : 5;
+        RK_S32 aq_stp_14t15    : 5;
+        RK_S32 aq_stp_b15      : 5;
+        RK_U32 reserved        : 7;
+    } aq_stp2;
+
+    /* 0x00001060 reg1048 */
+    struct {
+        RK_U32 aq16_rnge         : 4;
+        RK_U32 aq32_rnge         : 4;
+        RK_U32 aq8_rnge          : 5;
+        RK_U32 aq16_dif0         : 5;
+        RK_U32 aq16_dif1         : 5;
+        RK_U32 reserved          : 1;
+        RK_U32 aq_cme_en         : 1;
+        RK_U32 aq_subj_cme_en    : 1;
+        RK_U32 aq_rme_en         : 1;
+        RK_U32 aq_subj_rme_en    : 1;
+        RK_U32 reserved1         : 4;
+    } aq_clip;
+
+    /* 0x00001064 reg1049 */
+    struct {
+        RK_U32 madi_th0    : 8;
+        RK_U32 madi_th1    : 8;
+        RK_U32 madi_th2    : 8;
+        RK_U32 reserved    : 8;
+    } madi_st_thd;
+
+    /* 0x00001068 reg1050 */
+    struct {
+        RK_U32 madp_th0     : 12;
+        RK_U32 reserved     : 4;
+        RK_U32 madp_th1     : 12;
+        RK_U32 reserved1    : 4;
+    } madp_st_thd0;
+
+    /* 0x0000106c reg1051 */
+    struct {
+        RK_U32 madp_th2    : 12;
+        RK_U32 reserved    : 20;
+    } madp_st_thd1;
+
+    /* 0x1070 - 0x1078 */
+    RK_U32 reserved1052_1054[3];
+
+    /* 0x0000107c reg1055 */
+    struct {
+        RK_U32 chrm_klut_ofst    : 4;
+        RK_U32 reserved          : 28;
+    } klut_ofst;
+
+    /*0x00001080 reg1056 - 0x0000112c reg1099 */
+    Vepu511RoiCfg roi_cfg;
+
+    /* 0x00001130 reg1100 */
+    struct {
+        RK_U32 base_thre_rough_mad32_intra           : 4;
+        RK_U32 delta0_thre_rough_mad32_intra         : 4;
+        RK_U32 delta1_thre_rough_mad32_intra         : 6;
+        RK_U32 delta2_thre_rough_mad32_intra         : 6;
+        RK_U32 delta3_thre_rough_mad32_intra         : 7;
+        RK_U32 delta4_thre_rough_mad32_intra_low5    : 5;
+    } cudecis_thd0;
+
+    /* 0x00001134 reg1101 */
+    struct {
+        RK_U32 delta4_thre_rough_mad32_intra_high2    : 2;
+        RK_U32 delta5_thre_rough_mad32_intra          : 7;
+        RK_U32 delta6_thre_rough_mad32_intra          : 7;
+        RK_U32 base_thre_fine_mad32_intra             : 4;
+        RK_U32 delta0_thre_fine_mad32_intra           : 4;
+        RK_U32 delta1_thre_fine_mad32_intra           : 5;
+        RK_U32 delta2_thre_fine_mad32_intra_low3      : 3;
+    } cudecis_thd1;
+
+    /* 0x00001138 reg1102 */
+    struct {
+        RK_U32 delta2_thre_fine_mad32_intra_high2    : 2;
+        RK_U32 delta3_thre_fine_mad32_intra          : 5;
+        RK_U32 delta4_thre_fine_mad32_intra          : 5;
+        RK_U32 delta5_thre_fine_mad32_intra          : 6;
+        RK_U32 delta6_thre_fine_mad32_intra          : 6;
+        RK_U32 base_thre_str_edge_mad32_intra        : 3;
+        RK_U32 delta0_thre_str_edge_mad32_intra      : 2;
+        RK_U32 delta1_thre_str_edge_mad32_intra      : 3;
+    } cudecis_thd2;
+
+    /* 0x0000113c reg1103 */
+    struct {
+        RK_U32 delta2_thre_str_edge_mad32_intra      : 3;
+        RK_U32 delta3_thre_str_edge_mad32_intra      : 4;
+        RK_U32 base_thre_str_edge_bgrad32_intra      : 5;
+        RK_U32 delta0_thre_str_edge_bgrad32_intra    : 2;
+        RK_U32 delta1_thre_str_edge_bgrad32_intra    : 3;
+        RK_U32 delta2_thre_str_edge_bgrad32_intra    : 4;
+        RK_U32 delta3_thre_str_edge_bgrad32_intra    : 5;
+        RK_U32 base_thre_mad16_intra                 : 3;
+        RK_U32 delta0_thre_mad16_intra               : 3;
+    } cudecis_thd3;
+
+    /* 0x00001140 reg1104 */
+    struct {
+        RK_U32 delta1_thre_mad16_intra          : 3;
+        RK_U32 delta2_thre_mad16_intra          : 4;
+        RK_U32 delta3_thre_mad16_intra          : 5;
+        RK_U32 delta4_thre_mad16_intra          : 5;
+        RK_U32 delta5_thre_mad16_intra          : 6;
+        RK_U32 delta6_thre_mad16_intra          : 6;
+        RK_U32 delta0_thre_mad16_ratio_intra    : 3;
+    } cudecis_thd4;
+
+    /* 0x00001144 reg1105 */
+    struct {
+        RK_U32 delta1_thre_mad16_ratio_intra           : 3;
+        RK_U32 delta2_thre_mad16_ratio_intra           : 3;
+        RK_U32 delta3_thre_mad16_ratio_intra           : 3;
+        RK_U32 delta4_thre_mad16_ratio_intra           : 3;
+        RK_U32 delta5_thre_mad16_ratio_intra           : 3;
+        RK_U32 delta6_thre_mad16_ratio_intra           : 3;
+        RK_U32 delta7_thre_mad16_ratio_intra           : 3;
+        RK_U32 delta0_thre_rough_bgrad32_intra         : 3;
+        RK_U32 delta1_thre_rough_bgrad32_intra         : 4;
+        RK_U32 delta2_thre_rough_bgrad32_intra_low4    : 4;
+    } cudecis_thd5;
+
+    /* 0x00001148 reg1106 */
+    struct {
+        RK_U32 delta2_thre_rough_bgrad32_intra_high2    : 2;
+        RK_U32 delta3_thre_rough_bgrad32_intra          : 10;
+        RK_U32 delta4_thre_rough_bgrad32_intra          : 10;
+        RK_U32 delta5_thre_rough_bgrad32_intra_low10    : 10;
+    } cudecis_thd6;
+
+    /* 0x0000114c reg1107 */
+    struct {
+        RK_U32 delta5_thre_rough_bgrad32_intra_high1    : 1;
+        RK_U32 delta6_thre_rough_bgrad32_intra          : 12;
+        RK_U32 delta7_thre_rough_bgrad32_intra          : 13;
+        RK_U32 delta0_thre_bgrad16_ratio_intra          : 4;
+        RK_U32 delta1_thre_bgrad16_ratio_intra_low2     : 2;
+    } cudecis_thd7;
+
+    /* 0x00001150 reg1108 */
+    struct {
+        RK_U32 delta1_thre_bgrad16_ratio_intra_high2    : 2;
+        RK_U32 delta2_thre_bgrad16_ratio_intra          : 4;
+        RK_U32 delta3_thre_bgrad16_ratio_intra          : 4;
+        RK_U32 delta4_thre_bgrad16_ratio_intra          : 4;
+        RK_U32 delta5_thre_bgrad16_ratio_intra          : 4;
+        RK_U32 delta6_thre_bgrad16_ratio_intra          : 4;
+        RK_U32 delta7_thre_bgrad16_ratio_intra          : 4;
+        RK_U32 delta0_thre_fme_ratio_inter              : 3;
+        RK_U32 delta1_thre_fme_ratio_inter              : 3;
+    } cudecis_thd8;
+
+    /* 0x00001154 reg1109 */
+    struct {
+        RK_U32 delta2_thre_fme_ratio_inter    : 3;
+        RK_U32 delta3_thre_fme_ratio_inter    : 3;
+        RK_U32 delta4_thre_fme_ratio_inter    : 3;
+        RK_U32 delta5_thre_fme_ratio_inter    : 3;
+        RK_U32 delta6_thre_fme_ratio_inter    : 3;
+        RK_U32 delta7_thre_fme_ratio_inter    : 3;
+        RK_U32 base_thre_fme32_inter          : 3;
+        RK_U32 delta0_thre_fme32_inter        : 3;
+        RK_U32 delta1_thre_fme32_inter        : 4;
+        RK_U32 delta2_thre_fme32_inter        : 4;
+    } cudecis_thd9;
+
+    /* 0x00001158 reg1110 */
+    struct {
+        RK_U32 delta3_thre_fme32_inter    : 5;
+        RK_U32 delta4_thre_fme32_inter    : 6;
+        RK_U32 delta5_thre_fme32_inter    : 7;
+        RK_U32 delta6_thre_fme32_inter    : 8;
+        RK_U32 thre_cme32_inter           : 6;
+    } cudecis_thd10;
+
+    /* 0x0000115c reg1111 */
+    struct {
+        RK_U32 delta0_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta1_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta2_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta3_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta4_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta5_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta6_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta7_thre_mad_fme_ratio_inter    : 4;
+    } cudecis_thd11;
+
+    /* 0x00001160 reg1112 */
+    struct {
+        RK_U32 delta0_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta1_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta2_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta3_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta4_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta5_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta6_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta7_thre_mad_fme_ratio_inter    : 4;
+    } cudecis_thd12;
+} Vepu511RcRoi;
+
+typedef struct Vepu511OsdRegion_t {
+    struct {
+        RK_U32 osd_en                : 1;
+        RK_U32 reserved              : 4;
+        RK_U32 osd_qp_adj_en         : 1;
+        RK_U32 osd_range_trns_en     : 1;
+        RK_U32 osd_range_trns_sel    : 1;
+        RK_U32 osd_fmt               : 4;
+        RK_U32 osd_alpha_swap        : 1;
+        RK_U32 osd_rbuv_swap         : 1;
+        RK_U32 reserved1             : 8;
+        RK_U32 osd_fg_alpha          : 8;
+        RK_U32 osd_fg_alpha_sel      : 2;
+    } cfg0;
+
+    struct {
+        RK_U32 osd_lt_xcrd    : 14;
+        RK_U32 osd_lt_ycrd    : 14;
+        RK_U32 osd_endn       : 4;
+    } cfg1;
+
+    struct {
+        RK_U32 osd_rb_xcrd    : 14;
+        RK_U32 osd_rb_ycrd    : 14;
+        RK_U32 reserved        : 4;
+    } cfg2;
+
+    RK_U32 osd_st_addr;
+
+    RK_U32 reserved;
+
+    struct {
+        RK_U32 osd_stride        : 17;
+        RK_U32 reserved          : 8;
+        RK_U32 osd_ch_ds_mode    : 1;
+        RK_U32 reserved1         : 6;
+    } cfg5;
+
+    RK_U8 lut[8];
+
+    /* only for h.264/h.h265, jpeg no use */
+    struct {
+        RK_U32 osd_qp_adj_sel    : 1;
+        RK_U32 osd_qp            : 7;
+        RK_U32 osd_qp_max        : 6;
+        RK_U32 osd_qp_min        : 6;
+        RK_U32 osd_qp_prj        : 5;
+        RK_U32 reserved          : 7;
+    } cfg8;
+} Vepu511OsdRegion;
+
+/* class: osd */
+/* 0x00003000 reg3072 - 0x00003134 reg3149 */
+typedef struct Vepu511Osd_t {
+    /* 0x00003000 reg3072 - 0x0000311c reg3143*/
+    Vepu511OsdRegion osd_regions[8];
+
+    /* 0x00003120 reg3144 */
+    struct {
+        RK_U32 osd_csc_yr    : 9;
+        RK_U32 osd_csc_yg    : 9;
+        RK_U32 osd_csc_yb    : 9;
+        RK_U32 reserved      : 5;
+    } osd_whi_cfg0;
+
+    /* 0x00003124 reg3145 */
+    struct {
+        RK_U32 osd_csc_ur    : 9;
+        RK_U32 osd_csc_ug    : 9;
+        RK_U32 osd_csc_ub    : 9;
+        RK_U32 reserved      : 5;
+    } osd_whi_cfg1;
+
+    /* 0x00003128 reg3146 */
+    struct {
+        RK_U32 osd_csc_vr    : 9;
+        RK_U32 osd_csc_vg    : 9;
+        RK_U32 osd_csc_vb    : 9;
+        RK_U32 reserved      : 5;
+    } osd_whi_cfg2;
+
+    /* 0x0000312c reg3147 */
+    struct {
+        RK_U32 osd_csc_ofst_y    : 8;
+        RK_U32 osd_csc_ofst_u    : 8;
+        RK_U32 osd_csc_ofst_v    : 8;
+        RK_U32 reserved          : 8;
+    } osd_whi_cfg3;
+} Vepu511Osd;
+
+/* class: osd */
+/*0x00003000 reg3072 - 0x00003264 reg3225 */
+typedef struct Vepu511OsdRegs_t {
+    /*0x00003000 reg3072 - 0x0000312c reg3147 */
+    Vepu511Osd osd_comb_cfg;
+
+    /* 0x00003130 reg3148 - 0x00003134 reg3149 */
+    RK_U32 reserve[2];
+
+    /*0x00003138 reg3150 - 0x00003264 reg3225 */
+    Vepu511Osd osd_jpeg_cfg;
+} Vepu511OsdRegs;
+
+/* class: st */
+/* 0x00004000 reg4096 - 0x0000424c reg4243*/
+typedef struct Vepu511Status_t {
+    /* 0x00004000 reg4096 */
+    RK_U32 bs_lgth_l32;
+
+    /* 0x00004004 reg4097 */
+    struct {
+        RK_U32 bs_lgth_h8       : 8;
+        RK_U32 st_rc_lst_dqp    : 6;
+        RK_U32 reserved         : 2;
+        RK_U32 sse_l16          : 16;
+    } st_sse_bsl;
+
+    /* 0x00004008 reg4098 */
+    RK_U32 sse_h32;
+
+    /* 0x0000400c reg4099 */
+    RK_U32 qp_sum;
+
+    /* 0x00004010 reg4100 */
+    struct {
+        RK_U32 sao_cnum    : 16;
+        RK_U32 sao_ynum    : 16;
+    } st_sao;
+
+    /* 0x00004014 reg4101 */
+    RK_U32 rdo_head_bits;
+
+    /* 0x00004018 reg4102 */
+    struct {
+        RK_U32 rdo_head_bits_h8    : 8;
+        RK_U32 reserved            : 8;
+        RK_U32 rdo_res_bits_l16    : 16;
+    } st_head_res_bl;
+
+    /* 0x0000401c reg4103 */
+    RK_U32 rdo_res_bits_h24;
+
+    /* 0x00004020 reg4104 */
+    struct {
+        RK_U32 st_enc             : 2;
+        RK_U32 st_sclr            : 1;
+        RK_U32 vepu_fbd_err       : 5;
+        RK_U32 isp_src_oflw       : 1;
+        RK_U32 vepu_src_oflw      : 1;
+        RK_U32 vepu_sid_nmch      : 1;
+        RK_U32 vepu_fcnt_nmch     : 1;
+        RK_U32 reserved           : 4;
+        RK_U32 dvbm_finf_wful     : 1;
+        RK_U32 dvbm_linf_wful     : 1;
+        RK_U32 dvbm_fsid_nmch     : 1;
+        RK_U32 dvbm_fcnt_early    : 1;
+        RK_U32 dvbm_fcnt_late     : 1;
+        RK_U32 dvbm_isp_oflw      : 1;
+        RK_U32 dvbm_vepu_oflw     : 1;
+        RK_U32 isp_time_out       : 1;
+        RK_U32 dvbm_vsrc_fcnt     : 8;
+    } st_enc;
+
+    /* 0x00004024 reg4105 */
+    struct {
+        RK_U32 fnum_cfg_done    : 8;
+        RK_U32 fnum_cfg         : 8;
+        RK_U32 fnum_int         : 8;
+        RK_U32 fnum_enc_done    : 8;
+    } st_lkt;
+
+    /* 0x00004028 reg4106 */
+    struct {
+        RK_U32 reserved     : 4;
+        RK_U32 node_addr    : 28;
+    } st_nadr;
+
+    /* 0x0000402c reg4107 */
+    RK_U32 vbsbw_addr;
+
+    /* 0x00004030 reg4108 */
+    struct {
+        RK_U32 axib_idl     : 8;
+        RK_U32 axib_ovfl    : 8;
+        RK_U32 axib_err     : 8;
+        RK_U32 axir_err     : 8;
+    } st_bus;
+
+    /* 0x00004034 reg4109 */
+    struct {
+        RK_U32 sli_num_video     : 8;
+        RK_U32 sli_num_jpeg      : 8;
+        RK_U32 bpkt_num_video    : 7;
+        RK_U32 bpkt_lst_video    : 1;
+        RK_U32 bpkt_num_jpeg     : 7;
+        RK_U32 bpkt_lst_jpeg     : 1;
+    } st_snum;
+
+    /* 0x00004038 reg4110 */
+    struct {
+        RK_U32 sli_len    : 30;
+        RK_U32 sli_lst    : 1;
+        RK_U32 sli_sid    : 1;
+    } st_slen;
+
+    /* 0x0000403c reg4111 */
+    struct {
+        RK_U32 task_id_proc    : 12;
+        RK_U32 task_id_done    : 12;
+        RK_U32 task_done       : 1;
+        RK_U32 task_lkt_err    : 3;
+        RK_U32 reserved        : 4;
+    } st_link_task;
+
+    /* 0x00004040 reg4112 */
+    struct {
+        RK_U32 eslf_nptr     : 10;
+        RK_U32 eslf_empty    : 1;
+        RK_U32 eslf_full     : 1;
+        RK_U32 eslf_sid      : 1;
+        RK_U32 reserved      : 19;
+    } st_eslf_nptr;
+
+    /* 0x00004044 reg4113 */
+    struct {
+        RK_U32 vsrd_posy         : 10;
+        RK_U32 reserved          : 5;
+        RK_U32 vsrd_fend         : 1;
+        RK_U32 vsrd_posy_jpeg    : 10;
+        RK_U32 reserved1         : 5;
+        RK_U32 vsrd_fend_jpeg    : 1;
+    } st_vlsd_rlvl;
+
+    /* 0x00004048 reg4114 */
+    struct {
+        RK_U32 eslf_nptr_jpeg     : 10;
+        RK_U32 eslf_empty_jpeg    : 1;
+        RK_U32 eslf_full_jpeg     : 1;
+        RK_U32 eslf_sid_jpeg      : 1;
+        RK_U32 reserved           : 19;
+    } st_eslf_nptr_jpeg;
+
+    /* 0x404c - 0x405c */
+    RK_U32 reserved4115_4119[5];
+
+    /* 0x00004060 reg4120 */
+    struct {
+        RK_U32 sli_len_jpeg    : 30;
+        RK_U32 sli_lst_jpeg    : 1;
+        RK_U32 sli_sid_jpeg    : 1;
+    } st_slen_jpeg;
+
+    /* 0x00004064 reg4121 */
+    RK_U32 jpeg_head_bits_l32;
+
+    /* 0x00004068 reg4122 */
+    struct {
+        RK_U32 jpeg_head_bits_h8    : 1;
+        RK_U32 reserved             : 31;
+    } st_bsl_h8_jpeg;
+
+    /* 0x0000406c reg4123 */
+    RK_U32 jbsbw_addr;
+
+    /* 0x00004070 reg4124 */
+    RK_U32 luma_pix_sum_od;
+
+    /* 0x4074 - 0x407c */
+    RK_U32 reserved4125_4127[3];
+
+    /* 0x00004080 reg4128 */
+    struct {
+        RK_U32 pnum_p64    : 17;
+        RK_U32 reserved    : 15;
+    } st_pnum_p64;
+
+    /* 0x00004084 reg4129 */
+    struct {
+        RK_U32 pnum_p32    : 19;
+        RK_U32 reserved    : 13;
+    } st_pnum_p32;
+
+    /* 0x00004088 reg4130 */
+    struct {
+        RK_U32 pnum_p16    : 21;
+        RK_U32 reserved    : 11;
+    } st_pnum_p16;
+
+    /* 0x0000408c reg4131 */
+    struct {
+        RK_U32 pnum_p8     : 23;
+        RK_U32 reserved    : 9;
+    } st_pnum_p8;
+
+    /* 0x00004090 reg4132 */
+    struct {
+        RK_U32 pnum_i32    : 19;
+        RK_U32 reserved    : 13;
+    } st_pnum_i32;
+
+    /* 0x00004094 reg4133 */
+    struct {
+        RK_U32 pnum_i16    : 21;
+        RK_U32 reserved    : 11;
+    } st_pnum_i16;
+
+    /* 0x00004098 reg4134 */
+    struct {
+        RK_U32 pnum_i8     : 23;
+        RK_U32 reserved    : 9;
+    } st_pnum_i8;
+
+    /* 0x0000409c reg4135 */
+    struct {
+        RK_U32 pnum_i4     : 23;
+        RK_U32 reserved    : 9;
+    } st_pnum_i4;
+
+    /* 0x000040a0 reg4136 */
+    struct {
+        RK_U32 num_b16     : 23;
+        RK_U32 reserved    : 9;
+    } st_bnum_b16;
+
+    /* 0x40a4 */
+    RK_U32 reserved_4137;
+
+    /* 0x000040a8 reg4138 */
+    RK_U32 madi16_sum;
+
+    /* 0x000040ac reg4139 */
+    RK_U32 madi32_sum;
+
+    /* 0x000040b0 reg4140 */
+    RK_U32 madp16_sum;
+
+    /* 0x000040b4 reg4141 */
+    struct {
+        RK_U32 rdo_smear_cnt0    : 10;
+        RK_U32 reserved          : 6;
+        RK_U32 rdo_smear_cnt1    : 10;
+        RK_U32 reserved1         : 6;
+    } st_smear_cnt0;
+
+    /* 0x000040b8 reg4142 */
+    struct {
+        RK_U32 rdo_smear_cnt2    : 10;
+        RK_U32 reserved          : 6;
+        RK_U32 rdo_smear_cnt3    : 10;
+        RK_U32 reserved1         : 6;
+    } st_smear_cnt1;
+
+    /* 0x40bc */
+    RK_U32 reserved_4143;
+
+    /* 0x000040c0 reg4144 */
+    struct {
+        RK_U32 madi_th_lt_cnt0    : 16;
+        RK_U32 madi_th_lt_cnt1    : 16;
+    } st_madi_lt_num0;
+
+    /* 0x000040c4 reg4145 */
+    struct {
+        RK_U32 madi_th_lt_cnt2    : 16;
+        RK_U32 madi_th_lt_cnt3    : 16;
+    } st_madi_lt_num1;
+
+    /* 0x000040c8 reg4146 */
+    struct {
+        RK_U32 madi_th_rt_cnt0    : 16;
+        RK_U32 madi_th_rt_cnt1    : 16;
+    } st_madi_rt_num0;
+
+    /* 0x000040cc reg4147 */
+    struct {
+        RK_U32 madi_th_rt_cnt2    : 16;
+        RK_U32 madi_th_rt_cnt3    : 16;
+    } st_madi_rt_num1;
+
+    /* 0x000040d0 reg4148 */
+    struct {
+        RK_U32 madi_th_lb_cnt0    : 16;
+        RK_U32 madi_th_lb_cnt1    : 16;
+    } st_madi_lb_num0;
+
+    /* 0x000040d4 reg4149 */
+    struct {
+        RK_U32 madi_th_lb_cnt2    : 16;
+        RK_U32 madi_th_lb_cnt3    : 16;
+    } st_madi_lb_num1;
+
+    /* 0x000040d8 reg4150 */
+    struct {
+        RK_U32 madi_th_rb_cnt0    : 16;
+        RK_U32 madi_th_rb_cnt1    : 16;
+    } st_madi_rb_num0;
+
+    /* 0x000040dc reg4151 */
+    struct {
+        RK_U32 madi_th_rb_cnt2    : 16;
+        RK_U32 madi_th_rb_cnt3    : 16;
+    } st_madi_rb_num1;
+
+    /* 0x000040e0 reg4152 */
+    struct {
+        RK_U32 madp_th_lt_cnt0    : 16;
+        RK_U32 madp_th_lt_cnt1    : 16;
+    } st_madp_lt_num0;
+
+    /* 0x000040e4 reg4153 */
+    struct {
+        RK_U32 madp_th_lt_cnt2    : 16;
+        RK_U32 madp_th_lt_cnt3    : 16;
+    } st_madp_lt_num1;
+
+    /* 0x000040e8 reg4154 */
+    struct {
+        RK_U32 madp_th_rt_cnt0    : 16;
+        RK_U32 madp_th_rt_cnt1    : 16;
+    } st_madp_rt_num0;
+
+    /* 0x000040ec reg4155 */
+    struct {
+        RK_U32 madp_th_rt_cnt2    : 16;
+        RK_U32 madp_th_rt_cnt3    : 16;
+    } st_madp_rt_num1;
+
+    /* 0x000040f0 reg4156 */
+    struct {
+        RK_U32 madp_th_lb_cnt0    : 16;
+        RK_U32 madp_th_lb_cnt1    : 16;
+    } st_madp_lb_num0;
+
+    /* 0x000040f4 reg4157 */
+    struct {
+        RK_U32 madp_th_lb_cnt2    : 16;
+        RK_U32 madp_th_lb_cnt3    : 16;
+    } st_madp_lb_num1;
+
+    /* 0x000040f8 reg4158 */
+    struct {
+        RK_U32 madp_th_rb_cnt0    : 16;
+        RK_U32 madp_th_rb_cnt1    : 16;
+    } st_madp_rb_num0;
+
+    /* 0x000040fc reg4159 */
+    struct {
+        RK_U32 madp_th_rb_cnt2    : 16;
+        RK_U32 madp_th_rb_cnt3    : 16;
+    } st_madp_rb_num1;
+
+    /* 0x00004100 reg4160 */
+    struct {
+        RK_U32 cmv_th_lt_cnt0    : 16;
+        RK_U32 cmv_th_lt_cnt1    : 16;
+    } st_cmv_lt_num0;
+
+    /* 0x00004104 reg4161 */
+    struct {
+        RK_U32 cmv_th_lt_cnt2    : 16;
+        RK_U32 cmv_th_lt_cnt3    : 16;
+    } st_cmv_lt_num1;
+
+    /* 0x00004108 reg4162 */
+    struct {
+        RK_U32 cmv_th_rt_cnt0    : 16;
+        RK_U32 cmv_th_rt_cnt1    : 16;
+    } st_cmv_rt_num0;
+
+    /* 0x0000410c reg4163 */
+    struct {
+        RK_U32 cmv_th_rt_cnt2    : 16;
+        RK_U32 cmv_th_rt_cnt3    : 16;
+    } st_cmv_rt_num1;
+
+    /* 0x00004110 reg4164 */
+    struct {
+        RK_U32 cmv_th_lb_cnt0    : 16;
+        RK_U32 cmv_th_lb_cnt1    : 16;
+    } st_cmv_lb_num0;
+
+    /* 0x00004114 reg4165 */
+    struct {
+        RK_U32 cmv_th_lb_cnt2    : 16;
+        RK_U32 cmv_th_lb_cnt3    : 16;
+    } st_cmv_lb_num1;
+
+    /* 0x00004118 reg4166 */
+    struct {
+        RK_U32 cmv_th_rb_cnt0    : 16;
+        RK_U32 cmv_th_rb_cnt1    : 16;
+    } st_cmv_rb_num0;
+
+    /* 0x0000411c reg4167 */
+    struct {
+        RK_U32 cmv_th_rb_cnt2    : 16;
+        RK_U32 cmv_th_rb_cnt3    : 16;
+    } st_cmv_rb_num1;
+
+    /* 0x00004120 reg4168 */
+    struct {
+        RK_U32 org_y_r_max_value    : 8;
+        RK_U32 org_y_r_min_value    : 8;
+        RK_U32 org_u_g_max_value    : 8;
+        RK_U32 org_u_g_min_value    : 8;
+    } st_vsp_org_value0;
+
+    /* 0x00004124 reg4169 */
+    struct {
+        RK_U32 org_v_b_max_value    : 8;
+        RK_U32 org_v_b_min_value    : 8;
+        RK_U32 reserved             : 16;
+    } st_vsp_org_value1;
+
+    /* 0x00004128 reg4170 */
+    struct {
+        RK_U32 jpeg_y_r_max_value    : 8;
+        RK_U32 jpeg_y_r_min_value    : 8;
+        RK_U32 jpeg_u_g_max_value    : 8;
+        RK_U32 jpeg_u_g_min_value    : 8;
+    } st_vsp_jpeg_value0;
+
+    /* 0x0000412c reg4171 */
+    struct {
+        RK_U32 jpeg_v_b_max_value    : 8;
+        RK_U32 jpeg_v_b_min_value    : 8;
+        RK_U32 reserved              : 16;
+    } st_vsp_jpeg_value1;
+
+    /* 0x00004130 reg4172 */
+    RK_U32 dsp_y_sum;
+
+    /* 0x00004134 reg4173 */
+    RK_U32 acc_zero_mv;
+
+    /* 0x00004138 reg4174 */
+    struct {
+        RK_U32 ref1_inter8_num    : 23;
+        RK_U32 reserved           : 9;
+    } st_ref1_inter8;
+
+    /* 0x0000413c reg4175 */
+    struct {
+        RK_U32 acc_block_num    : 18;
+        RK_U32 reserved         : 14;
+    } st_blk_avb_sum;
+
+    /* 0x00004140 reg4176 */
+    struct {
+        RK_U32 num0_point_skin    : 15;
+        RK_U32 acc_cmplx_num      : 17;
+    } st_skin_sum0;
+
+    /* 0x00004144 reg4177 */
+    struct {
+        RK_U32 num1_point_skin    : 15;
+        RK_U32 acc_cover16_num    : 17;
+    } st_skin_sum1;
+
+    /* 0x00004148 reg4178 */
+    struct {
+        RK_U32 num2_point_skin    : 15;
+        RK_U32 acc_bndry16_num    : 17;
+    } st_skin_sum2;
+
+    /* 0x0000414c reg4179 */
+    RK_U32 num0_grdnt_point_dep0;
+
+    /* 0x00004150 reg4180 */
+    RK_U32 num1_grdnt_point_dep0;
+
+    /* 0x00004154 reg4181 */
+    RK_U32 num2_grdnt_point_dep0;
+
+    /* 0x00004158 reg4182 */
+    struct {
+        RK_U32 ref1_inter32_num    : 19;
+        RK_U32 reserved            : 13;
+    } st_ref1_inter32;
+
+    /* 0x0000415c reg4183 */
+    struct {
+        RK_U32 ref1_inter16_num    : 21;
+        RK_U32 reserved            : 11;
+    } st_ref1_inter16;
+
+    /* 0x4160 - 0x417c */
+    RK_U32 reserved4184_4191[8];
+
+    /* 0x00004180 reg4192 - 0x0000424c reg4243*/
+    RK_U32 st_b8_qp[52];
+} Vepu511Status;
+
+/* class: dbg/st/axipn */
+/* 0x00005000 reg5120 - 0x0000523c reg5263 */
+typedef struct Vepu511Dbg_t {
+    /* 0x00005000 reg5120 */
+    struct {
+        RK_U32 vsp0_pos_x    : 16;
+        RK_U32 vsp0_pos_y    : 16;
+    } st_ppl_pos_vsp0;
+
+    /* 0x00005004 reg5121 */
+    struct {
+        RK_U32 vsp1_pos_x    : 16;
+        RK_U32 vsp1_pos_y    : 16;
+    } st_ppl_pos_vsp1;
+
+    /* 0x00005008 reg5122 */
+    struct {
+        RK_U32 vsp2_pos_x    : 16;
+        RK_U32 vsp2_pos_y    : 16;
+    } st_ppl_pos_vsp2;
+
+    /* 0x0000500c reg5123 */
+    struct {
+        RK_U32 cme_pos_x    : 16;
+        RK_U32 cme_pos_y    : 16;
+    } st_ppl_pos_cme;
+
+    /* 0x00005010 reg5124 */
+    struct {
+        RK_U32 swin_cmd_x    : 16;
+        RK_U32 swin_cmd_y    : 16;
+    } st_ppl_cmd_swin;
+
+    /* 0x00005014 reg5125 */
+    struct {
+        RK_U32 swin_pos_x    : 16;
+        RK_U32 swin_pos_y    : 16;
+    } st_ppl_pos_swin;
+    /* 0x00005018 reg5126 */
+    struct {
+        RK_U32 pren_pos_x    : 16;
+        RK_U32 pren_pos_y    : 16;
+    } st_ppl_pos_pren;
+
+    /* 0x0000501c reg5127 */
+    struct {
+        RK_U32 rfme_pos_x    : 16;
+        RK_U32 rfme_pos_y    : 16;
+    } st_ppl_pos_rfme;
+
+    /* 0x00005020 reg5128 */
+    struct {
+        RK_U32 rdo_pos_x    : 16;
+        RK_U32 rdo_pos_y    : 16;
+    } st_ppl_pos_rdo;
+
+    /* 0x00005024 reg5129 */
+    struct {
+        RK_U32 lpf_pos_x    : 16;
+        RK_U32 lpf_pos_y    : 16;
+    } st_ppl_pos_lpf;
+
+    /* 0x00005028 reg5130 */
+    struct {
+        RK_U32 etpy_pos_x    : 16;
+        RK_U32 etpy_pos_y    : 16;
+    } st_ppl_pos_etpy;
+
+    /* 0x0000502c reg5131 */
+    struct {
+        RK_U32 jsp0_pos_x    : 16;
+        RK_U32 jsp0_pos_y    : 16;
+    } st_ppl_pos_jsp0;
+
+    /* 0x00005030 reg5132 */
+    struct {
+        RK_U32 jsp1_pos_x    : 16;
+        RK_U32 jsp1_pos_y    : 16;
+    } st_ppl_pos_jsp1;
+
+    /* 0x00005034 reg5133 */
+    struct {
+        RK_U32 jsp2_pos_x    : 16;
+        RK_U32 jsp2_pos_y    : 16;
+    } st_ppl_pos_jsp2;
+
+    /* 0x00005038 reg5134 */
+    struct {
+        RK_U32 jpeg_pos_x    : 16;
+        RK_U32 jpeg_pos_y    : 16;
+    } st_ppl_pos_jpeg;
+
+    /* 0x0000503c reg5135 */
+    struct {
+        RK_U32 vhdr_pos_y    : 16;
+        RK_U32 jhdr_pos_y    : 16;
+    } dbg_pos_pp_hdr;
+
+    /* 0x00005040 reg5136 */
+    struct {
+        RK_U32 reserved         : 7;
+        RK_U32 vsp0_cmd_flst    : 1;
+        RK_U32 reserved1        : 24;
+    } dbg_ctrl_vsp0;
+
+    /* 0x00005044 reg5137 - 0x00005048 reg5138*/
+    RK_U32 reserved[2];
+
+    /* 0x0000504c reg5139 */
+    struct {
+        RK_U32 cme_madp_vld       : 1;
+        RK_U32 cme_madp_rdy0      : 1;
+        RK_U32 cme_madp_rdy1      : 1;
+        RK_U32 reserved           : 1;
+        RK_U32 cme_mv16_vld       : 1;
+        RK_U32 cme_mv16_rdy       : 1;
+        RK_U32 cme_st_vld         : 1;
+        RK_U32 cme_st_rdy         : 1;
+        RK_U32 cme_stat_vld       : 1;
+        RK_U32 cme_stat_rdy       : 1;
+        RK_U32 cme_diff_vld       : 1;
+        RK_U32 cme_diff_rdy       : 1;
+        RK_U32 cme_cmmv_vld       : 1;
+        RK_U32 cme_cmmv_rdy       : 1;
+        RK_U32 cme_smvp_vld       : 1;
+        RK_U32 cme_smvp_rdy       : 1;
+        RK_U32 rdo_tmvp_rvld      : 1;
+        RK_U32 rdo_tmvp_rrdy      : 1;
+        RK_U32 rdo_tmvp_wvld      : 1;
+        RK_U32 rdo_tmvp_wrdy      : 1;
+        RK_U32 rdo_lbf_wvld       : 1;
+        RK_U32 rdo_lbf_wrdy       : 1;
+        RK_U32 rdo_lbf_rvld       : 1;
+        RK_U32 rdo_lbf_rrdy       : 1;
+        RK_U32 rdo_rfmv_rvld      : 1;
+        RK_U32 rdo_rfmv_rrdy      : 1;
+        RK_U32 rdo_hevc_qp_vld    : 1;
+        RK_U32 rdo_hevc_qp_rdy    : 1;
+        RK_U32 reserved1          : 4;
+    } dbg_hs_ppl;
+
+    /* 0x00005050 reg5140 */
+    struct {
+        RK_U32 swin_org_err      : 1;
+        RK_U32 swin_ref_err      : 1;
+        RK_U32 reserved          : 10;
+        RK_U32 swin_cmd_vld      : 1;
+        RK_U32 swin_cmd_rdy      : 1;
+        RK_U32 reserved1         : 2;
+        RK_U32 swin_buff_ptr     : 2;
+        RK_U32 swin_buff_num0    : 2;
+        RK_U32 swin_buff_num1    : 2;
+        RK_U32 swin_buff_num2    : 2;
+        RK_U32 reserved2         : 4;
+        RK_U32 swin_wrk          : 1;
+        RK_U32 swin_tout         : 1;
+        RK_U32 reserved3         : 2;
+    } dbg_ctrl_swin;
+
+    /* 0x00005054 reg5141 */
+    struct {
+        RK_U32 pnra_org_err     : 1;
+        RK_U32 pnra_qp_err      : 1;
+        RK_U32 pnra_rfme_err    : 1;
+        RK_U32 reserved         : 9;
+        RK_U32 pnra_olm_vld     : 1;
+        RK_U32 pnra_olm_rdy     : 1;
+        RK_U32 pnra_subj_vld    : 1;
+        RK_U32 pnra_subj_rdy    : 1;
+        RK_U32 reserved1        : 8;
+        RK_U32 pnra_wrk_ena     : 1;
+        RK_U32 reserved2        : 3;
+        RK_U32 pnra_wrk         : 1;
+        RK_U32 pnra_tout        : 1;
+        RK_U32 reserved3        : 2;
+    } dbg_ctrl_pren;
+
+    /* 0x00005058 reg5142 */
+    struct {
+        RK_U32 rfme_org_err     : 1;
+        RK_U32 rfme_ref_err     : 1;
+        RK_U32 rfme_cmmv_err    : 1;
+        RK_U32 rfme_rfmv_err    : 1;
+        RK_U32 rfme_tmvp_err    : 1;
+        RK_U32 rfme_qp_err      : 1;
+        RK_U32 rfme_pnra_err    : 1;
+        RK_U32 reserved         : 5;
+        RK_U32 rfme_tmvp_vld    : 1;
+        RK_U32 rfme_tmvp_rdy    : 1;
+        RK_U32 rfme_smvp_vld    : 1;
+        RK_U32 rfme_smvp_rdy    : 1;
+        RK_U32 rfme_cmmv_vld    : 1;
+        RK_U32 rfme_cmmv_rdy    : 1;
+        RK_U32 rfme_rfmv_vld    : 1;
+        RK_U32 rfme_rfmv_rdy    : 1;
+        RK_U32 reserved1        : 8;
+        RK_U32 rfme_wrk         : 1;
+        RK_U32 rfme_tout        : 1;
+        RK_U32 reserved2        : 2;
+    } dbg_ctrl_rfme;
+
+    /* 0x0000505c reg5143 */
+    struct {
+        RK_U32 rdo_org_err         : 1;
+        RK_U32 rdo_ref_err         : 1;
+        RK_U32 rdo_inf_err         : 1;
+        RK_U32 rdo_coef_err        : 1;
+        RK_U32 rdo_lbfr_err        : 1;
+        RK_U32 rdo_lbfw_err        : 1;
+        RK_U32 rdo_madi_lbf_err    : 1;
+        RK_U32 rdo_tmvp_wr_err     : 1;
+        RK_U32 rdo_smear_err       : 1;
+        RK_U32 rdo_mbqp_err        : 1;
+        RK_U32 rdo_rc_err          : 1;
+        RK_U32 rdo_ent_err         : 1;
+        RK_U32 rdo_lpf_err         : 1;
+        RK_U32 rdo_st_err          : 1;
+        RK_U32 rdo_tmvp_rd_err     : 1;
+        RK_U32 rdo_rfmv_err        : 1;
+        RK_U32 reserved            : 12;
+        RK_U32 rdo_wrk             : 1;
+        RK_U32 rdo_tout            : 1;
+        RK_U32 reserved1           : 2;
+    } dbg_ctrl_rdo;
+
+    /* 0x00005060 reg5144 */
+    struct {
+        RK_U32 lpf_org_err     : 1;
+        RK_U32 lpf_rdo_err     : 1;
+        RK_U32 reserved        : 10;
+        RK_U32 lpf_rcol_vld    : 1;
+        RK_U32 lpf_rcol_rdy    : 1;
+        RK_U32 lpf_lbf_wvld    : 1;
+        RK_U32 lpf_lbf_wrdy    : 1;
+        RK_U32 lpf_lbf_rvld    : 1;
+        RK_U32 lpf_lbf_rrdy    : 1;
+        RK_U32 reserved1       : 6;
+        RK_U32 lpf_wrk_ena     : 1;
+        RK_U32 reserved2       : 3;
+        RK_U32 lpf_wrk         : 1;
+        RK_U32 lpf_tout        : 1;
+        RK_U32 reserved3       : 2;
+    } dbg_ctrl_lpf;
+
+    /* 0x00005064 reg5145 */
+    struct {
+        RK_U32 reserved         : 12;
+        RK_U32 etpy_slf_full    : 1;
+        RK_U32 etpy_bsw_vld     : 1;
+        RK_U32 etpy_bsw_rdy     : 1;
+        RK_U32 reserved1        : 9;
+        RK_U32 etpy_wrk_ena     : 1;
+        RK_U32 reserved2        : 3;
+        RK_U32 etpy_wrk         : 1;
+        RK_U32 etpy_tout        : 1;
+        RK_U32 reserved3        : 2;
+    } dbg_ctrl_etpy;
+
+    /* 0x00005068 reg5146 */
+    struct {
+        RK_U32 jhdr_src_err      : 1;
+        RK_U32 jhdr_cmd_flst     : 1;
+        RK_U32 reserved          : 2;
+        RK_U32 jsp0_org_err      : 1;
+        RK_U32 jsp0_pp2_err      : 1;
+        RK_U32 jsp0_paral_err    : 1;
+        RK_U32 jsp0_cmd_flst     : 1;
+        RK_U32 jhdr_vld          : 1;
+        RK_U32 jhdr_rdy          : 1;
+        RK_U32 jsp0_cmd_vld      : 1;
+        RK_U32 jsp0_cmd_rdy      : 1;
+        RK_U32 reserved1         : 12;
+        RK_U32 jsp0_wrk_ena      : 1;
+        RK_U32 reserved2         : 3;
+        RK_U32 jsp0_wrk          : 1;
+        RK_U32 jsp0_tout         : 1;
+        RK_U32 reserved3         : 2;
+    } dbg_ctrl_jsp0;
+
+    /* 0x0000506c reg5147 */
+    struct {
+        RK_U32 jsp2_org_err     : 1;
+        RK_U32 reserved         : 11;
+        RK_U32 jsp2_madi_vld    : 1;
+        RK_U32 jsp2_madi_rdy    : 1;
+        RK_U32 reserved1        : 10;
+        RK_U32 jsp2_wrk_ena     : 1;
+        RK_U32 reserved2        : 3;
+        RK_U32 jsp2_wrk         : 1;
+        RK_U32 jsp2_tout        : 1;
+        RK_U32 reserved3        : 2;
+    } dbg_ctrl_jsp2;
+
+    /* 0x00005070 reg5148 */
+    struct {
+        RK_U32 jpeg_org_err    : 1;
+        RK_U32 jpeg_st_err     : 1;
+        RK_U32 reserved        : 10;
+        RK_U32 jpg_slf_full    : 1;
+        RK_U32 jpg_bsw_vld     : 1;
+        RK_U32 jpg_bsw_rdy     : 1;
+        RK_U32 reserved1       : 9;
+        RK_U32 jpeg_wrk_ena    : 1;
+        RK_U32 reserved2       : 3;
+        RK_U32 jpeg_wrk        : 1;
+        RK_U32 jpeg_tout       : 1;
+        RK_U32 reserved3       : 2;
+    } dbg_ctrl_jpeg;
+
+    /* 0x00005074 reg5149 */
+    struct {
+        RK_U32 vsp1_org_err    : 1;
+        RK_U32 reserved        : 7;
+        RK_U32 vsp1_wrk_ena    : 1;
+        RK_U32 reserved1       : 3;
+        RK_U32 vsp1_wrk        : 1;
+        RK_U32 vsp1_tout       : 1;
+        RK_U32 reserved2       : 2;
+        RK_U32 jsp1_org_err    : 1;
+        RK_U32 reserved3       : 7;
+        RK_U32 jsp1_wrk_ena    : 1;
+        RK_U32 reserved4       : 3;
+        RK_U32 jsp1_wrk        : 1;
+        RK_U32 jsp1_tout       : 1;
+        RK_U32 reserved5       : 2;
+    } dbg_ctrl_pp1;
+
+    /* 0x00005078 reg5150 */
+    struct {
+        RK_U32 pp2_frm_done     : 1;
+        RK_U32 cime_frm_done    : 1;
+        RK_U32 jpeg_frm_done    : 1;
+        RK_U32 rdo_frm_done     : 1;
+        RK_U32 lpf_frm_done     : 1;
+        RK_U32 ent_frm_done     : 1;
+        RK_U32 reserved         : 2;
+        RK_U32 criw_frm_done    : 1;
+        RK_U32 meiw_frm_done    : 1;
+        RK_U32 smiw_frm_done    : 1;
+        RK_U32 dma_frm_idle     : 1;
+        RK_U32 reserved1        : 12;
+        RK_U32 video_ena        : 1;
+        RK_U32 jpeg_ena         : 1;
+        RK_U32 vepu_pp_ena      : 1;
+        RK_U32 reserved2        : 1;
+        RK_U32 frm_wrk          : 1;
+        RK_U32 frm_tout         : 1;
+        RK_U32 reserved3        : 2;
+    } dbg_tctrl;
+
+    /* 0x0000507c reg5151 */
+    struct {
+        RK_U32 enc_frm_cur     : 3;
+        RK_U32 lkt_src_paus    : 1;
+        RK_U32 lkt_cfg_paus    : 1;
+        RK_U32 reserved        : 27;
+    } dbg_frm_task;
+
+    /* 0x00005080 reg5152 */
+    struct {
+        RK_U32 sli_num     : 15;
+        RK_U32 reserved    : 17;
+    } st_sli_num;
+
+    /* 0x5084 - 0x50fc */
+    RK_U32 reserved5153_5183[31];
+
+    /* 0x00005100 reg5184 */
+    struct {
+        RK_U32 empty_oafifo        : 1;
+        RK_U32 full_cmd_oafifo     : 1;
+        RK_U32 full_data_oafifo    : 1;
+        RK_U32 empty_iafifo        : 1;
+
+        RK_U32 full_cmd_iafifo     : 1;
+        RK_U32 full_info_iafifo    : 1;
+        RK_U32 fbd_brq_st          : 4;
+        RK_U32 fbd_hdr_vld         : 1;
+        RK_U32 fbd_bmng_end        : 1;
+
+        RK_U32 nfbd_req_st         : 4;
+        RK_U32 acc_axi_cmd         : 8;
+        RK_U32 reserved            : 8;
+    } dbg_pp_st;
+
+    /* 0x00005104 reg5185 */
+    struct {
+        RK_U32 r_ena_lambd        : 1;
+        RK_U32 r_fst_swinw_end    : 1;
+        RK_U32 r_swinw_end        : 1;
+        RK_U32 r_cnt_swinw        : 1;
+
+        RK_U32 r_dspw_end         : 1;
+        RK_U32 r_dspw_cnt         : 1;
+        RK_U32 i_sjgen_work       : 1;
+        RK_U32 r_end_rspgen       : 1;
+
+        RK_U32 r_cost_gate        : 1;
+        RK_U32 r_ds_gate          : 1;
+        RK_U32 r_mvp_gate         : 1;
+        RK_U32 i_smvp_arrdy       : 1;
+
+        RK_U32 i_smvp_arvld       : 1;
+        RK_U32 i_stptr_wrdy       : 1;
+        RK_U32 i_stptr_wvld       : 1;
+        RK_U32 i_rdy_atf          : 1;
+
+        RK_U32 i_vld_atf          : 1;
+        RK_U32 i_rdy_bmv16        : 1;
+        RK_U32 i_vld_bmv16        : 1;
+        RK_U32 i_wr_dsp           : 1;
+
+        RK_U32 i_rdy_dsp          : 1;
+        RK_U32 i_vld_dsp          : 1;
+        RK_U32 r_rdy_org          : 1;
+        RK_U32 i_vld_org          : 1;
+
+        RK_U32 i_rdy_state        : 1;
+        RK_U32 i_vld_state        : 1;
+        RK_U32 i_rdy_madp         : 1;
+        RK_U32 i_vld_madp         : 1;
+
+        RK_U32 i_rdy_diff         : 1;
+        RK_U32 i_vld_diff         : 1;
+        RK_U32 reserved           : 2;
+    } dbg_cime_st;
+
+    /* 0x00005108 reg5186 */
+    RK_U32 swin_dbg_inf;
+
+    /* 0x0000510c reg5187 */
+    struct {
+        RK_U32 bbrq_cmps_left_len2    : 1;
+        RK_U32 bbrq_cmps_left_len1    : 1;
+        RK_U32 cmps_left_len0         : 1;
+        RK_U32 bbrq_rdy2              : 1;
+        RK_U32 dcps_vld2              : 1;
+        RK_U32 bbrq_rdy1              : 1;
+        RK_U32 dcps_vld1              : 1;
+        RK_U32 bbrq_rdy0              : 1;
+        RK_U32 dcps_vld0              : 1;
+        RK_U32 hb_rdy2                : 1;
+        RK_U32 bbrq_vld2              : 1;
+        RK_U32 hb_rdy1                : 1;
+        RK_U32 bbrq_vld1              : 1;
+        RK_U32 hb_rdy0                : 1;
+        RK_U32 bbrq_vld0              : 1;
+        RK_U32 idle_msb2              : 1;
+        RK_U32 idle_msb1              : 1;
+        RK_U32 idle_msb0              : 1;
+        RK_U32 cur_state_dcps         : 1;
+        RK_U32 cur_state_bbrq         : 1;
+        RK_U32 cur_state_hb           : 1;
+        RK_U32 cke_bbrq_dcps          : 1;
+        RK_U32 cke_dcps               : 1;
+        RK_U32 cke_bbrq               : 1;
+        RK_U32 rdy_lwcd_rsp           : 1;
+        RK_U32 vld_lwcd_rsp           : 1;
+        RK_U32 rdy_lwcd_req           : 1;
+        RK_U32 vld_lwcd_req           : 1;
+        RK_U32 rdy_lwrsp              : 1;
+        RK_U32 vld_lwrsp              : 1;
+        RK_U32 rdy_lwreq              : 1;
+        RK_U32 vld_lwreq              : 1;
+    } dbg_fbd_hhit0;
+
+    /* 0x00005110 reg5188 */
+    RK_U32 rfme_dbg_inf;
+
+    /* 0x5114 */
+    RK_U32 reserved_5189;
+
+    /* 0x00005118 reg5190 */
+    RK_U32 dbg0_fbd;
+
+    /* 0x0000511c reg5191 */
+    RK_U32 dbg1_fbd;
+
+    /* 0x00005120 reg5192 */
+    RK_U32 rdo_dbg0;
+
+    /* 0x00005124 reg5193 */
+    RK_U32 rdo_dbg1;
+
+    /* 0x00005128 reg5194 */
+    struct {
+        RK_U32 h264_sh_st_cs    : 4;
+        RK_U32 rsd_st_cs        : 4;
+        RK_U32 h264_sd_st_cs    : 5;
+        RK_U32 etpy_rdy         : 1;
+        RK_U32 reserved         : 18;
+    } dbg_etpy;
+
+    /* 0x0000512c reg5195 */
+    struct {
+        RK_U32 chl_aw_vld        : 10;
+        RK_U32 chl_aw_rdy        : 10;
+        RK_U32 aw_vld_arb        : 1;
+        RK_U32 aw_rdy_arb        : 1;
+        RK_U32 aw_vld_crosclk    : 1;
+        RK_U32 aw_rdy_crosclk    : 1;
+        RK_U32 aw_rdy_mmu        : 1;
+        RK_U32 aw_vld_mmu        : 1;
+        RK_U32 aw_rdy_axi        : 1;
+        RK_U32 aw_vld_axi        : 1;
+        RK_U32 reserved          : 4;
+    } dbg_dma_aw;
+
+    /* 0x00005130 reg5196 */
+    struct {
+        RK_U32 chl_w_vld        : 10;
+        RK_U32 chl_w_rdy        : 10;
+        RK_U32 w_vld_arb        : 1;
+        RK_U32 w_rdy_arb        : 1;
+        RK_U32 w_vld_crosclk    : 1;
+        RK_U32 w_rdy_crosclk    : 1;
+        RK_U32 w_rdy_mmu        : 1;
+        RK_U32 w_vld_mmu        : 1;
+        RK_U32 w_rdy_axi        : 1;
+        RK_U32 w_vld_axi        : 1;
+        RK_U32 reserved         : 4;
+    } dbg_dma_w;
+
+    /* 0x00005134 reg5197 */
+    struct {
+        RK_U32 chl_ar_vld        : 9;
+        RK_U32 chl_ar_rdy        : 9;
+        RK_U32 reserved          : 2;
+        RK_U32 ar_vld_arb        : 1;
+        RK_U32 ar_rdy_arb        : 1;
+        RK_U32 ar_vld_crosclk    : 1;
+        RK_U32 ar_rdy_crosclk    : 1;
+        RK_U32 ar_rdy_mmu        : 1;
+        RK_U32 ar_vld_mmu        : 1;
+        RK_U32 ar_rdy_axi        : 1;
+        RK_U32 ar_vld_axi        : 1;
+        RK_U32 reserved1         : 4;
+    } dbg_dma_ar;
+
+    /* 0x00005138 reg5198 */
+    struct {
+        RK_U32 chl_r_vld        : 9;
+        RK_U32 chl_r_rdy        : 9;
+        RK_U32 reserved         : 2;
+        RK_U32 r_vld_arb        : 1;
+        RK_U32 r_rdy_arb        : 1;
+        RK_U32 r_vld_crosclk    : 1;
+        RK_U32 r_rdy_crosclk    : 1;
+        RK_U32 r_rdy_mmu        : 1;
+        RK_U32 r_vld_mmu        : 1;
+        RK_U32 r_rdy_axi        : 1;
+        RK_U32 r_vld_axi        : 1;
+        RK_U32 b_rdy_mmu        : 1;
+        RK_U32 b_vld_mmu        : 1;
+        RK_U32 b_rdy_axi        : 1;
+        RK_U32 b_vld_axi        : 1;
+    } dbg_dma_r;
+
+    /* 0x0000513c reg5199 */
+    struct {
+        RK_U32 dbg_sclr    : 20;
+        RK_U32 dbg_arb     : 12;
+    } dbg_dma_dbg0;
+
+    /* 0x00005140 reg5200 */
+    struct {
+        RK_U32 bsw_fsm_stus     : 4;
+        RK_U32 bsw_aw_full      : 1;
+        RK_U32 bsw_rdy_ent      : 1;
+        RK_U32 bsw_vld_ent      : 1;
+        RK_U32 jpg_bsw_stus     : 4;
+        RK_U32 jpg_aw_full      : 1;
+        RK_U32 jpg_bsw_rdy      : 1;
+        RK_U32 jpg_bsw_vld      : 1;
+        RK_U32 crpw_fsm_stus    : 3;
+        RK_U32 hdwr_rdy         : 1;
+        RK_U32 hdwr_vld         : 1;
+        RK_U32 bdwr_rdy         : 1;
+        RK_U32 bdwr_vld         : 1;
+        RK_U32 nfbc_rdy         : 1;
+        RK_U32 nfbc_vld         : 1;
+        RK_U32 dsp_fsm_stus     : 2;
+        RK_U32 dsp_wr_flg       : 1;
+        RK_U32 dsp_rsy          : 1;
+        RK_U32 dsp_vld          : 1;
+        RK_U32 lpfw_fsm_stus    : 3;
+        RK_U32 reserved         : 1;
+    } dbg_dma_dbg1;
+
+    /* 0x00005144 reg5201 */
+    struct {
+        RK_U32 awvld_mdo     : 1;
+        RK_U32 awrdy_mdo     : 1;
+        RK_U32 wvld_mdo      : 1;
+        RK_U32 wrdy_mdo      : 1;
+        RK_U32 awvld_odo     : 1;
+        RK_U32 awrdy_odo     : 1;
+        RK_U32 wvld_odo      : 1;
+        RK_U32 wrdy_odo      : 1;
+        RK_U32 awvld_rfmw    : 1;
+        RK_U32 awrdy_rfmw    : 1;
+        RK_U32 wvld_rfmw     : 1;
+        RK_U32 wrdy_rfmw     : 1;
+        RK_U32 arvld_rfmr    : 1;
+        RK_U32 arrdy_rfmr    : 1;
+        RK_U32 rvld_rfmr     : 1;
+        RK_U32 rrdy_rfmr     : 1;
+        RK_U32 reserved      : 16;
+    } dbg_dma_vpp;
+
+    /* 0x00005148 reg5202 */
+    struct {
+        RK_U32 rdo_st      : 20;
+        RK_U32 reserved    : 12;
+    } dbg_rdo_st;
+
+    /* 0x0000514c reg5203 */
+    struct {
+        RK_U32 lpf_work               : 1;
+        RK_U32 rdo_par_nrdy           : 1;
+        RK_U32 rdo_rcn_nrdy           : 1;
+        RK_U32 lpf_rcn_rdy            : 1;
+        RK_U32 dblk_work              : 1;
+        RK_U32 sao_work               : 1;
+        RK_U32 reserved               : 18;
+        RK_U32 tile_bdry_read         : 1;
+        RK_U32 tile_bdry_write        : 1;
+        RK_U32 tile_bdry_rrdy         : 1;
+        RK_U32 rdo_read_tile_bdry     : 1;
+        RK_U32 rdo_write_tile_bdry    : 1;
+        RK_U32 reserved1              : 3;
+    } dbg_lpf;
+
+    /* 0x5150 */
+    RK_U32 reserved_5204;
+
+    /* 0x00005154 reg5205 */
+    RK_U32 dbg0_cache;
+
+    /* 0x00005158 reg5206 */
+    RK_U32 dbg2_fbd;
+
+    /* 0x515c */
+    RK_U32 reserved_5207;
+
+    /* 0x00005160 reg5208 */
+    struct {
+        RK_U32 ebuf_diff_cmd      : 8;
+        RK_U32 lbuf_lpf_ncnt      : 7;
+        RK_U32 lbuf_lpf_cien      : 1;
+        RK_U32 lbuf_rdo_ncnt      : 7;
+        RK_U32 lbuf_rdo_cien      : 1;
+        RK_U32 lbuf_tctrl_ncnt    : 7;
+        RK_U32 lbuf_tctrl_cien    : 1;
+    } dbg_lbuf0;
+
+    /* 0x00005164 reg5209 */
+    struct {
+        RK_U32 rvld_ebfr          : 1;
+        RK_U32 rrdy_ebfr          : 1;
+        RK_U32 arvld_ebfr         : 1;
+        RK_U32 arrdy_ebfr         : 1;
+        RK_U32 wvld_ebfw          : 1;
+        RK_U32 wrdy_ebfw          : 1;
+        RK_U32 awvld_ebfw         : 1;
+        RK_U32 awrdy_ebfw         : 1;
+        RK_U32 lpf_lbuf_rvld      : 1;
+        RK_U32 lpf_lbuf_rrdy      : 1;
+        RK_U32 lpf_lbuf_wvld      : 1;
+        RK_U32 lpf_lbuf_wrdy      : 1;
+        RK_U32 rdo_lbuf_rvld      : 1;
+        RK_U32 rdo_lbuf_rrdy      : 1;
+        RK_U32 rdo_lbuf_wvld      : 1;
+        RK_U32 rdo_lbuf_wrdy      : 1;
+        RK_U32 fme_lbuf_rvld      : 1;
+        RK_U32 fme_lbuf_rrdy      : 1;
+        RK_U32 cme_lbuf_rvld      : 1;
+        RK_U32 cme_lbuf_rrdy      : 1;
+        RK_U32 smear_lbuf_rvld    : 1;
+        RK_U32 smear_lbuf_rrdy    : 1;
+        RK_U32 smear_lbuf_wvld    : 1;
+        RK_U32 smear_lbuf_wrdy    : 1;
+        RK_U32 depth_lbuf_wvld    : 1;
+        RK_U32 depth_lbuf_wrdy    : 1;
+        RK_U32 rdo_lbufw_flag     : 1;
+        RK_U32 rdo_lbufr_flag     : 1;
+        RK_U32 cme_lbufr_flag     : 1;
+        RK_U32 reserved           : 3;
+    } dbg_lbuf1;
+
+    /* 0x00005168 reg5210 */
+    struct {
+        RK_U32 dbg_isp_fcnt    : 8;
+        RK_U32 dbg_isp_fcyc    : 24;
+    } dbg_dvbm_isp0;
+
+    /* 0x0000516c reg5211 */
+    struct {
+        RK_U32 dbg_isp_lcnt    : 14;
+        RK_U32 reserved        : 1;
+        RK_U32 dbg_isp_ltgl    : 1;
+        RK_U32 dbg_isp_fcnt    : 8;
+        RK_U32 dbg_isp_oflw    : 1;
+        RK_U32 dbg_isp_ftgl    : 1;
+        RK_U32 dbg_isp_full    : 1;
+        RK_U32 dbg_isp_work    : 1;
+        RK_U32 dbg_isp_lvld    : 1;
+        RK_U32 dbg_isp_lrdy    : 1;
+        RK_U32 dbg_isp_fvld    : 1;
+        RK_U32 dbg_isp_frdy    : 1;
+    } dbg_dvbm_isp1;
+
+    /* 0x00005170 reg5212 */
+    struct {
+        RK_U32 dbg_bf0_isp_lcnt    : 14;
+        RK_U32 dbg_bf0_isp_llst    : 1;
+        RK_U32 dbg_bf0_isp_sofw    : 1;
+        RK_U32 dbg_bf0_isp_fcnt    : 8;
+        RK_U32 dbg_bf0_isp_fsid    : 1;
+        RK_U32 reserved            : 5;
+        RK_U32 dbg_bf0_isp_pnt     : 1;
+        RK_U32 dbg_bf0_vpu_pnt     : 1;
+    } dbg_dvbm_buf0_inf0;
+
+    /* 0x00005174 reg5213 */
+    struct {
+        RK_U32 dbg_bf0_src_lcnt    : 14;
+        RK_U32 dbg_bf0_src_llst    : 1;
+        RK_U32 reserved            : 1;
+        RK_U32 dbg_bf0_vpu_lcnt    : 14;
+        RK_U32 dbg_bf0_vpu_llst    : 1;
+        RK_U32 dbg_bf0_vpu_vofw    : 1;
+    } dbg_dvbm_buf0_inf1;
+
+    /* 0x00005178 reg5214 */
+    struct {
+        RK_U32 dbg_bf1_isp_lcnt    : 14;
+        RK_U32 dbg_bf1_isp_llst    : 1;
+        RK_U32 dbg_bf1_isp_sofw    : 1;
+        RK_U32 dbg_bf1_isp_fcnt    : 8;
+        RK_U32 dbg_bf1_isp_fsid    : 1;
+        RK_U32 reserved            : 5;
+        RK_U32 dbg_bf1_isp_pnt     : 1;
+        RK_U32 dbg_bf1_vpu_pnt     : 1;
+    } dbg_dvbm_buf1_inf0;
+
+    /* 0x0000517c reg5215 */
+    struct {
+        RK_U32 dbg_bf1_src_lcnt    : 14;
+        RK_U32 dbg_bf1_src_llst    : 1;
+        RK_U32 reserved            : 1;
+        RK_U32 dbg_bf1_vpu_lcnt    : 14;
+        RK_U32 dbg_bf1_vpu_llst    : 1;
+        RK_U32 dbg_bf1_vpu_vofw    : 1;
+    } dbg_dvbm_buf1_inf1;
+
+    /* 0x00005180 reg5216 */
+    struct {
+        RK_U32 dbg_bf2_isp_lcnt    : 14;
+        RK_U32 dbg_bf2_isp_llst    : 1;
+        RK_U32 dbg_bf2_isp_sofw    : 1;
+        RK_U32 dbg_bf2_isp_fcnt    : 1;
+        RK_U32 dbg_bf2_isp_fsid    : 1;
+        RK_U32 reserved            : 12;
+        RK_U32 dbg_bf2_isp_pnt     : 1;
+        RK_U32 dbg_bf2_vpu_pnt     : 1;
+    } dbg_dvbm_buf2_inf0;
+
+    /* 0x00005184 reg5217 */
+    struct {
+        RK_U32 dbg_bf2_src_lcnt    : 14;
+        RK_U32 dbg_bf2_src_llst    : 1;
+        RK_U32 reserved            : 1;
+        RK_U32 dbg_bf2_vpu_lcnt    : 14;
+        RK_U32 dbg_bf2_vpu_llst    : 1;
+        RK_U32 dbg_bf2_vpu_vofw    : 1;
+    } dbg_dvbm_buf2_inf1;
+
+    /* 0x00005188 reg5218 */
+    struct {
+        RK_U32 dbg_bf3_isp_lcnt    : 14;
+        RK_U32 dbg_bf3_isp_llst    : 1;
+        RK_U32 dbg_bf3_isp_sofw    : 1;
+        RK_U32 dbg_bf3_isp_fcnt    : 1;
+        RK_U32 dbg_bf3_isp_fsid    : 1;
+        RK_U32 reserved            : 12;
+        RK_U32 dbg_bf3_isp_pnt     : 1;
+        RK_U32 dbg_bf3_vpu_pnt     : 1;
+    } dbg_dvbm_buf3_inf0;
+
+    /* 0x0000518c reg5219 */
+    struct {
+        RK_U32 dbg_bf3_src_lcnt    : 14;
+        RK_U32 dbg_bf3_src_llst    : 1;
+        RK_U32 reserved            : 1;
+        RK_U32 dbg_bf3_vpu_lcnt    : 14;
+        RK_U32 dbg_bf3_vpu_llst    : 1;
+        RK_U32 dbg_bf3_vpu_vofw    : 1;
+    } dbg_dvbm_buf3_inf1;
+
+    /* 0x00005190 reg5220 */
+    struct {
+        RK_U32 dbg_isp_fptr     : 3;
+        RK_U32 dbg_isp_full     : 1;
+        RK_U32 dbg_src_fptr     : 3;
+        RK_U32 reserved         : 1;
+        RK_U32 dbg_vpu_fptr     : 3;
+        RK_U32 dbg_vpu_empt     : 1;
+        RK_U32 dbg_vpu_lvld     : 1;
+        RK_U32 dbg_vpu_lrdy     : 1;
+        RK_U32 dbg_vpu_fvld     : 1;
+        RK_U32 dbg_vpu_frdy     : 1;
+        RK_U32 dbg_fcnt_misp    : 4;
+        RK_U32 dbg_fcnt_mvpu    : 4;
+        RK_U32 dbg_fcnt_sofw    : 4;
+        RK_U32 dbg_fcnt_vofw    : 4;
+    } dbg_dvbm_ctrl;
+
+    /* 0x5194 - 0x519c */
+    RK_U32 reserved5221_5223[3];
+
+    /* 0x000051a0 reg5224 */
+    RK_U32 dbg_dvbm_buf0_yadr;
+
+    /* 0x000051a4 reg5225 */
+    RK_U32 dbg_dvbm_buf0_cadr;
+
+    /* 0x000051a8 reg5226 */
+    RK_U32 dbg_dvbm_buf1_yadr;
+
+    /* 0x000051ac reg5227 */
+    RK_U32 dbg_dvbm_buf1_cadr;
+
+    /* 0x000051b0 reg5228 */
+    RK_U32 dbg_dvbm_buf2_yadr;
+
+    /* 0x000051b4 reg5229 */
+    RK_U32 dbg_dvbm_buf2_cadr;
+
+    /* 0x000051b8 reg5230 */
+    RK_U32 dbg_dvbm_buf3_yadr;
+
+    /* 0x000051bc reg5231 */
+    RK_U32 dbg_dvbm_buf3_cadr;
+
+    /* 0x000051c0 reg5232 */
+    struct {
+        RK_U32 dchs_rx_cnt    : 11;
+        RK_U32 dchs_rx_id     : 2;
+        RK_U32 dchs_rx_en     : 1;
+        RK_U32 dchs_rx_ack    : 1;
+        RK_U32 dchs_rx_req    : 1;
+        RK_U32 dchs_tx_cnt    : 11;
+        RK_U32 dchs_tx_id     : 2;
+        RK_U32 dchs_tx_en     : 1;
+        RK_U32 dchs_tx_ack    : 1;
+        RK_U32 dchs_tx_req    : 1;
+    } dbg_dchs_intfc;
+
+    /* 0x000051c4 reg5233 */
+    struct {
+        RK_U32 lpfw_tx_cnt       : 11;
+        RK_U32 lpfw_tx_en        : 1;
+        RK_U32 crpw_tx_cnt       : 11;
+        RK_U32 crpw_tx_en        : 1;
+        RK_U32 dual_err_updt     : 1;
+        RK_U32 dlyc_fifo_oflw    : 1;
+        RK_U32 dlyc_tx_vld       : 1;
+        RK_U32 dlyc_tx_rdy       : 1;
+        RK_U32 dlyc_tx_empty     : 1;
+        RK_U32 dchs_tx_idle      : 1;
+        RK_U32 dchs_tx_asy       : 1;
+        RK_U32 dchs_tx_syn       : 1;
+    } dbg_dchs_tx_inf0;
+
+    /* 0x000051c8 reg5234 */
+    struct {
+        RK_U32 criw_tx_cnt    : 11;
+        RK_U32 criw_tx_en     : 1;
+        RK_U32 smrw_tx_cnt    : 11;
+        RK_U32 smrw_tx_en     : 1;
+        RK_U32 reserved       : 8;
+    } dbg_dchs_tx_inf1;
+
+    /* 0x000051cc reg5235 */
+    struct {
+        RK_U32 dual_rx_cnt        : 11;
+        RK_U32 dual_rx_id         : 2;
+        RK_U32 dual_rx_en         : 1;
+        RK_U32 dual_rx_syn        : 1;
+        RK_U32 dual_rx_lock       : 1;
+        RK_U32 dual_lpfr_dule     : 1;
+        RK_U32 dual_cime_dule     : 1;
+        RK_U32 dual_clomv_dule    : 1;
+        RK_U32 dual_smear_dule    : 1;
+        RK_U32 reserved           : 12;
+    } dbg_dchs_rx_inf0;
+
+    /* 0x51d0 - 0x51fc */
+    RK_U32 reserved5236_5247[12];
+
+    /* 0x00005200 reg5248 */
+    RK_U32 frame_cyc;
+
+    /* 0x00005204 reg5249 */
+    RK_U32 vsp0_fcyc;
+
+    /* 0x00005208 reg5250 */
+    RK_U32 vsp1_fcyc;
+
+    /* 0x0000520c reg5251 */
+    RK_U32 vsp2_fcyc;
+
+    /* 0x00005210 reg5252 */
+    RK_U32 cme_fcyc;
+
+    /* 0x00005214 reg5253 */
+    RK_U32 ldr_fcyc;
+
+    /* 0x00005218 reg5254 */
+    RK_U32 rfme_fcyc;
+
+    /* 0x0000521c reg5255 */
+    RK_U32 fme_fcyc;
+
+    /* 0x00005220 reg5256 */
+    RK_U32 rdo_fcyc;
+
+    /* 0x00005224 reg5257 */
+    RK_U32 lpf_fcyc;
+
+    /* 0x00005228 reg5258 */
+    RK_U32 etpy_fcyc;
+
+    /* 0x522c */
+    RK_U32 reserved_5259;
+
+    /* 0x00005230 reg5260 */
+    RK_U32 jsp0_fcyc;
+
+    /* 0x00005234 reg5261 */
+    RK_U32 jsp1_fcyc;
+
+    /* 0x00005238 reg5262 */
+    RK_U32 jsp2_fcyc;
+
+    /* 0x0000523c reg5263 */
+    RK_U32 jpeg_fcyc;
+
+} Vepu511Dbg;
+
+typedef struct Vepu511OsdCfg_t {
+    void *reg_base;
+    MppDev dev;
+    MppEncOSDData  *osd_data;
+    MppEncOSDData3 *osd_data3;
+} Vepu511OsdCfg;
+
+/* ROI block configuration */
+typedef struct Vepu511H264RoiBlkCfg {
+    RK_U32 qp_adju        : 8;
+    RK_U32 mdc_adju_inter : 4;
+    RK_U32 mdc_adju_skip  : 4;
+    RK_U32 mdc_adju_intra : 4;
+    RK_U32 reserved       : 12;
+} Vepu511H264RoiBlkCfg;
+
+typedef struct Vepu511H265RoiBlkCfg {
+    RK_U32 qp_adju        : 8;
+    RK_U32 reserved       : 12;
+    RK_U32 mdc_adju_inter : 4;
+    RK_U32 mdc_adju_skip  : 4;
+    RK_U32 mdc_adju_intra : 4;
+} Vepu511H265RoiBlkCfg;
+
+typedef struct Vepu511JpegCfg_t {
+    MppDev dev;
+    void *jpeg_reg_base;
+    void *reg_tab;
+    void *enc_task;
+    void *input_fmt;
+} Vepu511JpegCfg;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MPP_RET vepu511_set_osd(Vepu511OsdCfg * cfg, Vepu511Osd *osd);
+MPP_RET vepu511_set_roi(Vepu511RoiCfg *roi_reg_base, MppEncROICfg * roi, RK_S32 w, RK_S32 h);
+MPP_RET vepu511_set_jpeg_reg(Vepu511JpegCfg *cfg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __VEPU511_COMMON_H__ */
diff --git a/mpp/hal/rkenc/common/vepu5xx.h b/mpp/hal/rkenc/common/vepu5xx.h
index 9317ca7f..3d707888 100644
--- a/mpp/hal/rkenc/common/vepu5xx.h
+++ b/mpp/hal/rkenc/common/vepu5xx.h
@@ -20,5 +20,6 @@
 #define HWID_VEPU58X                (0x50603312)
 #define HWID_VEPU540C               (0x50603313)
 #define HWID_VEPU510                (0x506f2314)
+#define HWID_VEPU511                (0x50602715)
 
 #endif /* __VEPU5XX_H__ */
diff --git a/mpp/hal/rkenc/h264e/CMakeLists.txt b/mpp/hal/rkenc/h264e/CMakeLists.txt
index 91b88642..9d6f7c2a 100644
--- a/mpp/hal/rkenc/h264e/CMakeLists.txt
+++ b/mpp/hal/rkenc/h264e/CMakeLists.txt
@@ -16,6 +16,7 @@ set(HAL_H264E_SRC
     hal_h264e_vepu580.c
     hal_h264e_vepu540c.c
     hal_h264e_vepu510.c
+    hal_h264e_vepu511.c
     )
 
 add_library(hal_h264e_rkv STATIC
diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu511.c b/mpp/hal/rkenc/h264e/hal_h264e_vepu511.c
new file mode 100644
index 00000000..112883e3
--- /dev/null
+++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu511.c
@@ -0,0 +1,2511 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG "hal_h264e_vepu511"
+
+#include <string.h>
+
+#include "mpp_env.h"
+#include "mpp_mem.h"
+#include "mpp_common.h"
+#include "mpp_frame_impl.h"
+#include "mpp_packet_impl.h"
+#include "mpp_enc_cb_param.h"
+
+#include "rkv_enc_def.h"
+#include "hal_h264e_debug.h"
+#include "hal_bufs.h"
+#include "hal_h264e_vepu511_reg.h"
+#include "hal_h264e_vepu511.h"
+#include "hal_h264e_stream_amend.h"
+#include "h264e_dpb.h"
+
+#include "vepu5xx.h"
+#include "vepu5xx_common.h"
+#include "vepu541_common.h"
+#include "vepu511_common.h"
+
+#define DUMP_REG                0
+#define MAX_TASK_CNT            2
+#define VEPU540C_MAX_ROI_NUM    8
+
+/* Custom Quant Matrices: Joint Video Team */
+static RK_U8 vepu511_h264_cqm_jvt8i[64] = {
+    6, 10, 13, 16, 18, 23, 25, 27,
+    10, 11, 16, 18, 23, 25, 27, 29,
+    13, 16, 18, 23, 25, 27, 29, 31,
+    16, 18, 23, 25, 27, 29, 31, 33,
+    18, 23, 25, 27, 29, 31, 33, 36,
+    23, 25, 27, 29, 31, 33, 36, 38,
+    25, 27, 29, 31, 33, 36, 38, 40,
+    27, 29, 31, 33, 36, 38, 40, 42
+};
+
+static RK_U8 vepu511_h264_cqm_jvt8p[64] = {
+    9, 13, 15, 17, 19, 21, 22, 24,
+    13, 13, 17, 19, 21, 22, 24, 25,
+    15, 17, 19, 21, 22, 24, 25, 27,
+    17, 19, 21, 22, 24, 25, 27, 28,
+    19, 21, 22, 24, 25, 27, 28, 30,
+    21, 22, 24, 25, 27, 28, 30, 32,
+    22, 24, 25, 27, 28, 30, 32, 33,
+    24, 25, 27, 28, 30, 32, 33, 35
+};
+
+typedef struct Vepu511RoiH264BsCfg_t {
+    RK_U64 force_inter   : 42;
+    RK_U64 mode_mask     : 9;
+    RK_U64 reserved      : 10;
+    RK_U64 force_intra   : 1;
+    RK_U64 qp_adj_en     : 1;
+    RK_U64 amv_en        : 1;
+} Vepu511RoiH264BsCfg;
+
+typedef struct Vepu511H264Fbk_t {
+    RK_U32 hw_status;       /* 0:corret, 1:error */
+    RK_U32 frame_type;
+    RK_U32 qp_sum;
+    RK_U32 out_strm_size;
+    RK_U32 out_hw_strm_size;
+    RK_S64 sse_sum;
+    RK_U32 st_lvl64_inter_num;
+    RK_U32 st_lvl32_inter_num;
+    RK_U32 st_lvl16_inter_num;
+    RK_U32 st_lvl8_inter_num;
+    RK_U32 st_lvl32_intra_num;
+    RK_U32 st_lvl16_intra_num;
+    RK_U32 st_lvl8_intra_num;
+    RK_U32 st_lvl4_intra_num;
+    RK_U32 st_cu_num_qp[52];
+    RK_U32 st_madp;
+    RK_U32 st_madi;
+    RK_U32 st_mb_num;
+    RK_U32 st_ctu_num;
+    RK_U32 st_smear_cnt[5];
+} Vepu511H264Fbk;
+
+typedef struct HalH264eVepu511Ctx_t {
+    MppEncCfgSet            *cfg;
+
+    MppDev                  dev;
+    RK_S32                  frame_cnt;
+    RK_U32                  task_cnt;
+
+    /* buffers management */
+    HalBufs                 hw_recn;
+    RK_S32                  pixel_buf_fbc_hdr_size;
+    RK_S32                  pixel_buf_fbc_bdy_size;
+    RK_S32                  pixel_buf_size;
+    RK_S32                  thumb_buf_size;
+    RK_S32                  max_buf_cnt;
+    MppDevRegOffCfgs        *offsets;
+
+    /* external line buffer over 4K */
+    MppBufferGroup          ext_line_buf_grp;
+    MppBuffer               ext_line_bufs[MAX_TASK_CNT];
+    RK_S32                  ext_line_buf_size;
+
+    /* syntax for input from enc_impl */
+    RK_U32                  updated;
+    H264eSps                *sps;
+    H264ePps                *pps;
+    H264eDpb                *dpb;
+    H264eFrmInfo            *frms;
+
+    /* async encode TSVC info */
+    H264eReorderInfo        *reorder;
+    H264eMarkingInfo        *marking;
+
+    /* syntax for output to enc_impl */
+    EncRcTaskInfo           hal_rc_cfg;
+
+    /* osd */
+    Vepu511OsdCfg           osd_cfg;
+
+    /* roi */
+    void                    *roi_data;
+    MppBufferGroup          roi_grp;
+    MppBuffer               roi_base_cfg_buf;
+    RK_S32                  roi_base_buf_size;
+
+    /* two-pass deflicker */
+    MppBuffer               buf_pass1;
+
+    /* register */
+    HalVepu511RegSet        *regs_sets;
+    HalH264eVepuStreamAmend *amend_sets;
+
+    H264ePrefixNal          *prefix_sets;
+    H264eSlice              *slice_sets;
+
+    /* frame parallel info */
+    RK_S32                  task_idx;
+    RK_S32                  curr_idx;
+    RK_S32                  prev_idx;
+    HalVepu511RegSet        *regs_set;
+    HalH264eVepuStreamAmend *amend;
+    H264ePrefixNal          *prefix;
+    H264eSlice              *slice;
+
+    MppBuffer               ext_line_buf;
+
+    /* slice low delay output callback */
+    MppCbCtx                *output_cb;
+    RK_S32                  poll_slice_max;
+    RK_S32                  poll_cfg_size;
+    MppDevPollCfg           *poll_cfgs;
+
+    Vepu511H264Fbk          feedback;
+    Vepu511H264Fbk          last_frame_fb;
+
+    void                    *tune;
+    RK_S32                  smart_en;
+    RK_S32                  qpmap_en;
+} HalH264eVepu511Ctx;
+
+static RK_S32 h264_aq_tthd_default[16] = {
+    0,  0,  0,  0,  3,  3,  5,  5,
+    8,  8,  8, 15, 15, 20, 25, 25
+};
+
+static RK_S32 h264_P_aq_step_default[16] = {
+    -8, -7, -6, -5, -4, -3, -2, -1,
+    0,  1,  2,  3,  4,  5,  7,  8
+};
+
+static RK_S32 h264_I_aq_step_default[16] = {
+    -8, -7, -6, -5, -4, -3, -2, -1,
+    0,  1,  2,  3,  4,  5,  7,  8
+};
+
+static void setup_ext_line_bufs(HalH264eVepu511Ctx *ctx)
+{
+    RK_U32 i;
+
+    for (i = 0; i < ctx->task_cnt; i++) {
+        if (ctx->ext_line_bufs[i])
+            continue;
+
+        mpp_buffer_get(ctx->ext_line_buf_grp, &ctx->ext_line_bufs[i],
+                       ctx->ext_line_buf_size);
+    }
+}
+
+static void clear_ext_line_bufs(HalH264eVepu511Ctx *ctx)
+{
+    RK_U32 i;
+
+    for (i = 0; i < ctx->task_cnt; i++) {
+        if (ctx->ext_line_bufs[i]) {
+            mpp_buffer_put(ctx->ext_line_bufs[i]);
+            ctx->ext_line_bufs[i] = NULL;
+        }
+    }
+}
+
+static MPP_RET hal_h264e_vepu511_deinit(void *hal)
+{
+    HalH264eVepu511Ctx *p = (HalH264eVepu511Ctx *)hal;
+    RK_U32 i;
+
+    hal_h264e_dbg_func("enter %p\n", p);
+
+    if (p->dev) {
+        mpp_dev_deinit(p->dev);
+        p->dev = NULL;
+    }
+
+    clear_ext_line_bufs(p);
+
+    if (p->amend_sets) {
+        for (i = 0; i < p->task_cnt; i++)
+            h264e_vepu_stream_amend_deinit(&p->amend_sets[i]);
+    }
+
+    MPP_FREE(p->regs_sets);
+    MPP_FREE(p->amend_sets);
+    MPP_FREE(p->prefix_sets);
+    MPP_FREE(p->slice_sets);
+    MPP_FREE(p->reorder);
+    MPP_FREE(p->marking);
+    MPP_FREE(p->poll_cfgs);
+
+    if (p->ext_line_buf_grp) {
+        mpp_buffer_group_put(p->ext_line_buf_grp);
+        p->ext_line_buf_grp = NULL;
+    }
+
+    if (p->hw_recn) {
+        hal_bufs_deinit(p->hw_recn);
+        p->hw_recn = NULL;
+    }
+
+    if (p->roi_base_cfg_buf) {
+        mpp_buffer_put(p->roi_base_cfg_buf);
+        p->roi_base_cfg_buf = NULL;
+        p->roi_base_buf_size = 0;
+    }
+
+    if (p->roi_grp) {
+        mpp_buffer_group_put(p->roi_grp);
+        p->roi_grp = NULL;
+    }
+
+    if (p->offsets) {
+        mpp_dev_multi_offset_deinit(p->offsets);
+        p->offsets = NULL;
+    }
+
+    if (p->buf_pass1) {
+        mpp_buffer_put(p->buf_pass1);
+        p->buf_pass1 = NULL;
+    }
+
+    if (p->tune) {
+        // vepu511_h264e_tune_deinit(p->tune);
+        p->tune = NULL;
+    }
+
+    hal_h264e_dbg_func("leave %p\n", p);
+
+    return MPP_OK;
+}
+
+static MPP_RET hal_h264e_vepu511_init(void *hal, MppEncHalCfg *cfg)
+{
+    HalH264eVepu511Ctx *p = (HalH264eVepu511Ctx *)hal;
+    MPP_RET ret = MPP_OK;
+    RK_U32 i;
+
+    hal_h264e_dbg_func("enter %p\n", p);
+
+    p->cfg = cfg->cfg;
+    /* update output to MppEnc */
+    cfg->type = VPU_CLIENT_RKVENC;
+    ret = mpp_dev_init(&cfg->dev, cfg->type);
+    if (ret) {
+        mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
+        goto DONE;
+    }
+    p->dev = cfg->dev;
+    p->task_cnt = cfg->task_cnt;
+    mpp_assert(p->task_cnt && p->task_cnt <= MAX_TASK_CNT);
+
+    ret = hal_bufs_init(&p->hw_recn);
+    if (ret) {
+        mpp_err_f("init vepu buffer failed ret: %d\n", ret);
+        goto DONE;
+    }
+
+    p->regs_sets = mpp_malloc(HalVepu511RegSet, p->task_cnt);
+    if (NULL == p->regs_sets) {
+        ret = MPP_ERR_MALLOC;
+        mpp_err_f("init register buffer failed\n");
+        goto DONE;
+    }
+
+    p->amend_sets = mpp_malloc(HalH264eVepuStreamAmend, p->task_cnt);
+    if (NULL == p->amend_sets) {
+        ret = MPP_ERR_MALLOC;
+        mpp_err_f("init amend data failed\n");
+        goto DONE;
+    }
+
+    if (p->task_cnt > 1) {
+        p->prefix_sets = mpp_malloc(H264ePrefixNal, p->task_cnt);
+        if (NULL == p->prefix_sets) {
+            ret = MPP_ERR_MALLOC;
+            mpp_err_f("init amend data failed\n");
+            goto DONE;
+        }
+
+        p->slice_sets = mpp_malloc(H264eSlice, p->task_cnt);
+        if (NULL == p->slice_sets) {
+            ret = MPP_ERR_MALLOC;
+            mpp_err_f("init amend data failed\n");
+            goto DONE;
+        }
+
+        p->reorder = mpp_malloc(H264eReorderInfo, 1);
+        if (NULL == p->reorder) {
+            ret = MPP_ERR_MALLOC;
+            mpp_err_f("init amend data failed\n");
+            goto DONE;
+        }
+
+        p->marking = mpp_malloc(H264eMarkingInfo, 1);
+        if (NULL == p->marking) {
+            ret = MPP_ERR_MALLOC;
+            mpp_err_f("init amend data failed\n");
+            goto DONE;
+        }
+    }
+
+    p->poll_slice_max = 8;
+    p->poll_cfg_size = (sizeof(p->poll_cfgs) + sizeof(RK_S32) * p->poll_slice_max);
+    p->poll_cfgs = mpp_malloc_size(MppDevPollCfg, p->poll_cfg_size * p->task_cnt);
+    if (NULL == p->poll_cfgs) {
+        ret = MPP_ERR_MALLOC;
+        mpp_err_f("init poll cfg buffer failed\n");
+        goto DONE;
+    }
+
+    {   /* setup default hardware config */
+        MppEncHwCfg *hw = &cfg->cfg->hw;
+
+        hw->qp_delta_row_i  = 1;
+        hw->qp_delta_row    = 2;
+        hw->extra_buf       = 1;
+        hw->qbias_i         = 683;
+        hw->qbias_p         = 341;
+        hw->qbias_en        = 0;
+
+        memcpy(hw->aq_thrd_i, h264_aq_tthd_default, sizeof(hw->aq_thrd_i));
+        memcpy(hw->aq_thrd_p, h264_aq_tthd_default, sizeof(hw->aq_thrd_p));
+        memcpy(hw->aq_step_i, h264_I_aq_step_default, sizeof(hw->aq_step_i));
+        memcpy(hw->aq_step_p, h264_P_aq_step_default, sizeof(hw->aq_step_p));
+
+        for (i = 0; i < MPP_ARRAY_ELEMS(hw->mode_bias); i++)
+            hw->mode_bias[i] = 8;
+
+        hw->skip_sad  = 8;
+        hw->skip_bias = 8;
+    }
+
+    mpp_dev_multi_offset_init(&p->offsets, 24);
+    p->output_cb = cfg->output_cb;
+    cfg->cap_recn_out = 1;
+    for (i = 0; i < p->task_cnt; i++)
+        h264e_vepu_stream_amend_init(&p->amend_sets[i]);
+
+    // p->tune = vepu511_h264e_tune_init(p);
+
+DONE:
+    if (ret)
+        hal_h264e_vepu511_deinit(hal);
+
+    hal_h264e_dbg_func("leave %p\n", p);
+    return ret;
+}
+
+/*
+ * NOTE: recon / refer buffer is FBC data buffer.
+ * And FBC data require extra 16 lines space for hardware io.
+ */
+static void setup_hal_bufs(HalH264eVepu511Ctx *ctx)
+{
+    MppEncCfgSet *cfg = ctx->cfg;
+    MppEncPrepCfg *prep = &cfg->prep;
+    RK_S32 alignment_w = 64;
+    RK_S32 alignment_h = 16;
+    RK_S32 aligned_w = MPP_ALIGN(prep->width,  alignment_w);
+    RK_S32 aligned_h = MPP_ALIGN(prep->height, alignment_h) + 16;
+    RK_S32 pixel_buf_fbc_hdr_size = MPP_ALIGN(aligned_w * aligned_h / 64, SZ_8K);
+    RK_S32 pixel_buf_fbc_bdy_size = aligned_w * aligned_h * 3 / 2;
+    RK_S32 pixel_buf_size = pixel_buf_fbc_hdr_size + pixel_buf_fbc_bdy_size;
+    RK_S32 thumb_buf_size = MPP_ALIGN(aligned_w / 64 * aligned_h / 64 * 256, SZ_8K);
+    RK_S32 old_max_cnt = ctx->max_buf_cnt;
+    RK_S32 new_max_cnt = 4;
+    MppEncRefCfg ref_cfg = cfg->ref_cfg;
+
+    if (ref_cfg) {
+        MppEncCpbInfo *info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
+        if (new_max_cnt < MPP_MAX(new_max_cnt, info->dpb_size + 1))
+            new_max_cnt = MPP_MAX(new_max_cnt, info->dpb_size + 1);
+    }
+
+    if (aligned_w > SZ_4K) {
+        RK_S32 ctu_w = (aligned_w + 63) / 64;
+        RK_S32 ext_line_buf_size = ((ctu_w - 53) * 53 + 15) / 16 * 16 * 16;
+
+        if (NULL == ctx->ext_line_buf_grp)
+            mpp_buffer_group_get_internal(&ctx->ext_line_buf_grp, MPP_BUFFER_TYPE_ION);
+        else if (ext_line_buf_size != ctx->ext_line_buf_size) {
+            clear_ext_line_bufs(ctx);
+            mpp_buffer_group_clear(ctx->ext_line_buf_grp);
+        }
+
+        mpp_assert(ctx->ext_line_buf_grp);
+
+        ctx->ext_line_buf_size = ext_line_buf_size;
+        setup_ext_line_bufs(ctx);
+    } else {
+        clear_ext_line_bufs(ctx);
+        if (ctx->ext_line_buf_grp) {
+            mpp_buffer_group_clear(ctx->ext_line_buf_grp);
+            mpp_buffer_group_put(ctx->ext_line_buf_grp);
+            ctx->ext_line_buf_grp = NULL;
+        }
+        ctx->ext_line_buf_size = 0;
+    }
+
+    if ((ctx->pixel_buf_fbc_hdr_size != pixel_buf_fbc_hdr_size) ||
+        (ctx->pixel_buf_fbc_bdy_size != pixel_buf_fbc_bdy_size) ||
+        (ctx->pixel_buf_size != pixel_buf_size) ||
+        (ctx->thumb_buf_size != thumb_buf_size) ||
+        (new_max_cnt > old_max_cnt)) {
+        size_t sizes[3];
+
+        hal_h264e_dbg_detail("frame size %d -> %d max count %d -> %d\n",
+                             ctx->pixel_buf_size, pixel_buf_size,
+                             old_max_cnt, new_max_cnt);
+
+        /* pixel buffer */
+        sizes[0] = pixel_buf_size;
+        /* thumb buffer */
+        sizes[1] = thumb_buf_size;
+        /* smear buffer */
+        sizes[2] = MPP_ALIGN(aligned_w / 64, 16) * MPP_ALIGN(aligned_h / 16, 16);
+        new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt);
+
+        hal_bufs_setup(ctx->hw_recn, new_max_cnt, MPP_ARRAY_ELEMS(sizes), sizes);
+
+        ctx->pixel_buf_fbc_hdr_size = pixel_buf_fbc_hdr_size;
+        ctx->pixel_buf_fbc_bdy_size = pixel_buf_fbc_bdy_size;
+        ctx->pixel_buf_size = pixel_buf_size;
+        ctx->thumb_buf_size = thumb_buf_size;
+        ctx->max_buf_cnt = new_max_cnt;
+    }
+}
+
+static MPP_RET hal_h264e_vepu511_prepare(void *hal)
+{
+    HalH264eVepu511Ctx *ctx = (HalH264eVepu511Ctx *)hal;
+    MppEncPrepCfg *prep = &ctx->cfg->prep;
+
+    hal_h264e_dbg_func("enter %p\n", hal);
+
+    if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
+        RK_S32 i;
+
+        // pre-alloc required buffers to reduce first frame delay
+        setup_hal_bufs(ctx);
+        for (i = 0; i < ctx->max_buf_cnt; i++)
+            hal_bufs_get_buf(ctx->hw_recn, i);
+
+        prep->change = 0;
+    }
+
+    hal_h264e_dbg_func("leave %p\n", hal);
+
+    return MPP_OK;
+}
+
+static RK_U32 update_vepu511_syntax(HalH264eVepu511Ctx *ctx, MppSyntax *syntax)
+{
+    H264eSyntaxDesc *desc = syntax->data;
+    RK_S32 syn_num = syntax->number;
+    RK_U32 updated = 0;
+    RK_S32 i;
+
+    for (i = 0; i < syn_num; i++, desc++) {
+        switch (desc->type) {
+        case H264E_SYN_CFG : {
+            hal_h264e_dbg_detail("update cfg");
+            ctx->cfg = desc->p;
+        } break;
+        case H264E_SYN_SPS : {
+            hal_h264e_dbg_detail("update sps");
+            ctx->sps = desc->p;
+        } break;
+        case H264E_SYN_PPS : {
+            hal_h264e_dbg_detail("update pps");
+            ctx->pps = desc->p;
+        } break;
+        case H264E_SYN_DPB : {
+            hal_h264e_dbg_detail("update dpb");
+            ctx->dpb = desc->p;
+        } break;
+        case H264E_SYN_SLICE : {
+            hal_h264e_dbg_detail("update slice");
+            ctx->slice = desc->p;
+        } break;
+        case H264E_SYN_FRAME : {
+            hal_h264e_dbg_detail("update frames");
+            ctx->frms = desc->p;
+        } break;
+        case H264E_SYN_PREFIX : {
+            hal_h264e_dbg_detail("update prefix nal");
+            ctx->prefix = desc->p;
+        } break;
+        default : {
+            mpp_log_f("invalid syntax type %d\n", desc->type);
+        } break;
+        }
+
+        updated |= SYN_TYPE_FLAG(desc->type);
+    }
+
+    return updated;
+}
+
+static MPP_RET hal_h264e_vepu511_get_task(void *hal, HalEncTask *task)
+{
+    HalH264eVepu511Ctx *ctx = (HalH264eVepu511Ctx *)hal;
+    MppEncCfgSet *cfg_set = ctx->cfg;
+    MppEncRefCfgImpl *ref = (MppEncRefCfgImpl *)cfg_set->ref_cfg;
+    MppEncH264HwCfg *hw_cfg = &cfg_set->codec.h264.hw_cfg;
+    RK_U32 updated = update_vepu511_syntax(ctx, &task->syntax);
+    EncFrmStatus *frm_status = &task->rc_task->frm;
+    H264eFrmInfo *frms = ctx->frms;
+
+    hal_h264e_dbg_func("enter %p\n", hal);
+
+    ctx->smart_en = (ctx->cfg->rc.rc_mode == MPP_ENC_RC_MODE_SMTRC);
+    ctx->qpmap_en = ctx->cfg->tune.deblur_en;
+
+    if (updated & SYN_TYPE_FLAG(H264E_SYN_CFG))
+        setup_hal_bufs(ctx);
+
+    if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
+        MppMeta meta = mpp_frame_get_meta(task->frame);
+        mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
+        mpp_meta_get_ptr_d(meta, KEY_OSD_DATA3, (void **)&ctx->osd_cfg.osd_data3, NULL);
+    }
+
+    if (!frm_status->reencode)
+        ctx->last_frame_fb = ctx->feedback;
+
+    if (ctx->dpb) {
+        h264e_dpb_hal_start(ctx->dpb, frms->curr_idx);
+        h264e_dpb_hal_start(ctx->dpb, frms->refr_idx);
+    }
+
+    task->flags.reg_idx = ctx->task_idx;
+    task->flags.curr_idx = frms->curr_idx;
+    task->flags.refr_idx = frms->refr_idx;
+    task->part_first = 1;
+    task->part_last = 0;
+
+    ctx->ext_line_buf = ctx->ext_line_bufs[ctx->task_idx];
+    ctx->regs_set = &ctx->regs_sets[ctx->task_idx];
+    ctx->amend = &ctx->amend_sets[ctx->task_idx];
+
+    /* if not VEPU1/2, update log2_max_frame_num_minus4 in hw_cfg */
+    hw_cfg->hw_log2_max_frame_num_minus4 = ctx->sps->log2_max_frame_num_minus4;
+
+    if (ctx->task_cnt > 1 && (ref->lt_cfg_cnt || ref->st_cfg_cnt > 1)) {
+        H264ePrefixNal *prefix = &ctx->prefix_sets[ctx->task_idx];
+        H264eSlice *slice = &ctx->slice_sets[ctx->task_idx];
+
+        //store async encode TSVC info
+        if (ctx->prefix)
+            memcpy(prefix, ctx->prefix, sizeof(H264ePrefixNal));
+        else
+            prefix = NULL;
+
+        if (ctx->slice) {
+            memcpy(slice, ctx->slice, sizeof(H264eSlice));
+
+            /*
+             * Generally, reorder and marking are shared by dpb and slice.
+             * However, async encoding TSVC will change reorder and marking in each task.
+             * Therefore, malloc a special space for async encoding TSVC.
+             */
+            ctx->amend->reorder = ctx->reorder;
+            ctx->amend->marking = ctx->marking;
+        }
+
+        h264e_vepu_stream_amend_config(ctx->amend, task->packet, ctx->cfg,
+                                       slice, prefix);
+    } else {
+        h264e_vepu_stream_amend_config(ctx->amend, task->packet, ctx->cfg,
+                                       ctx->slice, ctx->prefix);
+    }
+
+    if (ctx->task_cnt > 1)
+        ctx->task_idx = !ctx->task_idx;
+
+    hal_h264e_dbg_func("leave %p\n", hal);
+
+    return MPP_OK;
+}
+
+static void setup_vepu511_normal(HalVepu511RegSet *regs)
+{
+    hal_h264e_dbg_func("enter\n");
+    /* reg000 VERSION is read only */
+
+    /* reg001 ENC_STRT */
+    regs->reg_ctl.enc_strt.lkt_num           = 0;
+    regs->reg_ctl.enc_strt.vepu_cmd          = 1;
+
+    regs->reg_ctl.opt_strg.cke                = 1;
+    regs->reg_ctl.opt_strg.resetn_hw_en       = 1;
+
+    /* reg002 ENC_CLR */
+    regs->reg_ctl.enc_clr.safe_clr           = 0;
+    regs->reg_ctl.enc_clr.force_clr          = 0;
+
+    /* reg004 INT_EN */
+    regs->reg_ctl.int_en.enc_done_en        = 1;
+    regs->reg_ctl.int_en.lkt_node_done_en   = 1;
+    regs->reg_ctl.int_en.sclr_done_en       = 1;
+    regs->reg_ctl.int_en.vslc_done_en       = 0;
+    regs->reg_ctl.int_en.vbsf_oflw_en       = 1;
+    regs->reg_ctl.int_en.vbuf_lens_en       = 1;
+    regs->reg_ctl.int_en.enc_err_en         = 1;
+
+    regs->reg_ctl.int_en.wdg_en             = 1;
+    regs->reg_ctl.int_en.vsrc_err_en        = 1;
+    regs->reg_ctl.int_en.wdg_en             = 1;
+    regs->reg_ctl.int_en.lkt_err_int_en     = 1;
+    regs->reg_ctl.int_en.lkt_err_stop_en    = 1;
+    regs->reg_ctl.int_en.lkt_force_stop_en  = 1;
+    regs->reg_ctl.int_en.jslc_done_en       = 1;
+    regs->reg_ctl.int_en.jbsf_oflw_en       = 1;
+    regs->reg_ctl.int_en.jbuf_lens_en       = 1;
+    regs->reg_ctl.int_en.dvbm_err_en        = 0;
+
+    /* reg005 INT_MSK */
+    regs->reg_ctl.int_msk.enc_done_msk        = 0;
+    regs->reg_ctl.int_msk.lkt_node_done_msk   = 0;
+    regs->reg_ctl.int_msk.sclr_done_msk       = 0;
+    regs->reg_ctl.int_msk.vslc_done_msk       = 0;
+    regs->reg_ctl.int_msk.vbsf_oflw_msk       = 0;
+    regs->reg_ctl.int_msk.vbuf_lens_msk       = 0;
+    regs->reg_ctl.int_msk.enc_err_msk         = 0;
+    regs->reg_ctl.int_msk.vsrc_err_msk        = 0;
+    regs->reg_ctl.int_msk.wdg_msk             = 0;
+    regs->reg_ctl.int_msk.lkt_err_int_msk     = 0;
+    regs->reg_ctl.int_msk.lkt_err_stop_msk    = 0;
+    regs->reg_ctl.int_msk.lkt_force_stop_msk  = 0;
+    regs->reg_ctl.int_msk.jslc_done_msk       = 0;
+    regs->reg_ctl.int_msk.jbsf_oflw_msk       = 0;
+    regs->reg_ctl.int_msk.jbuf_lens_msk       = 0;
+    regs->reg_ctl.int_msk.dvbm_err_msk        = 0;
+
+    /* reg006 INT_CLR is not set */
+    /* reg007 INT_STA is read only */
+    /* reg008 ~ reg0011 gap */
+    regs->reg_ctl.enc_wdg.vs_load_thd       = 0;
+
+    /* reg015 DTRNS_MAP */
+    regs->reg_ctl.dtrns_map.jpeg_bus_edin      = 0;
+    regs->reg_ctl.dtrns_map.src_bus_edin       = 0;
+    regs->reg_ctl.dtrns_map.meiw_bus_edin      = 0;
+    regs->reg_ctl.dtrns_map.bsw_bus_edin       = 7;
+    regs->reg_ctl.dtrns_map.lktw_bus_edin      = 0;
+    regs->reg_ctl.dtrns_map.rec_nfbc_bus_edin  = 0;
+
+    regs->reg_ctl.dtrns_cfg.axi_brsp_cke   = 0;
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static MPP_RET setup_vepu511_prep(HalVepu511RegSet *regs, MppEncPrepCfg *prep, HalEncTask *task)
+{
+    H264eVepu511Frame *reg_frm = &regs->reg_frm;
+    VepuFmtCfg cfg;
+    MppFrameFormat fmt = prep->format;
+    MPP_RET ret = vepu541_set_fmt(&cfg, fmt);
+    RK_U32 hw_fmt = cfg.format;
+    RK_S32 y_stride;
+    RK_S32 c_stride;
+
+    hal_h264e_dbg_func("enter\n");
+
+    /* do nothing when color format is not supported */
+    if (ret)
+        return ret;
+
+    reg_frm->common.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1;
+    reg_frm->common.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width;
+    reg_frm->common.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1;
+    reg_frm->common.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height;
+
+    regs->reg_ctl.dtrns_map.src_bus_edin = cfg.src_endian;
+
+    reg_frm->common.src_fmt.src_cfmt   = hw_fmt;
+    reg_frm->common.src_fmt.alpha_swap = cfg.alpha_swap;
+    reg_frm->common.src_fmt.rbuv_swap  = cfg.rbuv_swap;
+    reg_frm->common.src_fmt.out_fmt = ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400 ? 0 : 1);
+
+    if (MPP_FRAME_FMT_IS_FBC(fmt)) {
+        reg_frm->common.src_proc.rkfbcd_en = 1;
+
+        y_stride = mpp_frame_get_fbc_hdr_stride(task->frame);
+        if (!y_stride)
+            y_stride = MPP_ALIGN(prep->hor_stride, 64) >> 2;
+    } else if (prep->hor_stride) {
+        y_stride = prep->hor_stride;
+    } else {
+        if (hw_fmt == VEPU541_FMT_BGRA8888 )
+            y_stride = prep->width * 4;
+        else if (hw_fmt == VEPU541_FMT_BGR888 )
+            y_stride = prep->width * 3;
+        else if (hw_fmt == VEPU541_FMT_BGR565 ||
+                 hw_fmt == VEPU541_FMT_YUYV422 ||
+                 hw_fmt == VEPU541_FMT_UYVY422)
+            y_stride = prep->width * 2;
+        else
+            y_stride = prep->width;
+    }
+
+    switch (hw_fmt) {
+    case VEPU580_FMT_YUV444SP : {
+        c_stride = y_stride * 2;
+    } break;
+    case VEPU541_FMT_YUV422SP :
+    case VEPU541_FMT_YUV420SP :
+    case VEPU580_FMT_YUV444P : {
+        c_stride = y_stride;
+    } break;
+    default : {
+        c_stride = y_stride / 2;
+    } break;
+    }
+
+    if (hw_fmt < VEPU541_FMT_NONE) {
+        const VepuRgb2YuvCfg *cfg_coeffs = get_rgb2yuv_cfg(prep->range, prep->color);
+
+        hal_h264e_dbg_flow("input color range %d colorspace %d", prep->range, prep->color);
+
+        reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff;
+        reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff;
+        reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff;
+
+        reg_frm->common.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff;
+        reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff;
+        reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff;
+
+        reg_frm->common.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff;
+        reg_frm->common.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff;
+        reg_frm->common.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff;
+
+        reg_frm->common.src_udfo.csc_ofst_y  = cfg_coeffs->_2y.offset;
+        reg_frm->common.src_udfo.csc_ofst_u  = cfg_coeffs->_2u.offset;
+        reg_frm->common.src_udfo.csc_ofst_v  = cfg_coeffs->_2v.offset;
+
+        hal_h264e_dbg_flow("use color range %d colorspace %d", cfg_coeffs->dst_range, cfg_coeffs->color);
+    } else {
+        reg_frm->common.src_udfy.csc_wgt_b2y = cfg.weight[0];
+        reg_frm->common.src_udfy.csc_wgt_g2y = cfg.weight[1];
+        reg_frm->common.src_udfy.csc_wgt_r2y = cfg.weight[2];
+
+        reg_frm->common.src_udfu.csc_wgt_b2u = cfg.weight[3];
+        reg_frm->common.src_udfu.csc_wgt_g2u = cfg.weight[4];
+        reg_frm->common.src_udfu.csc_wgt_r2u = cfg.weight[5];
+
+        reg_frm->common.src_udfv.csc_wgt_b2v = cfg.weight[6];
+        reg_frm->common.src_udfv.csc_wgt_g2v = cfg.weight[7];
+        reg_frm->common.src_udfv.csc_wgt_r2v = cfg.weight[8];
+
+        reg_frm->common.src_udfo.csc_ofst_y  = cfg.offset[0];
+        reg_frm->common.src_udfo.csc_ofst_u  = cfg.offset[1];
+        reg_frm->common.src_udfo.csc_ofst_v  = cfg.offset[2];
+    }
+
+    reg_frm->common.src_strd0.src_strd0  = y_stride;
+    reg_frm->common.src_strd1.src_strd1  = c_stride;
+
+    reg_frm->common.src_proc.src_mirr    = prep->mirroring > 0;
+    reg_frm->common.src_proc.src_rot     = prep->rotation;
+
+    reg_frm->sli_cfg.mv_v_lmt_thd = 0;
+    reg_frm->sli_cfg.mv_v_lmt_en  = 0;
+
+    reg_frm->common.pic_ofst.pic_ofst_y  = 0;
+    reg_frm->common.pic_ofst.pic_ofst_x  = 0;
+
+    hal_h264e_dbg_func("leave\n");
+
+    return ret;
+}
+
+static MPP_RET vepu511_h264e_save_pass1_patch(HalVepu511RegSet *regs, HalH264eVepu511Ctx *ctx)
+{
+    H264eVepu511Frame *reg_frm = &regs->reg_frm;
+    RK_S32 width_align = MPP_ALIGN(ctx->cfg->prep.width, 16);
+    RK_S32 height_align = MPP_ALIGN(ctx->cfg->prep.height, 16);
+
+    if (NULL == ctx->buf_pass1) {
+        mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2);
+        if (!ctx->buf_pass1) {
+            mpp_err("buf_pass1 malloc fail, debreath invaild");
+            return MPP_NOK;
+        }
+    }
+
+    reg_frm->common.enc_pic.cur_frm_ref = 1;
+    reg_frm->common.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1);
+    reg_frm->common.rfpw_b_addr = reg_frm->common.rfpw_h_addr;
+    reg_frm->common.enc_pic.rec_fbc_dis = 1;
+
+    mpp_dev_multi_offset_update(ctx->offsets, 164, width_align * height_align);
+
+    /* NOTE: disable split to avoid lowdelay slice output */
+    reg_frm->common.sli_splt.sli_splt = 0;
+    reg_frm->common.enc_pic.slen_fifo = 0;
+
+    return MPP_OK;
+}
+
+static MPP_RET vepu511_h264e_use_pass1_patch(HalVepu511RegSet *regs, HalH264eVepu511Ctx *ctx)
+{
+    H264eVepu511Frame *reg_frm = &regs->reg_frm;
+    RK_S32 fd_in = mpp_buffer_get_fd(ctx->buf_pass1);
+    RK_S32 width_align = MPP_ALIGN(ctx->cfg->prep.width, 16);
+    RK_S32 height_align = MPP_ALIGN(ctx->cfg->prep.height, 16);
+    RK_S32 y_stride = width_align;
+
+    hal_h264e_dbg_func("enter\n");
+
+    reg_frm->common.enc_pic.rfpr_compress_mode = 1;
+    reg_frm->common.src_fmt.src_cfmt   = VEPU541_FMT_YUV420SP;
+    reg_frm->common.src_fmt.alpha_swap = 0;
+    reg_frm->common.src_fmt.rbuv_swap  = 0;
+    reg_frm->common.src_fmt.out_fmt    = 1;
+
+    reg_frm->common.src_strd0.src_strd0 = y_stride;
+    reg_frm->common.src_strd1.src_strd1 = y_stride;
+
+    reg_frm->common.src_proc.src_mirr   = 0;
+    reg_frm->common.src_proc.src_rot    = 0;
+
+    reg_frm->common.pic_ofst.pic_ofst_y = 0;
+    reg_frm->common.pic_ofst.pic_ofst_x = 0;
+
+    reg_frm->common.adr_src0   = fd_in;
+    reg_frm->common.adr_src1   = fd_in;
+
+    mpp_dev_multi_offset_update(ctx->offsets, 161, width_align * height_align);
+
+    hal_h264e_dbg_func("leave\n");
+    return MPP_OK;
+}
+
+static void setup_vepu511_codec(HalVepu511RegSet *regs, HalH264eVepu511Ctx *ctx)
+{
+    H264eVepu511Frame *reg_frm = &regs->reg_frm;
+    H264eSps *sps = ctx->sps;
+    H264ePps *pps = ctx->pps;
+    H264eSlice *slice = ctx->slice;
+
+    hal_h264e_dbg_func("enter\n");
+
+    reg_frm->common.enc_pic.enc_stnd       = 0;
+    reg_frm->common.enc_pic.cur_frm_ref    = slice->nal_reference_idc > 0;
+    reg_frm->common.enc_pic.bs_scp         = 1;
+
+    reg_frm->synt_nal.nal_ref_idc    = slice->nal_reference_idc;
+    reg_frm->synt_nal.nal_unit_type  = slice->nalu_type;
+
+    reg_frm->synt_sps.max_fnum       = sps->log2_max_frame_num_minus4;
+    reg_frm->synt_sps.drct_8x8       = sps->direct8x8_inference;
+    reg_frm->synt_sps.mpoc_lm4       = sps->log2_max_poc_lsb_minus4;
+
+    reg_frm->synt_pps.etpy_mode      = pps->entropy_coding_mode;
+    reg_frm->synt_pps.trns_8x8       = pps->transform_8x8_mode;
+    reg_frm->synt_pps.csip_flag      = pps->constrained_intra_pred;
+    reg_frm->synt_pps.num_ref0_idx   = pps->num_ref_idx_l0_default_active - 1;
+    reg_frm->synt_pps.num_ref1_idx   = pps->num_ref_idx_l1_default_active - 1;
+    reg_frm->synt_pps.pic_init_qp    = pps->pic_init_qp;
+    reg_frm->synt_pps.cb_ofst        = pps->chroma_qp_index_offset;
+    reg_frm->synt_pps.cr_ofst        = pps->second_chroma_qp_index_offset;
+    reg_frm->synt_pps.dbf_cp_flg     = pps->deblocking_filter_control;
+
+    reg_frm->synt_sli0.sli_type       = (slice->slice_type == H264_I_SLICE) ? (2) : (0);
+    reg_frm->synt_sli0.pps_id         = slice->pic_parameter_set_id;
+    reg_frm->synt_sli0.drct_smvp      = 0;
+    reg_frm->synt_sli0.num_ref_ovrd   = slice->num_ref_idx_override;
+    reg_frm->synt_sli0.cbc_init_idc   = slice->cabac_init_idc;
+    reg_frm->synt_sli0.frm_num        = slice->frame_num;
+
+    reg_frm->synt_sli1.idr_pid        = (slice->slice_type == H264_I_SLICE) ? slice->idr_pic_id : (RK_U32)(-1);
+    reg_frm->synt_sli1.poc_lsb        = slice->pic_order_cnt_lsb;
+
+    reg_frm->synt_sli2.dis_dblk_idc   = slice->disable_deblocking_filter_idc;
+    reg_frm->synt_sli2.sli_alph_ofst  = slice->slice_alpha_c0_offset_div2;
+
+    h264e_reorder_rd_rewind(slice->reorder);
+    {   /* reorder process */
+        H264eRplmo rplmo;
+        MPP_RET ret = h264e_reorder_rd_op(slice->reorder, &rplmo);
+
+        if (MPP_OK == ret) {
+            reg_frm->synt_sli2.ref_list0_rodr = 1;
+            reg_frm->synt_sli2.rodr_pic_idx   = rplmo.modification_of_pic_nums_idc;
+
+            switch (rplmo.modification_of_pic_nums_idc) {
+            case 0 :
+            case 1 : {
+                reg_frm->synt_sli2.rodr_pic_num   = rplmo.abs_diff_pic_num_minus1;
+            } break;
+            case 2 : {
+                reg_frm->synt_sli2.rodr_pic_num   = rplmo.long_term_pic_idx;
+            } break;
+            default : {
+                mpp_err_f("invalid modification_of_pic_nums_idc %d\n",
+                          rplmo.modification_of_pic_nums_idc);
+            } break;
+            }
+        } else {
+            // slice->ref_pic_list_modification_flag;
+            reg_frm->synt_sli2.ref_list0_rodr = 0;
+            reg_frm->synt_sli2.rodr_pic_idx   = 0;
+            reg_frm->synt_sli2.rodr_pic_num   = 0;
+        }
+    }
+
+    /* clear all mmco arg first */
+    reg_frm->synt_refm0.nopp_flg               = 0;
+    reg_frm->synt_refm0.ltrf_flg               = 0;
+    reg_frm->synt_refm0.arpm_flg               = 0;
+    reg_frm->synt_refm0.mmco4_pre              = 0;
+    reg_frm->synt_refm0.mmco_type0             = 0;
+    reg_frm->synt_refm0.mmco_parm0             = 0;
+    reg_frm->synt_refm0.mmco_type1             = 0;
+    reg_frm->synt_refm1.mmco_parm1             = 0;
+    reg_frm->synt_refm0.mmco_type2             = 0;
+    reg_frm->synt_refm1.mmco_parm2             = 0;
+    reg_frm->synt_refm2.long_term_frame_idx0   = 0;
+    reg_frm->synt_refm2.long_term_frame_idx1   = 0;
+    reg_frm->synt_refm2.long_term_frame_idx2   = 0;
+
+    h264e_marking_rd_rewind(slice->marking);
+
+    /* only update used parameter */
+    if (slice->slice_type == H264_I_SLICE) {
+        reg_frm->synt_refm0.nopp_flg       = slice->no_output_of_prior_pics;
+        reg_frm->synt_refm0.ltrf_flg       = slice->long_term_reference_flag;
+    } else {
+        if (!h264e_marking_is_empty(slice->marking)) {
+            H264eMmco mmco;
+
+            reg_frm->synt_refm0.arpm_flg       = 1;
+
+            /* max 3 mmco */
+            do {
+                RK_S32 type = 0;
+                RK_S32 param_0 = 0;
+                RK_S32 param_1 = 0;
+
+                h264e_marking_rd_op(slice->marking, &mmco);
+                type = mmco.mmco;
+                switch (type) {
+                case 1 : {
+                    param_0 = mmco.difference_of_pic_nums_minus1;
+                } break;
+                case 2 : {
+                    param_0 = mmco.long_term_pic_num;
+                } break;
+                case 3 : {
+                    param_0 = mmco.difference_of_pic_nums_minus1;
+                    param_1 = mmco.long_term_frame_idx;
+                } break;
+                case 4 : {
+                    param_0 = mmco.max_long_term_frame_idx_plus1;
+                } break;
+                case 5 : {
+                } break;
+                case 6 : {
+                    param_0 = mmco.long_term_frame_idx;
+                } break;
+                default : {
+                    mpp_err_f("unsupported mmco 0 %d\n", type);
+                    type = 0;
+                } break;
+                }
+
+                reg_frm->synt_refm0.mmco_type0 = type;
+                reg_frm->synt_refm0.mmco_parm0 = param_0;
+                reg_frm->synt_refm2.long_term_frame_idx0 = param_1;
+
+                if (h264e_marking_is_empty(slice->marking))
+                    break;
+
+                h264e_marking_rd_op(slice->marking, &mmco);
+                type = mmco.mmco;
+                param_0 = 0;
+                param_1 = 0;
+                switch (type) {
+                case 1 : {
+                    param_0 = mmco.difference_of_pic_nums_minus1;
+                } break;
+                case 2 : {
+                    param_0 = mmco.long_term_pic_num;
+                } break;
+                case 3 : {
+                    param_0 = mmco.difference_of_pic_nums_minus1;
+                    param_1 = mmco.long_term_frame_idx;
+                } break;
+                case 4 : {
+                    param_0 = mmco.max_long_term_frame_idx_plus1;
+                } break;
+                case 5 : {
+                } break;
+                case 6 : {
+                    param_0 = mmco.long_term_frame_idx;
+                } break;
+                default : {
+                    mpp_err_f("unsupported mmco 0 %d\n", type);
+                    type = 0;
+                } break;
+                }
+
+                reg_frm->synt_refm0.mmco_type1 = type;
+                reg_frm->synt_refm1.mmco_parm1 = param_0;
+                reg_frm->synt_refm2.long_term_frame_idx1 = param_1;
+
+                if (h264e_marking_is_empty(slice->marking))
+                    break;
+
+                h264e_marking_rd_op(slice->marking, &mmco);
+                type = mmco.mmco;
+                param_0 = 0;
+                param_1 = 0;
+                switch (type) {
+                case 1 : {
+                    param_0 = mmco.difference_of_pic_nums_minus1;
+                } break;
+                case 2 : {
+                    param_0 = mmco.long_term_pic_num;
+                } break;
+                case 3 : {
+                    param_0 = mmco.difference_of_pic_nums_minus1;
+                    param_1 = mmco.long_term_frame_idx;
+                } break;
+                case 4 : {
+                    param_0 = mmco.max_long_term_frame_idx_plus1;
+                } break;
+                case 5 : {
+                } break;
+                case 6 : {
+                    param_0 = mmco.long_term_frame_idx;
+                } break;
+                default : {
+                    mpp_err_f("unsupported mmco 0 %d\n", type);
+                    type = 0;
+                } break;
+                }
+
+                reg_frm->synt_refm0.mmco_type2 = type;
+                reg_frm->synt_refm1.mmco_parm2 = param_0;
+                reg_frm->synt_refm2.long_term_frame_idx2 = param_1;
+            } while (0);
+        }
+    }
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static void setup_vepu511_rdo_pred(HalH264eVepu511Ctx *ctx)
+{
+    HalVepu511RegSet *regs = ctx->regs_set;
+    H264eVepu511Frame *reg_frm = &regs->reg_frm;
+    H264eSps *sps = ctx->sps;
+    H264ePps *pps = ctx->pps;
+    H264eSlice *slice = ctx->slice;
+    RK_U32 is_ipc_scene = (ctx->cfg->tune.scene_mode == MPP_ENC_SCENE_MODE_IPC);
+
+    hal_h264e_dbg_func("enter\n");
+
+    if (slice->slice_type == H264_I_SLICE) {
+        regs->reg_rc_roi.klut_ofst.chrm_klut_ofst = 6;
+        reg_frm->rdo_mark_mode.iframe_i4_rdo_num = 1;
+        reg_frm->rdo_mark_mode.i8_rdo_num = 1;
+        reg_frm->rdo_mark_mode.iframe_i16_rdo_num = 2;
+        reg_frm->rdo_mark_mode.rdo_mark_mode = 0;
+    } else {
+        regs->reg_rc_roi.klut_ofst.chrm_klut_ofst = is_ipc_scene ? 9 : 6;
+        reg_frm->rdo_mark_mode.p16_interp_num = 2;
+        reg_frm->rdo_mark_mode.p16t8_rdo_num = 2;
+        reg_frm->rdo_mark_mode.p16t4_rmd_num = 2;
+        reg_frm->rdo_mark_mode.rdo_mark_mode = 0;
+        reg_frm->rdo_mark_mode.p8_interp_num = 3;
+        reg_frm->rdo_mark_mode.p8t8_rdo_num = 2;
+        reg_frm->rdo_mark_mode.p8t4_rmd_num = 2;
+        regs->reg_frm.rdo_mark_mode.i8_rdo_num = 1;
+        regs->reg_frm.rdo_mark_mode.iframe_i4_rdo_num = 1;
+        regs->reg_frm.rdo_mark_mode.iframe_i16_rdo_num = 1;
+    }
+
+    reg_frm->rdo_cfg.rect_size      = (sps->profile_idc == H264_PROFILE_BASELINE &&
+                                       sps->level_idc <= H264_LEVEL_3_0) ? 1 : 0;
+    reg_frm->rdo_cfg.vlc_lmt        = (sps->profile_idc < H264_PROFILE_MAIN) &&
+                                      !pps->entropy_coding_mode;
+    reg_frm->rdo_cfg.ccwa_e         = 1;
+    reg_frm->rdo_cfg.scl_lst_sel    = pps->pic_scaling_matrix_present;
+    reg_frm->rdo_cfg.atf_e          = ctx->cfg->tune.anti_flicker_str > 0;
+    reg_frm->rdo_cfg.atr_e          = ctx->cfg->tune.atr_str_i > 0;
+    reg_frm->rdo_cfg.atr_mult_sel_e = 1;
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static void setup_vepu511_rc_base(HalVepu511RegSet *regs, HalH264eVepu511Ctx *ctx, EncRcTask *rc_task)
+{
+    H264eSps *sps = ctx->sps;
+    H264eSlice *slice = ctx->slice;
+    MppEncCfgSet *cfg = ctx->cfg;
+    MppEncRcCfg *rc = &cfg->rc;
+    MppEncHwCfg *hw = &cfg->hw;
+    EncRcTaskInfo *rc_info = &rc_task->info;
+    H264eVepu511Frame *reg_frm = &regs->reg_frm;
+    RK_S32 mb_w = sps->pic_width_in_mbs;
+    RK_S32 mb_h = sps->pic_height_in_mbs;
+    RK_U32 qp_target = rc_info->quality_target;
+    RK_U32 qp_min = rc_info->quality_min;
+    RK_U32 qp_max = rc_info->quality_max;
+    RK_S32 mb_target_bits_mul_16 = (rc_info->bit_target << 4) / (mb_w * mb_h);
+    RK_S32 mb_target_bits;
+    RK_S32 negative_bits_thd;
+    RK_S32 positive_bits_thd;
+
+    hal_h264e_dbg_rc("bittarget %d qp [%d %d %d]\n", rc_info->bit_target,
+                     qp_min, qp_target, qp_max);
+
+    hal_h264e_dbg_func("enter\n");
+
+    regs->reg_rc_roi.roi_qthd0.qpmin_area0    = qp_min;
+    regs->reg_rc_roi.roi_qthd0.qpmax_area0    = qp_max;
+    regs->reg_rc_roi.roi_qthd0.qpmin_area1    = qp_min;
+    regs->reg_rc_roi.roi_qthd0.qpmax_area1    = qp_max;
+    regs->reg_rc_roi.roi_qthd0.qpmin_area2    = qp_min;
+
+    regs->reg_rc_roi.roi_qthd1.qpmax_area2    = qp_max;
+    regs->reg_rc_roi.roi_qthd1.qpmin_area3    = qp_min;
+    regs->reg_rc_roi.roi_qthd1.qpmax_area3    = qp_max;
+    regs->reg_rc_roi.roi_qthd1.qpmin_area4    = qp_min;
+    regs->reg_rc_roi.roi_qthd1.qpmax_area4    = qp_max;
+
+    regs->reg_rc_roi.roi_qthd2.qpmin_area5    = qp_min;
+    regs->reg_rc_roi.roi_qthd2.qpmax_area5    = qp_max;
+    regs->reg_rc_roi.roi_qthd2.qpmin_area6    = qp_min;
+    regs->reg_rc_roi.roi_qthd2.qpmax_area6    = qp_max;
+    regs->reg_rc_roi.roi_qthd2.qpmin_area7    = qp_min;
+    regs->reg_rc_roi.roi_qthd3.qpmax_area7    = qp_max;
+
+    if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) {
+        reg_frm->common.enc_pic.pic_qp    = rc_info->quality_target;
+        reg_frm->common.rc_qp.rc_max_qp   = rc_info->quality_target;
+        reg_frm->common.rc_qp.rc_min_qp   = rc_info->quality_target;
+
+        return;
+    }
+
+    if (mb_target_bits_mul_16 >= 0x100000)
+        mb_target_bits_mul_16 = 0x50000;
+
+    mb_target_bits = (mb_target_bits_mul_16 * mb_w) >> 4;
+    negative_bits_thd = 0 - 5 * mb_target_bits / 16;
+    positive_bits_thd = 5 * mb_target_bits / 16;
+
+    reg_frm->common.enc_pic.pic_qp         = qp_target;
+
+    reg_frm->common.rc_cfg.rc_en          = 1;
+    reg_frm->common.rc_cfg.aq_en          = 1;
+    reg_frm->common.rc_cfg.rc_ctu_num     = mb_w;
+
+    reg_frm->common.rc_qp.rc_max_qp       = qp_max;
+    reg_frm->common.rc_qp.rc_min_qp       = qp_min;
+    reg_frm->common.rc_tgt.ctu_ebit       = mb_target_bits_mul_16;
+
+    if (rc->rc_mode == MPP_ENC_RC_MODE_SMTRC) {
+        reg_frm->common.rc_qp.rc_qp_range = 0;
+    } else {
+        reg_frm->common.rc_qp.rc_qp_range = (slice->slice_type == H264_I_SLICE) ?
+                                            hw->qp_delta_row_i : hw->qp_delta_row;
+    }
+
+    {
+        /* fixed frame level QP */
+        RK_S32 fqp_min, fqp_max;
+
+        if (slice->slice_type == H264_I_SLICE) {
+            fqp_min = rc->fqp_min_i;
+            fqp_max = rc->fqp_max_i;
+        } else {
+            fqp_min = rc->fqp_min_p;
+            fqp_max = rc->fqp_max_p;
+        }
+
+        if ((fqp_min == fqp_max) && (fqp_min >= 1) && (fqp_max <= 51)) {
+            reg_frm->common.enc_pic.pic_qp = fqp_min;
+            reg_frm->common.rc_qp.rc_qp_range = 0;
+        }
+    }
+
+    regs->reg_rc_roi.rc_adj0.qp_adj0        = -2;
+    regs->reg_rc_roi.rc_adj0.qp_adj1        = -1;
+    regs->reg_rc_roi.rc_adj0.qp_adj2        = 0;
+    regs->reg_rc_roi.rc_adj0.qp_adj3        = 1;
+    regs->reg_rc_roi.rc_adj0.qp_adj4        = 2;
+    regs->reg_rc_roi.rc_adj1.qp_adj5        = 0;
+    regs->reg_rc_roi.rc_adj1.qp_adj6        = 0;
+    regs->reg_rc_roi.rc_adj1.qp_adj7        = 0;
+    regs->reg_rc_roi.rc_adj1.qp_adj8        = 0;
+
+    regs->reg_rc_roi.rc_dthd_0_8[0] = 4 * negative_bits_thd;
+    regs->reg_rc_roi.rc_dthd_0_8[1] = negative_bits_thd;
+    regs->reg_rc_roi.rc_dthd_0_8[2] = positive_bits_thd;
+    regs->reg_rc_roi.rc_dthd_0_8[3] = 4 * positive_bits_thd;
+    regs->reg_rc_roi.rc_dthd_0_8[4] = 0x7FFFFFFF;
+    regs->reg_rc_roi.rc_dthd_0_8[5] = 0x7FFFFFFF;
+    regs->reg_rc_roi.rc_dthd_0_8[6] = 0x7FFFFFFF;
+    regs->reg_rc_roi.rc_dthd_0_8[7] = 0x7FFFFFFF;
+    regs->reg_rc_roi.rc_dthd_0_8[8] = 0x7FFFFFFF;
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static void setup_vepu511_io_buf(HalVepu511RegSet *regs, MppDevRegOffCfgs *offsets,
+                                 HalEncTask *task)
+{
+    MppFrame frm = task->frame;
+    MppPacket pkt = task->packet;
+    MppBuffer buf_in = mpp_frame_get_buffer(frm);
+    MppBuffer buf_out = task->output;
+    MppFrameFormat fmt = mpp_frame_get_fmt(frm);
+    H264eVepu511Frame *reg_frm = &regs->reg_frm;
+    RK_S32 hor_stride = mpp_frame_get_hor_stride(frm);
+    RK_S32 ver_stride = mpp_frame_get_ver_stride(frm);
+    RK_S32 fd_in = mpp_buffer_get_fd(buf_in);
+    RK_U32 off_in[2] = {0};
+    RK_U32 off_out = mpp_packet_get_length(pkt);
+    size_t siz_out = mpp_buffer_get_size(buf_out);
+    RK_S32 fd_out = mpp_buffer_get_fd(buf_out);
+
+    hal_h264e_dbg_func("enter\n");
+
+    reg_frm->common.adr_src0   = fd_in;
+    reg_frm->common.adr_src1   = fd_in;
+    reg_frm->common.adr_src2   = fd_in;
+
+    reg_frm->common.bsbt_addr  = fd_out;
+    reg_frm->common.bsbb_addr  = fd_out;
+    reg_frm->common.adr_bsbs   = fd_out;
+    reg_frm->common.bsbr_addr  = fd_out;
+
+    reg_frm->common.rfpt_h_addr = 0xffffffff;
+    reg_frm->common.rfpb_h_addr = 0;
+    reg_frm->common.rfpt_b_addr = 0xffffffff;
+    reg_frm->common.adr_rfpb_b  = 0;
+
+    if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(task->frame))) {
+        off_in[0] = mpp_frame_get_fbc_offset(task->frame);;
+        off_in[1] = off_in[0];
+    } else if (MPP_FRAME_FMT_IS_YUV(fmt)) {
+        VepuFmtCfg cfg;
+
+        vepu541_set_fmt(&cfg, fmt);
+        switch (cfg.format) {
+        case VEPU541_FMT_BGRA8888 :
+        case VEPU541_FMT_BGR888 :
+        case VEPU541_FMT_BGR565 : {
+            off_in[0] = 0;
+            off_in[1] = 0;
+        } break;
+        case VEPU541_FMT_YUV420SP :
+        case VEPU541_FMT_YUV422SP : {
+            off_in[0] = hor_stride * ver_stride;
+            off_in[1] = hor_stride * ver_stride;
+        } break;
+        case VEPU541_FMT_YUV422P : {
+            off_in[0] = hor_stride * ver_stride;
+            off_in[1] = hor_stride * ver_stride * 3 / 2;
+        } break;
+        case VEPU541_FMT_YUV420P : {
+            off_in[0] = hor_stride * ver_stride;
+            off_in[1] = hor_stride * ver_stride * 5 / 4;
+        } break;
+        case VEPU540_FMT_YUV400 :
+        case VEPU541_FMT_YUYV422 :
+        case VEPU541_FMT_UYVY422 : {
+            off_in[0] = 0;
+            off_in[1] = 0;
+        } break;
+        case VEPU580_FMT_YUV444SP : {
+            off_in[0] = hor_stride * ver_stride;
+            off_in[1] = hor_stride * ver_stride;
+        } break;
+        case VEPU580_FMT_YUV444P : {
+            off_in[0] = hor_stride * ver_stride;
+            off_in[1] = hor_stride * ver_stride * 2;
+        } break;
+        case VEPU541_FMT_NONE :
+        default : {
+            off_in[0] = 0;
+            off_in[1] = 0;
+        } break;
+        }
+    }
+
+    mpp_dev_multi_offset_update(offsets, 161, off_in[0]);
+    mpp_dev_multi_offset_update(offsets, 162, off_in[1]);
+    mpp_dev_multi_offset_update(offsets, 172, siz_out);
+    mpp_dev_multi_offset_update(offsets, 174, off_out);
+
+    reg_frm->common.meiw_addr = task->md_info ? mpp_buffer_get_fd(task->md_info) : 0;
+    reg_frm->common.enc_pic.mei_stor = 0;
+    reg_frm->common.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
+    reg_frm->common.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static MPP_RET vepu511_h264_set_one_roi(void *buf, MppEncROIRegion *region, RK_S32 w, RK_S32 h)
+{
+    Vepu511RoiH264BsCfg *ptr = (Vepu511RoiH264BsCfg *)buf;
+    RK_S32 mb_w = MPP_ALIGN(w, 16) / 16;
+    RK_S32 mb_h = MPP_ALIGN(h, 16) / 16;
+    RK_S32 stride_h = MPP_ALIGN(mb_w, 4);
+    Vepu511RoiH264BsCfg cfg;
+    MPP_RET ret = MPP_NOK;
+
+    if (NULL == buf || NULL == region) {
+        mpp_err_f("invalid buf %p roi %p\n", buf, region);
+        goto DONE;
+    }
+
+    RK_S32 roi_width  = (region->w + 15) / 16;
+    RK_S32 roi_height = (region->h + 15) / 16;
+    RK_S32 pos_x_init = region->x / 16;
+    RK_S32 pos_y_init = region->y / 16;
+    RK_S32 pos_x_end  = pos_x_init + roi_width;
+    RK_S32 pos_y_end  = pos_y_init + roi_height;
+    RK_S32 x, y;
+
+    pos_x_end = MPP_MIN(pos_x_end, mb_w);
+    pos_y_end = MPP_MIN(pos_y_end, mb_h);
+    pos_x_init = MPP_MAX(pos_x_init, 0);
+    pos_y_init = MPP_MAX(pos_y_init, 0);
+
+    mpp_assert(pos_x_end > pos_x_init);
+    mpp_assert(pos_y_end > pos_y_init);
+
+    cfg.force_intra = 1;
+
+    ptr += pos_y_init * stride_h + pos_x_init;
+    roi_width = pos_x_end - pos_x_init;
+    roi_height = pos_y_end - pos_y_init;
+
+    for (y = 0; y < roi_height; y++) {
+        Vepu511RoiH264BsCfg *dst = ptr;
+
+        for (x = 0; x < roi_width; x++, dst++)
+            memcpy(dst, &cfg, sizeof(cfg));
+
+        ptr += stride_h;
+    }
+DONE:
+    return ret;
+}
+
+static MPP_RET setup_vepu511_intra_refresh(HalVepu511RegSet *regs, HalH264eVepu511Ctx *ctx, RK_U32 refresh_idx)
+{
+    MPP_RET ret = MPP_OK;
+    RK_U32 mb_w = ctx->sps->pic_width_in_mbs;
+    RK_U32 mb_h = ctx->sps->pic_height_in_mbs;
+    RK_U32 w = mb_w * 16;
+    RK_U32 h = mb_h * 16;
+    MppEncROIRegion *region = NULL;
+    H264eVepu511Frame *reg_frm = &regs->reg_frm;
+    RK_U32 refresh_num = ctx->cfg->rc.refresh_num;
+    RK_U32 stride_h = MPP_ALIGN(mb_w, 4);
+    RK_U32 stride_v = MPP_ALIGN(mb_h, 4);
+    RK_U32 roi_base_buf_size = stride_h * stride_v * 8;
+    RK_U32 i = 0;
+
+    hal_h264e_dbg_func("enter\n");
+
+    if (!ctx->cfg->rc.refresh_en) {
+        ret = MPP_ERR_VALUE;
+        goto RET;
+    }
+
+    if (NULL == ctx->roi_base_cfg_buf) {
+        if (NULL == ctx->roi_grp)
+            mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
+        mpp_buffer_get(ctx->roi_grp, &ctx->roi_base_cfg_buf, roi_base_buf_size);
+        ctx->roi_base_buf_size = roi_base_buf_size;
+    }
+
+    mpp_assert(ctx->roi_base_cfg_buf);
+    void *base_cfg_buf = mpp_buffer_get_ptr(ctx->roi_base_cfg_buf);
+    Vepu511RoiH264BsCfg base_cfg;
+    Vepu511RoiH264BsCfg *base_cfg_ptr = (Vepu511RoiH264BsCfg *)base_cfg_buf;
+
+    base_cfg.force_intra = 0;
+    base_cfg.qp_adj_en   = 1;
+
+    for (i = 0; i < stride_h * stride_v; i++, base_cfg_ptr++)
+        memcpy(base_cfg_ptr, &base_cfg, sizeof(base_cfg));
+
+    region = mpp_calloc(MppEncROIRegion, 1);
+
+    if (NULL == region) {
+        mpp_err_f("Failed to calloc for MppEncROIRegion !\n");
+        ret = MPP_ERR_MALLOC;
+    }
+
+    if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_ROW) {
+        region->x = 0;
+        region->w = w;
+        if (refresh_idx > 0) {
+            region->y = refresh_idx * 16 * refresh_num - 32;
+            region->h = 16 * refresh_num + 32;
+        } else {
+            region->y = refresh_idx * 16 * refresh_num;
+            region->h = 16 * refresh_num;
+        }
+        reg_frm->common.me_rnge.cime_srch_uph = 1;
+    } else if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_COL) {
+        region->y = 0;
+        region->h = h;
+        if (refresh_idx > 0) {
+            region->x = refresh_idx * 16 * refresh_num - 32;
+            region->w = 16 * refresh_num + 32;
+        } else {
+            region->x = refresh_idx * 16 * refresh_num;
+            region->w = 16 * refresh_num;
+        }
+        reg_frm->common.me_rnge.cime_srch_dwnh = 1;
+    }
+
+    region->intra = 1;
+    region->quality = -ctx->cfg->rc.qp_delta_ip;
+
+    region->area_map_en = 1;
+    region->qp_area_idx = 1;
+    region->abs_qp_en = 0;
+
+    vepu511_h264_set_one_roi(base_cfg_buf, region, w, h);
+    mpp_free(region);
+RET:
+    hal_h264e_dbg_func("leave, ret %d\n", ret);
+    return ret;
+}
+
+static void setup_vepu511_recn_refr(HalH264eVepu511Ctx *ctx, HalVepu511RegSet *regs)
+{
+
+    H264eVepu511Frame *reg_frm = &regs->reg_frm;
+    H264eFrmInfo *frms = ctx->frms;
+    HalBufs bufs = ctx->hw_recn;
+    RK_S32 fbc_hdr_size = ctx->pixel_buf_fbc_hdr_size;
+
+    HalBuf *curr = hal_bufs_get_buf(bufs, frms->curr_idx);
+    HalBuf *refr = hal_bufs_get_buf(bufs, frms->refr_idx);
+
+    hal_h264e_dbg_func("enter\n");
+
+    if (curr && curr->cnt) {
+        MppBuffer buf_pixel = curr->buf[0];
+        MppBuffer buf_thumb = curr->buf[1];
+        MppBuffer buf_smear = curr->buf[2];
+        RK_S32 fd = mpp_buffer_get_fd(buf_pixel);
+
+        mpp_assert(buf_pixel);
+        mpp_assert(buf_thumb);
+
+        reg_frm->common.rfpw_h_addr = fd;
+        reg_frm->common.rfpw_b_addr = fd;
+        reg_frm->common.dspw_addr = mpp_buffer_get_fd(buf_thumb);
+        reg_frm->common.adr_smear_wr = mpp_buffer_get_fd(buf_smear);
+    }
+
+    if (refr && refr->cnt) {
+        MppBuffer buf_pixel = refr->buf[0];
+        MppBuffer buf_thumb = refr->buf[1];
+        MppBuffer buf_smear = curr->buf[2];
+        RK_S32 fd = mpp_buffer_get_fd(buf_pixel);
+
+        mpp_assert(buf_pixel);
+        mpp_assert(buf_thumb);
+
+        reg_frm->common.rfpr_h_addr = fd;
+        reg_frm->common.rfpr_b_addr = fd;
+        reg_frm->common.dspr_addr = mpp_buffer_get_fd(buf_thumb);
+        reg_frm->common.adr_smear_rd = mpp_buffer_get_fd(buf_smear);
+    }
+    mpp_dev_multi_offset_update(ctx->offsets, 164, fbc_hdr_size);
+    mpp_dev_multi_offset_update(ctx->offsets, 166, fbc_hdr_size);
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static void setup_vepu511_split(HalVepu511RegSet *regs, MppEncCfgSet *enc_cfg)
+{
+    H264eVepu511Frame *reg_frm = &regs->reg_frm;
+    MppEncSliceSplit *cfg = &enc_cfg->split;
+
+    hal_h264e_dbg_func("enter\n");
+
+    switch (cfg->split_mode) {
+    case MPP_ENC_SPLIT_NONE : {
+        reg_frm->common.sli_splt.sli_splt         = 0;
+        reg_frm->common.sli_splt.sli_splt_mode    = 0;
+        reg_frm->common.sli_splt.sli_splt_cpst    = 0;
+        reg_frm->common.sli_splt.sli_max_num_m1   = 0;
+        reg_frm->common.sli_splt.sli_flsh         = 0;
+        reg_frm->common.sli_cnum.sli_splt_cnum_m1 = 0;
+
+        reg_frm->common.sli_byte.sli_splt_byte    = 0;
+        reg_frm->common.enc_pic.slen_fifo         = 0;
+    } break;
+    case MPP_ENC_SPLIT_BY_BYTE : {
+        reg_frm->common.sli_splt.sli_splt         = 1;
+        reg_frm->common.sli_splt.sli_splt_mode    = 0;
+        reg_frm->common.sli_splt.sli_splt_cpst    = 0;
+        reg_frm->common.sli_splt.sli_max_num_m1   = 500;
+        reg_frm->common.sli_splt.sli_flsh         = 1;
+        reg_frm->common.sli_cnum.sli_splt_cnum_m1 = 0;
+
+        reg_frm->common.sli_byte.sli_splt_byte    = cfg->split_arg;
+        reg_frm->common.enc_pic.slen_fifo         = cfg->split_out ? 1 : 0;
+        regs->reg_ctl.int_en.vslc_done_en         = reg_frm->common.enc_pic.slen_fifo;
+    } break;
+    case MPP_ENC_SPLIT_BY_CTU : {
+        RK_U32 mb_w = MPP_ALIGN(enc_cfg->prep.width, 16) / 16;
+        RK_U32 mb_h = MPP_ALIGN(enc_cfg->prep.height, 16) / 16;
+        RK_U32 slice_num = (mb_w * mb_h + cfg->split_arg - 1) / cfg->split_arg;
+
+        reg_frm->common.sli_splt.sli_splt         = 1;
+        reg_frm->common.sli_splt.sli_splt_mode    = 1;
+        reg_frm->common.sli_splt.sli_splt_cpst    = 0;
+        reg_frm->common.sli_splt.sli_max_num_m1   = 500;
+        reg_frm->common.sli_splt.sli_flsh         = 1;
+        reg_frm->common.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1;
+
+        reg_frm->common.sli_byte.sli_splt_byte    = 0;
+        reg_frm->common.enc_pic.slen_fifo         = cfg->split_out ? 1 : 0;
+        if ((cfg->split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) ||
+            (regs->reg_frm.common.enc_pic.slen_fifo && (slice_num > VEPU511_SLICE_FIFO_LEN)))
+            regs->reg_ctl.int_en.vslc_done_en = 1;
+    } break;
+    default : {
+        mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
+    } break;
+    }
+    cfg->change = 0;
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static void setup_vepu511_me(HalH264eVepu511Ctx *ctx)
+{
+    HalVepu511RegSet *regs = ctx->regs_set;
+    H264eVepu511Frame *reg_frm = &regs->reg_frm;
+    H264eVepu511Param *reg_param = &regs->reg_param;
+    MppEncSceneMode sm = ctx->cfg->tune.scene_mode;
+
+    hal_h264e_dbg_func("enter\n");
+
+    reg_frm->common.me_rnge.cime_srch_dwnh    = 15;
+    reg_frm->common.me_rnge.cime_srch_uph     = 15;
+    reg_frm->common.me_rnge.cime_srch_rgtw    = 12;
+    reg_frm->common.me_rnge.cime_srch_lftw    = 12;
+    reg_frm->common.me_cfg.rme_srch_h         = 3;
+    reg_frm->common.me_cfg.rme_srch_v         = 3;
+
+    reg_frm->common.me_cfg.srgn_max_num       = 54;
+    reg_frm->common.me_cfg.cime_dist_thre     = 1024;
+    reg_frm->common.me_cfg.rme_dis            = 0;
+    reg_frm->common.me_cfg.fme_dis            = 0;
+    reg_frm->common.me_rnge.dlt_frm_num       = 0x0;
+    reg_frm->common.me_cach.cime_zero_thre    = 64;
+
+    /* CIME: 0x1760 - 0x176C */
+    reg_param->me_sqi_comb.cime_pmv_num = 1;
+    reg_param->me_sqi_comb.cime_fuse    = 1;
+    reg_param->me_sqi_comb.move_lambda  = 0;
+    reg_param->me_sqi_comb.rime_lvl_mrg     = 1;
+    reg_param->me_sqi_comb.rime_prelvl_en   = 0;
+    reg_param->me_sqi_comb.rime_prersu_en   = 0;
+    reg_param->me_sqi_comb.fme_lvl_mrg   = 0;
+    reg_param->cime_mvd_th_comb.cime_mvd_th0 = 16;
+    reg_param->cime_mvd_th_comb.cime_mvd_th1 = 48;
+    reg_param->cime_mvd_th_comb.cime_mvd_th2 = 80;
+    reg_param->cime_madp_th_comb.cime_madp_th = 16;
+    reg_param->cime_multi_comb.cime_multi0 = 8;
+    reg_param->cime_multi_comb.cime_multi1 = 12;
+    reg_param->cime_multi_comb.cime_multi2 = 16;
+    reg_param->cime_multi_comb.cime_multi3 = 20;
+
+    /* RFME: 0x1770 - 0x1778 */
+    reg_param->rime_mvd_th_comb.rime_mvd_th0  = 1;
+    reg_param->rime_mvd_th_comb.rime_mvd_th1  = 2;
+    reg_param->rime_mvd_th_comb.fme_madp_th   = 0;
+    reg_param->rime_madp_th_comb.rime_madp_th0 = 8;
+    reg_param->rime_madp_th_comb.rime_madp_th1 = 16;
+    reg_param->rime_multi_comb.rime_multi0 = 4;
+    reg_param->rime_multi_comb.rime_multi1 = 8;
+    reg_param->rime_multi_comb.rime_multi2 = 12;
+    reg_param->cmv_st_th_comb.cmv_th0 = 64;
+    reg_param->cmv_st_th_comb.cmv_th1 = 96;
+    reg_param->cmv_st_th_comb.cmv_th2 = 128;
+
+    if (sm != MPP_ENC_SCENE_MODE_IPC) {
+        /* disable subjective optimization */
+        reg_param->cime_madp_th_comb.cime_madp_th = 0;
+        reg_param->rime_madp_th_comb.rime_madp_th0 = 0;
+        reg_param->rime_madp_th_comb.rime_madp_th1 = 0;
+        reg_param->cime_multi_comb.cime_multi0 = 4;
+        reg_param->cime_multi_comb.cime_multi1 = 4;
+        reg_param->cime_multi_comb.cime_multi2 = 4;
+        reg_param->cime_multi_comb.cime_multi3 = 4;
+        reg_param->rime_multi_comb.rime_multi0 = 4;
+        reg_param->rime_multi_comb.rime_multi1 = 4;
+        reg_param->rime_multi_comb.rime_multi2 = 4;
+    }
+
+    /* 0x1064 */
+    regs->reg_rc_roi.madi_st_thd.madi_th0 = 5;
+    regs->reg_rc_roi.madi_st_thd.madi_th1 = 12;
+    regs->reg_rc_roi.madi_st_thd.madi_th2 = 20;
+    /* 0x1068 */
+    regs->reg_rc_roi.madp_st_thd0.madp_th0 = 4 << 4;
+    regs->reg_rc_roi.madp_st_thd0.madp_th1 = 9 << 4;
+    /* 0x106C */
+    regs->reg_rc_roi.madp_st_thd1.madp_th2 = 15 << 4;
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+#define H264E_LAMBDA_TAB_SIZE       (52 * sizeof(RK_U32))
+
+static RK_U32 h264e_lambda_default[60] = {
+    0x00000005, 0x00000006, 0x00000007, 0x00000009,
+    0x0000000b, 0x0000000e, 0x00000012, 0x00000016,
+    0x0000001c, 0x00000024, 0x0000002d, 0x00000039,
+    0x00000048, 0x0000005b, 0x00000073, 0x00000091,
+    0x000000b6, 0x000000e6, 0x00000122, 0x0000016d,
+    0x000001cc, 0x00000244, 0x000002db, 0x00000399,
+    0x00000489, 0x000005b6, 0x00000733, 0x00000912,
+    0x00000b6d, 0x00000e66, 0x00001224, 0x000016db,
+    0x00001ccc, 0x00002449, 0x00002db7, 0x00003999,
+    0x00004892, 0x00005b6f, 0x00007333, 0x00009124,
+    0x0000b6de, 0x0000e666, 0x00012249, 0x00016dbc,
+    0x0001cccc, 0x00024492, 0x0002db79, 0x00039999,
+    0x00048924, 0x0005b6f2, 0x00073333, 0x00091249,
+    0x000b6de5, 0x000e6666, 0x00122492, 0x0016dbcb,
+    0x001ccccc, 0x00244924, 0x002db796, 0x00399998,
+};
+
+static RK_U32 h264e_lambda_cvr[60] = {
+    0x00000009, 0x0000000b, 0x0000000e, 0x00000011,
+    0x00000016, 0x0000001b, 0x00000022, 0x0000002b,
+    0x00000036, 0x00000045, 0x00000056, 0x0000006d,
+    0x00000089, 0x000000ad, 0x000000da, 0x00000112,
+    0x00000159, 0x000001b3, 0x00000224, 0x000002b3,
+    0x00000366, 0x00000449, 0x00000566, 0x000006cd,
+    0x00000891, 0x00000acb, 0x00000d9a, 0x000013c1,
+    0x000018e4, 0x00001f5c, 0x00002783, 0x000031c8,
+    0x00003eb8, 0x00004f06, 0x00006390, 0x00008e14,
+    0x0000b302, 0x0000e18a, 0x00011c29, 0x00016605,
+    0x0001c313, 0x00027ae1, 0x00031fe6, 0x0003efcf,
+    0x0004f5c3, 0x0006e785, 0x0008b2ef, 0x000af5c3,
+    0x000f1e7a, 0x00130c7f, 0x00180000, 0x001e3cf4,
+    0x002618fe, 0x00300000, 0x003c79e8, 0x004c31fc,
+    0x00600000, 0x0078f3d0, 0x009863f8, 0x0c000000,
+};
+
+static void
+setup_vepu511_l2(HalH264eVepu511Ctx *ctx)
+{
+    HalVepu511RegSet *regs = ctx->regs_set;
+    MppEncSceneMode sm = ctx->cfg->tune.scene_mode;
+    RK_S32 lambda_idx = ctx->cfg->tune.lambda_idx_i; //TODO: lambda_idx_p
+
+    hal_h264e_dbg_func("enter\n");
+
+    if (sm == MPP_ENC_SCENE_MODE_IPC) {
+        memcpy(regs->reg_param.rdo_wgta_qp_grpa_0_51,
+               &h264e_lambda_default[lambda_idx], H264E_LAMBDA_TAB_SIZE);
+    } else {
+        memcpy(regs->reg_param.rdo_wgta_qp_grpa_0_51,
+               &h264e_lambda_cvr[lambda_idx], H264E_LAMBDA_TAB_SIZE);
+    }
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static void setup_vepu511_ext_line_buf(HalVepu511RegSet *regs, HalH264eVepu511Ctx *ctx)
+{
+    H264eVepu511Frame *reg_frm = &regs->reg_frm;
+    MppDevRcbInfoCfg rcb_cfg;
+    RK_S32 offset = 0;
+    RK_S32 fd;
+
+    if (!ctx->ext_line_buf) {
+        reg_frm->common.ebufb_addr = 0;
+        reg_frm->common.ebufb_addr = 0;
+        return;
+    }
+
+    fd = mpp_buffer_get_fd(ctx->ext_line_buf);
+    offset = ctx->ext_line_buf_size;
+
+    reg_frm->common.ebuft_addr = fd;
+    reg_frm->common.ebufb_addr = fd;
+
+    mpp_dev_multi_offset_update(ctx->offsets, 178, offset);
+
+    /* rcb info for sram */
+    rcb_cfg.reg_idx = 179;
+    rcb_cfg.size = offset;
+
+    mpp_dev_ioctl(ctx->dev, MPP_DEV_RCB_INFO, &rcb_cfg);
+
+    rcb_cfg.reg_idx = 178;
+    rcb_cfg.size = 0;
+
+    mpp_dev_ioctl(ctx->dev, MPP_DEV_RCB_INFO, &rcb_cfg);
+}
+
+static void setup_vepu511_aq(HalH264eVepu511Ctx *ctx)
+{
+    MppEncCfgSet *cfg = ctx->cfg;
+    MppEncHwCfg *hw = &cfg->hw;
+    Vepu511RcRoi *s = &ctx->regs_set->reg_rc_roi;
+    RK_U8* thd = (RK_U8*)&s->aq_tthd0;
+    RK_S32 *aq_step, *aq_thd;
+    RK_U8 i;
+
+    if (ctx->slice->slice_type == H264_I_SLICE) {
+        aq_thd = (RK_S32 *)&hw->aq_thrd_i[0];
+        aq_step = &hw->aq_step_i[0];
+    } else {
+        aq_thd = (RK_S32 *)&hw->aq_thrd_p[0];
+        aq_step = &hw->aq_step_p[0];
+    }
+
+    for (i = 0; i < 16; i++)
+        thd[i] = aq_thd[i] & 0xff;
+
+    s->aq_stp0.aq_stp_s0 = aq_step[0] & 0x1f;
+    s->aq_stp0.aq_stp_0t1 = aq_step[1] & 0x1f;
+    s->aq_stp0.aq_stp_1t2 = aq_step[2] & 0x1f;
+    s->aq_stp0.aq_stp_2t3 = aq_step[3] & 0x1f;
+    s->aq_stp0.aq_stp_3t4 = aq_step[4] & 0x1f;
+    s->aq_stp0.aq_stp_4t5 = aq_step[5] & 0x1f;
+    s->aq_stp1.aq_stp_5t6 = aq_step[6] & 0x1f;
+    s->aq_stp1.aq_stp_6t7 = aq_step[7] & 0x1f;
+    s->aq_stp1.aq_stp_7t8 = 0;
+    s->aq_stp1.aq_stp_8t9 = aq_step[8] & 0x1f;
+    s->aq_stp1.aq_stp_9t10 = aq_step[9] & 0x1f;
+    s->aq_stp1.aq_stp_10t11 = aq_step[10] & 0x1f;
+    s->aq_stp2.aq_stp_11t12 = aq_step[11] & 0x1f;
+    s->aq_stp2.aq_stp_12t13 = aq_step[12] & 0x1f;
+    s->aq_stp2.aq_stp_13t14 = aq_step[13] & 0x1f;
+    s->aq_stp2.aq_stp_14t15 = aq_step[14] & 0x1f;
+    s->aq_stp2.aq_stp_b15 = aq_step[15] & 0x1f;
+}
+
+static void setup_vepu511_anti_stripe(HalH264eVepu511Ctx *ctx)
+{
+    HalVepu511RegSet *regs = ctx->regs_set;
+    H264eVepu511Param *s = &regs->reg_param;
+    RK_S32 str = ctx->cfg->tune.atl_str;
+
+    s->iprd_tthdy4_0.iprd_tthdy4_0 = 1;
+    s->iprd_tthdy4_0.iprd_tthdy4_1 = 3;
+    s->iprd_tthdy4_1.iprd_tthdy4_2 = 6;
+    s->iprd_tthdy4_1.iprd_tthdy4_3 = 8;
+    s->iprd_tthdc8_0.iprd_tthdc8_0 = 1;
+    s->iprd_tthdc8_0.iprd_tthdc8_1 = 3;
+    s->iprd_tthdc8_1.iprd_tthdc8_2 = 6;
+    s->iprd_tthdc8_1.iprd_tthdc8_3 = 8;
+    s->iprd_tthdy8_0.iprd_tthdy8_0 = 1;
+    s->iprd_tthdy8_0.iprd_tthdy8_1 = 3;
+    s->iprd_tthdy8_1.iprd_tthdy8_2 = 6;
+    s->iprd_tthdy8_1.iprd_tthdy8_3 = 8;
+
+    if (ctx->cfg->tune.scene_mode != MPP_ENC_SCENE_MODE_IPC)
+        s->iprd_tthd_ul.iprd_tthd_ul = 4095; /* disable anti-stripe */
+    else
+        s->iprd_tthd_ul.iprd_tthd_ul = str ? 4 : 255;
+
+    s->iprd_wgty8.iprd_wgty8_0 = str ? 22 : 16;
+    s->iprd_wgty8.iprd_wgty8_1 = str ? 23 : 16;
+    s->iprd_wgty8.iprd_wgty8_2 = str ? 20 : 16;
+    s->iprd_wgty8.iprd_wgty8_3 = str ? 22 : 16;
+    s->iprd_wgty4.iprd_wgty4_0 = str ? 22 : 16;
+    s->iprd_wgty4.iprd_wgty4_1 = str ? 26 : 16;
+    s->iprd_wgty4.iprd_wgty4_2 = str ? 20 : 16;
+    s->iprd_wgty4.iprd_wgty4_3 = str ? 22 : 16;
+    s->iprd_wgty16.iprd_wgty16_0 = 22;
+    s->iprd_wgty16.iprd_wgty16_1 = 26;
+    s->iprd_wgty16.iprd_wgty16_2 = 20;
+    s->iprd_wgty16.iprd_wgty16_3 = 22;
+    s->iprd_wgtc8.iprd_wgtc8_0 = 18;
+    s->iprd_wgtc8.iprd_wgtc8_1 = 21;
+    s->iprd_wgtc8.iprd_wgtc8_2 = 20;
+    s->iprd_wgtc8.iprd_wgtc8_3 = 19;
+}
+
+static void setup_vepu511_anti_ringing(HalH264eVepu511Ctx *ctx)
+{
+    HalVepu511RegSet *regs = ctx->regs_set;
+    H264eVepu511Sqi *s = &regs->reg_sqi;
+    MppEncSceneMode sm = ctx->cfg->tune.scene_mode;
+
+    s->atr_thd.atr_qp = (sm == MPP_ENC_SCENE_MODE_IPC) ? 32 : 45;
+    if (ctx->slice->slice_type == H264_I_SLICE) {
+        s->atr_thd.atr_thd0 = 1;
+        s->atr_thd.atr_thd1 = 2;
+        s->atr_thd.atr_thd2 = 6;
+        s->atr_wgt16.atr_lv16_wgt0 = 16;
+        s->atr_wgt16.atr_lv16_wgt1 = 16;
+        s->atr_wgt16.atr_lv16_wgt2 = 16;
+
+        if (sm == MPP_ENC_SCENE_MODE_IPC) {
+            s->atr_wgt8.atr_lv8_wgt0 = 22;
+            s->atr_wgt8.atr_lv8_wgt1 = 21;
+            s->atr_wgt8.atr_lv8_wgt2 = 20;
+            s->atr_wgt4.atr_lv4_wgt0 = 20;
+            s->atr_wgt4.atr_lv4_wgt1 = 18;
+            s->atr_wgt4.atr_lv4_wgt2 = 16;
+        } else {
+            s->atr_wgt8.atr_lv8_wgt0 = 18;
+            s->atr_wgt8.atr_lv8_wgt1 = 17;
+            s->atr_wgt8.atr_lv8_wgt2 = 18;
+            s->atr_wgt4.atr_lv4_wgt0 = 16;
+            s->atr_wgt4.atr_lv4_wgt1 = 16;
+            s->atr_wgt4.atr_lv4_wgt2 = 16;
+        }
+    } else {
+        if (sm == MPP_ENC_SCENE_MODE_IPC) {
+            s->atr_thd.atr_thd0 = 2;
+            s->atr_thd.atr_thd1 = 4;
+            s->atr_thd.atr_thd2 = 9;
+            s->atr_wgt16.atr_lv16_wgt0 = 25;
+            s->atr_wgt16.atr_lv16_wgt1 = 20;
+            s->atr_wgt16.atr_lv16_wgt2 = 16;
+            s->atr_wgt8.atr_lv8_wgt0 = 25;
+            s->atr_wgt8.atr_lv8_wgt1 = 20;
+            s->atr_wgt8.atr_lv8_wgt2 = 18;
+            s->atr_wgt4.atr_lv4_wgt0 = 25;
+            s->atr_wgt4.atr_lv4_wgt1 = 20;
+            s->atr_wgt4.atr_lv4_wgt2 = 16;
+        } else {
+            s->atr_thd.atr_thd0 = 1;
+            s->atr_thd.atr_thd1 = 2;
+            s->atr_thd.atr_thd2 = 7;
+            s->atr_wgt16.atr_lv16_wgt0 = 23;
+            s->atr_wgt16.atr_lv16_wgt1 = 22;
+            s->atr_wgt16.atr_lv16_wgt2 = 20;
+            s->atr_wgt8.atr_lv8_wgt0 = 24;
+            s->atr_wgt8.atr_lv8_wgt1 = 24;
+            s->atr_wgt8.atr_lv8_wgt2 = 24;
+            s->atr_wgt4.atr_lv4_wgt0 = 23;
+            s->atr_wgt4.atr_lv4_wgt1 = 22;
+            s->atr_wgt4.atr_lv4_wgt2 = 20;
+        }
+    }
+}
+
+static void setup_vepu511_anti_flicker(HalH264eVepu511Ctx *ctx)
+{
+    HalVepu511RegSet *regs = ctx->regs_set;
+    H264eVepu511Sqi *reg = &regs->reg_sqi;
+    RK_U32 str = ctx->cfg->tune.anti_flicker_str;
+    rdo_skip_par *p_skip = NULL;
+    rdo_noskip_par *p_no_skip = NULL;
+
+    static RK_U8 pskip_atf_th0[4] = { 0, 0, 0, 1 };
+    static RK_U8 pskip_atf_th1[4] = { 7, 7, 7, 10 };
+    static RK_U8 pskip_atf_wgt0[4] = { 16, 16, 16, 20 };
+    static RK_U8 pskip_atf_wgt1[4] = { 16, 16, 14, 16 };
+    static RK_U8 intra_atf_th0[4] = { 8, 16, 20, 20 };
+    static RK_U8 intra_atf_th1[4] = { 16, 32, 40, 40 };
+    static RK_U8 intra_atf_th2[4] = { 32, 56, 72, 72 };
+    static RK_U8 intra_atf_wgt0[4] = { 16, 24, 27, 27 };
+    static RK_U8 intra_atf_wgt1[4] = { 16, 22, 25, 25 };
+    static RK_U8 intra_atf_wgt2[4] = { 16, 19, 20, 20 };
+
+    p_skip = &reg->rdo_b16_skip;
+    p_skip->atf_thd0.madp_thd0 = pskip_atf_th0[str];
+    p_skip->atf_thd0.madp_thd1 = pskip_atf_th1[str];
+    p_skip->atf_thd1.madp_thd2 = 15;
+    p_skip->atf_thd1.madp_thd3 = 25;
+    p_skip->atf_wgt0.wgt0 = pskip_atf_wgt0[str];
+    p_skip->atf_wgt0.wgt1 = pskip_atf_wgt1[str];
+    p_skip->atf_wgt0.wgt2 = 16;
+    p_skip->atf_wgt0.wgt3 = 16;
+    p_skip->atf_wgt1.wgt4 = 16;
+
+    p_no_skip = &reg->rdo_b16_inter;
+    p_no_skip->ratf_thd0.madp_thd0 = 20;
+    p_no_skip->ratf_thd0.madp_thd1 = 40;
+    p_no_skip->ratf_thd1.madp_thd2 = 72;
+    p_no_skip->atf_wgt.wgt0 = 16;
+    p_no_skip->atf_wgt.wgt1 = 16;
+    p_no_skip->atf_wgt.wgt2 = 16;
+    p_no_skip->atf_wgt.wgt3 = 16;
+
+    p_no_skip = &reg->rdo_b16_intra;
+    p_no_skip->ratf_thd0.madp_thd0 = intra_atf_th0[str];
+    p_no_skip->ratf_thd0.madp_thd1 = intra_atf_th1[str];
+    p_no_skip->ratf_thd1.madp_thd2 = intra_atf_th2[str];
+    p_no_skip->atf_wgt.wgt0 = intra_atf_wgt0[str];
+    p_no_skip->atf_wgt.wgt1 = intra_atf_wgt1[str];
+    p_no_skip->atf_wgt.wgt2 = intra_atf_wgt2[str];
+    p_no_skip->atf_wgt.wgt3 = 16;
+
+    reg->rdo_b16_intra_atf_cnt_thd.thd0 = 1;
+    reg->rdo_b16_intra_atf_cnt_thd.thd1 = 4;
+    reg->rdo_b16_intra_atf_cnt_thd.thd2 = 1;
+    reg->rdo_b16_intra_atf_cnt_thd.thd3 = 4;
+
+    reg->rdo_atf_resi_thd.big_th0 = 16;
+    reg->rdo_atf_resi_thd.big_th1 = 16;
+    reg->rdo_atf_resi_thd.small_th0 = 8;
+    reg->rdo_atf_resi_thd.small_th1 = 8;
+}
+
+static void setup_vepu511_anti_smear(HalH264eVepu511Ctx *ctx)
+{
+    HalVepu511RegSet *regs = ctx->regs_set;
+    H264eVepu511Sqi *reg = &regs->reg_sqi;
+    H264eSlice *slice = ctx->slice;
+    Vepu511H264Fbk *last_fb = &ctx->last_frame_fb;
+    RK_U32 mb_cnt = last_fb->st_mb_num;
+    RK_U32 *smear_cnt = last_fb->st_smear_cnt;
+    RK_S32 deblur_str = ctx->cfg->tune.deblur_str;
+    RK_S32 delta_qp = 0;
+    RK_S32 flg0 = smear_cnt[4] < (mb_cnt >> 6);
+    RK_S32 flg1 = 1, flg2 = 0, flg3 = 0;
+    RK_S32 smear_multi[4] = { 9, 12, 16, 16 };
+
+    hal_h264e_dbg_func("enter\n");
+
+    if ((smear_cnt[3] < ((5 * mb_cnt) >> 10)) ||
+        (smear_cnt[3] < ((1126 * MPP_MAX3(smear_cnt[0], smear_cnt[1], smear_cnt[2])) >> 10)) ||
+        (deblur_str == 6) || (deblur_str == 7))
+        flg1 = 0;
+
+    flg3 = flg1 ? 3 : (smear_cnt[4] > ((102 * mb_cnt) >> 10)) ? 2 :
+           (smear_cnt[4] > ((66 * mb_cnt) >> 10)) ? 1 : 0;
+
+    if (ctx->cfg->tune.scene_mode == MPP_ENC_SCENE_MODE_IPC) {
+        reg->smear_opt_cfg.rdo_smear_en = ctx->qpmap_en;
+        if (ctx->qpmap_en && deblur_str > 3)
+            reg->smear_opt_cfg.rdo_smear_lvl16_multi = smear_multi[flg3];
+        else
+            reg->smear_opt_cfg.rdo_smear_lvl16_multi = flg0 ? 9 : 12;
+    } else {
+        reg->smear_opt_cfg.rdo_smear_en = 0;
+        reg->smear_opt_cfg.rdo_smear_lvl16_multi = 16;
+    }
+
+    if (ctx->qpmap_en && deblur_str > 3) {
+        flg2 = 1;
+        if (smear_cnt[2] + smear_cnt[3] > (3 * smear_cnt[4] / 4))
+            delta_qp = 1;
+        if (smear_cnt[4] < (mb_cnt >> 4))
+            delta_qp -= 8;
+        else if (smear_cnt[4] < ((3 * mb_cnt) >> 5))
+            delta_qp -= 7;
+        else
+            delta_qp -= 6;
+
+        if (flg3 == 2)
+            delta_qp = 0;
+        else if (flg3 == 1)
+            delta_qp = -2;
+    } else {
+        if (smear_cnt[2] + smear_cnt[3] > smear_cnt[4] / 2)
+            delta_qp = 1;
+        if (smear_cnt[4] < (mb_cnt >> 8))
+            delta_qp -= (deblur_str < 2) ? 6 : 8;
+        else if (smear_cnt[4] < (mb_cnt >> 7))
+            delta_qp -= (deblur_str < 2) ? 5 : 6;
+        else if (smear_cnt[4] < (mb_cnt >> 6))
+            delta_qp -= (deblur_str < 2) ? 3 : 4;
+        else
+            delta_qp -= 1;
+    }
+    reg->smear_opt_cfg.rdo_smear_dlt_qp = delta_qp;
+
+    if ((H264_I_SLICE == slice->slice_type) ||
+        (H264_I_SLICE == last_fb->frame_type))
+        reg->smear_opt_cfg.stated_mode = 1;
+    else
+        reg->smear_opt_cfg.stated_mode = 2;
+
+    reg->smear_madp_thd0.madp_cur_thd0 = 0;
+    reg->smear_madp_thd0.madp_cur_thd1 = flg2 ? 48 : 24;
+    reg->smear_madp_thd1.madp_cur_thd2 = flg2 ? 64 : 48;
+    reg->smear_madp_thd1.madp_cur_thd3 = flg2 ? 72 : 64;
+    reg->smear_madp_thd2.madp_around_thd0 = flg2 ? 4095 : 16;
+    reg->smear_madp_thd2.madp_around_thd1 = 32;
+    reg->smear_madp_thd3.madp_around_thd2 = 48;
+    reg->smear_madp_thd3.madp_around_thd3 = flg2 ? 0 : 96;
+    reg->smear_madp_thd4.madp_around_thd4 = 48;
+    reg->smear_madp_thd4.madp_around_thd5 = 24;
+    reg->smear_madp_thd5.madp_ref_thd0 = flg2 ? 64 : 96;
+    reg->smear_madp_thd5.madp_ref_thd1 = 48;
+
+    reg->smear_cnt_thd0.cnt_cur_thd0 = flg2 ?  2 : 1;
+    reg->smear_cnt_thd0.cnt_cur_thd1 = flg2 ?  5 : 3;
+    reg->smear_cnt_thd0.cnt_cur_thd2 = 1;
+    reg->smear_cnt_thd0.cnt_cur_thd3 = 3;
+    reg->smear_cnt_thd1.cnt_around_thd0 = 1;
+    reg->smear_cnt_thd1.cnt_around_thd1 = 4;
+    reg->smear_cnt_thd1.cnt_around_thd2 = 1;
+    reg->smear_cnt_thd1.cnt_around_thd3 = 4;
+    reg->smear_cnt_thd2.cnt_around_thd4 = 0;
+    reg->smear_cnt_thd2.cnt_around_thd5 = 3;
+    reg->smear_cnt_thd2.cnt_around_thd6 = 0;
+    reg->smear_cnt_thd2.cnt_around_thd7 = 3;
+    reg->smear_cnt_thd3.cnt_ref_thd0 = 1;
+    reg->smear_cnt_thd3.cnt_ref_thd1 = 3;
+
+    reg->smear_resi_thd0.resi_small_cur_th0 = 6;
+    reg->smear_resi_thd0.resi_big_cur_th0 = 9;
+    reg->smear_resi_thd0.resi_small_cur_th1 = 6;
+    reg->smear_resi_thd0.resi_big_cur_th1 = 9;
+    reg->smear_resi_thd1.resi_small_around_th0 = 6;
+    reg->smear_resi_thd1.resi_big_around_th0 = 11;
+    reg->smear_resi_thd1.resi_small_around_th1 = 6;
+    reg->smear_resi_thd1.resi_big_around_th1 = 8;
+    reg->smear_resi_thd2.resi_small_around_th2 = 9;
+    reg->smear_resi_thd2.resi_big_around_th2 = 20;
+    reg->smear_resi_thd2.resi_small_around_th3 = 6;
+    reg->smear_resi_thd2.resi_big_around_th3 = 20;
+    reg->smear_resi_thd3.resi_small_ref_th0 = 7;
+    reg->smear_resi_thd3.resi_big_ref_th0 = 16;
+    reg->smear_resi_thd4.resi_th0 = flg2 ? 0 : 10;
+    reg->smear_resi_thd4.resi_th1 = flg2 ? 0 : 6;
+
+    reg->smear_st_thd.madp_cnt_th0 = flg2 ? 0 : 1;
+    reg->smear_st_thd.madp_cnt_th1 = flg2 ? 0 : 5;
+    reg->smear_st_thd.madp_cnt_th2 = flg2 ? 0 : 1;
+    reg->smear_st_thd.madp_cnt_th3 = flg2 ? 0 : 3;
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static void setup_vepu511_scaling_list(HalH264eVepu511Ctx *ctx)
+{
+    HalVepu511RegSet *regs = ctx->regs_set;
+    H264eVepu511SclCfg *s = &regs->reg_scl;
+    RK_U8 *p = (RK_U8 *)&s->tu8_intra_y[0];
+    RK_U8 idx;
+
+    hal_h264e_dbg_func("enter\n");
+
+    /* intra4x4 and inter4x4 is not supported on VEPU500.
+     * valid range: 0x2200 ~ 0x221F
+     */
+    if (ctx->pps->pic_scaling_matrix_present == 1) {
+        for (idx = 0; idx < 64; idx++) {
+            p[idx] = vepu511_h264_cqm_jvt8i[63 - idx]; /* intra8x8 */
+            p[idx + 64] = vepu511_h264_cqm_jvt8p[63 - idx]; /* inter8x8 */
+        }
+    } else if (ctx->pps->pic_scaling_matrix_present == 2) {
+        //TODO: Update scaling list for (scaling_list_mode == 2)
+        mpp_log_f("scaling_list_mode 2 is not supported yet\n");
+    }
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static MPP_RET hal_h264e_vepu511_gen_regs(void *hal, HalEncTask *task)
+{
+    HalH264eVepu511Ctx *ctx = (HalH264eVepu511Ctx *)hal;
+    HalVepu511RegSet *regs = ctx->regs_set;
+    MppEncCfgSet *cfg = ctx->cfg;
+    EncRcTask *rc_task = task->rc_task;
+    EncFrmStatus *frm = &rc_task->frm;
+    MPP_RET ret = MPP_OK;
+
+    hal_h264e_dbg_func("enter %p\n", hal);
+    hal_h264e_dbg_detail("frame %d generate regs now", ctx->frms->seq_idx);
+
+    /* register setup */
+    memset(regs, 0, sizeof(*regs));
+
+    setup_vepu511_normal(regs);
+    ret = setup_vepu511_prep(regs, &ctx->cfg->prep, task);
+    if (ret)
+        return ret;
+
+    setup_vepu511_codec(regs, ctx);
+    setup_vepu511_rdo_pred(ctx);
+    setup_vepu511_aq(ctx);
+    setup_vepu511_anti_stripe(ctx);
+    setup_vepu511_anti_ringing(ctx);
+    setup_vepu511_anti_flicker(ctx);
+    setup_vepu511_anti_smear(ctx);
+    setup_vepu511_scaling_list(ctx);
+
+    setup_vepu511_rc_base(regs, ctx, rc_task);
+    setup_vepu511_io_buf(regs, ctx->offsets, task);
+    setup_vepu511_recn_refr(ctx, regs);
+    setup_vepu511_split(regs, cfg);
+    setup_vepu511_me(ctx);
+
+    if (frm->is_i_refresh)
+        setup_vepu511_intra_refresh(regs, ctx, frm->seq_idx % cfg->rc.gop);
+
+    setup_vepu511_l2(ctx);
+    setup_vepu511_ext_line_buf(regs, ctx);
+
+    if (ctx->osd_cfg.osd_data3)
+        vepu511_set_osd(&ctx->osd_cfg, &regs->reg_osd.osd_comb_cfg);
+
+    if (ctx->roi_data)
+        vepu511_set_roi(&ctx->regs_set->reg_rc_roi.roi_cfg, ctx->roi_data,
+                        ctx->cfg->prep.width, ctx->cfg->prep.height);
+
+    /* two pass register patch */
+    if (frm->save_pass1)
+        vepu511_h264e_save_pass1_patch(regs, ctx);
+
+    if (frm->use_pass1)
+        vepu511_h264e_use_pass1_patch(regs, ctx);
+
+    ctx->frame_cnt++;
+
+    hal_h264e_dbg_func("leave %p\n", hal);
+    return MPP_OK;
+}
+
+static MPP_RET hal_h264e_vepu511_start(void *hal, HalEncTask *task)
+{
+    MPP_RET ret = MPP_OK;
+    HalH264eVepu511Ctx *ctx = (HalH264eVepu511Ctx *)hal;
+    HalVepu511RegSet *regs = ctx->regs_set;
+
+    (void) task;
+
+    hal_h264e_dbg_func("enter %p\n", hal);
+
+    do {
+        MppDevRegWrCfg wr_cfg;
+        MppDevRegRdCfg rd_cfg;
+
+        wr_cfg.reg = &regs->reg_ctl;
+        wr_cfg.size = sizeof(regs->reg_ctl);
+        wr_cfg.offset = VEPU511_CTL_OFFSET;
+#if DUMP_REG
+        {
+            RK_U32 i;
+            RK_U32 *reg = (RK_U32)wr_cfg.reg;
+            for ( i = 0; i < sizeof(regs->reg_ctl) / sizeof(RK_U32); i++) {
+                mpp_log("reg[%d] = 0x%08x\n", i, reg[i]);
+            }
+
+        }
+#endif
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->reg_frm;
+        wr_cfg.size = sizeof(regs->reg_frm);
+        wr_cfg.offset = VEPU511_FRAME_OFFSET;
+
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->reg_rc_roi;
+        wr_cfg.size = sizeof(regs->reg_rc_roi);
+        wr_cfg.offset = VEPU511_RC_ROI_OFFSET;
+
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->reg_param;
+        wr_cfg.size = sizeof(regs->reg_param);
+        wr_cfg.offset = VEPU511_PARAM_OFFSET;
+
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->reg_sqi;
+        wr_cfg.size = sizeof(regs->reg_sqi);
+        wr_cfg.offset = VEPU511_SQI_OFFSET;
+
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->reg_scl;
+        wr_cfg.size = sizeof(regs->reg_scl);
+        wr_cfg.offset = VEPU511_SCL_OFFSET ;
+
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->reg_osd;
+        wr_cfg.size = sizeof(regs->reg_osd);
+        wr_cfg.offset = VEPU511_OSD_OFFSET ;
+
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            return ret;
+        }
+
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFS, ctx->offsets);
+        if (ret) {
+            mpp_err_f("set register offsets failed %d\n", ret);
+            break;
+        }
+
+        rd_cfg.reg = &regs->reg_ctl.int_sta;
+        rd_cfg.size = sizeof(RK_U32);
+        rd_cfg.offset = VEPU511_REG_BASE_HW_STATUS;
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
+        if (ret) {
+            mpp_err_f("set register read failed %d\n", ret);
+            break;
+        }
+
+        rd_cfg.reg = &regs->reg_st;
+        rd_cfg.size = sizeof(regs->reg_st);
+        rd_cfg.offset = VEPU511_STATUS_OFFSET;
+
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
+        if (ret) {
+            mpp_err_f("set register read failed %d\n", ret);
+            break;
+        }
+
+        /* send request to hardware */
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
+        if (ret) {
+            mpp_err_f("send cmd failed %d\n", ret);
+            break;
+        }
+    } while (0);
+
+    hal_h264e_dbg_func("leave %p\n", hal);
+
+    return ret;
+}
+
+static MPP_RET hal_h264e_vepu511_status_check(HalVepu511RegSet *regs)
+{
+    MPP_RET ret = MPP_OK;
+
+    if (regs->reg_ctl.int_sta.lkt_node_done_sta)
+        hal_h264e_dbg_detail("lkt_done finish");
+
+    if (regs->reg_ctl.int_sta.enc_done_sta)
+        hal_h264e_dbg_detail("enc_done finish");
+
+    if (regs->reg_ctl.int_sta.vslc_done_sta)
+        hal_h264e_dbg_detail("enc_slice finsh");
+
+    if (regs->reg_ctl.int_sta.sclr_done_sta)
+        hal_h264e_dbg_detail("safe clear finsh");
+
+    if (regs->reg_ctl.int_sta.vbsf_oflw_sta) {
+        mpp_err_f("bit stream overflow");
+        ret = MPP_NOK;
+    }
+
+    if (regs->reg_ctl.int_sta.vbuf_lens_sta) {
+        mpp_err_f("bus write full");
+        ret = MPP_NOK;
+    }
+
+    if (regs->reg_ctl.int_sta.enc_err_sta) {
+        mpp_err_f("bus error");
+        ret = MPP_NOK;
+    }
+
+    if (regs->reg_ctl.int_sta.wdg_sta) {
+        mpp_err_f("wdg timeout");
+        ret = MPP_NOK;
+    }
+
+    return ret;
+}
+
+static MPP_RET hal_h264e_vepu511_wait(void *hal, HalEncTask *task)
+{
+    MPP_RET ret = MPP_OK;
+    HalH264eVepu511Ctx *ctx = (HalH264eVepu511Ctx *)hal;
+    HalVepu511RegSet *regs = &ctx->regs_sets[task->flags.reg_idx];
+    RK_U32 split_out = ctx->cfg->split.split_out;
+    MppPacket pkt = task->packet;
+    RK_S32 offset = mpp_packet_get_length(pkt);
+    H264NaluType type = task->rc_task->frm.is_idr ?  H264_NALU_TYPE_IDR : H264_NALU_TYPE_SLICE;
+    MppEncH264HwCfg *hw_cfg = &ctx->cfg->codec.h264.hw_cfg;
+    RK_S32 i;
+
+    hal_h264e_dbg_func("enter %p\n", hal);
+
+    /* if pass1 mode, it will disable split mode and the split out need to be disable */
+    if (task->rc_task->frm.save_pass1)
+        split_out = 0;
+
+    /* update split_out in hw_cfg */
+    hw_cfg->hw_split_out = split_out;
+
+    if (split_out) {
+        EncOutParam param;
+        RK_U32 slice_len;
+        RK_U32 slice_last;
+        MppDevPollCfg *poll_cfg = (MppDevPollCfg *)((char *)ctx->poll_cfgs +
+                                                    task->flags.reg_idx * ctx->poll_cfg_size);
+        param.task = task;
+        param.base = mpp_packet_get_data(task->packet);
+
+        do {
+            poll_cfg->poll_type = 0;
+            poll_cfg->poll_ret  = 0;
+            poll_cfg->count_max = ctx->poll_slice_max;
+            poll_cfg->count_ret = 0;
+
+            ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, poll_cfg);
+
+            for (i = 0; i < poll_cfg->count_ret; i++) {
+                slice_last = poll_cfg->slice_info[i].last;
+                slice_len = poll_cfg->slice_info[i].length;
+
+                mpp_packet_add_segment_info(pkt, type, offset, slice_len);
+                offset += slice_len;
+
+                if (split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) {
+                    param.length = slice_len;
+
+                    if (slice_last)
+                        ctx->output_cb->cmd = ENC_OUTPUT_FINISH;
+                    else
+                        ctx->output_cb->cmd = ENC_OUTPUT_SLICE;
+
+                    mpp_callback(ctx->output_cb, &param);
+                }
+            }
+        } while (!slice_last);
+
+        ret = hal_h264e_vepu511_status_check(regs);
+        if (!ret)
+            task->hw_length += regs->reg_st.bs_lgth_l32;
+    } else {
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
+        if (ret) {
+            mpp_err_f("poll cmd failed %d\n", ret);
+            ret = MPP_ERR_VPUHW;
+        } else {
+            ret = hal_h264e_vepu511_status_check(regs);
+            if (!ret)
+                task->hw_length += regs->reg_st.bs_lgth_l32;
+        }
+
+        mpp_packet_add_segment_info(pkt, type, offset, regs->reg_st.bs_lgth_l32);
+    }
+
+    if (!(split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) && !ret) {
+        HalH264eVepuStreamAmend *amend = &ctx->amend_sets[task->flags.reg_idx];
+
+        if (amend->enable) {
+            amend->old_length = task->hw_length;
+            amend->slice->is_multi_slice = (ctx->cfg->split.split_mode > 0);
+            h264e_vepu_stream_amend_proc(amend, &ctx->cfg->codec.h264.hw_cfg);
+            task->hw_length = amend->new_length;
+        } else if (amend->prefix) {
+            /* check prefix value */
+            amend->old_length = task->hw_length;
+            h264e_vepu_stream_amend_sync_ref_idc(amend);
+        }
+    }
+
+    hal_h264e_dbg_func("leave %p ret %d\n", hal, ret);
+
+    return ret;
+}
+
+static MPP_RET hal_h264e_vepu511_ret_task(void * hal, HalEncTask * task)
+{
+    HalH264eVepu511Ctx *ctx = (HalH264eVepu511Ctx *)hal;
+    HalVepu511RegSet *regs = &ctx->regs_sets[task->flags.reg_idx];
+    EncRcTaskInfo *rc_info = &task->rc_task->info;
+    Vepu511H264Fbk *fb = &ctx->feedback;
+    Vepu511Status *reg_st = &regs->reg_st;
+    RK_U32 mb_w = ctx->sps->pic_width_in_mbs;
+    RK_U32 mb_h = ctx->sps->pic_height_in_mbs;
+    RK_U32 mbs = mb_w * mb_h;
+
+    hal_h264e_dbg_func("enter %p\n", hal);
+
+    fb->st_mb_num = mbs;
+    fb->st_smear_cnt[0] = reg_st->st_smear_cnt0.rdo_smear_cnt0 * 4;
+    fb->st_smear_cnt[1] = reg_st->st_smear_cnt0.rdo_smear_cnt1 * 4;
+    fb->st_smear_cnt[2] = reg_st->st_smear_cnt1.rdo_smear_cnt2 * 4;
+    fb->st_smear_cnt[3] = reg_st->st_smear_cnt1.rdo_smear_cnt3 * 4;
+    fb->st_smear_cnt[4] = fb->st_smear_cnt[0] + fb->st_smear_cnt[1] +
+                          fb->st_smear_cnt[2] + fb->st_smear_cnt[3];
+    fb->frame_type = ctx->slice->slice_type;
+
+    // update total hardware length
+    task->length += task->hw_length;
+
+    // setup bit length for rate control
+    rc_info->bit_real = task->hw_length * 8;
+    rc_info->quality_real = regs->reg_st.qp_sum / mbs;
+    rc_info->iblk4_prop = (regs->reg_st.st_pnum_i4.pnum_i4 +
+                           regs->reg_st.st_pnum_i8.pnum_i8 +
+                           regs->reg_st.st_pnum_i16.pnum_i16) * 256 / mbs;
+
+    rc_info->sse = ((RK_S64)regs->reg_st.sse_h32 << 16) +
+                   (regs->reg_st.st_sse_bsl.sse_l16 & 0xffff);
+    rc_info->lvl16_inter_num = regs->reg_st.st_pnum_p16.pnum_p16;
+    rc_info->lvl8_inter_num  = regs->reg_st.st_pnum_p8.pnum_p8;
+    rc_info->lvl16_intra_num = regs->reg_st.st_pnum_i16.pnum_i16;
+    rc_info->lvl8_intra_num  = regs->reg_st.st_pnum_i8.pnum_i8;
+    rc_info->lvl4_intra_num  = regs->reg_st.st_pnum_i4.pnum_i4;
+
+    ctx->hal_rc_cfg.bit_real = rc_info->bit_real;
+    ctx->hal_rc_cfg.quality_real = rc_info->quality_real;
+    ctx->hal_rc_cfg.iblk4_prop = rc_info->iblk4_prop;
+
+    task->hal_ret.data   = &ctx->hal_rc_cfg;
+    task->hal_ret.number = 1;
+
+    mpp_dev_multi_offset_reset(ctx->offsets);
+
+    if (ctx->dpb) {
+        h264e_dpb_hal_end(ctx->dpb, task->flags.curr_idx);
+        h264e_dpb_hal_end(ctx->dpb, task->flags.refr_idx);
+    }
+
+    // vepu511_h264e_tune_stat_update(ctx->tune, task);
+
+    hal_h264e_dbg_func("leave %p\n", hal);
+
+    return MPP_OK;
+}
+
+const MppEncHalApi hal_h264e_vepu511 = {
+    .name       = "hal_h264e_vepu511",
+    .coding     = MPP_VIDEO_CodingAVC,
+    .ctx_size   = sizeof(HalH264eVepu511Ctx),
+    .flag       = 0,
+    .init       = hal_h264e_vepu511_init,
+    .deinit     = hal_h264e_vepu511_deinit,
+    .prepare    = hal_h264e_vepu511_prepare,
+    .get_task   = hal_h264e_vepu511_get_task,
+    .gen_regs   = hal_h264e_vepu511_gen_regs,
+    .start      = hal_h264e_vepu511_start,
+    .wait       = hal_h264e_vepu511_wait,
+    .part_start = NULL,
+    .part_wait  = NULL,
+    .ret_task   = hal_h264e_vepu511_ret_task,
+};
diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu511.h b/mpp/hal/rkenc/h264e/hal_h264e_vepu511.h
new file mode 100644
index 00000000..a91ceaaa
--- /dev/null
+++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu511.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_H264E_VEPU511_H__
+#define __HAL_H264E_VEPU511_H__
+
+#include "mpp_enc_hal.h"
+
+extern const MppEncHalApi hal_h264e_vepu511;
+
+#endif /* __HAL_H264E_VEPU511_H__ */
diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu511_reg.h b/mpp/hal/rkenc/h264e/hal_h264e_vepu511_reg.h
new file mode 100644
index 00000000..85908faf
--- /dev/null
+++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu511_reg.h
@@ -0,0 +1,1204 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_H264E_VEPU511_REG_H__
+#define __HAL_H264E_VEPU511_REG_H__
+
+#include "rk_type.h"
+#include "vepu511_common.h"
+
+/* class: buffer/video syntax */
+/* 0x00000270 reg156 - 0x00000538 reg334 */
+typedef struct H264eVepu511Frame_t {
+    /* 0x00000270 reg156  - 0x0000039c reg231 */
+    Vepu511FrmCommon common;
+
+    /* 0x000003a0 reg232 */
+    struct {
+        RK_U32 rect_size         : 1;
+        RK_U32 reserved          : 2;
+        RK_U32 vlc_lmt           : 1;
+        RK_U32 reserved1         : 9;
+        RK_U32 ccwa_e            : 1;
+        RK_U32 reserved2         : 1;
+        RK_U32 atr_e             : 1;
+        RK_U32 reserved3         : 4;
+        RK_U32 scl_lst_sel       : 2;
+        RK_U32 reserved4         : 6;
+        RK_U32 atf_e             : 1;
+        RK_U32 atr_mult_sel_e    : 1;
+        RK_U32 reserved5         : 2;
+    } rdo_cfg;
+
+    /* 0x000003a4 reg233 */
+    struct {
+        RK_U32 rdo_mark_mode         : 9;
+        RK_U32 reserved              : 5;
+        RK_U32 p16_interp_num        : 2;
+        RK_U32 p16t8_rdo_num         : 2;
+        RK_U32 p16t4_rmd_num         : 2;
+        RK_U32 p8_interp_num         : 2;
+        RK_U32 p8t8_rdo_num          : 2;
+        RK_U32 p8t4_rmd_num          : 2;
+        RK_U32 iframe_i16_rdo_num    : 2;
+        RK_U32 i8_rdo_num            : 2;
+        RK_U32 iframe_i4_rdo_num     : 2;
+    } rdo_mark_mode;
+
+    /* 0x3a8 - 0x3ac */
+    RK_U32 reserved234_235[2];
+
+    /* 0x000003b0 reg236 */
+    struct {
+        RK_U32 nal_ref_idc      : 2;
+        RK_U32 nal_unit_type    : 5;
+        RK_U32 reserved         : 25;
+    } synt_nal;
+
+    /* 0x000003b4 reg237 */
+    struct {
+        RK_U32 max_fnum    : 4;
+        RK_U32 drct_8x8    : 1;
+        RK_U32 mpoc_lm4    : 4;
+        RK_U32 poc_type    : 2;
+        RK_U32 reserved    : 21;
+    } synt_sps;
+
+    /* 0x000003b8 reg238 */
+    struct {
+        RK_U32 etpy_mode       : 1;
+        RK_U32 trns_8x8        : 1;
+        RK_U32 csip_flag       : 1;
+        RK_U32 num_ref0_idx    : 2;
+        RK_U32 num_ref1_idx    : 2;
+        RK_U32 pic_init_qp     : 6;
+        RK_U32 cb_ofst         : 5;
+        RK_U32 cr_ofst         : 5;
+        RK_U32 reserved        : 1;
+        RK_U32 dbf_cp_flg      : 1;
+        RK_U32 reserved1       : 7;
+    } synt_pps;
+
+    /* 0x000003bc reg239 */
+    struct {
+        RK_U32 sli_type        : 2;
+        RK_U32 pps_id          : 8;
+        RK_U32 drct_smvp       : 1;
+        RK_U32 num_ref_ovrd    : 1;
+        RK_U32 cbc_init_idc    : 2;
+        RK_U32 reserved        : 2;
+        RK_U32 frm_num         : 16;
+    } synt_sli0;
+
+    /* 0x000003c0 reg240 */
+    struct {
+        RK_U32 idr_pid    : 16;
+        RK_U32 poc_lsb    : 16;
+    } synt_sli1;
+
+    /* 0x000003c4 reg241 */
+    struct {
+        RK_U32 rodr_pic_idx      : 2;
+        RK_U32 ref_list0_rodr    : 1;
+        RK_U32 sli_beta_ofst     : 4;
+        RK_U32 sli_alph_ofst     : 4;
+        RK_U32 dis_dblk_idc      : 2;
+        RK_U32 reserved          : 3;
+        RK_U32 rodr_pic_num      : 16;
+    } synt_sli2;
+
+    /* 0x000003c8 reg242 */
+    struct {
+        RK_U32 nopp_flg      : 1;
+        RK_U32 ltrf_flg      : 1;
+        RK_U32 arpm_flg      : 1;
+        RK_U32 mmco4_pre     : 1;
+        RK_U32 mmco_type0    : 3;
+        RK_U32 mmco_parm0    : 16;
+        RK_U32 mmco_type1    : 3;
+        RK_U32 mmco_type2    : 3;
+        RK_U32 reserved      : 3;
+    } synt_refm0;
+
+    /* 0x000003cc reg243 */
+    struct {
+        RK_U32 mmco_parm1    : 16;
+        RK_U32 mmco_parm2    : 16;
+    } synt_refm1;
+
+    /* 0x000003d0 reg244 */
+    struct {
+        RK_U32 long_term_frame_idx0    : 4;
+        RK_U32 long_term_frame_idx1    : 4;
+        RK_U32 long_term_frame_idx2    : 4;
+        RK_U32 reserved                : 20;
+    } synt_refm2;
+
+    /* 0x000003d4 reg245 - 0x0x00000 reg251 */
+    RK_U32 reserved245_251[7];
+
+    /* 0x000003f0 reg252 */
+    struct {
+        RK_U32 mv_v_lmt_thd    : 14;
+        RK_U32 reserved        : 1;
+        RK_U32 mv_v_lmt_en     : 1;
+        RK_U32 reserved1       : 16;
+    } sli_cfg;
+
+    /* 0x000003f4 reg253 */
+    RK_U32 reserved253;
+
+    /* 0x000003f8 reg254 */
+    struct {
+        RK_U32 slice_sta_x      : 9;
+        RK_U32 reserved1        : 7;
+        RK_U32 slice_sta_y      : 10;
+        RK_U32 reserved2        : 5;
+        RK_U32 slice_enc_ena    : 1;
+    } slice_enc_cfg0;
+
+    /* 0x000003fc reg255 */
+    struct {
+        RK_U32 slice_end_x    : 9;
+        RK_U32 reserved       : 7;
+        RK_U32 slice_end_y    : 10;
+        RK_U32 reserved1      : 6;
+    } slice_enc_cfg1;
+
+    /* 0x00000400 reg256 */
+    struct {
+        RK_U32 reserved          : 8;
+        RK_U32 bsbt_addr_jpeg    : 24;
+    } adr_bsbt_jpeg;
+
+    /* 0x00000404 reg257 */
+    struct {
+        RK_U32 reserved          : 8;
+        RK_U32 bsbb_addr_jpeg    : 24;
+    } adr_bsbb_jpeg;
+
+    /* 0x00000408 reg258 */
+    RK_U32 adr_bsbs_jpeg;
+
+    /* 0x0000040c reg259 */
+    struct {
+        RK_U32 bsadr_msk_jpeg    : 4;
+        RK_U32 reserved          : 4;
+        RK_U32 bsbr_addr_jpeg    : 24;
+    } adr_bsbr_jpeg;
+
+    /* 0x00000410 reg260 */
+    struct {
+        RK_U32 reserved          : 4;
+        RK_U32 adr_vsy_b_jpeg    : 28;
+    } adr_vsy_b_jpeg;
+
+    /* 0x00000414 reg261 */
+    struct {
+        RK_U32 reserved          : 4;
+        RK_U32 adr_vsc_b_jpeg    : 28;
+    } adr_vsc_b_jpeg;
+
+    /* 0x00000418 reg262 */
+    struct {
+        RK_U32 reserved          : 4;
+        RK_U32 adr_vsy_t_jpeg    : 28;
+    } adr_vsy_t_jpeg;
+
+    /* 0x0000041c reg263 */
+    struct {
+        RK_U32 reserved          : 4;
+        RK_U32 adr_vsc_t_jpeg    : 28;
+    } adr_vsc_t_jpeg;
+
+    /* 0x00000420 reg264 */
+    RK_U32 adr_src0_jpeg;
+
+    /* 0x00000424 reg265 */
+    RK_U32 adr_src1_jpeg;
+
+    /* 0x00000428 reg266 */
+    RK_U32 adr_src2_jpeg;
+
+    /* 0x0000042c reg267 */
+    RK_U32 bsp_size_jpeg;
+
+    /* 0x430 - 0x43c */
+    RK_U32 reserved268_271[4];
+
+    /* 0x00000440 reg272 */
+    struct {
+        RK_U32 pic_wd8_m1    : 11;
+        RK_U32 reserved      : 1;
+        RK_U32 pp0_vnum_m1   : 4;
+        RK_U32 pic_hd8_m1    : 11;
+        RK_U32 reserved1     : 1;
+        RK_U32 pp0_jnum_m1   : 4;
+    } enc_rsl_jpeg;
+
+    /* 0x00000444 reg273 */
+    struct {
+        RK_U32 pic_wfill_jpeg    : 6;
+        RK_U32 reserved          : 10;
+        RK_U32 pic_hfill_jpeg    : 6;
+        RK_U32 reserved1         : 10;
+    } src_fill_jpeg;
+
+    /* 0x00000448 reg274 */
+    struct {
+        RK_U32 alpha_swap_jpeg            : 1;
+        RK_U32 rbuv_swap_jpeg             : 1;
+        RK_U32 src_cfmt_jpeg              : 4;
+        RK_U32 reserved                   : 2;
+        RK_U32 src_range_trns_en_jpeg     : 1;
+        RK_U32 src_range_trns_sel_jpeg    : 1;
+        RK_U32 chroma_ds_mode_jpeg        : 1;
+        RK_U32 reserved1                  : 21;
+    } src_fmt_jpeg;
+
+    /* 0x0000044c reg275 */
+    struct {
+        RK_U32 csc_wgt_b2y_jpeg    : 9;
+        RK_U32 csc_wgt_g2y_jpeg    : 9;
+        RK_U32 csc_wgt_r2y_jpeg    : 9;
+        RK_U32 reserved            : 5;
+    } src_udfy_jpeg;
+
+    /* 0x00000450 reg276 */
+    struct {
+        RK_U32 csc_wgt_b2u_jpeg    : 9;
+        RK_U32 csc_wgt_g2u_jpeg    : 9;
+        RK_U32 csc_wgt_r2u_jpeg    : 9;
+        RK_U32 reserved            : 5;
+    } src_udfu_jpeg;
+
+    /* 0x00000454 reg277 */
+    struct {
+        RK_U32 csc_wgt_b2v_jpeg    : 9;
+        RK_U32 csc_wgt_g2v_jpeg    : 9;
+        RK_U32 csc_wgt_r2v_jpeg    : 9;
+        RK_U32 reserved            : 5;
+    } src_udfv_jpeg;
+
+    /* 0x00000458 reg278 */
+    struct {
+        RK_U32 csc_ofst_v_jpeg    : 8;
+        RK_U32 csc_ofst_u_jpeg    : 8;
+        RK_U32 csc_ofst_y_jpeg    : 5;
+        RK_U32 reserved           : 11;
+    } src_udfo_jpeg;
+
+    /* 0x0000045c reg279 */
+    struct {
+        RK_U32 cr_force_value_jpeg     : 8;
+        RK_U32 cb_force_value_jpeg     : 8;
+        RK_U32 chroma_force_en_jpeg    : 1;
+        RK_U32 reserved                : 9;
+        RK_U32 src_mirr_jpeg           : 1;
+        RK_U32 src_rot_jpeg            : 2;
+        RK_U32 reserved1               : 1;
+        RK_U32 rkfbcd_en_jpeg          : 1;
+        RK_U32 reserved2               : 1;
+    } src_proc_jpeg;
+
+    /* 0x00000460 reg280 */
+    struct {
+        RK_U32 pic_ofst_x_jpeg    : 14;
+        RK_U32 reserved           : 2;
+        RK_U32 pic_ofst_y_jpeg    : 14;
+        RK_U32 reserved1          : 2;
+    } pic_ofst_jpeg;
+
+    /* 0x00000464 reg281 */
+    struct {
+        RK_U32 src_strd0_jpeg    : 21;
+        RK_U32 reserved          : 11;
+    } src_strd0_jpeg;
+
+    /* 0x00000468 reg282 */
+    struct {
+        RK_U32 src_strd1_jpeg    : 16;
+        RK_U32 reserved          : 16;
+    } src_strd1_jpeg;
+
+    /* 0x0000046c reg283 */
+    struct {
+        RK_U32 pp_corner_filter_strength_jpeg      : 2;
+        RK_U32 reserved                            : 2;
+        RK_U32 pp_edge_filter_strength_jpeg        : 2;
+        RK_U32 reserved1                           : 2;
+        RK_U32 pp_internal_filter_strength_jpeg    : 2;
+        RK_U32 reserved2                           : 22;
+    } src_flt_cfg_jpeg;
+
+    /* 0x00000470 reg284 */
+    struct {
+        RK_U32 jpeg_bias_y    : 15;
+        RK_U32 reserved       : 17;
+    } jpeg_y_cfg;
+
+    /* 0x00000474 reg285 */
+    struct {
+        RK_U32 jpeg_bias_u    : 15;
+        RK_U32 reserved       : 17;
+    } jpeg_u_cfg;
+
+    /* 0x00000478 reg286 */
+    struct {
+        RK_U32 jpeg_bias_v    : 15;
+        RK_U32 reserved       : 17;
+    } jpeg_v_cfg;
+
+    /* 0x0000047c reg287 */
+    struct {
+        RK_U32 jpeg_ri              : 25;
+        RK_U32 jpeg_out_mode        : 1;
+        RK_U32 jpeg_start_rst_m     : 3;
+        RK_U32 jpeg_pic_last_ecs    : 1;
+        RK_U32 reserved             : 1;
+        RK_U32 jpeg_stnd            : 1;
+    } jpeg_base_cfg;
+
+    /* 0x00000480 reg288 */
+    struct {
+        RK_U32 uvc_partition0_len_jpeg    : 12;
+        RK_U32 uvc_partition_len_jpeg     : 12;
+        RK_U32 uvc_skip_len_jpeg          : 6;
+        RK_U32 reserved                   : 2;
+    } uvc_cfg_jpeg;
+
+    /* 0x00000484 reg289 */
+    struct {
+        RK_U32 reserved          : 4;
+        RK_U32 eslf_badr_jpeg    : 28;
+    } adr_eslf_jpeg;
+
+    /* 0x00000488 reg290 */
+    struct {
+        RK_U32 eslf_rptr_jpeg    : 10;
+        RK_U32 eslf_wptr_jpeg    : 10;
+        RK_U32 eslf_blen_jpeg    : 10;
+        RK_U32 eslf_updt_jpeg    : 2;
+    } eslf_buf_jpeg;
+
+    /* 0x48c */
+    RK_U32 reserved_291;
+
+    /* 0x00000490 reg292 */
+    struct {
+        RK_U32 roi0_rdoq_start_x    : 11;
+        RK_U32 roi0_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi0_rdoq_level      : 6;
+        RK_U32 roi0_rdoq_en         : 1;
+    } jpeg_roi0_cfg0;
+
+    /* 0x00000494 reg293 */
+    struct {
+        RK_U32 roi0_rdoq_width_m1     : 11;
+        RK_U32 roi0_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 3;
+        RK_U32 frm_rdoq_level         : 6;
+        RK_U32 frm_rdoq_en            : 1;
+    } jpeg_roi0_cfg1;
+
+    /* 0x00000498 reg294 */
+    struct {
+        RK_U32 roi1_rdoq_start_x    : 11;
+        RK_U32 roi1_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi1_rdoq_level      : 6;
+        RK_U32 roi1_rdoq_en         : 1;
+    } jpeg_roi1_cfg0;
+
+    /* 0x0000049c reg295 */
+    struct {
+        RK_U32 roi1_rdoq_width_m1     : 11;
+        RK_U32 roi1_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi1_cfg1;
+
+    /* 0x000004a0 reg296 */
+    struct {
+        RK_U32 roi2_rdoq_start_x    : 11;
+        RK_U32 roi2_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi2_rdoq_level      : 6;
+        RK_U32 roi2_rdoq_en         : 1;
+    } jpeg_roi2_cfg0;
+
+    /* 0x000004a4 reg297 */
+    struct {
+        RK_U32 roi2_rdoq_width_m1     : 11;
+        RK_U32 roi2_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi2_cfg1;
+
+    /* 0x000004a8 reg298 */
+    struct {
+        RK_U32 roi3_rdoq_start_x    : 11;
+        RK_U32 roi3_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi3_rdoq_level      : 6;
+        RK_U32 roi3_rdoq_en         : 1;
+    } jpeg_roi3_cfg0;
+
+    /* 0x000004ac reg299 */
+    struct {
+        RK_U32 roi3_rdoq_width_m1     : 11;
+        RK_U32 roi3_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi3_cfg1;
+
+    /* 0x000004b0 reg300 */
+    struct {
+        RK_U32 roi4_rdoq_start_x    : 11;
+        RK_U32 roi4_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi4_rdoq_level      : 6;
+        RK_U32 roi4_rdoq_en         : 1;
+    } jpeg_roi4_cfg0;
+
+    /* 0x000004b4 reg301 */
+    struct {
+        RK_U32 roi4_rdoq_width_m1     : 11;
+        RK_U32 roi4_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi4_cfg1;
+
+    /* 0x000004b8 reg302 */
+    struct {
+        RK_U32 roi5_rdoq_start_x    : 11;
+        RK_U32 roi5_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi5_rdoq_level      : 6;
+        RK_U32 roi5_rdoq_en         : 1;
+    } jpeg_roi5_cfg0;
+
+    /* 0x000004bc reg303 */
+    struct {
+        RK_U32 roi5_rdoq_width_m1     : 11;
+        RK_U32 roi5_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi5_cfg1;
+
+    /* 0x000004c0 reg304 */
+    struct {
+        RK_U32 roi6_rdoq_start_x    : 11;
+        RK_U32 roi6_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi6_rdoq_level      : 6;
+        RK_U32 roi6_rdoq_en         : 1;
+    } jpeg_roi6_cfg0;
+
+    /* 0x000004c4 reg305 */
+    struct {
+        RK_U32 roi6_rdoq_width_m1     : 11;
+        RK_U32 roi6_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi6_cfg1;
+
+    /* 0x000004c8 reg306 */
+    struct {
+        RK_U32 roi7_rdoq_start_x    : 11;
+        RK_U32 roi7_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi7_rdoq_level      : 6;
+        RK_U32 roi7_rdoq_en         : 1;
+    } jpeg_roi7_cfg0;
+
+    /* 0x000004cc reg307 */
+    struct {
+        RK_U32 roi7_rdoq_width_m1     : 11;
+        RK_U32 roi7_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi7_cfg1;
+
+    /* 0x000004d0 reg308 */
+    struct {
+        RK_U32 roi8_rdoq_start_x    : 11;
+        RK_U32 roi8_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi8_rdoq_level      : 6;
+        RK_U32 roi8_rdoq_en         : 1;
+    } jpeg_roi8_cfg0;
+
+    /* 0x000004d4 reg309 */
+    struct {
+        RK_U32 roi8_rdoq_width_m1     : 11;
+        RK_U32 roi8_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi8_cfg1;
+
+    /* 0x000004d8 reg310 */
+    struct {
+        RK_U32 roi9_rdoq_start_x    : 11;
+        RK_U32 roi9_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi9_rdoq_level      : 6;
+        RK_U32 roi9_rdoq_en         : 1;
+    } jpeg_roi9_cfg0;
+
+    /* 0x000004dc reg311 */
+    struct {
+        RK_U32 roi9_rdoq_width_m1     : 11;
+        RK_U32 roi9_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi9_cfg1;
+
+    /* 0x000004e0 reg312 */
+    struct {
+        RK_U32 roi10_rdoq_start_x    : 11;
+        RK_U32 roi10_rdoq_start_y    : 11;
+        RK_U32 reserved              : 3;
+        RK_U32 roi10_rdoq_level      : 6;
+        RK_U32 roi10_rdoq_en         : 1;
+    } jpeg_roi10_cfg0;
+
+    /* 0x000004e4 reg313 */
+    struct {
+        RK_U32 roi10_rdoq_width_m1     : 11;
+        RK_U32 roi10_rdoq_height_m1    : 11;
+        RK_U32 reserved                : 10;
+    } jpeg_roi10_cfg1;
+
+    /* 0x000004e8 reg314 */
+    struct {
+        RK_U32 roi11_rdoq_start_x    : 11;
+        RK_U32 roi11_rdoq_start_y    : 11;
+        RK_U32 reserved              : 3;
+        RK_U32 roi11_rdoq_level      : 6;
+        RK_U32 roi11_rdoq_en         : 1;
+    } jpeg_roi11_cfg0;
+
+    /* 0x000004ec reg315 */
+    struct {
+        RK_U32 roi11_rdoq_width_m1     : 11;
+        RK_U32 roi11_rdoq_height_m1    : 11;
+        RK_U32 reserved                : 10;
+    } jpeg_roi11_cfg1;
+
+    /* 0x000004f0 reg316 */
+    struct {
+        RK_U32 roi12_rdoq_start_x    : 11;
+        RK_U32 roi12_rdoq_start_y    : 11;
+        RK_U32 reserved              : 3;
+        RK_U32 roi12_rdoq_level      : 6;
+        RK_U32 roi12_rdoq_en         : 1;
+    } jpeg_roi12_cfg0;
+
+    /* 0x000004f4 reg317 */
+    struct {
+        RK_U32 roi12_rdoq_width_m1     : 11;
+        RK_U32 roi12_rdoq_height_m1    : 11;
+        RK_U32 reserved                : 10;
+    } jpeg_roi12_cfg1;
+
+    /* 0x000004f8 reg318 */
+    struct {
+        RK_U32 roi13_rdoq_start_x    : 11;
+        RK_U32 roi13_rdoq_start_y    : 11;
+        RK_U32 reserved              : 3;
+        RK_U32 roi13_rdoq_level      : 6;
+        RK_U32 roi13_rdoq_en         : 1;
+    } jpeg_roi13_cfg0;
+
+    /* 0x000004fc reg319 */
+    struct {
+        RK_U32 roi13_rdoq_width_m1     : 11;
+        RK_U32 roi13_rdoq_height_m1    : 11;
+        RK_U32 reserved                : 10;
+    } jpeg_roi13_cfg1;
+
+    /* 0x00000500 reg320 */
+    struct {
+        RK_U32 roi14_rdoq_start_x    : 11;
+        RK_U32 roi14_rdoq_start_y    : 11;
+        RK_U32 reserved              : 3;
+        RK_U32 roi14_rdoq_level      : 6;
+        RK_U32 roi14_rdoq_en         : 1;
+    } jpeg_roi14_cfg0;
+
+    /* 0x00000504 reg321 */
+    struct {
+        RK_U32 roi14_rdoq_width_m1     : 11;
+        RK_U32 roi14_rdoq_height_m1    : 11;
+        RK_U32 reserved                : 10;
+    } jpeg_roi14_cfg1;
+
+    /* 0x00000508 reg322 */
+    struct {
+        RK_U32 roi15_rdoq_start_x    : 11;
+        RK_U32 roi15_rdoq_start_y    : 11;
+        RK_U32 reserved              : 3;
+        RK_U32 roi15_rdoq_level      : 6;
+        RK_U32 roi15_rdoq_en         : 1;
+    } jpeg_roi15_cfg0;
+
+    /* 0x0000050c reg323 */
+    struct {
+        RK_U32 roi15_rdoq_width_m1     : 11;
+        RK_U32 roi15_rdoq_height_m1    : 11;
+        RK_U32 reserved                : 10;
+    } jpeg_roi15_cfg1;
+
+    /* 0x510 - 0x51c */
+    RK_U32 reserved324_327[4];
+
+    /* 0x00000520 reg328 */
+    struct {
+        RK_U32 reserved        : 4;
+        RK_U32 base_addr_md    : 28;
+    } adr_md_vpp;
+
+    /* 0x00000524 reg329 */
+    struct {
+        RK_U32 reserved        : 4;
+        RK_U32 base_addr_od    : 28;
+    } adr_od_vpp;
+
+    /* 0x00000528 reg330 */
+    struct {
+        RK_U32 reserved             : 4;
+        RK_U32 base_addr_ref_mdw    : 28;
+    } adr_ref_mdw;
+
+    /* 0x0000052c reg331 */
+    struct {
+        RK_U32 reserved             : 4;
+        RK_U32 base_addr_ref_mdr    : 28;
+    } adr_ref_mdr;
+
+    /* 0x00000530 reg332 */
+    struct {
+        RK_U32 sto_stride_md          : 8;
+        RK_U32 sto_stride_od          : 8;
+        RK_U32 cur_frm_en_md          : 1;
+        RK_U32 ref_frm_en_md          : 1;
+        RK_U32 switch_sad_md          : 2;
+        RK_U32 night_mode_en_md       : 1;
+        RK_U32 flycatkin_flt_en_md    : 1;
+        RK_U32 en_od                  : 1;
+        RK_U32 background_en_od       : 1;
+        RK_U32 sad_comp_en_od         : 1;
+        RK_U32 reserved               : 6;
+        RK_U32 vepu_pp_en             : 1;
+    } vpp_base_cfg;
+
+    /* 0x00000534 reg333 */
+    struct {
+        RK_U32 thres_sad_md          : 12;
+        RK_U32 thres_move_md         : 3;
+        RK_U32 reserved              : 1;
+        RK_U32 thres_dust_move_md    : 4;
+        RK_U32 thres_dust_blk_md     : 3;
+        RK_U32 reserved1             : 1;
+        RK_U32 thres_dust_chng_md    : 8;
+    } thd_md_vpp;
+
+    /* 0x00000538 reg334 */
+    struct {
+        RK_U32 thres_complex_od        : 12;
+        RK_U32 thres_complex_cnt_od    : 3;
+        RK_U32 thres_sad_od            : 14;
+        RK_U32 reserved                : 3;
+    } thd_od_vpp;
+} H264eVepu511Frame;
+
+/* class: param */
+/* 0x00001700 reg1472 - 0x000019cc reg1651 */
+typedef struct H264eVepu511Param_t {
+    /* 0x00001700 reg1472 */
+    struct {
+        RK_U32 iprd_tthdy4_0    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 iprd_tthdy4_1    : 12;
+        RK_U32 reserved1        : 4;
+    } iprd_tthdy4_0;
+
+    /* 0x00001704 reg1473 */
+    struct {
+        RK_U32 iprd_tthdy4_2    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 iprd_tthdy4_3    : 12;
+        RK_U32 reserved1        : 4;
+    } iprd_tthdy4_1;
+
+    /* 0x00001708 reg1474 */
+    struct {
+        RK_U32 iprd_tthdc8_0    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 iprd_tthdc8_1    : 12;
+        RK_U32 reserved1        : 4;
+    } iprd_tthdc8_0;
+
+    /* 0x0000170c reg1475 */
+    struct {
+        RK_U32 iprd_tthdc8_2    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 iprd_tthdc8_3    : 12;
+        RK_U32 reserved1        : 4;
+    } iprd_tthdc8_1;
+
+    /* 0x00001710 reg1476 */
+    struct {
+        RK_U32 iprd_tthdy8_0    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 iprd_tthdy8_1    : 12;
+        RK_U32 reserved1        : 4;
+    } iprd_tthdy8_0;
+
+    /* 0x00001714 reg1477 */
+    struct {
+        RK_U32 iprd_tthdy8_2    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 iprd_tthdy8_3    : 12;
+        RK_U32 reserved1        : 4;
+    } iprd_tthdy8_1;
+
+    /* 0x00001718 reg1478 */
+    struct {
+        RK_U32 iprd_tthd_ul    : 12;
+        RK_U32 reserved        : 20;
+    } iprd_tthd_ul;
+
+    /* 0x0000171c reg1479 */
+    struct {
+        RK_U32 iprd_wgty8_0    : 8;
+        RK_U32 iprd_wgty8_1    : 8;
+        RK_U32 iprd_wgty8_2    : 8;
+        RK_U32 iprd_wgty8_3    : 8;
+    } iprd_wgty8;
+
+    /* 0x00001720 reg1480 */
+    struct {
+        RK_U32 iprd_wgty4_0    : 8;
+        RK_U32 iprd_wgty4_1    : 8;
+        RK_U32 iprd_wgty4_2    : 8;
+        RK_U32 iprd_wgty4_3    : 8;
+    } iprd_wgty4;
+
+    /* 0x00001724 reg1481 */
+    struct {
+        RK_U32 iprd_wgty16_0    : 8;
+        RK_U32 iprd_wgty16_1    : 8;
+        RK_U32 iprd_wgty16_2    : 8;
+        RK_U32 iprd_wgty16_3    : 8;
+    } iprd_wgty16;
+
+    /* 0x00001728 reg1482 */
+    struct {
+        RK_U32 iprd_wgtc8_0    : 8;
+        RK_U32 iprd_wgtc8_1    : 8;
+        RK_U32 iprd_wgtc8_2    : 8;
+        RK_U32 iprd_wgtc8_3    : 8;
+    } iprd_wgtc8;
+
+    /* 0x172c */
+    RK_U32 reserved_1483;
+
+    /* 0x00001730 reg1484 */
+    struct {
+        RK_U32 bias_madi_th0    : 8;
+        RK_U32 bias_madi_th1    : 8;
+        RK_U32 bias_madi_th2    : 8;
+        RK_U32 reserved         : 8;
+    } bias_madi_thd_comb;
+
+    /* 0x00001738 reg1486 */
+    struct {
+        RK_U32 bias_i_val3    : 10;
+        RK_U32 reserved       : 22;
+    } qnt1_i_bias_comb;
+
+    /* 0x0000173c reg1487 */
+    struct {
+        RK_U32 bias_p_val0    : 10;
+        RK_U32 bias_p_val1    : 10;
+        RK_U32 bias_p_val2    : 10;
+        RK_U32 reserved       : 2;
+    } qnt0_p_bias_comb;
+
+    /* 0x00001740 reg1488 */
+    struct {
+        RK_U32 bias_p_val3    : 10;
+        RK_U32 reserved       : 22;
+    } qnt1_p_bias_comb;
+
+    /* 0x1744 - 0x175c */
+    RK_U32 reserved1489_1495[7];
+
+    /* 0x00001760 reg1496 */
+    struct {
+        RK_U32 cime_pmv_num      : 1;
+        RK_U32 cime_fuse         : 1;
+        RK_U32 reserved          : 2;
+        RK_U32 move_lambda       : 4;
+        RK_U32 rime_lvl_mrg      : 2;
+        RK_U32 rime_prelvl_en    : 2;
+        RK_U32 rime_prersu_en    : 3;
+        RK_U32 fme_lvl_mrg       : 1;
+        RK_U32 reserved1         : 16;
+    } me_sqi_comb;
+
+    /* 0x00001764 reg1497 */
+    struct {
+        RK_U32 cime_mvd_th0    : 9;
+        RK_U32 reserved        : 1;
+        RK_U32 cime_mvd_th1    : 9;
+        RK_U32 reserved1       : 1;
+        RK_U32 cime_mvd_th2    : 9;
+        RK_U32 reserved2       : 3;
+    }  cime_mvd_th_comb;
+
+    /* 0x00001768 reg1498 */
+    struct {
+        RK_U32 cime_madp_th       : 12;
+        RK_U32 ratio_consi_cfg    : 4;
+        RK_U32 ratio_bmv_dist     : 4;
+        RK_U32 reserved           : 12;
+    } cime_madp_th_comb;
+
+    /* 0x0000176c reg1499 */
+    struct {
+        RK_U32 cime_multi0    : 8;
+        RK_U32 cime_multi1    : 8;
+        RK_U32 cime_multi2    : 8;
+        RK_U32 cime_multi3    : 8;
+    } cime_multi_comb;
+
+    /* 0x00001770 reg1500 */
+    struct {
+        RK_U32 rime_mvd_th0    : 3;
+        RK_U32 reserved        : 1;
+        RK_U32 rime_mvd_th1    : 3;
+        RK_U32 reserved1       : 9;
+        RK_U32 fme_madp_th     : 12;
+        RK_U32 reserved2       : 4;
+    } rime_mvd_th_comb;
+
+    /* 0x00001774 reg1501 */
+    struct {
+        RK_U32 rime_madp_th0    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 rime_madp_th1    : 12;
+        RK_U32 reserved1        : 4;
+    } rime_madp_th_comb;
+
+    /* 0x00001778 reg1502 */
+    struct {
+        RK_U32 rime_multi0    : 10;
+        RK_U32 rime_multi1    : 10;
+        RK_U32 rime_multi2    : 10;
+        RK_U32 reserved       : 2;
+    } rime_multi_comb;
+
+    /* 0x0000177c reg1503 */
+    struct {
+        RK_U32 cmv_th0     : 8;
+        RK_U32 cmv_th1     : 8;
+        RK_U32 cmv_th2     : 8;
+        RK_U32 reserved    : 8;
+    } cmv_st_th_comb;
+
+    /* 0x1780 - 0x18fc */
+    RK_U32 reserved1504_1599[96];
+
+    /* 0x00001900 reg1600 - 0x000019cc reg1651*/
+    RK_U32 rdo_wgta_qp_grpa_0_51[52];
+} H264eVepu511Param;
+
+/* class: rdo/q_i */
+/* 0x00002000 reg2048 - 0x000020b8 reg2094 */
+typedef struct H264eVepu511SqiCfg_t {
+    /* 0x00002000 reg2048 - 0x00002010 reg2052*/
+    RK_U32 reserved_2048_2052[5];
+
+    /* 0x00002014 reg2053 */
+    struct {
+        RK_U32 rdo_smear_lvl16_multi    : 8;
+        RK_U32 rdo_smear_dlt_qp         : 4;
+        RK_U32 reserved                 : 1;
+        RK_U32 stated_mode              : 2;
+        RK_U32 rdo_smear_en             : 1;
+        RK_U32 reserved1                : 16;
+    } smear_opt_cfg;
+
+    /* 0x00002018 reg2054 */
+    struct {
+        RK_U32 madp_cur_thd0    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 madp_cur_thd1    : 12;
+        RK_U32 reserved1        : 4;
+    } smear_madp_thd0;
+
+    /* 0x0000201c reg2055 */
+    struct {
+        RK_U32 madp_cur_thd2    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 madp_cur_thd3    : 12;
+        RK_U32 reserved1        : 4;
+    } smear_madp_thd1;
+
+    /* 0x00002020 reg2056 */
+    struct {
+        RK_U32 madp_around_thd0    : 12;
+        RK_U32 reserved            : 4;
+        RK_U32 madp_around_thd1    : 12;
+        RK_U32 reserved1           : 4;
+    } smear_madp_thd2;
+
+    /* 0x00002024 reg2057 */
+    struct {
+        RK_U32 madp_around_thd2    : 12;
+        RK_U32 reserved            : 4;
+        RK_U32 madp_around_thd3    : 12;
+        RK_U32 reserved1           : 4;
+    } smear_madp_thd3;
+
+    /* 0x00002028 reg2058 */
+    struct {
+        RK_U32 madp_around_thd4    : 12;
+        RK_U32 reserved            : 4;
+        RK_U32 madp_around_thd5    : 12;
+        RK_U32 reserved1           : 4;
+    } smear_madp_thd4;
+
+    /* 0x0000202c reg2059 */
+    struct {
+        RK_U32 madp_ref_thd0    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 madp_ref_thd1    : 12;
+        RK_U32 reserved1        : 4;
+    } smear_madp_thd5;
+
+    /* 0x00002030 reg2060 */
+    struct {
+        RK_U32 cnt_cur_thd0    : 4;
+        RK_U32 reserved        : 4;
+        RK_U32 cnt_cur_thd1    : 4;
+        RK_U32 reserved1       : 4;
+        RK_U32 cnt_cur_thd2    : 4;
+        RK_U32 reserved2       : 4;
+        RK_U32 cnt_cur_thd3    : 4;
+        RK_U32 reserved3       : 4;
+    } smear_cnt_thd0;
+
+    /* 0x00002034 reg2061 */
+    struct {
+        RK_U32 cnt_around_thd0    : 4;
+        RK_U32 reserved           : 4;
+        RK_U32 cnt_around_thd1    : 4;
+        RK_U32 reserved1          : 4;
+        RK_U32 cnt_around_thd2    : 4;
+        RK_U32 reserved2          : 4;
+        RK_U32 cnt_around_thd3    : 4;
+        RK_U32 reserved3          : 4;
+    } smear_cnt_thd1;
+
+    /* 0x00002038 reg2062 */
+    struct {
+        RK_U32 cnt_around_thd4    : 4;
+        RK_U32 reserved           : 4;
+        RK_U32 cnt_around_thd5    : 4;
+        RK_U32 reserved1          : 4;
+        RK_U32 cnt_around_thd6    : 4;
+        RK_U32 reserved2          : 4;
+        RK_U32 cnt_around_thd7    : 4;
+        RK_U32 reserved3          : 4;
+    } smear_cnt_thd2;
+
+    /* 0x0000203c reg2063 */
+    struct {
+        RK_U32 cnt_ref_thd0    : 4;
+        RK_U32 reserved        : 4;
+        RK_U32 cnt_ref_thd1    : 4;
+        RK_U32 reserved1       : 20;
+    } smear_cnt_thd3;
+
+    /* 0x00002040 reg2064 */
+    struct {
+        RK_U32 resi_small_cur_th0    : 6;
+        RK_U32 reserved              : 2;
+        RK_U32 resi_big_cur_th0      : 6;
+        RK_U32 reserved1             : 2;
+        RK_U32 resi_small_cur_th1    : 6;
+        RK_U32 reserved2             : 2;
+        RK_U32 resi_big_cur_th1      : 6;
+        RK_U32 reserved3             : 2;
+    } smear_resi_thd0;
+
+    /* 0x00002044 reg2065 */
+    struct {
+        RK_U32 resi_small_around_th0    : 6;
+        RK_U32 reserved                 : 2;
+        RK_U32 resi_big_around_th0      : 6;
+        RK_U32 reserved1                : 2;
+        RK_U32 resi_small_around_th1    : 6;
+        RK_U32 reserved2                : 2;
+        RK_U32 resi_big_around_th1      : 6;
+        RK_U32 reserved3                : 2;
+    } smear_resi_thd1;
+
+    /* 0x00002048 reg2066 */
+    struct {
+        RK_U32 resi_small_around_th2    : 6;
+        RK_U32 reserved                 : 2;
+        RK_U32 resi_big_around_th2      : 6;
+        RK_U32 reserved1                : 2;
+        RK_U32 resi_small_around_th3    : 6;
+        RK_U32 reserved2                : 2;
+        RK_U32 resi_big_around_th3      : 6;
+        RK_U32 reserved3                : 2;
+    } smear_resi_thd2;
+
+    /* 0x0000204c reg2067 */
+    struct {
+        RK_U32 resi_small_ref_th0    : 6;
+        RK_U32 reserved              : 2;
+        RK_U32 resi_big_ref_th0      : 6;
+        RK_U32 reserved1             : 18;
+    } smear_resi_thd3;
+
+    /* 0x00002050 reg2068 */
+    struct {
+        RK_U32 resi_th0    : 8;
+        RK_U32 reserved    : 8;
+        RK_U32 resi_th1    : 8;
+        RK_U32 reserved1   : 8;
+    } smear_resi_thd4;
+
+    /* 0x00002054 reg2069 */
+    struct {
+        RK_U32 madp_cnt_th0    : 4;
+        RK_U32 madp_cnt_th1    : 4;
+        RK_U32 madp_cnt_th2    : 4;
+        RK_U32 madp_cnt_th3    : 4;
+        RK_U32 reserved        : 16;
+    } smear_st_thd;
+
+    /* 0x2058 - 0x206c */
+    RK_U32 reserved_2070;
+
+    /* 0x0000205c reg2071 */
+    struct {
+        RK_U32 lid_grdn_blk_cu16_th       : 8;
+        RK_U32 lid_rmd_intra_jcoef_ang    : 5;
+        RK_U32 lid_rdo_intra_rcoef_ang    : 5;
+        RK_U32 lid_rmd_intra_jcoef_dp     : 6;
+        RK_U32 lid_rdo_intra_rcoef_dp     : 6;
+        RK_U32 lid_en                     : 1;
+        RK_U32 reserved                   : 1;
+    } line_intra_dir_cfg;
+
+    RK_U32 reserved2072_2075[4];
+
+    /* 0x00002070 reg2076 - 0x0000207c reg2079*/
+    rdo_skip_par rdo_b16_skip;
+
+    /* 0x00002080 reg2080 - 0x00002088 reg2082 */
+    RK_U32 reserved2080_2082[3];
+
+    /* 0x0000208c reg2083 - 0x00002094 reg2085 */
+    rdo_noskip_par rdo_b16_inter;
+
+    /* 0x00002098 reg2086 - 0x000020a4 reg2088 */
+    RK_U32 reserved2086_2088[3];
+
+    /* 0x000020a8 reg2089 - 0x000020ac reg2091 */
+    rdo_noskip_par rdo_b16_intra;
+
+    /* 0x000020b0 reg2092 */
+    RK_U32 reserved2092;
+
+    /* 0x000020b4 reg2093 */
+    struct {
+        RK_U32 thd0         : 4;
+        RK_U32 reserved     : 4;
+        RK_U32 thd1         : 4;
+        RK_U32 reserved1    : 4;
+        RK_U32 thd2         : 4;
+        RK_U32 reserved2    : 4;
+        RK_U32 thd3         : 4;
+        RK_U32 reserved3    : 4;
+    } rdo_b16_intra_atf_cnt_thd;
+
+    /* 0x000020b8 reg2094 */
+    struct {
+        RK_U32 big_th0      : 6;
+        RK_U32 reserved     : 2;
+        RK_U32 big_th1      : 6;
+        RK_U32 reserved1    : 2;
+        RK_U32 small_th0    : 6;
+        RK_U32 reserved2    : 2;
+        RK_U32 small_th1    : 6;
+        RK_U32 reserved3    : 2;
+    } rdo_atf_resi_thd;
+
+    /* 0x000020bc reg2095 - 0x0000215c reg2135*/
+    RK_U32 reserved_2095_2135[40];
+
+    /* 0x00002160 reg2136 */
+    struct {
+        RK_U32 atr_thd0    : 8;
+        RK_U32 atr_thd1    : 8;
+        RK_U32 atr_thd2    : 8;
+        RK_U32 atr_qp      : 6;
+        RK_U32 reserved    : 2;
+    } atr_thd;
+
+    /* 0x00002164 reg2137 */
+    struct {
+        RK_U32 atr_lv16_wgt0    : 8;
+        RK_U32 atr_lv16_wgt1    : 8;
+        RK_U32 atr_lv16_wgt2    : 8;
+        RK_U32 reserved         : 8;
+    } atr_wgt16;
+
+    /* 0x00002168 reg2138 */
+    struct {
+        RK_U32 atr_lv8_wgt0    : 8;
+        RK_U32 atr_lv8_wgt1    : 8;
+        RK_U32 atr_lv8_wgt2    : 8;
+        RK_U32 reserved        : 8;
+    } atr_wgt8;
+
+    /* 0x0000216c reg2139 */
+    struct {
+        RK_U32 atr_lv4_wgt0    : 8;
+        RK_U32 atr_lv4_wgt1    : 8;
+        RK_U32 atr_lv4_wgt2    : 8;
+        RK_U32 reserved        : 8;
+    } atr_wgt4;
+} H264eVepu511Sqi;
+
+/* class: scaling list  */
+/* 0x00002200 reg2176- 0x0000268c reg2467*/
+typedef struct H264eVepu511SclCfg_t {
+    /* 0x2200 - 0x227c, valid for h.264 iq_scal_t8_intra0~15 iq_scal_t8_inter0~15*/
+    RK_U32 tu8_intra_y[16];
+    RK_U32 tu8_intra_u[16];
+
+    /* 0x2280 - 0x258c*/
+    RK_U32 reserved_2208_2215[196];
+
+    /* 0x2590 - 0x268c, valid for h.264 q_scal_t8_intra0~31 q_scal_t8_inter0~31*/
+    RK_U32 q_t8_intra[32];
+    RK_U32 q_t8_inter[32];
+} H264eVepu511SclCfg;
+
+typedef struct HalVepu511Reg_t {
+    Vepu511ControlCfg       reg_ctl;
+    H264eVepu511Frame       reg_frm;
+    Vepu511RcRoi            reg_rc_roi;
+    H264eVepu511Param       reg_param;
+    H264eVepu511Sqi         reg_sqi;
+    H264eVepu511SclCfg      reg_scl;
+    Vepu511OsdRegs          reg_osd;
+    Vepu511Status           reg_st;
+    Vepu511Dbg              reg_dbg;
+} HalVepu511RegSet;
+
+#endif
\ No newline at end of file
diff --git a/mpp/hal/rkenc/h265e/CMakeLists.txt b/mpp/hal/rkenc/h265e/CMakeLists.txt
index 7dd872e6..edfc7f9a 100644
--- a/mpp/hal/rkenc/h265e/CMakeLists.txt
+++ b/mpp/hal/rkenc/h265e/CMakeLists.txt
@@ -10,6 +10,7 @@ set(HAL_H265E_HDR
     hal_h265e_vepu541_reg.h
     hal_h265e_vepu580_reg.h
     hal_h265e_vepu510_reg.h
+    hal_h265e_vepu511_reg.h
     )
 
 # hal h265 encoder sourse
@@ -18,6 +19,7 @@ set(HAL_H265E_SRC
     hal_h265e_vepu580.c
     hal_h265e_vepu540c.c
     hal_h265e_vepu510.c
+    hal_h265e_vepu511.c
     )
 
 add_library(hal_h265e_vepu541 STATIC
diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu511.c b/mpp/hal/rkenc/h265e/hal_h265e_vepu511.c
new file mode 100644
index 00000000..5b61fca1
--- /dev/null
+++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu511.c
@@ -0,0 +1,2721 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG  "hal_h265e_v511"
+
+#include <string.h>
+#include <math.h>
+#include <limits.h>
+
+#include "mpp_env.h"
+#include "mpp_mem.h"
+#include "mpp_common.h"
+#include "mpp_frame_impl.h"
+#include "mpp_packet_impl.h"
+#include "mpp_enc_cb_param.h"
+
+#include "rkv_enc_def.h"
+#include "h265e_syntax_new.h"
+#include "h265e_dpb.h"
+#include "hal_bufs.h"
+#include "hal_h265e_debug.h"
+#include "hal_h265e_vepu511.h"
+#include "hal_h265e_vepu511_reg.h"
+#include "hal_h265e_stream_amend.h"
+
+#include "vepu5xx_common.h"
+#include "vepu541_common.h"
+#include "vepu511_common.h"
+
+#define MAX_FRAME_TASK_NUM      2
+#define H265E_LAMBDA_TAB_SIZE  (52 * sizeof(RK_U32))
+#define H265E_SMEAR_STR_NUM    (8)
+
+#define hal_h265e_err(fmt, ...) \
+    do {\
+        mpp_err_f(fmt, ## __VA_ARGS__);\
+    } while (0)
+
+typedef struct Vepu511H265Fbk_t {
+    RK_U32 hw_status; /* 0:corret, 1:error */
+    RK_U32 frame_type;
+    RK_U32 qp_sum;
+    RK_U32 out_strm_size;
+    RK_U32 out_hw_strm_size;
+    RK_S64 sse_sum;
+    RK_U32 st_lvl64_inter_num;
+    RK_U32 st_lvl32_inter_num;
+    RK_U32 st_lvl16_inter_num;
+    RK_U32 st_lvl8_inter_num;
+    RK_U32 st_lvl32_intra_num;
+    RK_U32 st_lvl16_intra_num;
+    RK_U32 st_lvl8_intra_num;
+    RK_U32 st_lvl4_intra_num;
+    RK_U32 st_cu_num_qp[52];
+    RK_U32 st_madp;
+    RK_U32 st_madi;
+    RK_U32 st_mb_num;
+    RK_U32 st_ctu_num;
+    RK_U32 st_smear_cnt[5];
+    RK_S32 reg_idx;
+    RK_U32 acc_cover16_num;
+    RK_U32 acc_bndry16_num;
+    RK_U32 acc_zero_mv;
+    RK_S8 tgt_sub_real_lvl[6];
+} Vepu511H265Fbk;
+
+typedef struct Vepu511H265eFrmCfg_t {
+    RK_S32              frame_count;
+    RK_S32              frame_type;
+
+    /* dchs cfg on frame parallel */
+    RK_S32              dchs_curr_idx;
+    RK_S32              dchs_prev_idx;
+
+    /* hal dpb management slot idx */
+    RK_S32              hal_curr_idx;
+    RK_S32              hal_refr_idx;
+
+    /* regs cfg */
+    H265eV511RegSet     *regs_set;
+    H265eV511StatusElem *regs_ret;
+
+    /* hardware return info collection cfg */
+    Vepu511H265Fbk      feedback;
+
+    void                *roi_data;
+
+    /* roi buffer for qpmap or gdr */
+    MppBuffer           roir_buf;
+    RK_S32              roir_buf_size;
+    void                *roi_base_cfg_sw_buf;
+
+    /* variable length cfg */
+    MppDevRegOffCfgs    *reg_cfg;
+} Vepu511H265eFrmCfg;
+
+typedef struct H265eV511HalContext_t {
+    MppEncHalApi        api;
+    MppDev              dev;
+    void                *regs;
+    void                *reg_out;
+    Vepu511H265eFrmCfg  *frms[MAX_FRAME_TASK_NUM];
+
+    /* current used frame config */
+    Vepu511H265eFrmCfg  *frm;
+
+    /* slice split poll cfg */
+    RK_S32              poll_slice_max;
+    RK_S32              poll_cfg_size;
+    MppDevPollCfg       *poll_cfgs;
+    MppCbCtx            *output_cb;
+
+    /* @frame_cnt starts from ZERO */
+    RK_S32              frame_count;
+
+    /* frame parallel info */
+    RK_S32              task_cnt;
+    RK_S32              task_idx;
+
+    /* dchs cfg */
+    RK_S32              curr_idx;
+    RK_S32              prev_idx;
+
+    Vepu511H265Fbk      feedback;
+    Vepu511H265Fbk      last_frame_fb;
+    void                *dump_files;
+    RK_U32              frame_cnt_gen_ready;
+
+    RK_S32              frame_type;
+    RK_S32              last_frame_type;
+
+    MppBufferGroup      roi_grp;
+    void                *roi_data;
+    Vepu511OsdCfg       osd_cfg;
+
+    MppEncCfgSet        *cfg;
+    MppDevRegOffCfgs    *reg_cfg;
+    H265eSyntax_new     *syn;
+    H265eDpb            *dpb;
+
+    RK_U32              enc_mode;
+    RK_U32              frame_size;
+    RK_S32              max_buf_cnt;
+    RK_S32              hdr_status;
+    void                *input_fmt;
+    RK_U8               *src_buf;
+    RK_U8               *dst_buf;
+    RK_S32              buf_size;
+    RK_U32              frame_num;
+    HalBufs             dpb_bufs;
+    RK_S32              fbc_header_len;
+    RK_U32              title_num;
+
+    RK_S32              qpmap_en;
+    RK_S32              smart_en;
+
+    /* external line buffer over 3K */
+    MppBufferGroup      ext_line_buf_grp;
+    RK_S32              ext_line_buf_size;
+    MppBuffer           ext_line_buf;
+    MppBuffer           buf_pass1;
+    MppBuffer           ext_line_bufs[MAX_FRAME_TASK_NUM];
+
+    void                *tune;
+} H265eV511HalContext;
+
+static const  RK_U32 lambda_tbl_pre_intra[52] = {
+    4206,   4945,   5814,   6835,   8035,   9446,   11105,  13056,
+    15348,  18044,  21213,  24938,  29318,  34467,  40521,  47637,
+    56003,  65839,  77402,  90996,  106977, 125765, 147852, 173819,
+    204346, 240234, 983,    1206,   1479,   1813,   2223,   2727,
+    3344,   4100,   5028,   6166,   7561,   9272,   11371,  13944,
+    17099,  20969,  25714,  31533,  38669,  47420,  58150,  71310,
+    87447, 107236, 131504, 161263,
+};
+
+static const  RK_U32 lambda_tbl_pre_inter[52] = {
+    760,    959,    1210,   1526,   1925,   2428,   3063,   3864,
+    4874,   6147,   7754,   9781,   12337,  15562,  19629,  24760,
+    31231,  39394,  49691,  62678,  79061,  99725,  125790, 158668,
+    200140, 252451, 579,    730,    919,    1159,   1461,   1993,
+    2898,   3652,   4601,   5411,   6818,   7362,   9276,   11688,
+    14725,  18553,  25324,  31906,  40200,  50649,  68724,  74217,
+    101300, 127630, 148435, 187017,
+};
+
+static RK_U32 rdo_lambda_table_I[60] = {
+    0x00000012, 0x00000017,
+    0x0000001d, 0x00000024, 0x0000002e, 0x0000003a,
+    0x00000049, 0x0000005c, 0x00000074, 0x00000092,
+    0x000000b8, 0x000000e8, 0x00000124, 0x00000170,
+    0x000001cf, 0x00000248, 0x000002df, 0x0000039f,
+    0x0000048f, 0x000005bf, 0x0000073d, 0x0000091f,
+    0x00000b7e, 0x00000e7a, 0x0000123d, 0x000016fb,
+    0x00001cf4, 0x0000247b, 0x00002df6, 0x000039e9,
+    0x000048f6, 0x00005bed, 0x000073d1, 0x000091ec,
+    0x0000b7d9, 0x0000e7a2, 0x000123d7, 0x00016fb2,
+    0x0001cf44, 0x000247ae, 0x0002df64, 0x00039e89,
+    0x00048f5c, 0x0005bec8, 0x00073d12, 0x00091eb8,
+    0x000b7d90, 0x000e7a23, 0x00123d71, 0x0016fb20,
+    0x001cf446, 0x00247ae1, 0x002df640, 0x0039e88c,
+    0x0048f5c3, 0x005bec81, 0x0073d119, 0x0091eb85,
+    0x00b7d902, 0x00e7a232
+};
+
+static RK_U32 rdo_lambda_table_P[60] = {
+    0x0000002c, 0x00000038, 0x00000044, 0x00000058,
+    0x00000070, 0x00000089, 0x000000b0, 0x000000e0,
+    0x00000112, 0x00000160, 0x000001c0, 0x00000224,
+    0x000002c0, 0x00000380, 0x00000448, 0x00000580,
+    0x00000700, 0x00000890, 0x00000b00, 0x00000e00,
+    0x00001120, 0x00001600, 0x00001c00, 0x00002240,
+    0x00002c00, 0x00003800, 0x00004480, 0x00005800,
+    0x00007000, 0x00008900, 0x0000b000, 0x0000e000,
+    0x00011200, 0x00016000, 0x0001c000, 0x00022400,
+    0x0002c000, 0x00038000, 0x00044800, 0x00058000,
+    0x00070000, 0x00089000, 0x000b0000, 0x000e0000,
+    0x00112000, 0x00160000, 0x001c0000, 0x00224000,
+    0x002c0000, 0x00380000, 0x00448000, 0x00580000,
+    0x00700000, 0x00890000, 0x00b00000, 0x00e00000,
+    0x01120000, 0x01600000, 0x01c00000, 0x02240000,
+};
+
+static RK_U8 vepu511_h265_cqm_intra8[64] = {
+    16, 16, 16, 16, 17, 18, 21, 24,
+    16, 16, 16, 16, 17, 19, 22, 25,
+    16, 16, 17, 18, 20, 22, 25, 29,
+    16, 16, 18, 21, 24, 27, 31, 36,
+    17, 17, 20, 24, 30, 35, 41, 47,
+    18, 19, 22, 27, 35, 44, 54, 65,
+    21, 22, 25, 31, 41, 54, 70, 88,
+    24, 25, 29, 36, 47, 65, 88, 115
+};
+
+static RK_U8 vepu511_h265_cqm_inter8[64] = {
+    16, 16, 16, 16, 17, 18, 20, 24,
+    16, 16, 16, 17, 18, 20, 24, 25,
+    16, 16, 17, 18, 20, 24, 25, 28,
+    16, 17, 18, 20, 24, 25, 28, 33,
+    17, 18, 20, 24, 25, 28, 33, 41,
+    18, 20, 24, 25, 28, 33, 41, 54,
+    20, 24, 25, 28, 33, 41, 54, 71,
+    24, 25, 28, 33, 41, 54, 71, 91
+};
+
+void save_to_file_511(char *name, void *ptr, size_t size)
+{
+    FILE *fp = fopen(name, "w+b");
+    if (fp) {
+        fwrite(ptr, 1, size, fp);
+        fclose(fp);
+    } else
+        mpp_err("create file %s failed\n", name);
+}
+
+void vepu511_h265e_dump(H265eV511HalContext *ctx, HalEncTask *enc_task)
+{
+    H265eSyntax_new *syn = ctx->syn;
+    HalBuf *hal_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.ref_pic.slot_idx);
+    size_t buf_size = mpp_buffer_get_size(hal_buf->buf[0]);
+    size_t dws_size = mpp_buffer_get_size(hal_buf->buf[1]);
+    void *ptr = mpp_buffer_get_ptr(hal_buf->buf[0]);
+    void *dws_ptr = mpp_buffer_get_ptr(hal_buf->buf[1]);
+    RK_U32 frm_num = ctx->frms[enc_task->flags.reg_idx]->frame_count;
+    RK_S32 pid = getpid();
+    char name[128];
+    size_t name_len = sizeof(name) - 1;
+
+    snprintf(name, name_len, "/mnt/sdcard/dump/refr_fbd_%d_frm%d.bin", pid, frm_num);
+    save_to_file_511(name, ptr + ctx->fbc_header_len, buf_size - ctx->fbc_header_len);
+
+    snprintf(name, name_len, "/mnt/sdcard/dump/refr_fbh_%d_frm%d.bin", pid, frm_num);
+    save_to_file_511(name, ptr, ctx->fbc_header_len);
+
+    snprintf(name, name_len, "/mnt/sdcard/dump/refr_dsp_%d_frm%d.bin", pid, frm_num);
+    save_to_file_511(name, dws_ptr, dws_size);
+
+    hal_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx);
+    buf_size = mpp_buffer_get_size(hal_buf->buf[0]);
+    dws_size = mpp_buffer_get_size(hal_buf->buf[1]);
+    ptr = mpp_buffer_get_ptr(hal_buf->buf[0]);
+    dws_ptr = mpp_buffer_get_ptr(hal_buf->buf[1]);
+
+    snprintf(name, name_len, "/mnt/sdcard/dump/recn_fbd_%d_frm%d_slot%d.bin", pid, frm_num,  syn->sp.recon_pic.slot_idx);
+    save_to_file_511(name, ptr + ctx->fbc_header_len, buf_size - ctx->fbc_header_len);
+
+    snprintf(name, name_len, "/mnt/sdcard/dump/recn_fbh_%d_frm%d_slot%d.bin", pid, frm_num,  syn->sp.recon_pic.slot_idx);
+    save_to_file_511(name, ptr, ctx->fbc_header_len);
+
+    snprintf(name, name_len, "/mnt/sdcard/dump/recn_dsp_%d_frm%d_slot%d.bin", pid, frm_num,  syn->sp.recon_pic.slot_idx);
+    save_to_file_511(name, dws_ptr, dws_size);
+
+}
+
+static void setup_ext_line_bufs(H265eV511HalContext *ctx)
+{
+    RK_S32 i;
+
+    for (i = 0; i < ctx->task_cnt; i++) {
+        if (ctx->ext_line_bufs[i])
+            continue;
+
+        mpp_buffer_get(ctx->ext_line_buf_grp, &ctx->ext_line_bufs[i],
+                       ctx->ext_line_buf_size);
+    }
+}
+
+static void clear_ext_line_bufs(H265eV511HalContext *ctx)
+{
+    RK_S32 i;
+
+    for (i = 0; i < ctx->task_cnt; i++) {
+        if (ctx->ext_line_bufs[i]) {
+            mpp_buffer_put(ctx->ext_line_bufs[i]);
+            ctx->ext_line_bufs[i] = NULL;
+        }
+    }
+}
+
+static MPP_RET vepu511_h265_setup_hal_bufs(H265eV511HalContext *ctx)
+{
+    MPP_RET ret = MPP_OK;
+    VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
+    RK_U32 frame_size;
+    Vepu541Fmt input_fmt = VEPU541_FMT_YUV420P;
+    RK_S32 mb_wd64, mb_h64;
+    MppEncRefCfg ref_cfg = ctx->cfg->ref_cfg;
+    MppEncPrepCfg *prep = &ctx->cfg->prep;
+    RK_S32 old_max_cnt = ctx->max_buf_cnt;
+    RK_S32 new_max_cnt = 4;
+    RK_S32 alignment = 32;
+    RK_S32 aligned_w = MPP_ALIGN(prep->width,  alignment);
+
+    hal_h265e_enter();
+
+    mb_wd64 = (prep->width + 63) / 64;
+    mb_h64 = (prep->height + 63) / 64 + 1;
+
+    frame_size = MPP_ALIGN(prep->width, 16) * MPP_ALIGN(prep->height, 16);
+    vepu541_set_fmt(fmt, ctx->cfg->prep.format);
+    input_fmt = (Vepu541Fmt)fmt->format;
+    switch (input_fmt) {
+    case VEPU540_FMT_YUV400:
+        break;
+    case VEPU541_FMT_YUV420P:
+    case VEPU541_FMT_YUV420SP: {
+        frame_size = frame_size * 3 / 2;
+    } break;
+    case VEPU541_FMT_YUV422P:
+    case VEPU541_FMT_YUV422SP:
+    case VEPU541_FMT_YUYV422:
+    case VEPU541_FMT_UYVY422:
+    case VEPU541_FMT_BGR565: {
+        frame_size *= 2;
+    } break;
+    case VEPU541_FMT_BGR888:
+    case VEPU580_FMT_YUV444SP:
+    case VEPU580_FMT_YUV444P: {
+        frame_size *= 3;
+    } break;
+    case VEPU541_FMT_BGRA8888: {
+        frame_size *= 4;
+    } break;
+    default: {
+        hal_h265e_err("invalid src color space: %d\n", input_fmt);
+        return MPP_NOK;
+    }
+    }
+
+    if (ref_cfg) {
+        MppEncCpbInfo *info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
+        new_max_cnt = MPP_MAX(new_max_cnt, info->dpb_size + 1);
+    }
+
+    if (aligned_w > SZ_4K) {
+        RK_S32 ctu_w = (aligned_w + 31) / 32;
+        RK_S32 ext_line_buf_size = ((ctu_w - 113) * 27 + 15) / 16 * 16 * 16;
+
+        if (NULL == ctx->ext_line_buf_grp)
+            mpp_buffer_group_get_internal(&ctx->ext_line_buf_grp, MPP_BUFFER_TYPE_ION);
+        else if (ext_line_buf_size != ctx->ext_line_buf_size) {
+            clear_ext_line_bufs(ctx);
+            mpp_buffer_group_clear(ctx->ext_line_buf_grp);
+        }
+
+        mpp_assert(ctx->ext_line_buf_grp);
+        setup_ext_line_bufs(ctx);
+        ctx->ext_line_buf_size = ext_line_buf_size;
+    } else {
+        clear_ext_line_bufs(ctx);
+
+        if (ctx->ext_line_buf_grp) {
+            mpp_buffer_group_clear(ctx->ext_line_buf_grp);
+            mpp_buffer_group_put(ctx->ext_line_buf_grp);
+            ctx->ext_line_buf_grp = NULL;
+        }
+        ctx->ext_line_buf_size = 0;
+    }
+
+    if (frame_size > ctx->frame_size || new_max_cnt > old_max_cnt) {
+        size_t size[4] = {0};
+        RK_S32 ctu_w = (prep->width + 31) / 32;
+        RK_S32 ctu_h = (prep->height + 31) / 32;
+
+        hal_bufs_deinit(ctx->dpb_bufs);
+        hal_bufs_init(&ctx->dpb_bufs);
+
+        ctx->fbc_header_len = MPP_ALIGN(((mb_wd64 * mb_h64) << 6), SZ_8K);
+        size[0] = ctx->fbc_header_len + ((mb_wd64 * mb_h64) << 12) * 3 / 2; //fbc_h + fbc_b
+        size[1] = (mb_wd64 * mb_h64 << 8);
+        size[2] = MPP_ALIGN(mb_wd64 * mb_h64 * 16 * 4, 256) * 16;
+        /* smear bufs */
+        size[3] = MPP_ALIGN(ctu_w, 16) * MPP_ALIGN(ctu_h, 16);
+        new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt);
+
+        hal_h265e_dbg_detail("frame size %d -> %d max count %d -> %d\n",
+                             ctx->frame_size, frame_size, old_max_cnt, new_max_cnt);
+
+        hal_bufs_setup(ctx->dpb_bufs, new_max_cnt, MPP_ARRAY_ELEMS(size), size);
+
+        ctx->frame_size = frame_size;
+        ctx->max_buf_cnt = new_max_cnt;
+    }
+    hal_h265e_leave();
+    return ret;
+}
+
+MPP_RET hal_h265e_vepu511_deinit(void *hal)
+{
+    H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
+    RK_S32 i = 0;
+
+    hal_h265e_enter();
+    MPP_FREE(ctx->poll_cfgs);
+    MPP_FREE(ctx->input_fmt);
+    hal_bufs_deinit(ctx->dpb_bufs);
+
+    for (i = 0; i < ctx->task_cnt; i++) {
+        Vepu511H265eFrmCfg *frm = ctx->frms[i];
+
+        if (!frm)
+            continue;
+
+        if (frm->roir_buf) {
+            mpp_buffer_put(frm->roir_buf);
+            frm->roir_buf = NULL;
+            frm->roir_buf_size = 0;
+        }
+
+        MPP_FREE(frm->roi_base_cfg_sw_buf);
+
+        if (frm->reg_cfg) {
+            mpp_dev_multi_offset_deinit(frm->reg_cfg);
+            frm->reg_cfg = NULL;
+        }
+
+        MPP_FREE(frm->regs_set);
+        MPP_FREE(frm->regs_ret);
+        MPP_FREE(ctx->frms[i]);
+    }
+
+    clear_ext_line_bufs(ctx);
+
+    if (ctx->ext_line_buf_grp) {
+        mpp_buffer_group_put(ctx->ext_line_buf_grp);
+        ctx->ext_line_buf_grp = NULL;
+    }
+
+    if (ctx->buf_pass1) {
+        mpp_buffer_put(ctx->buf_pass1);
+        ctx->buf_pass1 = NULL;
+    }
+
+    if (ctx->dev) {
+        mpp_dev_deinit(ctx->dev);
+        ctx->dev = NULL;
+    }
+
+    if (ctx->reg_cfg) {
+        mpp_dev_multi_offset_deinit(ctx->reg_cfg);
+        ctx->reg_cfg = NULL;
+    }
+
+    if (ctx->roi_grp) {
+        mpp_buffer_group_put(ctx->roi_grp);
+        ctx->roi_grp = NULL;
+    }
+
+    if (ctx->tune) {
+        // vepu511_h265e_tune_deinit(ctx->tune);
+        ctx->tune = NULL;
+    }
+
+    hal_h265e_leave();
+    return MPP_OK;
+}
+
+MPP_RET hal_h265e_vepu511_init(void *hal, MppEncHalCfg *cfg)
+{
+    MPP_RET ret = MPP_OK;
+    H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
+    RK_S32 i = 0;
+
+    mpp_env_get_u32("hal_h265e_debug", &hal_h265e_debug, 0);
+    hal_h265e_enter();
+
+    ctx->task_cnt = cfg->task_cnt;
+    mpp_assert(ctx->task_cnt && ctx->task_cnt <= MAX_FRAME_TASK_NUM);
+    if (ctx->task_cnt > MAX_FRAME_TASK_NUM)
+        ctx->task_cnt = MAX_FRAME_TASK_NUM;
+
+    for (i = 0; i < ctx->task_cnt; i++) {
+        Vepu511H265eFrmCfg *frm_cfg = mpp_calloc(Vepu511H265eFrmCfg, 1);
+
+        frm_cfg->regs_set = mpp_calloc(H265eV511RegSet, 1);
+        frm_cfg->regs_ret = mpp_calloc(H265eV511StatusElem, 1);
+        frm_cfg->frame_type = INTRA_FRAME;
+        ctx->frms[i] = frm_cfg;
+    }
+
+    ctx->input_fmt      = mpp_calloc(VepuFmtCfg, 1);
+    ctx->cfg            = cfg->cfg;
+    hal_bufs_init(&ctx->dpb_bufs);
+
+    ctx->frame_count = -1;
+    ctx->frame_cnt_gen_ready = 0;
+    ctx->enc_mode = 1;
+    cfg->cap_recn_out = 1;
+    cfg->type = VPU_CLIENT_RKVENC;
+    ret = mpp_dev_init(&cfg->dev, cfg->type);
+    if (ret) {
+        mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
+        return ret;
+    }
+    mpp_dev_multi_offset_init(&ctx->reg_cfg, 24);
+    ctx->dev = cfg->dev;
+    ctx->frame_type = INTRA_FRAME;
+
+    {   /* setup default hardware config */
+        MppEncHwCfg *hw = &cfg->cfg->hw;
+        RK_U32 j;
+
+        hw->qp_delta_row_i  = 2;
+        hw->qp_delta_row    = 2;
+        hw->qbias_i         = 171;
+        hw->qbias_p         = 85;
+        hw->qbias_en        = 0;
+
+        for (j = 0; j < MPP_ARRAY_ELEMS(hw->mode_bias); j++)
+            hw->mode_bias[j] = 8;
+    }
+
+    ctx->poll_slice_max = 8;
+    ctx->poll_cfg_size = (sizeof(ctx->poll_cfgs) + sizeof(RK_S32) * ctx->poll_slice_max) * 2;
+    ctx->poll_cfgs = mpp_malloc_size(MppDevPollCfg, ctx->poll_cfg_size);
+
+    if (NULL == ctx->poll_cfgs) {
+        ret = MPP_ERR_MALLOC;
+        mpp_err_f("init poll cfg buffer failed\n");
+        goto DONE;
+    }
+
+    ctx->output_cb = cfg->output_cb;
+    cfg->cap_recn_out = 1;
+
+    // ctx->tune = vepu511_h265e_tune_init(ctx);
+
+DONE:
+    if (ret)
+        hal_h265e_vepu511_deinit(hal);
+
+    hal_h265e_leave();
+    return ret;
+}
+
+static MPP_RET hal_h265e_vepu511_prepare(void *hal)
+{
+    H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
+    MppEncPrepCfg *prep = &ctx->cfg->prep;
+
+    hal_h265e_dbg_func("enter %p\n", hal);
+
+    if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
+        RK_S32 i;
+
+        // pre-alloc required buffers to reduce first frame delay
+        vepu511_h265_setup_hal_bufs(ctx);
+        for (i = 0; i < ctx->max_buf_cnt; i++)
+            hal_bufs_get_buf(ctx->dpb_bufs, i);
+
+        prep->change = 0;
+    }
+
+    hal_h265e_dbg_func("leave %p\n", hal);
+
+    return MPP_OK;
+}
+
+static MPP_RET
+vepu511_h265_set_patch_info(H265eSyntax_new *syn, Vepu541Fmt input_fmt,  MppDevRegOffCfgs *offsets, HalEncTask *task)
+{
+    RK_U32 hor_stride = syn->pp.hor_stride;
+    RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height;
+    RK_U32 frame_size = hor_stride * ver_stride;
+    RK_U32 u_offset = 0, v_offset = 0;
+    MPP_RET ret = MPP_OK;
+
+    if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(task->frame))) {
+        u_offset = mpp_frame_get_fbc_offset(task->frame);
+        v_offset = u_offset;
+    } else {
+        switch (input_fmt) {
+        case VEPU541_FMT_YUV420P: {
+            u_offset = frame_size;
+            v_offset = frame_size * 5 / 4;
+        } break;
+        case VEPU541_FMT_YUV420SP:
+        case VEPU541_FMT_YUV422SP: {
+            u_offset = frame_size;
+            v_offset = frame_size;
+        } break;
+        case VEPU541_FMT_YUV422P: {
+            u_offset = frame_size;
+            v_offset = frame_size * 3 / 2;
+        } break;
+        case VEPU540_FMT_YUV400:
+        case VEPU541_FMT_YUYV422:
+        case VEPU541_FMT_UYVY422: {
+            u_offset = 0;
+            v_offset = 0;
+        } break;
+        case VEPU541_FMT_BGR565:
+        case VEPU541_FMT_BGR888:
+        case VEPU541_FMT_BGRA8888: {
+            u_offset = 0;
+            v_offset = 0;
+        } break;
+        case VEPU580_FMT_YUV444SP : {
+            u_offset = hor_stride * ver_stride;
+            v_offset = hor_stride * ver_stride;
+        } break;
+        case VEPU580_FMT_YUV444P : {
+            u_offset = hor_stride * ver_stride;
+            v_offset = hor_stride * ver_stride * 2;
+        } break;
+        default: {
+            hal_h265e_err("unknown color space: %d\n", input_fmt);
+            u_offset = frame_size;
+            v_offset = frame_size * 5 / 4;
+        }
+        }
+    }
+    mpp_dev_multi_offset_update(offsets, 161, u_offset);
+    mpp_dev_multi_offset_update(offsets, 162, v_offset);
+
+    return ret;
+}
+
+static MPP_RET vepu511_h265e_save_pass1_patch(H265eV511RegSet *regs, H265eV511HalContext *ctx,
+                                              RK_S32 tiles_enabled_flag)
+{
+    H265eVepu511Frame *reg_frm = &regs->reg_frm;
+    RK_S32 width = ctx->cfg->prep.width;
+    RK_S32 height = ctx->cfg->prep.height;
+    RK_S32 width_align = MPP_ALIGN(width, 16);
+    RK_S32 height_align = MPP_ALIGN(height, 16);
+
+    if (NULL == ctx->buf_pass1) {
+        mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2);
+        if (!ctx->buf_pass1) {
+            mpp_err("buf_pass1 malloc fail, debreath invaild");
+            return MPP_NOK;
+        }
+    }
+
+    reg_frm->common.enc_pic.cur_frm_ref = 1;
+    reg_frm->common.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1);
+    reg_frm->common.rfpw_b_addr = reg_frm->common.rfpw_h_addr;
+    reg_frm->common.enc_pic.rec_fbc_dis = 1;
+
+    if (tiles_enabled_flag)
+        reg_frm->synt_pps.lpf_fltr_acrs_til = 0;
+
+    mpp_dev_multi_offset_update(ctx->reg_cfg, 164, width_align * height_align);
+
+    /* NOTE: disable split to avoid lowdelay slice output */
+    reg_frm->common.sli_splt.sli_splt = 0;
+    reg_frm->common.enc_pic.slen_fifo = 0;
+
+    return MPP_OK;
+}
+
+static MPP_RET vepu511_h265e_use_pass1_patch(H265eV511RegSet *regs, H265eV511HalContext *ctx)
+{
+    Vepu511ControlCfg *reg_ctl = &regs->reg_ctl;
+    H265eVepu511Frame *reg_frm = &regs->reg_frm;
+    RK_S32 width_align = MPP_ALIGN(ctx->cfg->prep.width, 16);
+    RK_S32 height_align = MPP_ALIGN(ctx->cfg->prep.height, 16);
+    RK_S32 y_stride = width_align;
+    VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
+    MPP_RET ret = MPP_OK;
+
+    hal_h265e_dbg_func("enter\n");
+
+    reg_frm->common.enc_pic.rfpr_compress_mode = 1;
+    reg_ctl->dtrns_map.src_bus_edin = fmt->src_endian;
+    reg_frm->common.src_fmt.src_cfmt = VEPU541_FMT_YUV420SP;
+    reg_frm->common.src_fmt.alpha_swap = 0;
+    reg_frm->common.src_fmt.rbuv_swap = 0;
+    reg_frm->common.src_fmt.out_fmt = 1;
+
+    reg_frm->common.src_strd0.src_strd0 = y_stride;
+    reg_frm->common.src_strd1.src_strd1 = y_stride;
+
+    reg_frm->common.src_proc.src_mirr = 0;
+    reg_frm->common.src_proc.src_rot = 0;
+
+    reg_frm->common.adr_src0 = mpp_buffer_get_fd(ctx->buf_pass1);
+    reg_frm->common.adr_src1 = reg_frm->common.adr_src0;
+
+    /* input cb addr */
+    ret = mpp_dev_multi_offset_update(ctx->reg_cfg, 161, width_align * height_align);
+    if (ret)
+        mpp_err_f("set input cb addr offset failed %d\n", ret);
+
+    return MPP_OK;
+}
+
+static void setup_vepu511_ext_line_buf(H265eV511HalContext *ctx, H265eV511RegSet *regs)
+{
+    H265eVepu511Frame *reg_frm = &regs->reg_frm;
+    RK_S32 fd;
+
+    if (ctx->ext_line_buf) {
+        fd = mpp_buffer_get_fd(ctx->ext_line_buf);
+
+        reg_frm->common.ebufb_addr = fd;
+        reg_frm->common.ebuft_addr = fd;
+        mpp_dev_multi_offset_update(ctx->reg_cfg, 178, ctx->ext_line_buf_size);
+    } else {
+        reg_frm->common.ebufb_addr = 0;
+        reg_frm->common.ebuft_addr = 0;
+    }
+}
+
+static void vepu511_h265_set_scaling_list(H265eV511RegSet *regs)
+{
+    H265eVepu511SclCfg *s = &regs->reg_scl;
+    RK_U8 *p = (RK_U8 *)&s->tu8_intra_y[0];
+    RK_U32 scl_lst_sel = regs->reg_frm.rdo_cfg.scl_lst_sel;
+    RK_U8 idx;
+
+    hal_h265e_dbg_func("enter\n");
+
+    if (scl_lst_sel == 1) {
+        for (idx = 0; idx < 64; idx++) {
+            /* TU8 intra Y/U/V */
+            p[idx + 64 * 0] = vepu511_h265_cqm_intra8[63 - idx];
+
+            p[idx + 64 * 1] = vepu511_h265_cqm_intra8[63 - idx];
+            p[idx + 64 * 2] = vepu511_h265_cqm_intra8[63 - idx];
+
+            /* TU8 inter Y/U/V */
+            p[idx + 64 * 3] = vepu511_h265_cqm_inter8[63 - idx];
+            p[idx + 64 * 4] = vepu511_h265_cqm_inter8[63 - idx];
+            p[idx + 64 * 5] = vepu511_h265_cqm_inter8[63 - idx];
+
+            /* TU16 intra Y/U/V AC */
+            p[idx + 64 * 6] = vepu511_h265_cqm_intra8[63 - idx];
+            p[idx + 64 * 7] = vepu511_h265_cqm_intra8[63 - idx];
+            p[idx + 64 * 8] = vepu511_h265_cqm_intra8[63 - idx];
+
+            /* TU16 inter Y/U/V AC */
+            p[idx + 64 *  9] = vepu511_h265_cqm_inter8[63 - idx];
+            p[idx + 64 * 10] = vepu511_h265_cqm_inter8[63 - idx];
+            p[idx + 64 * 11] = vepu511_h265_cqm_inter8[63 - idx];
+
+            /* TU32 intra/inter Y AC */
+            p[idx + 64 * 12] = vepu511_h265_cqm_intra8[63 - idx];
+            p[idx + 64 * 13] = vepu511_h265_cqm_inter8[63 - idx];
+        }
+
+        s->tu_dc0.tu16_intra_y_dc = 16;
+        s->tu_dc0.tu16_intra_u_dc = 16;
+        s->tu_dc0.tu16_intra_v_dc = 16;
+        s->tu_dc0.tu16_inter_y_dc = 16;
+        s->tu_dc1.tu16_inter_u_dc = 16;
+        s->tu_dc1.tu16_inter_v_dc = 16;
+        s->tu_dc1.tu32_intra_y_dc = 16;
+        s->tu_dc1.tu32_inter_y_dc = 16;
+    } else if (scl_lst_sel == 2) {
+        mpp_log_f("scaling_list_mode 2 is not supported yet\n");
+    }
+
+    hal_h265e_dbg_func("leave\n");
+}
+
+static void vepu511_h265_set_normal(H265eV511HalContext *ctx, H265eV511RegSet *regs)
+{
+    Vepu511ControlCfg *reg_ctl = &regs->reg_ctl;
+
+    reg_ctl->enc_strt.lkt_num      = 0;
+    reg_ctl->enc_strt.vepu_cmd     = ctx->enc_mode;
+    reg_ctl->enc_clr.safe_clr      = 0;
+    reg_ctl->enc_clr.force_clr     = 0;
+
+    reg_ctl->int_en.enc_done_en        = 1;
+    reg_ctl->int_en.lkt_node_done_en   = 1;
+    reg_ctl->int_en.sclr_done_en       = 1;
+    reg_ctl->int_en.vslc_done_en       = 1;
+    reg_ctl->int_en.vbsf_oflw_en       = 1;
+    reg_ctl->int_en.vbuf_lens_en       = 1;
+    reg_ctl->int_en.enc_err_en         = 1;
+    reg_ctl->int_en.vsrc_err_en        = 1;
+    reg_ctl->int_en.wdg_en             = 1;
+    reg_ctl->int_en.lkt_err_int_en     = 1;
+    reg_ctl->int_en.lkt_err_int_en     = 1;
+    reg_ctl->int_en.lkt_err_stop_en    = 1;
+    reg_ctl->int_en.lkt_force_stop_en  = 1;
+    reg_ctl->int_en.jslc_done_en       = 1;
+    reg_ctl->int_en.jbsf_oflw_en       = 1;
+    reg_ctl->int_en.jbuf_lens_en       = 1;
+    reg_ctl->int_en.dvbm_err_en        = 0;
+
+    reg_ctl->int_clr.enc_done_clr = 1;
+
+    reg_ctl->dtrns_map.jpeg_bus_edin    = 0x7;
+    reg_ctl->int_clr.enc_done_clr = 1;
+
+    reg_ctl->dtrns_map.jpeg_bus_edin     = 0x7;
+    reg_ctl->dtrns_map.src_bus_edin      = 0x0;
+    reg_ctl->dtrns_map.meiw_bus_edin     = 0x0;
+    reg_ctl->dtrns_map.bsw_bus_edin      = 0x7;
+    reg_ctl->dtrns_map.lktr_bus_edin     = 0x0;
+    reg_ctl->dtrns_map.roir_bus_edin     = 0x0;
+    reg_ctl->dtrns_map.lktw_bus_edin     = 0x0;
+    reg_ctl->dtrns_map.rec_nfbc_bus_edin = 0x0;
+
+    reg_ctl->dtrns_cfg.axi_brsp_cke     = 0x3ff;
+    reg_ctl->dtrns_cfg.axi_brsp_cke     = 0x3ff;
+    reg_ctl->enc_wdg.vs_load_thd        = 0;
+    reg_ctl->opt_strg.cke               = 1;
+    reg_ctl->opt_strg.resetn_hw_en      = 0;
+    reg_ctl->opt_strg.rfpr_err_e        = 1;
+    reg_ctl->opt_strg.sram_ckg_en       = 0;
+
+    /* enable rdo clk gating */
+    {
+        RK_U32 *rdo_ckg = (RK_U32*)&regs->reg_ctl.reg0022.rdo_ckg_hevc;
+
+        *rdo_ckg = 0x0;
+    }
+
+}
+
+static void vepu511_h265_set_prep(void *hal, HalEncTask *task, H265eV511RegSet *regs)
+{
+    H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
+    H265eVepu511Frame *reg_frm = &regs->reg_frm;
+    Vepu511RcRoi *reg_klut = &regs->reg_rc_roi;
+    H265eSyntax_new *syn = (H265eSyntax_new *)task->syntax.data;
+    RK_U32 pic_width_align8, pic_height_align8;
+    RK_S32 pic_wd32, pic_h32;
+    MppEncSceneMode sm = ctx->cfg->tune.scene_mode;
+
+    hal_h265e_enter();
+
+    pic_width_align8 = (syn->pp.pic_width + 7) & (~7);
+    pic_height_align8 = (syn->pp.pic_height + 7) & (~7);
+    pic_wd32 = (syn->pp.pic_width +  31) / 32;
+    pic_h32 = (syn->pp.pic_height + 31) / 32;
+
+    reg_frm->common.enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1;
+    reg_frm->common.enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1;
+    reg_frm->common.src_fill.pic_wfill = (syn->pp.pic_width & 0x7)
+                                         ? (8 - (syn->pp.pic_width & 0x7)) : 0;
+    reg_frm->common.src_fill.pic_hfill = (syn->pp.pic_height & 0x7)
+                                         ? (8 - (syn->pp.pic_height & 0x7)) : 0;
+
+    /* H.265 mode */
+    reg_frm->common.enc_pic.enc_stnd      = 1;
+    /* current frame will be refered */
+    reg_frm->common.enc_pic.cur_frm_ref   = !syn->sp.non_reference_flag;
+
+    reg_frm->common.enc_pic.bs_scp        = 1;
+    reg_frm->common.enc_pic.log2_ctu_num_hevc  = mpp_ceil_log2(pic_wd32 * pic_h32);
+
+    reg_klut->klut_ofst.chrm_klut_ofst = (ctx->frame_type == INTRA_FRAME) ? 6 :
+                                         (sm == MPP_ENC_SCENE_MODE_IPC ? 9 : 6);
+
+    reg_frm->common.enc_pic.rfpr_compress_mode = 0;
+    reg_frm->common.enc_pic.rec_fbc_dis = 0;
+
+    reg_frm->rdo_cfg.chrm_spcl  = 0;
+    reg_frm->rdo_cfg.cu_inter_e = 0x5b;
+
+    if (syn->pp.num_long_term_ref_pics_sps) {
+        reg_frm->rdo_cfg.ltm_col = 0;
+        reg_frm->rdo_cfg.ltm_idx0l0 = 1;
+    } else {
+        reg_frm->rdo_cfg.ltm_col = 0;
+        reg_frm->rdo_cfg.ltm_idx0l0 = 0;
+    }
+
+    reg_frm->rdo_cfg.ccwa_e = 1;
+    reg_frm->rdo_cfg.scl_lst_sel = syn->pp.scaling_list_enabled_flag;
+
+    {
+        RK_U32 i_nal_type = 0;
+
+        if (ctx->frame_type == INTRA_FRAME)
+            i_nal_type = NAL_IDR_W_RADL;
+        else if (ctx->frame_type == INTER_P_FRAME )
+            i_nal_type = NAL_TRAIL_R;
+        else
+            i_nal_type = NAL_TRAIL_R;
+
+        reg_frm->synt_nal.nal_unit_type = i_nal_type;
+    }
+
+    reg_frm->rdo_intra_mode.intra_pu4_mode_num  = 1;
+    reg_frm->rdo_intra_mode.intra_pu8_mode_num  = 2;
+    reg_frm->rdo_intra_mode.intra_pu16_mode_num = 2;
+    reg_frm->rdo_intra_mode.intra_pu32_mode_num = 2;
+
+}
+
+static void vepu511_h265_set_split(H265eV511RegSet *regs, MppEncCfgSet *enc_cfg)
+{
+    MppEncSliceSplit *cfg = &enc_cfg->split;
+
+    hal_h265e_dbg_func("enter\n");
+
+    switch (cfg->split_mode) {
+    case MPP_ENC_SPLIT_NONE : {
+        regs->reg_frm.common.sli_splt.sli_splt = 0;
+        regs->reg_frm.common.sli_splt.sli_splt_mode = 0;
+        regs->reg_frm.common.sli_splt.sli_splt_cpst = 0;
+        regs->reg_frm.common.sli_splt.sli_max_num_m1 = 0;
+        regs->reg_frm.common.sli_splt.sli_flsh = 0;
+        regs->reg_frm.common.sli_cnum.sli_splt_cnum_m1 = 0;
+
+        regs->reg_frm.common.sli_byte.sli_splt_byte = 0;
+        regs->reg_frm.common.enc_pic.slen_fifo = 0;
+    } break;
+    case MPP_ENC_SPLIT_BY_BYTE : {
+        regs->reg_frm.common.sli_splt.sli_splt = 1;
+        regs->reg_frm.common.sli_splt.sli_splt_mode = 0;
+        regs->reg_frm.common.sli_splt.sli_splt_cpst = 0;
+        regs->reg_frm.common.sli_splt.sli_max_num_m1 = 500;
+        regs->reg_frm.common.sli_splt.sli_flsh = 1;
+        regs->reg_frm.common.sli_cnum.sli_splt_cnum_m1 = 0;
+
+        regs->reg_frm.common.sli_byte.sli_splt_byte = cfg->split_arg;
+        regs->reg_frm.common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
+        regs->reg_ctl.int_en.vslc_done_en = cfg->split_out ? 1 : 0;
+    } break;
+    case MPP_ENC_SPLIT_BY_CTU : {
+        regs->reg_frm.common.sli_splt.sli_splt = 1;
+        regs->reg_frm.common.sli_splt.sli_splt_mode = 1;
+        regs->reg_frm.common.sli_splt.sli_splt_cpst = 0;
+        regs->reg_frm.common.sli_splt.sli_max_num_m1 = 500;
+        regs->reg_frm.common.sli_splt.sli_flsh = 1;
+        regs->reg_frm.common.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1;
+
+        regs->reg_frm.common.sli_byte.sli_splt_byte = 0;
+        regs->reg_frm.common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
+        regs->reg_ctl.int_en.vslc_done_en = cfg->split_out ? 1 : 0;
+    } break;
+    default : {
+        mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
+    } break;
+    }
+    cfg->change = 0;
+    hal_h265e_dbg_func("leave\n");
+}
+
+static void vepu511_h265_set_me_regs(H265eV511HalContext *ctx, H265eSyntax_new *syn, H265eV511RegSet *regs)
+{
+    H265eVepu511Param *s = &regs->reg_param;
+    H265eVepu511Frame *reg_frm = &regs->reg_frm;
+
+    reg_frm->common.me_rnge.cime_srch_dwnh = 15;
+    reg_frm->common.me_rnge.cime_srch_uph  = 15;
+    reg_frm->common.me_rnge.cime_srch_rgtw = 12;
+    reg_frm->common.me_rnge.cime_srch_lftw = 12;
+    reg_frm->common.me_cfg.rme_srch_h      = 3;
+    reg_frm->common.me_cfg.rme_srch_v      = 3;
+
+    reg_frm->common.me_cfg.srgn_max_num      = 72;
+    reg_frm->common.me_cfg.cime_dist_thre    = 1024;
+    reg_frm->common.me_cfg.rme_dis           = 0;
+    reg_frm->common.me_cfg.fme_dis           = 0;
+    reg_frm->common.me_rnge.dlt_frm_num      = 0x1;
+
+    if (syn->pp.sps_temporal_mvp_enabled_flag && (ctx->frame_type != INTRA_FRAME)) {
+        if (ctx->last_frame_fb.frame_type == INTRA_FRAME)
+            reg_frm->common.me_cach.colmv_load_hevc = 0;
+        else
+            reg_frm->common.me_cach.colmv_load_hevc = 1;
+
+        reg_frm->common.me_cach.colmv_stor_hevc = 1;
+    }
+
+    reg_frm->common.me_cach.cime_zero_thre = 64;
+    reg_frm->common.me_cach.fme_prefsu_en = 0;
+
+    /* CIME: 0x1760 - 0x176C */
+    s->me_sqi_comb.cime_pmv_num = 1;
+    s->me_sqi_comb.cime_fuse   = 1;
+    s->me_sqi_comb.move_lambda = 2;
+    s->me_sqi_comb.rime_lvl_mrg     = 0;
+    s->me_sqi_comb.rime_prelvl_en   = 3;
+    s->me_sqi_comb.rime_prersu_en   = 0;
+    s->me_sqi_comb.fme_lvl_mrg = 0;
+    s->cime_mvd_th_comb.cime_mvd_th0 = 8;
+    s->cime_mvd_th_comb.cime_mvd_th1 = 20;
+    s->cime_mvd_th_comb.cime_mvd_th2 = 32;
+    s->cime_madp_th_comb.cime_madp_th = 16;
+    s->cime_madp_th_comb.ratio_consi_cfg = 8;
+    s->cime_madp_th_comb.ratio_bmv_dist = 8;
+    s->cime_multi_comb.cime_multi0 = 8;
+    s->cime_multi_comb.cime_multi1 = 12;
+    s->cime_multi_comb.cime_multi2 = 16;
+    s->cime_multi_comb.cime_multi3 = 20;
+
+    /* RFME: 0x1770 - 0x177C */
+    s->rime_mvd_th_comb.rime_mvd_th0  = 1;
+    s->rime_mvd_th_comb.rime_mvd_th1  = 2;
+    s->rime_mvd_th_comb.fme_madp_th   = 0;
+    s->rime_madp_th_comb.rime_madp_th0 = 8;
+    s->rime_madp_th_comb.rime_madp_th1 = 16;
+    s->rime_multi_comb.rime_multi0 = 4;
+    s->rime_multi_comb.rime_multi1 = 8;
+    s->rime_multi_comb.rime_multi2 = 12;
+    s->cmv_st_th_comb.cmv_th0 = 64;
+    s->cmv_st_th_comb.cmv_th1 = 96;
+    s->cmv_st_th_comb.cmv_th2 = 128;
+
+    if (ctx->cfg->tune.scene_mode != MPP_ENC_SCENE_MODE_IPC) {
+        s->cime_madp_th_comb.cime_madp_th = 0;
+        s->rime_madp_th_comb.rime_madp_th0 = 0;
+        s->rime_madp_th_comb.rime_madp_th1 = 0;
+        s->cime_multi_comb.cime_multi0 = 4;
+        s->cime_multi_comb.cime_multi1 = 4;
+        s->cime_multi_comb.cime_multi2 = 4;
+        s->cime_multi_comb.cime_multi3 = 4;
+        s->rime_multi_comb.rime_multi0 = 4;
+        s->rime_multi_comb.rime_multi1 = 4;
+        s->rime_multi_comb.rime_multi2 = 4;
+    } else if (ctx->smart_en) {
+        s->cime_multi_comb.cime_multi0 = 4;
+        s->cime_multi_comb.cime_multi1 = 6;
+        s->cime_multi_comb.cime_multi2 = 8;
+        s->cime_multi_comb.cime_multi3 = 12;
+        s->rime_multi_comb.rime_multi0 = 4;
+        s->rime_multi_comb.rime_multi1 = 6;
+        s->rime_multi_comb.rime_multi2 = 8;
+    }
+
+    s->rime_mvd_th_comb.fme_madp_th  = 0;
+    s->rime_multi_comb.rime_multi0   = 0;
+    s->rime_multi_comb.rime_multi1   = 0;
+    s->rime_multi_comb.rime_multi2   = 0;
+}
+
+static void vepu511_h265_set_hw_address(H265eV511HalContext *ctx, H265eVepu511Frame *regs,
+                                        HalEncTask *task)
+{
+    HalEncTask *enc_task = task;
+    HalBuf *recon_buf, *ref_buf;
+    MppBuffer md_info_buf = enc_task->md_info;
+    Vepu511H265eFrmCfg *frm = ctx->frm;
+    H265eSyntax_new *syn = ctx->syn;
+
+    hal_h265e_enter();
+
+    regs->common.adr_src0  = mpp_buffer_get_fd(enc_task->input);
+    regs->common.adr_src1  = regs->common.adr_src0;
+    regs->common.adr_src2  = regs->common.adr_src0;
+
+    recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, frm->hal_curr_idx);
+    ref_buf = hal_bufs_get_buf(ctx->dpb_bufs, frm->hal_refr_idx);
+
+    if (!syn->sp.non_reference_flag) {
+        regs->common.rfpw_h_addr  = mpp_buffer_get_fd(recon_buf->buf[0]);
+        regs->common.rfpw_b_addr  = regs->common.rfpw_h_addr;
+        mpp_dev_multi_offset_update(ctx->reg_cfg, 164, ctx->fbc_header_len);
+    }
+    regs->common.rfpr_h_addr = mpp_buffer_get_fd(ref_buf->buf[0]);
+    regs->common.rfpr_b_addr = regs->common.rfpr_h_addr;
+    regs->common.colmvw_addr = mpp_buffer_get_fd(recon_buf->buf[2]);
+    regs->common.colmvr_addr = mpp_buffer_get_fd(ref_buf->buf[2]);
+    regs->common.dspw_addr = mpp_buffer_get_fd(recon_buf->buf[1]);
+    regs->common.dspr_addr = mpp_buffer_get_fd(ref_buf->buf[1]);
+
+    mpp_dev_multi_offset_update(ctx->reg_cfg, 166, ctx->fbc_header_len);
+
+    if (md_info_buf) {
+        regs->common.enc_pic.mei_stor = 1;
+        regs->common.meiw_addr = mpp_buffer_get_fd(md_info_buf);
+    } else {
+        regs->common.enc_pic.mei_stor = 0;
+        regs->common.meiw_addr = 0;
+    }
+
+    regs->common.bsbt_addr = mpp_buffer_get_fd(enc_task->output);
+    /* TODO: stream size relative with syntax */
+    regs->common.bsbb_addr  = regs->common.bsbt_addr;
+    regs->common.bsbr_addr  = regs->common.bsbt_addr;
+    regs->common.adr_bsbs   = regs->common.bsbt_addr;
+
+    regs->common.rfpt_h_addr = 0xffffffff;
+    regs->common.rfpb_h_addr = 0;
+    regs->common.rfpt_b_addr = 0xffffffff;
+    regs->common.adr_rfpb_b  = 0;
+    regs->common.adr_roir    = 0;
+
+    mpp_dev_multi_offset_update(ctx->reg_cfg, 174, mpp_packet_get_length(task->packet));
+    mpp_dev_multi_offset_update(ctx->reg_cfg, 172, mpp_buffer_get_size(enc_task->output));
+
+    regs->common.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
+    regs->common.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
+
+    /* smear bufs */
+    regs->common.adr_smear_rd = mpp_buffer_get_fd(ref_buf->buf[3]);
+    regs->common.adr_smear_wr = mpp_buffer_get_fd(recon_buf->buf[3]);
+}
+
+static void vepu511_h265_set_pp_regs(H265eV511RegSet *regs, VepuFmtCfg *fmt,
+                                     MppEncPrepCfg *prep_cfg, HalEncTask *task)
+{
+    Vepu511ControlCfg *reg_ctl = &regs->reg_ctl;
+    H265eVepu511Frame *reg_frm = &regs->reg_frm;
+    RK_S32 stridey = 0;
+    RK_S32 stridec = 0;
+
+    reg_ctl->dtrns_map.src_bus_edin = fmt->src_endian;
+    reg_frm->common.src_fmt.src_cfmt = fmt->format;
+    reg_frm->common.src_fmt.alpha_swap = fmt->alpha_swap;
+    reg_frm->common.src_fmt.rbuv_swap = fmt->rbuv_swap;
+
+    reg_frm->common.src_fmt.out_fmt = (prep_cfg->format == MPP_FMT_YUV400) ? 0 : 1;
+
+    reg_frm->common.src_proc.src_mirr = prep_cfg->mirroring > 0;
+    reg_frm->common.src_proc.src_rot = prep_cfg->rotation;
+
+    if (MPP_FRAME_FMT_IS_FBC(prep_cfg->format)) {
+        reg_frm->common.src_proc.rkfbcd_en = 1;
+
+        stridey = mpp_frame_get_fbc_hdr_stride(task->frame);
+        if (!stridey)
+            stridey = MPP_ALIGN(prep_cfg->hor_stride, 64) >> 2;
+    } else if (prep_cfg->hor_stride)
+        stridey = prep_cfg->hor_stride;
+    else {
+        if (reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_BGRA8888 )
+            stridey = prep_cfg->width * 4;
+        else if (reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_BGR888 )
+            stridey = prep_cfg->width * 3;
+        else if (reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_BGR565 ||
+                 reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_YUYV422 ||
+                 reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_UYVY422)
+            stridey = prep_cfg->width * 2;
+    }
+
+    switch (fmt->format) {
+    case VEPU580_FMT_YUV444SP : {
+        stridec = stridey * 2;
+    } break;
+    case VEPU541_FMT_YUV422SP :
+    case VEPU541_FMT_YUV420SP :
+    case VEPU580_FMT_YUV444P : {
+        stridec = stridey;
+    } break;
+    default : {
+        stridec = stridey / 2;
+    } break;
+    }
+
+    if (reg_frm->common.src_fmt.src_cfmt < VEPU541_FMT_NONE) {
+        reg_frm->common.src_udfy.csc_wgt_r2y = 77;
+        reg_frm->common.src_udfy.csc_wgt_g2y = 150;
+        reg_frm->common.src_udfy.csc_wgt_b2y = 29;
+
+        reg_frm->common.src_udfu.csc_wgt_r2u = -43;
+        reg_frm->common.src_udfu.csc_wgt_g2u = -85;
+        reg_frm->common.src_udfu.csc_wgt_b2u = 128;
+
+        reg_frm->common.src_udfv.csc_wgt_r2v = 128;
+        reg_frm->common.src_udfv.csc_wgt_g2v = -107;
+        reg_frm->common.src_udfv.csc_wgt_b2v = -21;
+
+        reg_frm->common.src_udfo.csc_ofst_y = 0;
+        reg_frm->common.src_udfo.csc_ofst_u = 128;
+        reg_frm->common.src_udfo.csc_ofst_v = 128;
+    }
+
+    reg_frm->common.src_strd0.src_strd0  = stridey;
+    reg_frm->common.src_strd1.src_strd1  = stridec;
+}
+
+static void vepu511_h265_set_vsp_filtering(H265eV511HalContext *ctx, H265eV511RegSet *regs)
+{
+    // H265eV511RegSet *regs = ctx->regs;
+    H265eVepu511Frame *s = &regs->reg_frm;
+    MppEncCfgSet *cfg = ctx->cfg;
+    MppEncHwCfg *hw = &cfg->hw;
+    RK_U8 bit_chg_lvl = ctx->last_frame_fb.tgt_sub_real_lvl[5]; /* [0, 2] */
+    RK_U8 corner_str = 0, edge_str = 0, internal_str = 0; /* [0, 3] */
+
+    if (cfg->tune.deblur_en && (cfg->tune.deblur_str % 2 == 0) &&
+        (hw->flt_str_i == 0) && (hw->flt_str_p == 0)) {
+        if (bit_chg_lvl == 2 && ctx->frame_type != INTRA_FRAME) {
+            corner_str = 3;
+            edge_str = 3;
+            internal_str = 3;
+        } else if (bit_chg_lvl > 0) {
+            corner_str = 2;
+            edge_str = 2;
+            internal_str = 2;
+        }
+    } else {
+        if (ctx->frame_type == INTRA_FRAME) {
+            corner_str = hw->flt_str_i;
+            edge_str = hw->flt_str_i;
+            internal_str = hw->flt_str_i;
+        } else {
+            corner_str = hw->flt_str_p;
+            edge_str = hw->flt_str_p;
+            internal_str = hw->flt_str_p;
+        }
+    }
+
+    s->common.src_flt_cfg.pp_corner_filter_strength = corner_str;
+    s->common.src_flt_cfg.pp_edge_filter_strength = edge_str;
+    s->common.src_flt_cfg.pp_internal_filter_strength = internal_str;
+}
+
+static void vepu511_h265_set_rc_regs(H265eV511HalContext *ctx, H265eV511RegSet *regs,
+                                     HalEncTask *task)
+{
+    H265eSyntax_new *syn = (H265eSyntax_new *)task->syntax.data;
+    EncRcTaskInfo *rc_cfg = &task->rc_task->info;
+    H265eVepu511Frame *reg_frm = &regs->reg_frm;
+    Vepu511RcRoi *reg_rc = &regs->reg_rc_roi;
+    MppEncCfgSet *cfg = ctx->cfg;
+    MppEncRcCfg *rc = &cfg->rc;
+    MppEncHwCfg *hw = &cfg->hw;
+    MppEncCodecCfg *codec = &cfg->codec;
+    MppEncH265Cfg *h265 = &codec->h265;
+    RK_S32 mb_wd32 = (syn->pp.pic_width + 31) / 32;
+    RK_S32 mb_h32 = (syn->pp.pic_height + 31) / 32;
+
+    RK_U32 ctu_target_bits_mul_16 = (rc_cfg->bit_target << 4) / (mb_wd32 * mb_h32);
+    RK_U32 ctu_target_bits;
+    RK_S32 negative_bits_thd, positive_bits_thd;
+
+    if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) {
+        reg_frm->common.enc_pic.pic_qp    = rc_cfg->quality_target;
+        reg_frm->synt_sli1.sli_qp         = rc_cfg->quality_target;
+        reg_frm->common.rc_qp.rc_max_qp   = rc_cfg->quality_target;
+        reg_frm->common.rc_qp.rc_min_qp   = rc_cfg->quality_target;
+        reg_frm->common.rc_cfg.rc_ctu_num = 1;
+    } else {
+        if (ctu_target_bits_mul_16 >= 0x100000) {
+            ctu_target_bits_mul_16 = 0x50000;
+        }
+        ctu_target_bits = (ctu_target_bits_mul_16 * mb_wd32) >> 4;
+        negative_bits_thd = 0 - 5 * ctu_target_bits / 16;
+        positive_bits_thd = 5 * ctu_target_bits / 16;
+
+        reg_frm->common.enc_pic.pic_qp      = rc_cfg->quality_target;
+        reg_frm->synt_sli1.sli_qp           = rc_cfg->quality_target;
+        reg_frm->common.rc_cfg.rc_en        = 1;
+        reg_frm->common.rc_cfg.aq_en        = 1;
+        reg_frm->common.rc_cfg.rc_ctu_num   = mb_wd32;
+
+        reg_frm->common.rc_qp.rc_max_qp     = rc_cfg->quality_max;
+        reg_frm->common.rc_qp.rc_min_qp     = rc_cfg->quality_min;
+        reg_frm->common.rc_tgt.ctu_ebit     = ctu_target_bits_mul_16;
+
+        if (ctx->smart_en) {
+            reg_frm->common.rc_qp.rc_qp_range = 0;
+        } else {
+            reg_frm->common.rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ?
+                                                hw->qp_delta_row_i : hw->qp_delta_row;
+        }
+
+        {
+            /* fixed frame qp */
+            RK_S32 fqp_min, fqp_max;
+
+            if (ctx->frame_type == INTRA_FRAME) {
+                fqp_min = rc->fqp_min_i;
+                fqp_max = rc->fqp_max_i;
+            } else {
+                fqp_min = rc->fqp_min_p;
+                fqp_max = rc->fqp_max_p;
+            }
+
+            if ((fqp_min == fqp_max) && (fqp_min >= 0) && (fqp_max <= 51)) {
+                reg_frm->common.enc_pic.pic_qp = fqp_min;
+                reg_frm->synt_sli1.sli_qp  = fqp_min;
+                reg_frm->common.rc_qp.rc_qp_range = 0;
+            }
+        }
+
+        reg_rc->rc_dthd_0_8[0] = 2 * negative_bits_thd;
+        reg_rc->rc_dthd_0_8[1] = negative_bits_thd;
+        reg_rc->rc_dthd_0_8[2] = positive_bits_thd;
+        reg_rc->rc_dthd_0_8[3] = 2 * positive_bits_thd;
+        reg_rc->rc_dthd_0_8[4] = 0x7FFFFFFF;
+        reg_rc->rc_dthd_0_8[5] = 0x7FFFFFFF;
+        reg_rc->rc_dthd_0_8[6] = 0x7FFFFFFF;
+        reg_rc->rc_dthd_0_8[7] = 0x7FFFFFFF;
+        reg_rc->rc_dthd_0_8[8] = 0x7FFFFFFF;
+
+        reg_rc->rc_adj0.qp_adj0  = -2;
+        reg_rc->rc_adj0.qp_adj1  = -1;
+        reg_rc->rc_adj0.qp_adj2  = 0;
+        reg_rc->rc_adj0.qp_adj3  = 1;
+        reg_rc->rc_adj0.qp_adj4  = 2;
+        reg_rc->rc_adj1.qp_adj5  = 0;
+        reg_rc->rc_adj1.qp_adj6  = 0;
+        reg_rc->rc_adj1.qp_adj7  = 0;
+        reg_rc->rc_adj1.qp_adj8  = 0;
+    }
+
+    reg_rc->roi_qthd0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min;
+    reg_rc->roi_qthd0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max;
+    reg_rc->roi_qthd0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min;
+    reg_rc->roi_qthd0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max;
+    reg_rc->roi_qthd0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;
+    reg_rc->roi_qthd1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max;
+    reg_rc->roi_qthd1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;
+    reg_rc->roi_qthd1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max;
+    reg_rc->roi_qthd1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;
+    reg_rc->roi_qthd1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max;
+    reg_rc->roi_qthd2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;
+    reg_rc->roi_qthd2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max;
+    reg_rc->roi_qthd2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;
+    reg_rc->roi_qthd2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max;
+    reg_rc->roi_qthd2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;
+    reg_rc->roi_qthd3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max;
+}
+
+static void vepu511_h265_set_quant_regs(H265eV511HalContext *ctx, H265eV511RegSet *regs)
+{
+    MppEncHwCfg *hw = &ctx->cfg->hw;
+    // H265eV511RegSet *regs = ctx->regs;
+    H265eVepu511Param *s = &regs->reg_param;
+    RK_U8 th0 = 3, th1 = 6, th2 = 13;
+    RK_U16 bias_i0 = 171, bias_i1 = 171, bias_i2 = 171, bias_i3 = 171;
+    RK_U16 bias_p0 = 85, bias_p1 = 85, bias_p2 = 85, bias_p3 = 85;
+    RK_U32 frm_type = ctx->frame_type;
+
+    if (!hw->qbias_en) {
+        if (ctx->smart_en) {
+            bias_i0 = bias_i1 = bias_i3 = 144;
+            bias_i2 = (frm_type == INTRA_FRAME) ? 144 : 171;
+        } else {
+            bias_i0 = bias_i1 = bias_i3 = 171;
+            bias_i2 = (frm_type == INTRA_FRAME) ? 171 : 220;
+        }
+
+        /* used for venc_info log */
+        hw->qbias_arr[IFRAME_THD0] = hw->qbias_arr[PFRAME_THD0] = th0;
+        hw->qbias_arr[IFRAME_THD1] = hw->qbias_arr[PFRAME_THD1] = th1;
+        hw->qbias_arr[IFRAME_THD2] = hw->qbias_arr[PFRAME_THD2] = th2;
+        hw->qbias_arr[IFRAME_BIAS0] = hw->qbias_arr[PFRAME_IBLK_BIAS0] = bias_i0;
+        hw->qbias_arr[IFRAME_BIAS1] = hw->qbias_arr[PFRAME_IBLK_BIAS1] = bias_i1;
+        hw->qbias_arr[IFRAME_BIAS2] = hw->qbias_arr[PFRAME_IBLK_BIAS2] = bias_i2;
+        hw->qbias_arr[IFRAME_BIAS3] = hw->qbias_arr[PFRAME_IBLK_BIAS3] = bias_i3;
+        hw->qbias_arr[PFRAME_PBLK_BIAS0] = bias_p0;
+        hw->qbias_arr[PFRAME_PBLK_BIAS1] = bias_p1;
+        hw->qbias_arr[PFRAME_PBLK_BIAS2] = bias_p2;
+        hw->qbias_arr[PFRAME_PBLK_BIAS3] = bias_p3;
+    } else {
+        if (frm_type == INTRA_FRAME) {
+            th0 = hw->qbias_arr[IFRAME_THD0];
+            th1 = hw->qbias_arr[IFRAME_THD1];
+            th2 = hw->qbias_arr[IFRAME_THD2];
+            bias_i0 = hw->qbias_arr[IFRAME_BIAS0];
+            bias_i1 = hw->qbias_arr[IFRAME_BIAS1];
+            bias_i2 = hw->qbias_arr[IFRAME_BIAS2];
+            bias_i3 = hw->qbias_arr[IFRAME_BIAS3];
+        } else {
+            th0 = hw->qbias_arr[PFRAME_THD0];
+            th1 = hw->qbias_arr[PFRAME_THD1];
+            th2 = hw->qbias_arr[PFRAME_THD2];
+            bias_i0 = hw->qbias_arr[PFRAME_IBLK_BIAS0];
+            bias_i1 = hw->qbias_arr[PFRAME_IBLK_BIAS1];
+            bias_i2 = hw->qbias_arr[PFRAME_IBLK_BIAS2];
+            bias_i3 = hw->qbias_arr[PFRAME_IBLK_BIAS3];
+            bias_p0 = hw->qbias_arr[PFRAME_PBLK_BIAS0];
+            bias_p1 = hw->qbias_arr[PFRAME_PBLK_BIAS1];
+            bias_p2 = hw->qbias_arr[PFRAME_PBLK_BIAS2];
+            bias_p3 = hw->qbias_arr[PFRAME_PBLK_BIAS3];
+        }
+    }
+
+    s->bias_madi_thd_comb.bias_madi_th0 = th0;
+    s->bias_madi_thd_comb.bias_madi_th1 = th1;
+    s->bias_madi_thd_comb.bias_madi_th2 = th2;
+    s->qnt0_i_bias_comb.bias_i_val0 = bias_i0;
+    s->qnt0_i_bias_comb.bias_i_val1 = bias_i1;
+    s->qnt0_i_bias_comb.bias_i_val2 = bias_i2;
+    s->qnt1_i_bias_comb.bias_i_val3 = bias_i3;
+    s->qnt0_p_bias_comb.bias_p_val0 = bias_p0;
+    s->qnt0_p_bias_comb.bias_p_val1 = bias_p1;
+    s->qnt0_p_bias_comb.bias_p_val2 = bias_p2;
+    s->qnt1_p_bias_comb.bias_p_val3 = bias_p3;
+}
+
+static void vepu511_h265_set_atr_regs(H265eV511RegSet *regs)
+{
+    H265eVepu511Sqi *s = &regs->reg_sqi;
+    RK_U32 str = 0;
+
+    /* 0 - disable; 1 - weak; 2 - medium; 3 - strong */
+    if (str == 0) {
+        s->block_opt_cfg.block_en = 0; /* block_en and cmplx_en are not used so far(20240708) */
+        s->cmplx_opt_cfg.cmplx_en = 0;
+        s->line_opt_cfg.line_en = 0;
+    } else {
+        s->block_opt_cfg.block_en = 0;
+        s->cmplx_opt_cfg.cmplx_en = 0;
+        s->line_opt_cfg.line_en = 1;
+    }
+
+    s->subj_opt_cfg.subj_opt_en = 0;
+    s->subj_opt_cfg.subj_opt_strength = 3;
+    s->subj_opt_cfg.aq_subj_en = 0;
+    s->subj_opt_cfg.aq_subj_strength = 4;
+    s->subj_opt_cfg.bndry_cmplx_static_choose_en = 0;
+    s->subj_opt_cfg.feature_cal_en = 0;
+    s->subj_opt_dpth_thd.common_thre_num_grdn_point_dep0   = 64;
+    s->subj_opt_dpth_thd.common_thre_num_grdn_point_dep1   = 32;
+    s->subj_opt_dpth_thd.common_thre_num_grdn_point_dep2   = 16;
+
+    if (str == 3) {
+        s->block_opt_cfg.block_thre_cst_best_mad      = 1000;
+        s->block_opt_cfg.block_thre_cst_best_grdn_blk = 39;
+        s->block_opt_cfg.thre_num_grdnt_point_cmplx   = 3;
+        s->block_opt_cfg.block_delta_qp_flag          = 3;
+
+        s->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0 = 4000;
+        s->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1 = 2000;
+
+        s->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2       = 200;
+        s->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0  = 977;
+
+        s->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1 = 0;
+        s->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2 = 488;
+
+        s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0 = 4;
+        s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1 = 30;
+        s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2 = 30;
+        s->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0   = 7;
+        s->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1   = 6;
+
+        s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0 = 1;
+        s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1 = 50;
+        s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2 = 50;
+
+        s->subj_opt_dqp0.line_thre_qp   = 20;
+        s->subj_opt_dqp0.block_strength = 4;
+        s->subj_opt_dqp0.block_thre_qp  = 30;
+        s->subj_opt_dqp0.cmplx_strength = 4;
+        s->subj_opt_dqp0.cmplx_thre_qp  = 34;
+        s->subj_opt_dqp0.cmplx_thre_max_grdn_blk = 32;
+    } else if (str == 2) {
+        s->block_opt_cfg.block_thre_cst_best_mad      = 1000;
+        s->block_opt_cfg.block_thre_cst_best_grdn_blk = 39;
+        s->block_opt_cfg.thre_num_grdnt_point_cmplx   = 3;
+        s->block_opt_cfg.block_delta_qp_flag          = 3;
+
+        s->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0 = 4000;
+        s->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1 = 2000;
+
+        s->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2      = 200;
+        s->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0 = 977;
+
+        s->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1 = 0;
+        s->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2 = 488;
+
+        s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0 = 3;
+        s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1 = 20;
+        s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2 = 20;
+        s->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0   = 7;
+        s->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1   = 8;
+
+        s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0 = 1;
+        s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1 = 60;
+        s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2 = 60;
+
+        s->subj_opt_dqp0.line_thre_qp            = 25;
+        s->subj_opt_dqp0.block_strength          = 4;
+        s->subj_opt_dqp0.block_thre_qp           = 30;
+        s->subj_opt_dqp0.cmplx_strength          = 4;
+        s->subj_opt_dqp0.cmplx_thre_qp           = 34;
+        s->subj_opt_dqp0.cmplx_thre_max_grdn_blk = 32;
+    } else {
+        s->block_opt_cfg.block_thre_cst_best_mad      = 1000;
+        s->block_opt_cfg.block_thre_cst_best_grdn_blk = 39;
+        s->block_opt_cfg.thre_num_grdnt_point_cmplx   = 3;
+        s->block_opt_cfg.block_delta_qp_flag          = 3;
+
+        s->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0 = 6000;
+        s->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1 = 2000;
+
+        s->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2       = 300;
+        s->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0  = 1280;
+
+        s->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1 = 0;
+        s->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2 = 512;
+
+        s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0 = 3;
+        s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1 = 20;
+        s->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2 = 20;
+        s->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0   = 7;
+        s->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1   = 8;
+
+        s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0 = 1;
+        s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1 = 70;
+        s->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2 = 70;
+
+        s->subj_opt_dqp0.line_thre_qp            = 30;
+        s->subj_opt_dqp0.block_strength          = 4;
+        s->subj_opt_dqp0.block_thre_qp           = 30;
+        s->subj_opt_dqp0.cmplx_strength          = 4;
+        s->subj_opt_dqp0.cmplx_thre_qp           = 34;
+        s->subj_opt_dqp0.cmplx_thre_max_grdn_blk = 32;
+    }
+}
+
+static void vepu511_h265_set_smear_regs(H265eV511HalContext *ctx, H265eV511RegSet *regs)
+{
+    H265eVepu511Sqi *s = &regs->reg_sqi;
+    RK_S32 frm_num = ctx->frame_num;
+    RK_S32 gop = (ctx->cfg->rc.gop > 0) ? ctx->cfg->rc.gop : 1; //TODO: gop = 0
+    RK_U32 cover_num = ctx->last_frame_fb.acc_cover16_num;
+    RK_U32 bndry_num = ctx->last_frame_fb.acc_bndry16_num;
+    RK_U32 st_ctu_num = ctx->last_frame_fb.st_ctu_num;
+    RK_S32 str = ctx->cfg->tune.deblur_str;
+    RK_S16 flag_cover = 0;
+    RK_S16 flag_bndry = 0;
+
+    static RK_U8 qp_strength[H265E_SMEAR_STR_NUM] = { 4, 6, 7, 7, 3, 5, 7, 7 };
+    static RK_U8 smear_strength[H265E_SMEAR_STR_NUM] = { 1, 1, 1, 1, 1, 1, 1, 1 };
+    static RK_U8 bndry_intra_r_dep0[H265E_SMEAR_STR_NUM] = { 240, 240, 240, 240, 240, 240, 240, 240 };
+    static RK_U8 bndry_intra_r_dep1[H265E_SMEAR_STR_NUM] = { 240, 240, 240, 240, 240, 240, 240, 240 };
+    static RK_U8 thre_madp_stc_cover0[H265E_SMEAR_STR_NUM] = { 20, 22, 22, 22, 20, 22, 22, 30 };
+    static RK_U8 thre_madp_stc_cover1[H265E_SMEAR_STR_NUM] = { 20, 22, 22, 22, 20, 22, 22, 30 };
+    static RK_U8 thre_madp_mov_cover0[H265E_SMEAR_STR_NUM] = { 10, 9, 9, 9, 10, 9, 9, 6 };
+    static RK_U8 thre_madp_mov_cover1[H265E_SMEAR_STR_NUM] = { 10, 9, 9, 9, 10, 9, 9, 6 };
+
+    static RK_U8 flag_cover_thd0[H265E_SMEAR_STR_NUM] = { 12, 13, 13, 13, 12, 13, 13, 17 };
+    static RK_U8 flag_cover_thd1[H265E_SMEAR_STR_NUM] = { 61, 70, 70, 70, 61, 70, 70, 90 };
+    static RK_U8 flag_bndry_thd0[H265E_SMEAR_STR_NUM] = { 12, 12, 12, 12, 12, 12, 12, 12 };
+    static RK_U8 flag_bndry_thd1[H265E_SMEAR_STR_NUM] = { 73, 73, 73, 73, 73, 73, 73, 73 };
+
+    static RK_S8 flag_cover_wgt[3] = { 1, 0, -3 };
+    static RK_S8 flag_bndry_wgt[3] = { 0, 0, 0 };
+    static RK_S8 flag_bndry_intra_wgt0[3] = { -12, 0, 12 };
+    static RK_S8 flag_bndry_intra_wgt1[3] = { -12, 0, 12 };
+
+    flag_cover = (cover_num * 1000 < flag_cover_thd0[str] * st_ctu_num) ? 0 :
+                 (cover_num * 1000 < flag_cover_thd1[str] * st_ctu_num) ? 1 : 2;
+
+    flag_bndry = (bndry_num * 1000 < flag_bndry_thd0[str] * st_ctu_num) ? 0 :
+                 (bndry_num * 1000 < flag_bndry_thd1[str] * st_ctu_num) ? 1 : 2;
+
+    /* anti smear */
+    s->smear_opt_cfg0.anti_smear_en = ctx->cfg->tune.deblur_en;
+    s->smear_opt_cfg0.smear_strength = (smear_strength[str] > 2) ?
+                                       (smear_strength[str] + flag_bndry_wgt[flag_bndry]) : smear_strength[str];
+
+    s->smear_opt_cfg0.thre_mv_inconfor_cime       = 8;
+    s->smear_opt_cfg0.thre_mv_confor_cime         = 2;
+    s->smear_opt_cfg0.thre_mv_inconfor_cime_gmv   = 8;
+    s->smear_opt_cfg0.thre_mv_confor_cime_gmv     = 2;
+    s->smear_opt_cfg0.thre_num_mv_confor_cime     = 3;
+    s->smear_opt_cfg0.thre_num_mv_confor_cime_gmv = 2;
+    s->smear_opt_cfg0.frm_static                  = 1;
+
+    s->smear_opt_cfg0.smear_load_en = ((frm_num % gop == 0) ||
+                                       (s->smear_opt_cfg0.frm_static == 0) || (frm_num % gop == 1)) ? 0 : 1;
+    s->smear_opt_cfg0.smear_stor_en = ((frm_num % gop == 0) ||
+                                       (s->smear_opt_cfg0.frm_static == 0) || (frm_num % gop == gop - 1)) ? 0 : 1;
+    s->smear_opt_cfg1.dist0_frm_avg               = 0;
+    s->smear_opt_cfg1.thre_dsp_static             = 10;
+    s->smear_opt_cfg1.thre_dsp_mov                = 15;
+    s->smear_opt_cfg1.thre_dist_mv_confor_cime    = 32;
+
+    s->smear_madp_thd.thre_madp_stc_dep0          = 10;
+    s->smear_madp_thd.thre_madp_stc_dep1          = 8;
+    s->smear_madp_thd.thre_madp_stc_dep2          = 8;
+    s->smear_madp_thd.thre_madp_mov_dep0          = 16;
+    s->smear_madp_thd.thre_madp_mov_dep1          = 18;
+    s->smear_madp_thd.thre_madp_mov_dep2          = 20;
+
+    s->smear_stat_thd.thre_num_pt_stc_dep0        = 47;
+    s->smear_stat_thd.thre_num_pt_stc_dep1        = 11;
+    s->smear_stat_thd.thre_num_pt_stc_dep2        = 3;
+    s->smear_stat_thd.thre_num_pt_mov_dep0        = 47;
+    s->smear_stat_thd.thre_num_pt_mov_dep1        = 11;
+    s->smear_stat_thd.thre_num_pt_mov_dep2        = 3;
+
+    s->smear_bmv_dist_thd0.confor_cime_gmv0      = 21;
+    s->smear_bmv_dist_thd0.confor_cime_gmv1      = 16;
+    s->smear_bmv_dist_thd0.inconfor_cime_gmv0    = 48;
+    s->smear_bmv_dist_thd0.inconfor_cime_gmv1    = 34;
+
+    s->smear_bmv_dist_thd1.inconfor_cime_gmv2    = 32;
+    s->smear_bmv_dist_thd1.inconfor_cime_gmv3    = 29;
+    s->smear_bmv_dist_thd1.inconfor_cime_gmv4    = 27;
+
+    s->smear_min_bndry_gmv.thre_min_num_confor_csu0_bndry_cime_gmv      = 0;
+    s->smear_min_bndry_gmv.thre_max_num_confor_csu0_bndry_cime_gmv      = 3;
+    s->smear_min_bndry_gmv.thre_min_num_inconfor_csu0_bndry_cime_gmv    = 0;
+    s->smear_min_bndry_gmv.thre_max_num_inconfor_csu0_bndry_cime_gmv    = 3;
+    s->smear_min_bndry_gmv.thre_split_dep0                              = 2;
+    s->smear_min_bndry_gmv.thre_zero_srgn                               = 8;
+    s->smear_min_bndry_gmv.madi_thre_dep0                               = 22;
+    s->smear_min_bndry_gmv.madi_thre_dep1                               = 18;
+
+    s->smear_madp_cov_thd.thre_madp_stc_cover0    = thre_madp_stc_cover0[str];
+    s->smear_madp_cov_thd.thre_madp_stc_cover1    = thre_madp_stc_cover1[str];
+    s->smear_madp_cov_thd.thre_madp_mov_cover0    = thre_madp_mov_cover0[str];
+    s->smear_madp_cov_thd.thre_madp_mov_cover1    = thre_madp_mov_cover1[str];
+    s->smear_madp_cov_thd.smear_qp_strength       = qp_strength[str] +
+                                                    flag_cover_wgt[flag_cover];
+    s->smear_madp_cov_thd.smear_thre_qp           = 30;
+
+    s->subj_opt_dqp1.bndry_rdo_mode_intra_jcoef_d0   = bndry_intra_r_dep0[str] +
+                                                       flag_bndry_intra_wgt0[flag_bndry];
+    s->subj_opt_dqp1.bndry_rdo_mode_intra_jcoef_d1   = bndry_intra_r_dep1[str] +
+                                                       flag_bndry_intra_wgt1[flag_bndry];
+
+    s->subj_opt_dqp1.skin_thre_qp = 31;
+    s->subj_opt_dqp1.skin_thre_madp = 64;
+    s->subj_opt_dqp1.bndry_rdo_mode_intra_jcoef_d0 = 15;
+    s->subj_opt_dqp1.bndry_rdo_mode_intra_jcoef_d1 = 14;
+    s->subj_opt_dqp1.smear_frame_thre_qp = 35;
+    s->subj_opt_rdo_split.line_rdo_split_rcoef_d0 = 11;
+    s->subj_opt_rdo_split.line_rdo_split_rcoef_d1 = 13;
+
+    s->subj_opt_inrar_coef.cover_rmd_mode_intra_jcoef_d0 = 8;
+    s->subj_opt_inrar_coef.cover_rmd_mode_intra_jcoef_d1 = 8;
+    s->subj_opt_inrar_coef.cover_rdo_mode_intra_jcoef_d0 = 12;
+    s->subj_opt_inrar_coef.cover_rdo_mode_intra_jcoef_d1 = 10;
+    s->subj_opt_inrar_coef.cover_rdoq_rcoef_d0 = 7;
+    s->subj_opt_inrar_coef.cover_rdoq_rcoef_d1 = 7;
+
+    s->smear_opt_cfc_coef.cfc_rmd_mode_intra_jcoef_d0 = 20;
+    s->smear_opt_cfc_coef.cfc_rmd_mode_intra_jcoef_d1 = 20;
+    s->smear_opt_cfc_coef.cfc_rdo_mode_intra_jcoef_d0 = 20;
+    s->smear_opt_cfc_coef.cfc_rdo_mode_intra_jcoef_d1 = 20;
+    s->smear_opt_cfc_coef.cfc_rdoq_rcoef_d0 = 7;
+    s->smear_opt_cfc_coef.cfc_rdoq_rcoef_d1 = 7;
+
+    s->subj_opt_rdo_split.choose_cu32_split_jcoef = 20;
+    s->subj_opt_rdo_split.choose_cu16_split_jcoef = 8;
+}
+
+static void vepu511_h265_set_anti_stripe_regs(H265eV511HalContext *ctx, H265eV511RegSet *regs)
+{
+    H265eVepu511Sqi *s = &regs->reg_sqi;
+    pre_cst_par* pre_i32 = (pre_cst_par*)&s->preintra32_cst;
+    pre_cst_par* pre_i16 = (pre_cst_par*)&s->preintra16_cst;
+
+    pre_i32->cst_wgt3.anti_strp_e = !!ctx->cfg->tune.atl_str;
+
+    pre_i32->cst_madi_thd0.madi_thd0 = 5;
+    pre_i32->cst_madi_thd0.madi_thd1 = 15;
+    pre_i32->cst_madi_thd0.madi_thd2 = 5;
+    pre_i32->cst_madi_thd0.madi_thd3 = 3;
+    pre_i32->cst_madi_thd1.madi_thd4 = 3;
+    pre_i32->cst_madi_thd1.madi_thd5 = 6;
+    pre_i32->cst_madi_thd1.madi_thd6 = 7;
+    pre_i32->cst_madi_thd1.madi_thd7 = 5;
+    pre_i32->cst_madi_thd2.madi_thd8 = 10;
+    pre_i32->cst_madi_thd2.madi_thd9 = 5;
+    pre_i32->cst_madi_thd2.madi_thd10 = 7;
+    pre_i32->cst_madi_thd2.madi_thd11 = 5;
+    pre_i32->cst_madi_thd3.madi_thd12 = 7;
+    pre_i32->cst_madi_thd3.madi_thd13 = 5;
+    pre_i32->cst_madi_thd3.mode_th = 5;
+
+    pre_i32->cst_wgt0.wgt0 = 20;
+    pre_i32->cst_wgt0.wgt1 = 18;
+    pre_i32->cst_wgt0.wgt2 = 19;
+    pre_i32->cst_wgt0.wgt3 = 18;
+    pre_i32->cst_wgt1.wgt4 = 12;
+    pre_i32->cst_wgt1.wgt5 = 6;
+    pre_i32->cst_wgt1.wgt6 = 13;
+    pre_i32->cst_wgt1.wgt7 = 9;
+    pre_i32->cst_wgt2.wgt8 = 12;
+    pre_i32->cst_wgt2.wgt9 = 6;
+    pre_i32->cst_wgt2.wgt10 = 13;
+    pre_i32->cst_wgt2.wgt11 = 9;
+    pre_i32->cst_wgt3.wgt12 = 18;
+    pre_i32->cst_wgt3.wgt13 = 17;
+    pre_i32->cst_wgt3.wgt14 = 17;
+
+    pre_i16->cst_madi_thd0.madi_thd0 = 5;
+    pre_i16->cst_madi_thd0.madi_thd1 = 15;
+    pre_i16->cst_madi_thd0.madi_thd2 = 5;
+    pre_i16->cst_madi_thd0.madi_thd3 = 3;
+    pre_i16->cst_madi_thd1.madi_thd4 = 3;
+    pre_i16->cst_madi_thd1.madi_thd5 = 6;
+    pre_i16->cst_madi_thd1.madi_thd6 = 7;
+    pre_i16->cst_madi_thd1.madi_thd7 = 5;
+    pre_i16->cst_madi_thd2.madi_thd8 = 10;
+    pre_i16->cst_madi_thd2.madi_thd9 = 5;
+    pre_i16->cst_madi_thd2.madi_thd10 = 7;
+    pre_i16->cst_madi_thd2.madi_thd11 = 5;
+    pre_i16->cst_madi_thd3.madi_thd12 = 7;
+    pre_i16->cst_madi_thd3.madi_thd13 = 5;
+    pre_i16->cst_madi_thd3.mode_th = 5;
+
+    pre_i16->cst_wgt0.wgt0 = 20;
+    pre_i16->cst_wgt0.wgt1 = 18;
+    pre_i16->cst_wgt0.wgt2 = 19;
+    pre_i16->cst_wgt0.wgt3 = 18;
+    pre_i16->cst_wgt1.wgt4 = 12;
+    pre_i16->cst_wgt1.wgt5 = 6;
+    pre_i16->cst_wgt1.wgt6 = 13;
+    pre_i16->cst_wgt1.wgt7 = 9;
+    pre_i16->cst_wgt2.wgt8 = 12;
+    pre_i16->cst_wgt2.wgt9 = 6;
+    pre_i16->cst_wgt2.wgt10 = 13;
+    pre_i16->cst_wgt2.wgt11 = 9;
+    pre_i16->cst_wgt3.wgt12 = 18;
+    pre_i16->cst_wgt3.wgt13 = 17;
+    pre_i16->cst_wgt3.wgt14 = 17;
+
+    pre_i32->cst_madi_thd3.qp_thd = 28;
+    pre_i32->cst_wgt3.lambda_mv_bit_0 = 5; // lv32
+    pre_i32->cst_wgt3.lambda_mv_bit_1 = 4; // lv16
+    pre_i16->cst_wgt3.lambda_mv_bit_0 = 4; // lv8
+    pre_i16->cst_wgt3.lambda_mv_bit_1 = 3; // lv4
+}
+
+static MPP_RET vepu511_h265_set_rdo_regs(H265eV511RegSet *regs)
+{
+    Vepu511RcRoi *reg_rc = &regs->reg_rc_roi;
+
+    reg_rc->cudecis_thd0.base_thre_rough_mad32_intra           = 9;
+    reg_rc->cudecis_thd0.delta0_thre_rough_mad32_intra         = 10;
+    reg_rc->cudecis_thd0.delta1_thre_rough_mad32_intra         = 55;
+    reg_rc->cudecis_thd0.delta2_thre_rough_mad32_intra         = 55;
+    reg_rc->cudecis_thd0.delta3_thre_rough_mad32_intra         = 66;
+    reg_rc->cudecis_thd0.delta4_thre_rough_mad32_intra_low5    = 2;
+
+    reg_rc->cudecis_thd1.delta4_thre_rough_mad32_intra_high2   = 2;
+    reg_rc->cudecis_thd1.delta5_thre_rough_mad32_intra         = 74;
+    reg_rc->cudecis_thd1.delta6_thre_rough_mad32_intra         = 106;
+    reg_rc->cudecis_thd1.base_thre_fine_mad32_intra            = 8;
+    reg_rc->cudecis_thd1.delta0_thre_fine_mad32_intra          = 0;
+    reg_rc->cudecis_thd1.delta1_thre_fine_mad32_intra          = 13;
+    reg_rc->cudecis_thd1.delta2_thre_fine_mad32_intra_low3     = 6;
+
+    reg_rc->cudecis_thd2.delta2_thre_fine_mad32_intra_high2    = 1;
+    reg_rc->cudecis_thd2.delta3_thre_fine_mad32_intra          = 17;
+    reg_rc->cudecis_thd2.delta4_thre_fine_mad32_intra          = 23;
+    reg_rc->cudecis_thd2.delta5_thre_fine_mad32_intra          = 50;
+    reg_rc->cudecis_thd2.delta6_thre_fine_mad32_intra          = 54;
+    reg_rc->cudecis_thd2.base_thre_str_edge_mad32_intra        = 6;
+    reg_rc->cudecis_thd2.delta0_thre_str_edge_mad32_intra      = 0;
+    reg_rc->cudecis_thd2.delta1_thre_str_edge_mad32_intra      = 0;
+
+    reg_rc->cudecis_thd3.delta2_thre_str_edge_mad32_intra      = 3;
+    reg_rc->cudecis_thd3.delta3_thre_str_edge_mad32_intra      = 8;
+    reg_rc->cudecis_thd3.base_thre_str_edge_bgrad32_intra      = 25;
+    reg_rc->cudecis_thd3.delta0_thre_str_edge_bgrad32_intra    = 0;
+    reg_rc->cudecis_thd3.delta1_thre_str_edge_bgrad32_intra    = 0;
+    reg_rc->cudecis_thd3.delta2_thre_str_edge_bgrad32_intra    = 7;
+    reg_rc->cudecis_thd3.delta3_thre_str_edge_bgrad32_intra    = 19;
+    reg_rc->cudecis_thd3.base_thre_mad16_intra                 = 6;
+    reg_rc->cudecis_thd3.delta0_thre_mad16_intra               = 0;
+
+    reg_rc->cudecis_thd4.delta1_thre_mad16_intra          = 3;
+    reg_rc->cudecis_thd4.delta2_thre_mad16_intra          = 3;
+    reg_rc->cudecis_thd4.delta3_thre_mad16_intra          = 24;
+    reg_rc->cudecis_thd4.delta4_thre_mad16_intra          = 28;
+    reg_rc->cudecis_thd4.delta5_thre_mad16_intra          = 40;
+    reg_rc->cudecis_thd4.delta6_thre_mad16_intra          = 52;
+    reg_rc->cudecis_thd4.delta0_thre_mad16_ratio_intra    = 7;
+
+    reg_rc->cudecis_thd5.delta1_thre_mad16_ratio_intra           =  7;
+    reg_rc->cudecis_thd5.delta2_thre_mad16_ratio_intra           =  2;
+    reg_rc->cudecis_thd5.delta3_thre_mad16_ratio_intra           =  2;
+    reg_rc->cudecis_thd5.delta4_thre_mad16_ratio_intra           =  0;
+    reg_rc->cudecis_thd5.delta5_thre_mad16_ratio_intra           =  0;
+    reg_rc->cudecis_thd5.delta6_thre_mad16_ratio_intra           =  0;
+    reg_rc->cudecis_thd5.delta7_thre_mad16_ratio_intra           =  4;
+    reg_rc->cudecis_thd5.delta0_thre_rough_bgrad32_intra         =  1;
+    reg_rc->cudecis_thd5.delta1_thre_rough_bgrad32_intra         =  5;
+    reg_rc->cudecis_thd5.delta2_thre_rough_bgrad32_intra_low4    =  8;
+
+    reg_rc->cudecis_thd6.delta2_thre_rough_bgrad32_intra_high2    = 2;
+    reg_rc->cudecis_thd6.delta3_thre_rough_bgrad32_intra          = 540;
+    reg_rc->cudecis_thd6.delta4_thre_rough_bgrad32_intra          = 692;
+    reg_rc->cudecis_thd6.delta5_thre_rough_bgrad32_intra_low10    = 866;
+
+    reg_rc->cudecis_thd7.delta5_thre_rough_bgrad32_intra_high1   = 1;
+    reg_rc->cudecis_thd7.delta6_thre_rough_bgrad32_intra         = 3286;
+    reg_rc->cudecis_thd7.delta7_thre_rough_bgrad32_intra         = 6620;
+    reg_rc->cudecis_thd7.delta0_thre_bgrad16_ratio_intra         = 8;
+    reg_rc->cudecis_thd7.delta1_thre_bgrad16_ratio_intra_low2    = 3;
+
+    reg_rc->cudecis_thd8.delta1_thre_bgrad16_ratio_intra_high2    = 2;
+    reg_rc->cudecis_thd8.delta2_thre_bgrad16_ratio_intra          = 15;
+    reg_rc->cudecis_thd8.delta3_thre_bgrad16_ratio_intra          = 15;
+    reg_rc->cudecis_thd8.delta4_thre_bgrad16_ratio_intra          = 13;
+    reg_rc->cudecis_thd8.delta5_thre_bgrad16_ratio_intra          = 13;
+    reg_rc->cudecis_thd8.delta6_thre_bgrad16_ratio_intra          = 7;
+    reg_rc->cudecis_thd8.delta7_thre_bgrad16_ratio_intra          = 15;
+    reg_rc->cudecis_thd8.delta0_thre_fme_ratio_inter              = 4;
+    reg_rc->cudecis_thd8.delta1_thre_fme_ratio_inter              = 4;
+
+    reg_rc->cudecis_thd9.delta2_thre_fme_ratio_inter    = 3;
+    reg_rc->cudecis_thd9.delta3_thre_fme_ratio_inter    = 2;
+    reg_rc->cudecis_thd9.delta4_thre_fme_ratio_inter    = 0;
+    reg_rc->cudecis_thd9.delta5_thre_fme_ratio_inter    = 0;
+    reg_rc->cudecis_thd9.delta6_thre_fme_ratio_inter    = 0;
+    reg_rc->cudecis_thd9.delta7_thre_fme_ratio_inter    = 0;
+    reg_rc->cudecis_thd9.base_thre_fme32_inter          = 4;
+    reg_rc->cudecis_thd9.delta0_thre_fme32_inter        = 2;
+    reg_rc->cudecis_thd9.delta1_thre_fme32_inter        = 7;
+    reg_rc->cudecis_thd9.delta2_thre_fme32_inter        = 12;
+
+    reg_rc->cudecis_thd10.delta3_thre_fme32_inter    = 23;
+    reg_rc->cudecis_thd10.delta4_thre_fme32_inter    = 41;
+    reg_rc->cudecis_thd10.delta5_thre_fme32_inter    = 71;
+    reg_rc->cudecis_thd10.delta6_thre_fme32_inter    = 123;
+    reg_rc->cudecis_thd10.thre_cme32_inter           = 48;
+
+    reg_rc->cudecis_thd11.delta0_thre_mad_fme_ratio_inter    = 0;
+    reg_rc->cudecis_thd11.delta1_thre_mad_fme_ratio_inter    = 7;
+    reg_rc->cudecis_thd11.delta2_thre_mad_fme_ratio_inter    = 7;
+    reg_rc->cudecis_thd11.delta3_thre_mad_fme_ratio_inter    = 6;
+    reg_rc->cudecis_thd11.delta4_thre_mad_fme_ratio_inter    = 5;
+    reg_rc->cudecis_thd11.delta5_thre_mad_fme_ratio_inter    = 4;
+    reg_rc->cudecis_thd11.delta6_thre_mad_fme_ratio_inter    = 4;
+    reg_rc->cudecis_thd11.delta7_thre_mad_fme_ratio_inter    = 4;
+
+    reg_rc->cudecis_thd12.delta0_thre_mad_fme_ratio_inter    = 1;
+    reg_rc->cudecis_thd12.delta1_thre_mad_fme_ratio_inter    = 3;
+    reg_rc->cudecis_thd12.delta2_thre_mad_fme_ratio_inter    = 6;
+    reg_rc->cudecis_thd12.delta3_thre_mad_fme_ratio_inter    = 9;
+    reg_rc->cudecis_thd12.delta4_thre_mad_fme_ratio_inter    = 10;
+    reg_rc->cudecis_thd12.delta5_thre_mad_fme_ratio_inter    = 11;
+    reg_rc->cudecis_thd12.delta6_thre_mad_fme_ratio_inter    = 12;
+    reg_rc->cudecis_thd12.delta7_thre_mad_fme_ratio_inter    = 15;
+
+    return MPP_OK;
+}
+
+static void vepu511_h265_set_sao_regs(H265eV511RegSet *regs)
+{
+    H265eVepu511Sqi *sqi = &regs->reg_sqi;
+
+    /* Weight values are set to 4 to disable SAO subjective optimization.
+     * They are not under the control of anti_blur_en.
+     */
+    sqi->subj_anti_blur_wgt3.merge_cost_dist_eo_wgt0 = 4;
+    sqi->subj_anti_blur_wgt3.merge_cost_dist_bo_wgt0 = 4;
+    sqi->subj_anti_blur_wgt4.merge_cost_dist_eo_wgt1 = 4;
+    sqi->subj_anti_blur_wgt4.merge_cost_dist_bo_wgt1 = 4;
+    sqi->subj_anti_blur_wgt4.merge_cost_bit_eo_wgt0 = 4;
+    sqi->subj_anti_blur_wgt4.merge_cost_bit_bo_wgt0 = 4;
+}
+
+static void vepu511_h265_set_slice_regs(H265eSyntax_new *syn, H265eVepu511Frame *regs)
+{
+    regs->synt_sps.smpl_adpt_ofst_e     = syn->pp.sample_adaptive_offset_enabled_flag;
+    regs->synt_sps.num_st_ref_pic       = syn->pp.num_short_term_ref_pic_sets;
+    regs->synt_sps.num_lt_ref_pic       = syn->pp.num_long_term_ref_pics_sps;
+    regs->synt_sps.lt_ref_pic_prsnt     = syn->pp.long_term_ref_pics_present_flag;
+    regs->synt_sps.tmpl_mvp_e           = syn->pp.sps_temporal_mvp_enabled_flag;
+    regs->synt_sps.log2_max_poc_lsb     = syn->pp.log2_max_pic_order_cnt_lsb_minus4;
+    regs->synt_sps.strg_intra_smth      = syn->pp.strong_intra_smoothing_enabled_flag;
+
+    regs->synt_pps.dpdnt_sli_seg_en     = syn->pp.dependent_slice_segments_enabled_flag;
+    regs->synt_pps.out_flg_prsnt_flg    = syn->pp.output_flag_present_flag;
+    regs->synt_pps.num_extr_sli_hdr     = syn->pp.num_extra_slice_header_bits;
+    regs->synt_pps.sgn_dat_hid_en       = syn->pp.sign_data_hiding_enabled_flag;
+    regs->synt_pps.cbc_init_prsnt_flg   = syn->pp.cabac_init_present_flag;
+    regs->synt_pps.pic_init_qp          = syn->pp.init_qp_minus26 + 26;
+    regs->synt_pps.cu_qp_dlt_en         = syn->pp.cu_qp_delta_enabled_flag;
+    regs->synt_pps.chrm_qp_ofst_prsn    = syn->pp.pps_slice_chroma_qp_offsets_present_flag;
+    regs->synt_pps.lp_fltr_acrs_sli     = syn->pp.pps_loop_filter_across_slices_enabled_flag;
+    regs->synt_pps.dblk_fltr_ovrd_en    = syn->pp.deblocking_filter_override_enabled_flag;
+    regs->synt_pps.lst_mdfy_prsnt_flg   = syn->pp.lists_modification_present_flag;
+    regs->synt_pps.sli_seg_hdr_extn     = syn->pp.slice_segment_header_extension_present_flag;
+    regs->synt_pps.cu_qp_dlt_depth      = syn->pp.diff_cu_qp_delta_depth;
+    regs->synt_pps.lpf_fltr_acrs_til    = syn->pp.loop_filter_across_tiles_enabled_flag;
+
+    regs->synt_sli0.cbc_init_flg        = syn->sp.cbc_init_flg;
+    regs->synt_sli0.mvd_l1_zero_flg     = syn->sp.mvd_l1_zero_flg;
+    regs->synt_sli0.ref_pic_lst_mdf_l0  = syn->sp.ref_pic_lst_mdf_l0;
+
+    regs->synt_sli0.num_refidx_l1_act   = syn->sp.num_refidx_l1_act;
+    regs->synt_sli0.num_refidx_l0_act   = syn->sp.num_refidx_l0_act;
+
+    regs->synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd;
+
+    regs->synt_sli0.sli_sao_chrm_flg    = syn->sp.sli_sao_chrm_flg;
+    regs->synt_sli0.sli_sao_luma_flg    = syn->sp.sli_sao_luma_flg;
+    regs->synt_sli0.sli_tmprl_mvp_e     = syn->sp.sli_tmprl_mvp_en;
+    regs->common.enc_pic.num_pic_tot_cur_hevc  = syn->sp.tot_poc_num;
+
+    regs->synt_sli0.pic_out_flg         = syn->sp.pic_out_flg;
+    regs->synt_sli0.sli_type            = syn->sp.slice_type;
+    regs->synt_sli0.sli_rsrv_flg        = syn->sp.slice_rsrv_flg;
+    regs->synt_sli0.dpdnt_sli_seg_flg   = syn->sp.dpdnt_sli_seg_flg;
+    regs->synt_sli0.sli_pps_id          = syn->sp.sli_pps_id;
+    regs->synt_sli0.no_out_pri_pic      = syn->sp.no_out_pri_pic;
+
+
+    regs->synt_sli1.sp_tc_ofst_div2       = syn->sp.sli_tc_ofst_div2;;
+    regs->synt_sli1.sp_beta_ofst_div2     = syn->sp.sli_beta_ofst_div2;
+    regs->synt_sli1.sli_lp_fltr_acrs_sli  = syn->sp.sli_lp_fltr_acrs_sli;
+    regs->synt_sli1.sp_dblk_fltr_dis      = syn->sp.sli_dblk_fltr_dis;
+    regs->synt_sli1.dblk_fltr_ovrd_flg    = syn->sp.dblk_fltr_ovrd_flg;
+    regs->synt_sli1.sli_cb_qp_ofst = syn->pp.pps_slice_chroma_qp_offsets_present_flag ?
+                                     syn->sp.sli_cb_qp_ofst : syn->pp.pps_cb_qp_offset;
+    regs->synt_sli1.max_mrg_cnd           = syn->sp.max_mrg_cnd;
+
+    regs->synt_sli1.col_ref_idx           = syn->sp.col_ref_idx;
+    regs->synt_sli1.col_frm_l0_flg        = syn->sp.col_frm_l0_flg;
+    regs->synt_sli2.sli_poc_lsb           = syn->sp.sli_poc_lsb;
+    regs->synt_sli2.sli_hdr_ext_len       = syn->sp.sli_hdr_ext_len;
+}
+
+static void vepu511_h265_set_ref_regs(H265eSyntax_new *syn, H265eVepu511Frame *regs)
+{
+    regs->synt_refm0.st_ref_pic_flg = syn->sp.st_ref_pic_flg;
+    regs->synt_refm0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0;
+    regs->synt_refm0.num_lt_pic = syn->sp.num_lt_pic;
+
+    regs->synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
+    regs->synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
+    regs->synt_refm1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0;
+    regs->synt_refm1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1;
+    regs->synt_refm1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2;
+    regs->synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
+    regs->synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
+    regs->synt_refm1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1;
+    regs->synt_refm1.num_negative_pics = syn->sp.num_neg_pic;
+    regs->synt_refm1.num_pos_pic = syn->sp.num_pos_pic;
+
+    regs->synt_refm1.used_by_s0_flg = syn->sp.used_by_s0_flg;
+    regs->synt_refm2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10;
+    regs->synt_refm2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11;
+    regs->synt_refm3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12;
+    regs->synt_refm3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13;
+
+    regs->synt_long_refm0.poc_lsb_lt1 = syn->sp.poc_lsb_lt1;
+    regs->synt_long_refm1.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1;
+    regs->synt_long_refm0.poc_lsb_lt2 = syn->sp.poc_lsb_lt2;
+    regs->synt_refm1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2;
+    regs->synt_long_refm1.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2;
+    regs->synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0;
+    regs->synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
+
+    return;
+}
+
+static void vepu511_h265_set_atf_regs(H265eV511HalContext *ctx, H265eV511RegSet *regs)
+{
+    H265eVepu511Sqi *reg = &regs->reg_sqi;
+    RK_U32 str = ctx->cfg->tune.atf_str;
+    rdo_b32_skip_par *p_rdo_b32_skip = NULL;
+    rdo_b32_noskip_par *p_rdo_b32_noskip = NULL;
+    rdo_skip_par *p_rdo_skip = NULL;
+    rdo_noskip_par *p_rdo_noskip = NULL;
+
+    static RK_U16 b32_skip_thd2[4] = { 15, 15, 15, 200 };
+    static RK_U16 b32_skip_thd3[4] = { 72, 72, 72, 1000 };
+    static RK_U8 b32_skip_wgt0[4] = { 16, 20, 20, 16 };
+    static RK_U8 b32_skip_wgt3[4] = { 16, 16, 16, 17 };
+    static RK_U16 b16_skip_thd2[4] = { 15, 15, 15, 200 };
+    static RK_U16 b16_skip_thd3[4] = { 25, 25, 25, 1000 };
+    static RK_U8 b16_skip_wgt0[4] = { 16, 20, 20, 16 };
+    static RK_U8 b16_skip_wgt3[4] = { 16, 16, 16, 17 };
+    static RK_U16 b32_intra_thd0[4] = { 20, 20, 20, 24 };
+    static RK_U16 b32_intra_thd1[4] = { 40, 40, 40, 48 };
+    static RK_U16 b32_intra_thd2[4] = { 60, 72, 72, 96 };
+    static RK_U8 b32_intra_wgt0[4] = { 16, 22, 27, 28 };
+    static RK_U8 b32_intra_wgt1[4] = { 16, 20, 25, 26 };
+    static RK_U8 b32_intra_wgt2[4] = { 16, 18, 20, 24 };
+    static RK_U16 b16_intra_thd0[4] = { 20, 20, 20, 24 };
+    static RK_U16 b16_intra_thd1[4] = { 40, 40, 40, 48 };
+    static RK_U16 b16_intra_thd2[4] = { 60, 72, 72, 96 };
+    static RK_U8 b16_intra_wgt0[4] = { 16, 22, 27, 28 };
+    static RK_U8 b16_intra_wgt1[4] = { 16, 20, 25, 26 };
+    static RK_U8 b16_intra_wgt2[4] = { 16, 18, 20, 24 };
+
+    regs->reg_frm.rdo_cfg.atf_e = !!str;
+
+    p_rdo_b32_skip = &reg->rdo_b32_skip;
+    p_rdo_b32_skip->atf_thd0.madp_thd0 = 5;
+    p_rdo_b32_skip->atf_thd0.madp_thd1 = 10;
+    p_rdo_b32_skip->atf_thd1.madp_thd2 = b32_skip_thd2[str];
+    p_rdo_b32_skip->atf_thd1.madp_thd3 = b32_skip_thd3[str];
+    p_rdo_b32_skip->atf_wgt0.wgt0 = b32_skip_wgt0[str];
+    p_rdo_b32_skip->atf_wgt0.wgt1 = 16;
+    p_rdo_b32_skip->atf_wgt0.wgt2 = 16;
+    p_rdo_b32_skip->atf_wgt0.wgt3 = b32_skip_wgt3[str];
+    p_rdo_b32_skip->atf_thd0.flckr_frame_qp_en = 1;
+    p_rdo_b32_skip->atf_thd0.flckr_lgt_chng_en = 1;
+
+    p_rdo_b32_noskip = &reg->rdo_b32_inter;
+    p_rdo_b32_noskip->atf_thd0.madp_thd0 = 20;
+    p_rdo_b32_noskip->atf_thd0.madp_thd1 = 40;
+    p_rdo_b32_noskip->atf_thd1.madp_thd2 = 72;
+    p_rdo_b32_noskip->atf_wgt.wgt0 = 16;
+    p_rdo_b32_noskip->atf_wgt.wgt1 = 16;
+    p_rdo_b32_noskip->atf_wgt.wgt2 = 16;
+
+    p_rdo_noskip = &reg->rdo_b32_intra;
+    p_rdo_noskip->ratf_thd0.madp_thd0 = b32_intra_thd0[str];
+    p_rdo_noskip->ratf_thd0.madp_thd1 = b32_intra_thd1[str];
+    p_rdo_noskip->ratf_thd1.madp_thd2 = b32_intra_thd2[str];
+    p_rdo_noskip->atf_wgt.wgt0 = b32_intra_wgt0[str];
+    p_rdo_noskip->atf_wgt.wgt1 = b32_intra_wgt1[str];
+    p_rdo_noskip->atf_wgt.wgt2 = b32_intra_wgt2[str];
+
+    p_rdo_skip = &reg->rdo_b16_skip;
+    p_rdo_skip->atf_thd0.madp_thd0 = 1;
+    p_rdo_skip->atf_thd0.madp_thd1 = 10;
+    p_rdo_skip->atf_thd1.madp_thd2 = b16_skip_thd2[str];
+    p_rdo_skip->atf_thd1.madp_thd3 = b16_skip_thd3[str];
+    p_rdo_skip->atf_wgt0.wgt0 = b16_skip_wgt0[str];
+    p_rdo_skip->atf_wgt0.wgt1 = 16;
+    p_rdo_skip->atf_wgt0.wgt2 = 16;
+    p_rdo_skip->atf_wgt0.wgt3 = b16_skip_wgt3[str];
+
+    p_rdo_noskip = &reg->rdo_b16_inter;
+    p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
+    p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
+    p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
+    p_rdo_noskip->atf_wgt.wgt0 = 16;
+    p_rdo_noskip->atf_wgt.wgt1 = 16;
+    p_rdo_noskip->atf_wgt.wgt2 = 16;
+    p_rdo_noskip->atf_wgt.wgt3 = 16;
+
+    p_rdo_noskip = &reg->rdo_b16_intra;
+    p_rdo_noskip->ratf_thd0.madp_thd0 = b16_intra_thd0[str];
+    p_rdo_noskip->ratf_thd0.madp_thd1 = b16_intra_thd1[str];
+    p_rdo_noskip->ratf_thd1.madp_thd2 = b16_intra_thd2[str];
+    p_rdo_noskip->atf_wgt.wgt0 = b16_intra_wgt0[str];
+    p_rdo_noskip->atf_wgt.wgt1 = b16_intra_wgt1[str];
+    p_rdo_noskip->atf_wgt.wgt2 = b16_intra_wgt2[str];
+    p_rdo_noskip->atf_wgt.wgt3 = 16;
+}
+
+static void vepu511_h265_set_aq(H265eV511HalContext *ctx, H265eV511RegSet *regs)
+{
+    MppEncHwCfg *hw = &ctx->cfg->hw;
+    Vepu511RcRoi *rc_regs =  &regs->reg_rc_roi;
+    RK_U8* thd = (RK_U8*)&rc_regs->aq_tthd0;
+    RK_S32 *aq_step, *aq_rnge;
+    RK_U32 *aq_thd;
+    RK_U32 i;
+
+    if (ctx->frame_type == INTRA_FRAME) {
+        aq_thd = &hw->aq_thrd_i[0];
+        aq_step = &hw->aq_step_i[0];
+        aq_rnge = &hw->aq_rnge_arr[0];
+    } else {
+        aq_thd = &hw->aq_thrd_p[0];
+        aq_step = &hw->aq_step_p[0];
+        aq_rnge = &hw->aq_rnge_arr[5];
+    }
+
+    rc_regs->aq_stp0.aq_stp_s0 = aq_step[0] & 0x1f;
+    rc_regs->aq_stp0.aq_stp_0t1 = aq_step[1] & 0x1f;
+    rc_regs->aq_stp0.aq_stp_1t2 = aq_step[2] & 0x1f;
+    rc_regs->aq_stp0.aq_stp_2t3 = aq_step[3] & 0x1f;
+    rc_regs->aq_stp0.aq_stp_3t4 = aq_step[4] & 0x1f;
+    rc_regs->aq_stp0.aq_stp_4t5 = aq_step[5] & 0x1f;
+    rc_regs->aq_stp1.aq_stp_5t6 = aq_step[6] & 0x1f;
+    rc_regs->aq_stp1.aq_stp_6t7 = aq_step[7] & 0x1f;
+    rc_regs->aq_stp1.aq_stp_7t8 = 0;
+    rc_regs->aq_stp1.aq_stp_8t9 = aq_step[8] & 0x1f;
+    rc_regs->aq_stp1.aq_stp_9t10 = aq_step[9] & 0x1f;
+    rc_regs->aq_stp1.aq_stp_10t11 = aq_step[10] & 0x1f;
+    rc_regs->aq_stp2.aq_stp_11t12 = aq_step[11] & 0x1f;
+    rc_regs->aq_stp2.aq_stp_12t13 = aq_step[12] & 0x1f;
+    rc_regs->aq_stp2.aq_stp_13t14 = aq_step[13] & 0x1f;
+    rc_regs->aq_stp2.aq_stp_14t15 = aq_step[14] & 0x1f;
+    rc_regs->aq_stp2.aq_stp_b15 = aq_step[15];
+
+    for (i = 0; i < 16; i++)
+        thd[i] = aq_thd[i];
+
+    rc_regs->aq_clip.aq16_rnge = aq_rnge[0];
+    rc_regs->aq_clip.aq32_rnge = aq_rnge[1];
+    rc_regs->aq_clip.aq8_rnge = aq_rnge[2];
+    rc_regs->aq_clip.aq16_dif0 = aq_rnge[3];
+    rc_regs->aq_clip.aq16_dif1 = aq_rnge[4];
+
+    rc_regs->aq_clip.aq_rme_en = 1;
+    rc_regs->aq_clip.aq_cme_en = 1;
+}
+
+static void vepu511_h265_global_cfg_set(H265eV511HalContext *ctx, H265eV511RegSet *regs)
+{
+    H265eVepu511Frame *reg_frm = &regs->reg_frm;
+    H265eVepu511Param *reg_param = &regs->reg_param;
+    RK_S32 lambda_idx_p = ctx->cfg->tune.lambda_idx_i;
+
+    reg_frm->sao_cfg.sao_lambda_multi = ctx->cfg->codec.h265.sao_cfg.sao_bit_ratio;
+
+    if (ctx->frame_type == INTRA_FRAME) {
+        memcpy(&reg_param->pprd_lamb_satd_0_51[0], lambda_tbl_pre_intra, sizeof(lambda_tbl_pre_intra));
+    } else {
+        memcpy(&reg_param->pprd_lamb_satd_0_51[0], lambda_tbl_pre_inter, sizeof(lambda_tbl_pre_inter));
+    }
+
+    {
+        RK_U32 *lambda_tbl;
+
+        if (ctx->frame_type == INTRA_FRAME) {
+            lambda_tbl = &rdo_lambda_table_I[lambda_idx_p];
+        } else {
+            lambda_idx_p = ctx->cfg->tune.lambda_idx_p;
+            lambda_tbl = &rdo_lambda_table_P[lambda_idx_p];
+        }
+
+        memcpy(&reg_param->rdo_wgta_qp_grpa_0_51[0], lambda_tbl, H265E_LAMBDA_TAB_SIZE);
+    }
+
+    /* 0x1064 */
+    regs->reg_rc_roi.madi_st_thd.madi_th0 = 5;
+    regs->reg_rc_roi.madi_st_thd.madi_th1 = 12;
+    regs->reg_rc_roi.madi_st_thd.madi_th2 = 20;
+    /* 0x1068 */
+    regs->reg_rc_roi.madp_st_thd0.madp_th0 = 4 << 4;
+    regs->reg_rc_roi.madp_st_thd0.madp_th1 = 9 << 4;
+    /* 0x106C */
+    regs->reg_rc_roi.madp_st_thd1.madp_th2 = 15 << 4;
+    regs->reg_param.prmd_intra_lamb_ofst.lambda_luma_offset = 11;
+    regs->reg_param.prmd_intra_lamb_ofst.lambda_chroma_offset = 11;
+
+}
+
+MPP_RET hal_h265e_vepu511_gen_regs(void *hal, HalEncTask *task)
+{
+    H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
+    Vepu511H265eFrmCfg *frm_cfg = ctx->frm;
+    H265eV511RegSet *regs = frm_cfg->regs_set;
+    MPP_RET ret = MPP_OK;
+
+    HalEncTask *enc_task = task;
+    H265eSyntax_new *syn = ctx->syn;
+    VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
+    H265eVepu511Frame *reg_frm = &regs->reg_frm;
+    EncFrmStatus *frm = &task->rc_task->frm;
+
+    hal_h265e_enter();
+
+    hal_h265e_dbg_simple("frame %d | type %d | start gen regs11",
+                         ctx->frame_num, ctx->frame_type);
+
+    memset(regs, 0, sizeof(H265eV511RegSet));
+
+    vepu511_h265_set_normal(ctx, regs);
+    vepu511_h265_set_prep(ctx, task, regs);
+    vepu511_h265_set_me_regs(ctx, syn , regs);
+    vepu511_h265_set_split(regs, ctx->cfg);
+    vepu511_h265_set_hw_address(ctx, reg_frm, task);
+    vepu511_h265_set_pp_regs(regs, fmt, &ctx->cfg->prep, task);
+    vepu511_h265_set_vsp_filtering(ctx, regs);
+    vepu511_h265_set_rc_regs(ctx, regs, task);
+    vepu511_h265_set_rdo_regs(regs);
+    vepu511_h265_set_quant_regs(ctx, regs);
+    vepu511_h265_set_sao_regs(regs);
+    vepu511_h265_set_slice_regs(syn, reg_frm);
+    vepu511_h265_set_ref_regs(syn, reg_frm);
+
+    ret = vepu511_h265_set_patch_info(syn, (Vepu541Fmt)fmt->format, ctx->reg_cfg, enc_task);
+    if (ret)
+        return ret;
+
+    setup_vepu511_ext_line_buf(ctx, regs);
+    vepu511_h265_set_atf_regs(ctx, regs);
+    vepu511_h265_set_anti_stripe_regs(ctx, regs);
+    vepu511_h265_set_atr_regs(regs);
+    vepu511_h265_set_smear_regs(ctx, regs);
+    vepu511_h265_set_scaling_list(regs);
+    vepu511_h265_set_aq(ctx, regs);
+
+    if (ctx->osd_cfg.osd_data3)
+        vepu511_set_osd(&ctx->osd_cfg, &regs->reg_osd.osd_comb_cfg);
+
+    if (ctx->roi_data)
+        vepu511_set_roi(&regs->reg_rc_roi.roi_cfg, ctx->roi_data,
+                        ctx->cfg->prep.width, ctx->cfg->prep.height);
+
+    /*paramet cfg*/
+    vepu511_h265_global_cfg_set(ctx, regs);
+
+    /* two pass register patch */
+    if (frm->save_pass1)
+        vepu511_h265e_save_pass1_patch(regs, ctx, syn->pp.tiles_enabled_flag);
+
+    if (frm->use_pass1)
+        vepu511_h265e_use_pass1_patch(regs, ctx);
+
+    ctx->frame_num++;
+
+    hal_h265e_leave();
+    return MPP_OK;
+}
+
+MPP_RET hal_h265e_vepu511_start(void *hal, HalEncTask *enc_task)
+{
+    MPP_RET ret = MPP_OK;
+    H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
+    Vepu511H265eFrmCfg *frm = ctx->frm;
+    RK_U32 *regs = (RK_U32*)frm->regs_set;
+    H265eV511RegSet *hw_regs = frm->regs_set;
+    H265eV511StatusElem *reg_out = (H265eV511StatusElem *)frm->regs_ret;
+    MppDevRegWrCfg cfg;
+    MppDevRegRdCfg cfg1;
+    RK_U32 i = 0;
+
+    hal_h265e_enter();
+    if (enc_task->flags.err) {
+        hal_h265e_err("enc_task->flags.err %08x, return e arly",
+                      enc_task->flags.err);
+        return MPP_NOK;
+    }
+
+    cfg.reg = (RK_U32*)&hw_regs->reg_ctl;
+    cfg.size = sizeof(Vepu511ControlCfg);
+    cfg.offset = VEPU511_CTL_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    if (hal_h265e_debug & HAL_H265E_DBG_CTL_REGS) {
+        regs = (RK_U32*)&hw_regs->reg_ctl;
+        for (i = 0; i < sizeof(Vepu511ControlCfg) / 4; i++) {
+            hal_h265e_dbg_ctl("ctl reg[%04x]: 0%08x\n", i * 4, regs[i]);
+        }
+    }
+
+    cfg.reg = &hw_regs->reg_frm;
+    cfg.size = sizeof(H265eVepu511Frame);
+    cfg.offset = VEPU511_FRAME_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    if (hal_h265e_debug & HAL_H265E_DBG_REGS) {
+        regs = (RK_U32*)(&hw_regs->reg_frm);
+        for (i = 0; i < 32; i++) {
+            hal_h265e_dbg_regs("hw add cfg reg[%04x]: 0x%08x\n", i * 4, regs[i]);
+        }
+        regs += 32;
+        for (i = 0; i < (sizeof(H265eVepu511Frame) - 128) / 4; i++) {
+            hal_h265e_dbg_regs("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
+        }
+    }
+    cfg.reg = &hw_regs->reg_rc_roi;
+    cfg.size = sizeof(Vepu511RcRoi);
+    cfg.offset = VEPU511_RC_ROI_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    if (hal_h265e_debug & HAL_H265E_DBG_RCKUT_REGS) {
+        regs = (RK_U32*)&hw_regs->reg_rc_roi;
+        for (i = 0; i < sizeof(Vepu511RcRoi) / 4; i++) {
+            hal_h265e_dbg_rckut("set rc roi reg[%04x]: 0%08x\n", i * 4, regs[i]);
+        }
+    }
+
+    cfg.reg =  &hw_regs->reg_param;
+    cfg.size = sizeof(H265eVepu511Param);
+    cfg.offset = VEPU511_PARAM_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    if (hal_h265e_debug & HAL_H265E_DBG_WGT_REGS) {
+        regs = (RK_U32*)&hw_regs->reg_param;
+        for (i = 0; i < sizeof(H265eVepu511Param) / 4; i++) {
+            hal_h265e_dbg_wgt("set param reg[%04x]: 0%08x\n", i * 4, regs[i]);
+        }
+    }
+
+    cfg.reg = &hw_regs->reg_sqi;
+    cfg.size = sizeof(H265eVepu511Sqi);
+    cfg.offset = VEPU511_SQI_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    if (hal_h265e_debug & HAL_H265E_DBG_WGT_REGS) {
+        regs = (RK_U32*)&hw_regs->reg_sqi;
+        for (i = 0; i < sizeof(H265eVepu511Sqi) / 4; i++) {
+            hal_h265e_dbg_wgt("set sqi reg[%04x]: 0%08x\n", i * 4, regs[i]);
+        }
+    }
+
+    cfg.reg = &hw_regs->reg_scl;
+    cfg.size = sizeof(hw_regs->reg_scl);
+    cfg.offset = VEPU511_SCL_OFFSET ;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    if (hal_h265e_debug & HAL_H265E_DBG_WGT_REGS) {
+        regs = (RK_U32*)&hw_regs->reg_scl;
+        for (i = 0; i < sizeof(H265eVepu511SclCfg) / 4; i++) {
+            hal_h265e_dbg_wgt("set scl reg[%04x]: 0%08x\n", i * 4, regs[i]);
+        }
+    }
+
+    cfg.reg = &hw_regs->reg_osd;
+    cfg.size = sizeof(hw_regs->reg_osd);
+    cfg.offset = VEPU511_OSD_OFFSET ;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    if (hal_h265e_debug & HAL_H265E_DBG_WGT_REGS) {
+        regs = (RK_U32*)&hw_regs->reg_osd;
+        for (i = 0; i < sizeof(Vepu511OsdRegs) / 4; i++) {
+            hal_h265e_dbg_wgt("set osd reg[%04x]: 0%08x\n", i * 4, regs[i]);
+        }
+    }
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFS, ctx->reg_cfg);
+    if (ret) {
+        mpp_err_f("set register offsets failed %d\n", ret);
+        return ret;
+    }
+
+    cfg1.reg = &reg_out->hw_status;
+    cfg1.size = sizeof(RK_U32);
+    cfg1.offset = VEPU511_REG_BASE_HW_STATUS;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
+    if (ret) {
+        mpp_err_f("set register read failed %d\n", ret);
+        return ret;
+    }
+
+    cfg1.reg = &reg_out->st;
+    cfg1.size = sizeof(H265eV511StatusElem) - 4;
+    cfg1.offset = VEPU511_STATUS_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
+    if (ret) {
+        mpp_err_f("set register read failed %d\n", ret);
+        return ret;
+    }
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
+    if (ret) {
+        mpp_err_f("send cmd failed %d\n", ret);
+    }
+    hal_h265e_leave();
+    return ret;
+}
+
+static MPP_RET vepu511_h265_set_feedback(H265eV511HalContext *ctx, HalEncTask *enc_task)
+{
+    EncRcTaskInfo *hal_rc_ret = (EncRcTaskInfo *)&enc_task->rc_task->info;
+    Vepu511H265eFrmCfg *frm = ctx->frms[enc_task->flags.reg_idx];
+    Vepu511H265Fbk  *fb = &frm->feedback;
+    MppEncCfgSet    *cfg = ctx->cfg;
+    RK_S32 mb8_num = MPP_ALIGN(cfg->prep.width, 8) * MPP_ALIGN(cfg->prep.height, 8) / 64;
+    RK_S32 mb4_num = (mb8_num << 2);
+    H265eV511StatusElem *elem = (H265eV511StatusElem *)frm->regs_ret;
+    RK_U32 hw_status = elem->hw_status;
+
+    hal_h265e_enter();
+
+    fb->qp_sum += elem->st.qp_sum;
+    fb->out_strm_size += elem->st.bs_lgth_l32;
+    fb->sse_sum += (RK_S64)(elem->st.sse_h32 << 16) +
+                   (elem->st.st_sse_bsl.sse_l16 & 0xffff);
+
+    fb->hw_status = hw_status;
+    hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status);
+    if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH)
+        hal_h265e_err("RKV_ENC_INT_LINKTABLE_FINISH");
+
+    if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH)
+        hal_h265e_dbg_detail("RKV_ENC_INT_ONE_FRAME_FINISH");
+
+    if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH)
+        hal_h265e_dbg_detail("RKV_ENC_INT_ONE_SLICE_FINISH");
+
+    if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH)
+        hal_h265e_err("RKV_ENC_INT_SAFE_CLEAR_FINISH");
+
+    if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW)
+        hal_h265e_err("RKV_ENC_INT_BIT_STREAM_OVERFLOW");
+
+    if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL)
+        hal_h265e_err("RKV_ENC_INT_BUS_WRITE_FULL");
+
+    if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR)
+        hal_h265e_err("RKV_ENC_INT_BUS_WRITE_ERROR");
+
+    if (hw_status & RKV_ENC_INT_BUS_READ_ERROR)
+        hal_h265e_err("RKV_ENC_INT_BUS_READ_ERROR");
+
+    if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR)
+        hal_h265e_err("RKV_ENC_INT_TIMEOUT_ERROR");
+
+    fb->st_mb_num += elem->st.st_bnum_b16.num_b16;
+
+    fb->st_lvl64_inter_num += elem->st.st_pnum_p64.pnum_p64;
+    fb->st_lvl32_inter_num += elem->st.st_pnum_p32.pnum_p32;
+    fb->st_lvl32_intra_num += elem->st.st_pnum_i32.pnum_i32;
+    fb->st_lvl16_inter_num += elem->st.st_pnum_p16.pnum_p16;
+    fb->st_lvl16_intra_num += elem->st.st_pnum_i16.pnum_i16;
+    fb->st_lvl8_inter_num  += elem->st.st_pnum_p8.pnum_p8;
+    fb->st_lvl8_intra_num  += elem->st.st_pnum_i8.pnum_i8;
+    fb->st_lvl4_intra_num  += elem->st.st_pnum_i4.pnum_i4;
+
+    ctx->feedback.acc_cover16_num = elem->st.st_skin_sum1.num1_point_skin;
+    ctx->feedback.acc_bndry16_num = elem->st.st_skin_sum2.num2_point_skin;
+    ctx->feedback.acc_zero_mv = elem->st.acc_zero_mv;
+    ctx->feedback.st_ctu_num = elem->st.st_bnum_b16.num_b16;
+    memcpy(&fb->st_cu_num_qp[0], &elem->st.st_b8_qp, 52 * sizeof(RK_U32));
+
+    if (mb4_num > 0)
+        hal_rc_ret->iblk4_prop =  ((((fb->st_lvl4_intra_num + fb->st_lvl8_intra_num) << 2) +
+                                    (fb->st_lvl16_intra_num << 4) +
+                                    (fb->st_lvl32_intra_num << 6)) << 8) / mb4_num;
+
+    if (mb8_num > 0) {
+        hal_rc_ret->quality_real = fb->qp_sum / mb8_num;
+    }
+
+    hal_h265e_leave();
+    return MPP_OK;
+}
+
+static MPP_RET hal_h265e_vepu511_status_check(H265eV511RegSet *regs)
+{
+    MPP_RET ret = MPP_OK;
+
+    if (regs->reg_ctl.int_sta.lkt_node_done_sta)
+        hal_h265e_dbg_detail("lkt_done finish");
+
+    if (regs->reg_ctl.int_sta.enc_done_sta)
+        hal_h265e_dbg_detail("enc_done finish");
+
+    if (regs->reg_ctl.int_sta.vslc_done_sta)
+        hal_h265e_dbg_detail("enc_slice finsh");
+
+    if (regs->reg_ctl.int_sta.sclr_done_sta)
+        hal_h265e_dbg_detail("safe clear finsh");
+
+    if (regs->reg_ctl.int_sta.vbsf_oflw_sta) {
+        mpp_err_f("bit stream overflow");
+        ret = MPP_NOK;
+    }
+
+    if (regs->reg_ctl.int_sta.vbuf_lens_sta) {
+        mpp_err_f("bus write full");
+        ret = MPP_NOK;
+    }
+
+    if (regs->reg_ctl.int_sta.enc_err_sta) {
+        mpp_err_f("bus error");
+        ret = MPP_NOK;
+    }
+
+    if (regs->reg_ctl.int_sta.wdg_sta) {
+        mpp_err_f("wdg timeout");
+        ret = MPP_NOK;
+    }
+
+    return ret;
+}
+
+//#define DUMP_DATA
+MPP_RET hal_h265e_vepu511_wait(void *hal, HalEncTask *task)
+{
+    MPP_RET ret = MPP_OK;
+    H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
+    HalEncTask *enc_task = task;
+    MppPacket pkt = enc_task->packet;
+    RK_U32 split_out = ctx->cfg->split.split_out;
+    RK_S32 task_idx = task->flags.reg_idx;
+    Vepu511H265eFrmCfg *frm = ctx->frms[task_idx];
+    H265eV511RegSet *regs = frm->regs_set;
+    RK_U32 offset = mpp_packet_get_length(pkt);
+    RK_U32 seg_offset = offset;
+    H265eVepu511Frame *reg_frm = &regs->reg_frm;
+    RK_U32 type = reg_frm->synt_nal.nal_unit_type;
+    H265eV511StatusElem *elem = (H265eV511StatusElem *)frm->regs_ret;
+
+    hal_h265e_enter();
+
+    if (enc_task->flags.err) {
+        hal_h265e_err("enc_task->flags.err %08x, return early",
+                      enc_task->flags.err);
+        return MPP_NOK;
+    }
+
+    /* if pass1 mode, it will disable split mode and the split out need to be disable */
+    if (enc_task->rc_task->frm.save_pass1)
+        split_out = 0;
+
+    if (split_out) {
+        EncOutParam param;
+        RK_U32 slice_len = 0;
+        RK_U32 slice_last = 0;
+        MppDevPollCfg *poll_cfg = (MppDevPollCfg *)((char *)ctx->poll_cfgs);
+        param.task = task;
+        param.base = mpp_packet_get_data(task->packet);
+
+        do {
+            RK_S32 i = 0;
+            poll_cfg->poll_type = 0;
+            poll_cfg->poll_ret  = 0;
+            poll_cfg->count_max = ctx->poll_slice_max;
+            poll_cfg->count_ret = 0;
+
+            ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, poll_cfg);
+            for (i = 0; i < poll_cfg->count_ret; i++) {
+                slice_last = poll_cfg->slice_info[i].last;
+                slice_len = poll_cfg->slice_info[i].length;
+                param.length = slice_len;
+
+                mpp_packet_add_segment_info(pkt, type, seg_offset, slice_len);
+                seg_offset += slice_len;
+
+                if (split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) {
+                    param.length = slice_len;
+                    if (slice_last)
+                        ctx->output_cb->cmd = ENC_OUTPUT_FINISH;
+                    else
+                        ctx->output_cb->cmd = ENC_OUTPUT_SLICE;
+
+                    mpp_callback(ctx->output_cb, &param);
+                }
+            }
+        } while (!slice_last);
+
+        ret = hal_h265e_vepu511_status_check(regs);
+        if (!ret)
+            task->hw_length += elem->st.bs_lgth_l32;
+
+    } else {
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
+        if (ret) {
+            mpp_err_f("poll cmd failed %d\n", ret);
+            ret = MPP_ERR_VPUHW;
+        } else {
+            ret = hal_h265e_vepu511_status_check(regs);
+            if (!ret)
+                task->hw_length += elem->st.bs_lgth_l32;
+        }
+        mpp_packet_add_segment_info(pkt, type, offset, elem->st.bs_lgth_l32);
+    }
+
+#ifdef DUMP_DATA
+    vepu511_h265e_dump(ctx, task);
+#endif
+
+    if (ret)
+        mpp_err_f("poll cmd failed %d status %d \n", ret, elem->hw_status);
+
+    hal_h265e_leave();
+    return ret;
+}
+
+MPP_RET hal_h265e_vepu511_get_task(void *hal, HalEncTask *task)
+{
+    H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
+    Vepu511H265eFrmCfg *frm_cfg = NULL;
+    MppFrame frame = task->frame;
+    EncFrmStatus  *frm_status = &task->rc_task->frm;
+    RK_S32 task_idx = ctx->task_idx;
+
+    hal_h265e_enter();
+
+    ctx->syn = (H265eSyntax_new *)task->syntax.data;
+    ctx->dpb = (H265eDpb*)ctx->syn->dpb;
+    ctx->smart_en = (ctx->cfg->rc.rc_mode == MPP_ENC_RC_MODE_SMTRC);
+    ctx->qpmap_en = ctx->cfg->tune.deblur_en;
+
+    if (vepu511_h265_setup_hal_bufs(ctx)) {
+        hal_h265e_err("vepu541_h265_allocate_buffers failed, free buffers and return\n");
+        task->flags.err |= HAL_ENC_TASK_ERR_ALLOC;
+        return MPP_ERR_MALLOC;
+    }
+
+    ctx->last_frame_type = ctx->frame_type;
+    frm_cfg = ctx->frms[task_idx];
+    ctx->frm = frm_cfg;
+
+    if (frm_status->is_intra) {
+        ctx->frame_type = INTRA_FRAME;
+    } else {
+        ctx->frame_type = INTER_P_FRAME;
+    }
+
+    if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
+        MppMeta meta = mpp_frame_get_meta(frame);
+
+        mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
+        mpp_meta_get_ptr_d(meta, KEY_OSD_DATA3, (void **)&ctx->osd_cfg.osd_data3, NULL);
+    }
+
+    task->flags.reg_idx = ctx->task_idx;
+    ctx->ext_line_buf = ctx->ext_line_bufs[ctx->task_idx];
+    frm_cfg->frame_count = ++ctx->frame_count;
+
+    ctx->task_idx++;
+    if (ctx->task_idx >= ctx->task_cnt)
+        ctx->task_idx = 0;
+
+    frm_cfg->hal_curr_idx = ctx->syn->sp.recon_pic.slot_idx;
+    frm_cfg->hal_refr_idx = ctx->syn->sp.ref_pic.slot_idx;
+
+    h265e_dpb_hal_start(ctx->dpb, frm_cfg->hal_curr_idx);
+    h265e_dpb_hal_start(ctx->dpb, frm_cfg->hal_refr_idx);
+
+    memset(&frm_cfg->feedback, 0, sizeof(Vepu511H265Fbk));
+
+    hal_h265e_leave();
+    return MPP_OK;
+}
+
+MPP_RET hal_h265e_vepu511_ret_task(void *hal, HalEncTask *task)
+{
+    H265eV511HalContext *ctx = (H265eV511HalContext *)hal;
+    HalEncTask *enc_task = task;
+    RK_S32 task_idx = task->flags.reg_idx;
+    Vepu511H265eFrmCfg *frm = ctx->frms[task_idx];
+    Vepu511H265Fbk *fb = &frm->feedback;
+    EncRcTaskInfo *rc_info = &task->rc_task->info;
+    RK_U32 offset = mpp_packet_get_length(enc_task->packet);
+
+    hal_h265e_enter();
+
+    vepu511_h265_set_feedback(ctx, enc_task);
+    mpp_buffer_sync_partial_begin(enc_task->output, offset, fb->out_strm_size);
+    hal_h265e_amend_temporal_id(task, fb->out_strm_size);
+
+    rc_info->sse = fb->sse_sum;
+    rc_info->lvl64_inter_num = fb->st_lvl64_inter_num;
+    rc_info->lvl32_inter_num = fb->st_lvl32_inter_num;
+    rc_info->lvl16_inter_num = fb->st_lvl16_inter_num;
+    rc_info->lvl8_inter_num  = fb->st_lvl8_inter_num;
+    rc_info->lvl32_intra_num = fb->st_lvl32_intra_num;
+    rc_info->lvl16_intra_num = fb->st_lvl16_intra_num;
+    rc_info->lvl8_intra_num  = fb->st_lvl8_intra_num;
+    rc_info->lvl4_intra_num  = fb->st_lvl4_intra_num;
+
+    enc_task->hw_length = fb->out_strm_size;
+    enc_task->length += fb->out_strm_size;
+
+    h265e_dpb_hal_end(ctx->dpb, frm->hal_curr_idx);
+    h265e_dpb_hal_end(ctx->dpb, frm->hal_refr_idx);
+
+    // vepu511_h265e_tune_stat_update(ctx->tune, enc_task);
+
+    hal_h265e_dbg_detail("output stream size %d\n", fb->out_strm_size);
+    hal_h265e_leave();
+    return MPP_OK;
+}
+
+const MppEncHalApi hal_h265e_vepu511 = {
+    .name       = "hal_h265e_v511",
+    .coding     = MPP_VIDEO_CodingHEVC,
+    .ctx_size   = sizeof(H265eV511HalContext),
+    .flag       = 0,
+    .init       = hal_h265e_vepu511_init,
+    .deinit     = hal_h265e_vepu511_deinit,
+    .prepare    = hal_h265e_vepu511_prepare,
+    .get_task   = hal_h265e_vepu511_get_task,
+    .gen_regs   = hal_h265e_vepu511_gen_regs,
+    .start      = hal_h265e_vepu511_start,
+    .wait       = hal_h265e_vepu511_wait,
+    .part_start = NULL,
+    .part_wait  = NULL,
+    .ret_task   = hal_h265e_vepu511_ret_task,
+};
diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu511.h b/mpp/hal/rkenc/h265e/hal_h265e_vepu511.h
new file mode 100644
index 00000000..88f41705
--- /dev/null
+++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu511.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_H265E_VEPU511_H__
+#define __HAL_H265E_VEPU511_H__
+
+#include "mpp_enc_hal.h"
+
+extern const MppEncHalApi hal_h265e_vepu511;
+
+#endif /* __HAL_H265E_VEPU511_H__ */
\ No newline at end of file
diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu511_reg.h b/mpp/hal/rkenc/h265e/hal_h265e_vepu511_reg.h
new file mode 100644
index 00000000..b0a75f0f
--- /dev/null
+++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu511_reg.h
@@ -0,0 +1,1575 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_H265E_VEPU511_REG_H__
+#define __HAL_H265E_VEPU511_REG_H__
+
+#include "rk_type.h"
+#include "vepu511_common.h"
+
+typedef struct PreCstPar_t {
+    /* 0x00002120 reg2120 - 0x00002140 reg2128 */
+    struct {
+        RK_U32 madi_thd0    : 7;
+        RK_U32 reserved     : 1;
+        RK_U32 madi_thd1    : 7;
+        RK_U32 reserved1    : 1;
+        RK_U32 madi_thd2    : 7;
+        RK_U32 reserved2    : 1;
+        RK_U32 madi_thd3    : 7;
+        RK_U32 reserved3    : 1;
+    } cst_madi_thd0;
+
+    /* 0x00002124 reg2121 */
+    struct {
+        RK_U32 madi_thd4    : 7;
+        RK_U32 reserved     : 1;
+        RK_U32 madi_thd5    : 7;
+        RK_U32 reserved1    : 1;
+        RK_U32 madi_thd6    : 7;
+        RK_U32 reserved2    : 1;
+        RK_U32 madi_thd7    : 7;
+        RK_U32 reserved3    : 1;
+    } cst_madi_thd1;
+
+    /* 0x00002128 reg2122 */
+    struct {
+        RK_U32 madi_thd8    : 7;
+        RK_U32 reserved     : 1;
+        RK_U32 madi_thd9    : 7;
+        RK_U32 reserved1    : 1;
+        RK_U32 madi_thd10   : 7;
+        RK_U32 reserved2    : 1;
+        RK_U32 madi_thd11   : 7;
+        RK_U32 reserved3    : 1;
+    } cst_madi_thd2;
+
+    /* 0x0000212c reg2123 */
+    struct {
+        RK_U32 madi_thd12   : 7;
+        RK_U32 reserved     : 1;
+        RK_U32 madi_thd13   : 7;
+        RK_U32 reserved1    : 1;
+        RK_U32 mode_th      : 3;
+        RK_U32 reserved2    : 1;
+        RK_U32 qp_thd       : 6;
+        RK_U32 reserved3    : 6;
+    } cst_madi_thd3;
+
+    /* 0x00002130 reg2124 */
+    struct {
+        RK_U32 wgt0    : 8;
+        RK_U32 wgt1    : 8;
+        RK_U32 wgt2    : 8;
+        RK_U32 wgt3    : 8;
+    } cst_wgt0;
+
+    /* 0x00002134 reg2125 */
+    struct {
+        RK_U32 wgt4    : 8;
+        RK_U32 wgt5    : 8;
+        RK_U32 wgt6    : 8;
+        RK_U32 wgt7    : 8;
+    } cst_wgt1;
+
+    /* 0x00002138 reg2126 */
+    struct {
+        RK_U32 wgt8     : 8;
+        RK_U32 wgt9     : 8;
+        RK_U32 wgt10    : 8;
+        RK_U32 wgt11    : 8;
+    } cst_wgt2;
+
+    /* 0x0000213c reg2127 */
+    struct {
+        RK_U32 wgt12            : 8;
+        RK_U32 wgt13            : 8;
+        RK_U32 wgt14            : 8;
+        RK_U32 lambda_mv_bit_0  : 3;
+        RK_U32 reserved         : 1;
+        RK_U32 lambda_mv_bit_1  : 3;
+        RK_U32 anti_strp_e      : 1;
+    } cst_wgt3;
+} pre_cst_par;
+
+/* class: buffer/video syntax */
+/* 0x00000270 reg156 - 0x00000538 reg334 */
+typedef struct H265eVepu511Frame_t {
+    /* 0x00000270 reg156  - 0x0000039c reg231 */
+    Vepu511FrmCommon common;
+
+    /* 0x000003a0 reg232 */
+    struct {
+        RK_U32 ltm_col                     : 1;
+        RK_U32 ltm_idx0l0                  : 1;
+        RK_U32 chrm_spcl                   : 1;
+        RK_U32 cu_inter_e                  : 12;
+        RK_U32 reserved                    : 1;
+        RK_U32 cu32_split_lambda_qp_sel    : 3;
+        RK_U32 reserved1                   : 4;
+        RK_U32 ccwa_e                      : 1;
+        RK_U32 scl_lst_sel                 : 2;
+        RK_U32 reserved2                   : 2;
+        RK_U32 atf_e                       : 1;
+        RK_U32 atr_e                       : 1;
+        RK_U32 reserved3                   : 2;
+    } rdo_cfg;
+
+    struct {
+        RK_U32 intra_pu32_mode_num    : 2;
+        RK_U32 intra_pu16_mode_num    : 2;
+        RK_U32 intra_pu8_mode_num     : 2;
+        RK_U32 intra_pu4_mode_num     : 2;
+        RK_U32 reserved               : 24;
+    } rdo_intra_mode;
+
+    /* 0x000003a8 reg234 */
+    struct {
+        RK_U32 rdoqx_pixel_e        : 1;
+        RK_U32 rdoqx_cgzero_e       : 1;
+        RK_U32 rdoqx_lastxy_e       : 1;
+        RK_U32 rdoq4_rdoq_e         : 1;
+        RK_U32 reserved             : 4;
+        RK_U32 rdoq_intra_r_coef    : 5;
+        RK_U32 reserved1            : 19;
+    } rdoq_cfg_hevc;
+
+    /* 0x3ac */
+    RK_U32 reserved_235;
+
+    /* 0x000003b0 reg236 */
+    struct {
+        RK_U32 nal_unit_type    : 6;
+        RK_U32 reserved         : 26;
+    } synt_nal;
+
+    /* 0x000003b4 reg237 */
+    struct {
+        RK_U32 smpl_adpt_ofst_e    : 1;
+        RK_U32 num_st_ref_pic      : 7;
+        RK_U32 lt_ref_pic_prsnt    : 1;
+        RK_U32 num_lt_ref_pic      : 6;
+        RK_U32 tmpl_mvp_e          : 1;
+        RK_U32 log2_max_poc_lsb    : 4;
+        RK_U32 strg_intra_smth     : 1;
+        RK_U32 reserved            : 11;
+    } synt_sps;
+
+    /* 0x000003b8 reg238 */
+    struct {
+        RK_U32 dpdnt_sli_seg_en       : 1;
+        RK_U32 out_flg_prsnt_flg      : 1;
+        RK_U32 num_extr_sli_hdr       : 3;
+        RK_U32 sgn_dat_hid_en         : 1;
+        RK_U32 cbc_init_prsnt_flg     : 1;
+        RK_U32 pic_init_qp            : 6;
+        RK_U32 cu_qp_dlt_en           : 1;
+        RK_U32 chrm_qp_ofst_prsn      : 1;
+        RK_U32 lp_fltr_acrs_sli       : 1;
+        RK_U32 dblk_fltr_ovrd_en      : 1;
+        RK_U32 lst_mdfy_prsnt_flg     : 1;
+        RK_U32 sli_seg_hdr_extn       : 1;
+        RK_U32 cu_qp_dlt_depth        : 2;
+        RK_U32 lpf_fltr_acrs_til      : 1;
+        RK_U32 csip_flag              : 1;
+        RK_U32 reserved               : 9;
+    } synt_pps;
+
+    /* 0x000003bc reg239 */
+    struct {
+        RK_U32 cbc_init_flg           : 1;
+        RK_U32 mvd_l1_zero_flg        : 1;
+        RK_U32 mrg_up_flg             : 1;
+        RK_U32 mrg_lft_flg            : 1;
+        RK_U32 reserved               : 1;
+        RK_U32 ref_pic_lst_mdf_l0     : 1;
+        RK_U32 num_refidx_l1_act      : 2;
+        RK_U32 num_refidx_l0_act      : 2;
+        RK_U32 num_refidx_act_ovrd    : 1;
+        RK_U32 sli_sao_chrm_flg       : 1;
+        RK_U32 sli_sao_luma_flg       : 1;
+        RK_U32 sli_tmprl_mvp_e        : 1;
+        RK_U32 pic_out_flg            : 1;
+        RK_U32 sli_type               : 2;
+        RK_U32 sli_rsrv_flg           : 7;
+        RK_U32 dpdnt_sli_seg_flg      : 1;
+        RK_U32 sli_pps_id             : 6;
+        RK_U32 no_out_pri_pic         : 1;
+    } synt_sli0;
+
+    /* 0x000003c0 reg240 */
+    struct {
+        RK_U32 sp_tc_ofst_div2         : 4;
+        RK_U32 sp_beta_ofst_div2       : 4;
+        RK_U32 sli_lp_fltr_acrs_sli    : 1;
+        RK_U32 sp_dblk_fltr_dis        : 1;
+        RK_U32 dblk_fltr_ovrd_flg      : 1;
+        RK_U32 sli_cb_qp_ofst          : 5;
+        RK_U32 sli_qp                  : 6;
+        RK_U32 max_mrg_cnd             : 2;
+        RK_U32 reserved                : 1;
+        RK_U32 col_ref_idx             : 1;
+        RK_U32 col_frm_l0_flg          : 1;
+        RK_U32 lst_entry_l0            : 4;
+        RK_U32 reserved1               : 1;
+    } synt_sli1;
+
+    /* 0x000003c4 reg241 */
+    struct {
+        RK_U32 sli_poc_lsb        : 16;
+        RK_U32 sli_hdr_ext_len    : 9;
+        RK_U32 reserved           : 7;
+    } synt_sli2;
+
+    /* 0x000003c8 reg242 */
+    struct {
+        RK_U32 st_ref_pic_flg    : 1;
+        RK_U32 poc_lsb_lt0       : 16;
+        RK_U32 lt_idx_sps        : 5;
+        RK_U32 num_lt_pic        : 2;
+        RK_U32 st_ref_pic_idx    : 6;
+        RK_U32 num_lt_sps        : 2;
+    } synt_refm0;
+
+    /* 0x000003cc reg243 */
+    struct {
+        RK_U32 used_by_s0_flg        : 4;
+        RK_U32 num_pos_pic           : 1;
+        RK_U32 num_negative_pics     : 5;
+        RK_U32 dlt_poc_msb_cycl0     : 16;
+        RK_U32 dlt_poc_msb_prsnt0    : 1;
+        RK_U32 dlt_poc_msb_prsnt1    : 1;
+        RK_U32 dlt_poc_msb_prsnt2    : 1;
+        RK_U32 used_by_lt_flg0       : 1;
+        RK_U32 used_by_lt_flg1       : 1;
+        RK_U32 used_by_lt_flg2       : 1;
+    } synt_refm1;
+
+    /* 0x000003d0 reg244 */
+    struct {
+        RK_U32 dlt_poc_s0_m10    : 16;
+        RK_U32 dlt_poc_s0_m11    : 16;
+    } synt_refm2;
+
+    /* 0x000003d4 reg245 */
+    struct {
+        RK_U32 dlt_poc_s0_m12    : 16;
+        RK_U32 dlt_poc_s0_m13    : 16;
+    } synt_refm3;
+
+    /* 0x000003d8 reg246 */
+    struct {
+        RK_U32 poc_lsb_lt1    : 16;
+        RK_U32 poc_lsb_lt2    : 16;
+    } synt_long_refm0;
+
+    /* 0x000003dc reg247 */
+    struct {
+        RK_U32 dlt_poc_msb_cycl1    : 16;
+        RK_U32 dlt_poc_msb_cycl2    : 16;
+    } synt_long_refm1;
+
+    /* 0x000003e0 reg248 */
+    struct {
+        RK_U32 sao_lambda_multi    : 3;
+        RK_U32 reserved            : 29;
+    } sao_cfg;
+
+    /* 0x3e4 - 0x3ec */
+    RK_U32 reserved249_251[3];
+
+    /* 0x000003f0 reg252 */
+    struct {
+        RK_U32 tile_w_m1    : 9;
+        RK_U32 reserved     : 7;
+        RK_U32 tile_h_m1    : 9;
+        RK_U32 reserved1    : 6;
+        RK_U32 tile_en      : 1;
+    } tile_cfg;
+
+    /* 0x000003f4 reg253 */
+    struct {
+        RK_U32 tile_x       : 9;
+        RK_U32 reserved     : 7;
+        RK_U32 tile_y       : 9;
+        RK_U32 reserved1    : 7;
+    } tile_pos_hevc;
+
+    /* 0x000003f8 reg254 */
+    struct {
+        RK_U32 slice_sta_x      : 9;
+        RK_U32 reserved1        : 7;
+        RK_U32 slice_sta_y      : 10;
+        RK_U32 reserved2        : 5;
+        RK_U32 slice_enc_ena    : 1;
+    } slice_enc_cfg0;
+
+    /* 0x000003fc reg255 */
+    struct {
+        RK_U32 slice_end_x    : 9;
+        RK_U32 reserved       : 7;
+        RK_U32 slice_end_y    : 10;
+        RK_U32 reserved1      : 6;
+    } slice_enc_cfg1;
+
+    /* 0x00000400 reg256 */
+    struct {
+        RK_U32 reserved          : 8;
+        RK_U32 bsbt_addr_jpeg    : 24;
+    } adr_bsbt_jpeg;
+
+    /* 0x00000404 reg257 */
+    struct {
+        RK_U32 reserved          : 8;
+        RK_U32 bsbb_addr_jpeg    : 24;
+    } adr_bsbb_jpeg;
+
+    /* 0x00000408 reg258 */
+    RK_U32 adr_bsbs_jpeg;
+
+    /* 0x0000040c reg259 */
+    struct {
+        RK_U32 bsadr_msk_jpeg    : 4;
+        RK_U32 reserved          : 4;
+        RK_U32 bsbr_addr_jpeg    : 24;
+    } adr_bsbr_jpeg;
+
+    /* 0x00000410 reg260 */
+    struct {
+        RK_U32 reserved          : 4;
+        RK_U32 adr_vsy_b_jpeg    : 28;
+    } adr_vsy_b_jpeg;
+
+    /* 0x00000414 reg261 */
+    struct {
+        RK_U32 reserved          : 4;
+        RK_U32 adr_vsc_b_jpeg    : 28;
+    } adr_vsc_b_jpeg;
+
+    /* 0x00000418 reg262 */
+    struct {
+        RK_U32 reserved          : 4;
+        RK_U32 adr_vsy_t_jpeg    : 28;
+    } adr_vsy_t_jpeg;
+
+    /* 0x0000041c reg263 */
+    struct {
+        RK_U32 reserved          : 4;
+        RK_U32 adr_vsc_t_jpeg    : 28;
+    } adr_vsc_t_jpeg;
+
+    /* 0x00000420 reg264 */
+    RK_U32 adr_src0_jpeg;
+
+    /* 0x00000424 reg265 */
+    RK_U32 adr_src1_jpeg;
+
+    /* 0x00000428 reg266 */
+    RK_U32 adr_src2_jpeg;
+
+    /* 0x0000042c reg267 */
+    RK_U32 bsp_size_jpeg;
+
+    /* 0x430 - 0x43c */
+    RK_U32 reserved268_271[4];
+
+    /* 0x00000440 reg272 */
+    struct {
+        RK_U32 pic_wd8_m1    : 11;
+        RK_U32 reserved      : 1;
+        RK_U32 pp0_vnum_m1   : 4;
+        RK_U32 pic_hd8_m1    : 11;
+        RK_U32 reserved1     : 1;
+        RK_U32 pp0_jnum_m1   : 4;
+    } enc_rsl_jpeg;
+
+    /* 0x00000444 reg273 */
+    struct {
+        RK_U32 pic_wfill_jpeg    : 6;
+        RK_U32 reserved          : 10;
+        RK_U32 pic_hfill_jpeg    : 6;
+        RK_U32 reserved1         : 10;
+    } src_fill_jpeg;
+
+    /* 0x00000448 reg274 */
+    struct {
+        RK_U32 alpha_swap_jpeg            : 1;
+        RK_U32 rbuv_swap_jpeg             : 1;
+        RK_U32 src_cfmt_jpeg              : 4;
+        RK_U32 reserved                   : 2;
+        RK_U32 src_range_trns_en_jpeg     : 1;
+        RK_U32 src_range_trns_sel_jpeg    : 1;
+        RK_U32 chroma_ds_mode_jpeg        : 1;
+        RK_U32 reserved1                  : 21;
+    } src_fmt_jpeg;
+
+    /* 0x0000044c reg275 */
+    struct {
+        RK_U32 csc_wgt_b2y_jpeg    : 9;
+        RK_U32 csc_wgt_g2y_jpeg    : 9;
+        RK_U32 csc_wgt_r2y_jpeg    : 9;
+        RK_U32 reserved            : 5;
+    } src_udfy_jpeg;
+
+    /* 0x00000450 reg276 */
+    struct {
+        RK_U32 csc_wgt_b2u_jpeg    : 9;
+        RK_U32 csc_wgt_g2u_jpeg    : 9;
+        RK_U32 csc_wgt_r2u_jpeg    : 9;
+        RK_U32 reserved            : 5;
+    } src_udfu_jpeg;
+
+    /* 0x00000454 reg277 */
+    struct {
+        RK_U32 csc_wgt_b2v_jpeg    : 9;
+        RK_U32 csc_wgt_g2v_jpeg    : 9;
+        RK_U32 csc_wgt_r2v_jpeg    : 9;
+        RK_U32 reserved            : 5;
+    } src_udfv_jpeg;
+
+    /* 0x00000458 reg278 */
+    struct {
+        RK_U32 csc_ofst_v_jpeg    : 8;
+        RK_U32 csc_ofst_u_jpeg    : 8;
+        RK_U32 csc_ofst_y_jpeg    : 5;
+        RK_U32 reserved           : 11;
+    } src_udfo_jpeg;
+
+    /* 0x0000045c reg279 */
+    struct {
+        RK_U32 cr_force_value_jpeg     : 8;
+        RK_U32 cb_force_value_jpeg     : 8;
+        RK_U32 chroma_force_en_jpeg    : 1;
+        RK_U32 reserved                : 9;
+        RK_U32 src_mirr_jpeg           : 1;
+        RK_U32 src_rot_jpeg            : 2;
+        RK_U32 reserved1               : 1;
+        RK_U32 rkfbcd_en_jpeg          : 1;
+        RK_U32 reserved2               : 1;
+    } src_proc_jpeg;
+
+    /* 0x00000460 reg280 */
+    struct {
+        RK_U32 pic_ofst_x_jpeg    : 14;
+        RK_U32 reserved           : 2;
+        RK_U32 pic_ofst_y_jpeg    : 14;
+        RK_U32 reserved1          : 2;
+    } pic_ofst_jpeg;
+
+    /* 0x00000464 reg281 */
+    struct {
+        RK_U32 src_strd0_jpeg    : 21;
+        RK_U32 reserved          : 11;
+    } src_strd0_jpeg;
+
+    /* 0x00000468 reg282 */
+    struct {
+        RK_U32 src_strd1_jpeg    : 16;
+        RK_U32 reserved          : 16;
+    } src_strd1_jpeg;
+
+    /* 0x0000046c reg283 */
+    struct {
+        RK_U32 pp_corner_filter_strength_jpeg      : 2;
+        RK_U32 reserved                            : 2;
+        RK_U32 pp_edge_filter_strength_jpeg        : 2;
+        RK_U32 reserved1                           : 2;
+        RK_U32 pp_internal_filter_strength_jpeg    : 2;
+        RK_U32 reserved2                           : 22;
+    } src_flt_cfg_jpeg;
+
+    /* 0x00000470 reg284 */
+    struct {
+        RK_U32 jpeg_bias_y    : 15;
+        RK_U32 reserved       : 17;
+    } jpeg_y_cfg;
+
+    /* 0x00000474 reg285 */
+    struct {
+        RK_U32 jpeg_bias_u    : 15;
+        RK_U32 reserved       : 17;
+    } jpeg_u_cfg;
+
+    /* 0x00000478 reg286 */
+    struct {
+        RK_U32 jpeg_bias_v    : 15;
+        RK_U32 reserved       : 17;
+    } jpeg_v_cfg;
+
+    /* 0x0000047c reg287 */
+    struct {
+        RK_U32 jpeg_ri              : 25;
+        RK_U32 jpeg_out_mode        : 1;
+        RK_U32 jpeg_start_rst_m     : 3;
+        RK_U32 jpeg_pic_last_ecs    : 1;
+        RK_U32 reserved             : 1;
+        RK_U32 jpeg_stnd            : 1;
+    } jpeg_base_cfg;
+
+    /* 0x00000480 reg288 */
+    struct {
+        RK_U32 uvc_partition0_len_jpeg    : 12;
+        RK_U32 uvc_partition_len_jpeg     : 12;
+        RK_U32 uvc_skip_len_jpeg          : 6;
+        RK_U32 reserved                   : 2;
+    } uvc_cfg_jpeg;
+
+    /* 0x00000484 reg289 */
+    struct {
+        RK_U32 reserved          : 4;
+        RK_U32 eslf_badr_jpeg    : 28;
+    } adr_eslf_jpeg;
+
+    /* 0x00000488 reg290 */
+    struct {
+        RK_U32 eslf_rptr_jpeg    : 10;
+        RK_U32 eslf_wptr_jpeg    : 10;
+        RK_U32 eslf_blen_jpeg    : 10;
+        RK_U32 eslf_updt_jpeg    : 2;
+    } eslf_buf_jpeg;
+
+    /* 0x48c */
+    RK_U32 reserved_291;
+
+    /* 0x00000490 reg292 */
+    struct {
+        RK_U32 roi0_rdoq_start_x    : 11;
+        RK_U32 roi0_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi0_rdoq_level      : 6;
+        RK_U32 roi0_rdoq_en         : 1;
+    } jpeg_roi0_cfg0;
+
+    /* 0x00000494 reg293 */
+    struct {
+        RK_U32 roi0_rdoq_width_m1     : 11;
+        RK_U32 roi0_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 3;
+        RK_U32 frm_rdoq_level         : 6;
+        RK_U32 frm_rdoq_en            : 1;
+    } jpeg_roi0_cfg1;
+
+    /* 0x00000498 reg294 */
+    struct {
+        RK_U32 roi1_rdoq_start_x    : 11;
+        RK_U32 roi1_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi1_rdoq_level      : 6;
+        RK_U32 roi1_rdoq_en         : 1;
+    } jpeg_roi1_cfg0;
+
+    /* 0x0000049c reg295 */
+    struct {
+        RK_U32 roi1_rdoq_width_m1     : 11;
+        RK_U32 roi1_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi1_cfg1;
+
+    /* 0x000004a0 reg296 */
+    struct {
+        RK_U32 roi2_rdoq_start_x    : 11;
+        RK_U32 roi2_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi2_rdoq_level      : 6;
+        RK_U32 roi2_rdoq_en         : 1;
+    } jpeg_roi2_cfg0;
+
+    /* 0x000004a4 reg297 */
+    struct {
+        RK_U32 roi2_rdoq_width_m1     : 11;
+        RK_U32 roi2_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi2_cfg1;
+
+    /* 0x000004a8 reg298 */
+    struct {
+        RK_U32 roi3_rdoq_start_x    : 11;
+        RK_U32 roi3_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi3_rdoq_level      : 6;
+        RK_U32 roi3_rdoq_en         : 1;
+    } jpeg_roi3_cfg0;
+
+    /* 0x000004ac reg299 */
+    struct {
+        RK_U32 roi3_rdoq_width_m1     : 11;
+        RK_U32 roi3_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi3_cfg1;
+
+    /* 0x000004b0 reg300 */
+    struct {
+        RK_U32 roi4_rdoq_start_x    : 11;
+        RK_U32 roi4_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi4_rdoq_level      : 6;
+        RK_U32 roi4_rdoq_en         : 1;
+    } jpeg_roi4_cfg0;
+
+    /* 0x000004b4 reg301 */
+    struct {
+        RK_U32 roi4_rdoq_width_m1     : 11;
+        RK_U32 roi4_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi4_cfg1;
+
+    /* 0x000004b8 reg302 */
+    struct {
+        RK_U32 roi5_rdoq_start_x    : 11;
+        RK_U32 roi5_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi5_rdoq_level      : 6;
+        RK_U32 roi5_rdoq_en         : 1;
+    } jpeg_roi5_cfg0;
+
+    /* 0x000004bc reg303 */
+    struct {
+        RK_U32 roi5_rdoq_width_m1     : 11;
+        RK_U32 roi5_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi5_cfg1;
+
+    /* 0x000004c0 reg304 */
+    struct {
+        RK_U32 roi6_rdoq_start_x    : 11;
+        RK_U32 roi6_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi6_rdoq_level      : 6;
+        RK_U32 roi6_rdoq_en         : 1;
+    } jpeg_roi6_cfg0;
+
+    /* 0x000004c4 reg305 */
+    struct {
+        RK_U32 roi6_rdoq_width_m1     : 11;
+        RK_U32 roi6_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi6_cfg1;
+
+    /* 0x000004c8 reg306 */
+    struct {
+        RK_U32 roi7_rdoq_start_x    : 11;
+        RK_U32 roi7_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi7_rdoq_level      : 6;
+        RK_U32 roi7_rdoq_en         : 1;
+    } jpeg_roi7_cfg0;
+
+    /* 0x000004cc reg307 */
+    struct {
+        RK_U32 roi7_rdoq_width_m1     : 11;
+        RK_U32 roi7_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi7_cfg1;
+
+    /* 0x000004d0 reg308 */
+    struct {
+        RK_U32 roi8_rdoq_start_x    : 11;
+        RK_U32 roi8_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi8_rdoq_level      : 6;
+        RK_U32 roi8_rdoq_en         : 1;
+    } jpeg_roi8_cfg0;
+
+    /* 0x000004d4 reg309 */
+    struct {
+        RK_U32 roi8_rdoq_width_m1     : 11;
+        RK_U32 roi8_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi8_cfg1;
+
+    /* 0x000004d8 reg310 */
+    struct {
+        RK_U32 roi9_rdoq_start_x    : 11;
+        RK_U32 roi9_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi9_rdoq_level      : 6;
+        RK_U32 roi9_rdoq_en         : 1;
+    } jpeg_roi9_cfg0;
+
+    /* 0x000004dc reg311 */
+    struct {
+        RK_U32 roi9_rdoq_width_m1     : 11;
+        RK_U32 roi9_rdoq_height_m1    : 11;
+        RK_U32 reserved               : 10;
+    } jpeg_roi9_cfg1;
+
+    /* 0x000004e0 reg312 */
+    struct {
+        RK_U32 roi10_rdoq_start_x    : 11;
+        RK_U32 roi10_rdoq_start_y    : 11;
+        RK_U32 reserved              : 3;
+        RK_U32 roi10_rdoq_level      : 6;
+        RK_U32 roi10_rdoq_en         : 1;
+    } jpeg_roi10_cfg0;
+
+    /* 0x000004e4 reg313 */
+    struct {
+        RK_U32 roi10_rdoq_width_m1     : 11;
+        RK_U32 roi10_rdoq_height_m1    : 11;
+        RK_U32 reserved                : 10;
+    } jpeg_roi10_cfg1;
+
+    /* 0x000004e8 reg314 */
+    struct {
+        RK_U32 roi11_rdoq_start_x    : 11;
+        RK_U32 roi11_rdoq_start_y    : 11;
+        RK_U32 reserved              : 3;
+        RK_U32 roi11_rdoq_level      : 6;
+        RK_U32 roi11_rdoq_en         : 1;
+    } jpeg_roi11_cfg0;
+
+    /* 0x000004ec reg315 */
+    struct {
+        RK_U32 roi11_rdoq_width_m1     : 11;
+        RK_U32 roi11_rdoq_height_m1    : 11;
+        RK_U32 reserved                : 10;
+    } jpeg_roi11_cfg1;
+
+    /* 0x000004f0 reg316 */
+    struct {
+        RK_U32 roi12_rdoq_start_x    : 11;
+        RK_U32 roi12_rdoq_start_y    : 11;
+        RK_U32 reserved              : 3;
+        RK_U32 roi12_rdoq_level      : 6;
+        RK_U32 roi12_rdoq_en         : 1;
+    } jpeg_roi12_cfg0;
+
+    /* 0x000004f4 reg317 */
+    struct {
+        RK_U32 roi12_rdoq_width_m1     : 11;
+        RK_U32 roi12_rdoq_height_m1    : 11;
+        RK_U32 reserved                : 10;
+    } jpeg_roi12_cfg1;
+
+    /* 0x000004f8 reg318 */
+    struct {
+        RK_U32 roi13_rdoq_start_x    : 11;
+        RK_U32 roi13_rdoq_start_y    : 11;
+        RK_U32 reserved              : 3;
+        RK_U32 roi13_rdoq_level      : 6;
+        RK_U32 roi13_rdoq_en         : 1;
+    } jpeg_roi13_cfg0;
+
+    /* 0x000004fc reg319 */
+    struct {
+        RK_U32 roi13_rdoq_width_m1     : 11;
+        RK_U32 roi13_rdoq_height_m1    : 11;
+        RK_U32 reserved                : 10;
+    } jpeg_roi13_cfg1;
+
+    /* 0x00000500 reg320 */
+    struct {
+        RK_U32 roi14_rdoq_start_x    : 11;
+        RK_U32 roi14_rdoq_start_y    : 11;
+        RK_U32 reserved              : 3;
+        RK_U32 roi14_rdoq_level      : 6;
+        RK_U32 roi14_rdoq_en         : 1;
+    } jpeg_roi14_cfg0;
+
+    /* 0x00000504 reg321 */
+    struct {
+        RK_U32 roi14_rdoq_width_m1     : 11;
+        RK_U32 roi14_rdoq_height_m1    : 11;
+        RK_U32 reserved                : 10;
+    } jpeg_roi14_cfg1;
+
+    /* 0x00000508 reg322 */
+    struct {
+        RK_U32 roi15_rdoq_start_x    : 11;
+        RK_U32 roi15_rdoq_start_y    : 11;
+        RK_U32 reserved              : 3;
+        RK_U32 roi15_rdoq_level      : 6;
+        RK_U32 roi15_rdoq_en         : 1;
+    } jpeg_roi15_cfg0;
+
+    /* 0x0000050c reg323 */
+    struct {
+        RK_U32 roi15_rdoq_width_m1     : 11;
+        RK_U32 roi15_rdoq_height_m1    : 11;
+        RK_U32 reserved                : 10;
+    } jpeg_roi15_cfg1;
+
+    /* 0x510 - 0x51c */
+    RK_U32 reserved324_327[4];
+
+    /* 0x00000520 reg328 */
+    struct {
+        RK_U32 reserved        : 4;
+        RK_U32 base_addr_md    : 28;
+    } adr_md_vpp;
+
+    /* 0x00000524 reg329 */
+    struct {
+        RK_U32 reserved        : 4;
+        RK_U32 base_addr_od    : 28;
+    } adr_od_vpp;
+
+    /* 0x00000528 reg330 */
+    struct {
+        RK_U32 reserved             : 4;
+        RK_U32 base_addr_ref_mdw    : 28;
+    } adr_ref_mdw;
+
+    /* 0x0000052c reg331 */
+    struct {
+        RK_U32 reserved             : 4;
+        RK_U32 base_addr_ref_mdr    : 28;
+    } adr_ref_mdr;
+
+    /* 0x00000530 reg332 */
+    struct {
+        RK_U32 sto_stride_md          : 8;
+        RK_U32 sto_stride_od          : 8;
+        RK_U32 cur_frm_en_md          : 1;
+        RK_U32 ref_frm_en_md          : 1;
+        RK_U32 switch_sad_md          : 2;
+        RK_U32 night_mode_en_md       : 1;
+        RK_U32 flycatkin_flt_en_md    : 1;
+        RK_U32 en_od                  : 1;
+        RK_U32 background_en_od       : 1;
+        RK_U32 sad_comp_en_od         : 1;
+        RK_U32 reserved               : 6;
+        RK_U32 vepu_pp_en             : 1;
+    } vpp_base_cfg;
+
+    /* 0x00000534 reg333 */
+    struct {
+        RK_U32 thres_sad_md          : 12;
+        RK_U32 thres_move_md         : 3;
+        RK_U32 reserved              : 1;
+        RK_U32 thres_dust_move_md    : 4;
+        RK_U32 thres_dust_blk_md     : 3;
+        RK_U32 reserved1             : 1;
+        RK_U32 thres_dust_chng_md    : 8;
+    } thd_md_vpp;
+
+    /* 0x00000538 reg334 */
+    struct {
+        RK_U32 thres_complex_od        : 12;
+        RK_U32 thres_complex_cnt_od    : 3;
+        RK_U32 thres_sad_od            : 14;
+        RK_U32 reserved                : 3;
+    } thd_od_vpp;
+} H265eVepu511Frame;
+
+/* class: param */
+/* 0x00001700 reg1472 - 0x000019cc reg1651*/
+typedef struct H265eVepu511Param_t {
+    /* 0x00001700 reg1472 - 0x0000172c reg1483*/
+    RK_U32 reserved_1472_1483[12];
+
+    /* 0x00001730 reg1484 */
+    struct {
+        RK_U32 bias_madi_th0    : 8;
+        RK_U32 bias_madi_th1    : 8;
+        RK_U32 bias_madi_th2    : 8;
+        RK_U32 reserved         : 8;
+    } bias_madi_thd_comb;
+
+    /* 0x00001734 reg1485 */
+    struct {
+        RK_U32 bias_i_val0    : 10;
+        RK_U32 bias_i_val1    : 10;
+        RK_U32 bias_i_val2    : 10;
+        RK_U32 reserved       : 2;
+    } qnt0_i_bias_comb;
+
+    /* 0x00001738 reg1486 */
+    struct {
+        RK_U32 bias_i_val3    : 10;
+        RK_U32 reserved       : 22;
+    } qnt1_i_bias_comb;
+
+    /* 0x0000173c reg1487 */
+    struct {
+        RK_U32 bias_p_val0    : 10;
+        RK_U32 bias_p_val1    : 10;
+        RK_U32 bias_p_val2    : 10;
+        RK_U32 reserved       : 2;
+    } qnt0_p_bias_comb;
+
+    /* 0x00001740 reg1488 */
+    struct {
+        RK_U32 bias_p_val3    : 10;
+        RK_U32 reserved       : 22;
+    } qnt1_p_bias_comb;
+
+    /* 0x00001744 reg1489 */
+    struct {
+        RK_U32 light_change_en         : 1;
+        RK_U32 light_ratio_mult1       : 5;
+        RK_U32 light_ratio_mult2       : 4;
+        RK_U32 light_thre_csu1_cnt     : 2;
+        RK_U32 srch_rgn_en             : 1;
+        RK_U32 reserved                : 3;
+        RK_U32 light_thre_madp         : 8;
+        RK_U32 light_thre_lightmadp    : 8;
+    } light_cfg_hevc;
+
+    /* 0x1748 - 0x175c */
+    RK_U32 reserved1490_1495[6];
+
+    /* 0x00001760 reg1496 */
+    struct {
+        RK_U32 cime_pmv_num      : 1;
+        RK_U32 cime_fuse         : 1;
+        RK_U32 reserved          : 2;
+        RK_U32 move_lambda       : 4;
+        RK_U32 rime_lvl_mrg      : 2;
+        RK_U32 rime_prelvl_en    : 2;
+        RK_U32 rime_prersu_en    : 3;
+        RK_U32 fme_lvl_mrg       : 1;
+        RK_U32 reserved1         : 16;
+    } me_sqi_comb;
+
+    /* 0x00001764 reg1497 */
+    struct {
+        RK_U32 cime_mvd_th0    : 9;
+        RK_U32 reserved        : 1;
+        RK_U32 cime_mvd_th1    : 9;
+        RK_U32 reserved1       : 1;
+        RK_U32 cime_mvd_th2    : 9;
+        RK_U32 reserved2       : 3;
+    }  cime_mvd_th_comb;
+
+    /* 0x00001768 reg1498 */
+    struct {
+        RK_U32 cime_madp_th       : 12;
+        RK_U32 ratio_consi_cfg    : 4;
+        RK_U32 ratio_bmv_dist     : 4;
+        RK_U32 reserved           : 12;
+    } cime_madp_th_comb;
+
+    /* 0x0000176c reg1499 */
+    struct {
+        RK_U32 cime_multi0    : 8;
+        RK_U32 cime_multi1    : 8;
+        RK_U32 cime_multi2    : 8;
+        RK_U32 cime_multi3    : 8;
+    } cime_multi_comb;
+
+    /* 0x00001770 reg1500 */
+    struct {
+        RK_U32 rime_mvd_th0    : 3;
+        RK_U32 reserved        : 1;
+        RK_U32 rime_mvd_th1    : 3;
+        RK_U32 reserved1       : 9;
+        RK_U32 fme_madp_th     : 12;
+        RK_U32 reserved2       : 4;
+    } rime_mvd_th_comb;
+
+    /* 0x00001774 reg1501 */
+    struct {
+        RK_U32 rime_madp_th0    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 rime_madp_th1    : 12;
+        RK_U32 reserved1        : 4;
+    } rime_madp_th_comb;
+
+    /* 0x00001778 reg1502 */
+    struct {
+        RK_U32 rime_multi0    : 10;
+        RK_U32 rime_multi1    : 10;
+        RK_U32 rime_multi2    : 10;
+        RK_U32 reserved       : 2;
+    } rime_multi_comb;
+
+    /* 0x0000177c reg1503 */
+    struct {
+        RK_U32 cmv_th0     : 8;
+        RK_U32 cmv_th1     : 8;
+        RK_U32 cmv_th2     : 8;
+        RK_U32 reserved    : 8;
+    } cmv_st_th_comb;
+
+    /* 0x1780 - 0x17fc */
+    RK_U32 reserved1504_1535[32];
+
+    /* 0x00001800 reg1536 - 0x000018cc reg1587*/
+    RK_U32 pprd_lamb_satd_0_51[52];
+
+    /* 0x000018d0 reg1588 */
+    struct {
+        RK_U32 lambda_luma_offset      : 5;
+        RK_U32 lambda_chroma_offset    : 5;
+        RK_U32 reserved                : 22;
+    } prmd_intra_lamb_ofst;
+
+    /* 0x18d4 - 0x18fc */
+    RK_U32 reserved1589_1599[11];
+
+    /* 0x00001900 reg1600 - 0x000019cc reg1651*/
+    RK_U32 rdo_wgta_qp_grpa_0_51[52];
+} H265eVepu511Param;
+
+/* class: rdo/q_i */
+/* 0x00002000 reg2048 - 0x00002160 reg2136 */
+typedef struct H265eVepu511SqiCfg_t {
+    /* 0x00002000 reg2048 */
+    struct {
+        RK_U32 subj_opt_en                     : 1;
+        RK_U32 subj_opt_strength               : 3;
+        RK_U32 aq_subj_en                      : 1;
+        RK_U32 aq_subj_strength                : 3;
+        RK_U32 bndry_cmplx_static_choose_en    : 2;
+        RK_U32 feature_cal_en                  : 1;
+        RK_U32 reserved                        : 1;
+        RK_U32 thre_sum_grdn_point             : 20;
+    } subj_opt_cfg;
+
+    /* 0x00002004 reg2049 */
+    struct {
+        RK_U32 common_thre_num_grdn_point_dep0    : 8;
+        RK_U32 common_thre_num_grdn_point_dep1    : 8;
+        RK_U32 common_thre_num_grdn_point_dep2    : 8;
+        RK_U32 reserved                           : 8;
+    } subj_opt_dpth_thd;
+
+    /* 0x00002008 reg2050 */
+    struct {
+        RK_U32 cover_rdo_mode_intra_jcoef_d0    : 6;
+        RK_U32 cover_rdo_mode_intra_jcoef_d1    : 6;
+        RK_U32 cover_rmd_mode_intra_jcoef_d0    : 6;
+        RK_U32 cover_rmd_mode_intra_jcoef_d1    : 6;
+        RK_U32 cover_rdoq_rcoef_d0              : 4;
+        RK_U32 cover_rdoq_rcoef_d1              : 4;
+    } subj_opt_inrar_coef;
+
+    /* 0x0000200c reg2051 */
+    struct {
+        RK_U32 cfc_rmd_mode_intra_jcoef_d0    : 6;
+        RK_U32 cfc_rmd_mode_intra_jcoef_d1    : 6;
+        RK_U32 cfc_rdo_mode_intra_jcoef_d0    : 6;
+        RK_U32 cfc_rdo_mode_intra_jcoef_d1    : 6;
+        RK_U32 cfc_rdoq_rcoef_d0              : 4;
+        RK_U32 cfc_rdoq_rcoef_d1              : 4;
+    } smear_opt_cfc_coef;
+
+    /* 0x00002010 reg2052 */
+    struct {
+        RK_U32 anti_smear_en                  : 1;
+        RK_U32 frm_static                     : 1;
+        RK_U32 smear_stor_en                  : 1;
+        RK_U32 smear_load_en                  : 1;
+        RK_U32 smear_strength                 : 3;
+        RK_U32 reserved                       : 1;
+        RK_U32 thre_mv_inconfor_cime          : 4;
+        RK_U32 thre_mv_confor_cime            : 2;
+        RK_U32 thre_mv_confor_cime_gmv        : 2;
+        RK_U32 thre_mv_inconfor_cime_gmv      : 4;
+        RK_U32 thre_num_mv_confor_cime        : 2;
+        RK_U32 thre_num_mv_confor_cime_gmv    : 2;
+        RK_U32 ref1_subj_opt_en               : 1;
+        RK_U32 smear_cfc_en                   : 1;
+        RK_U32 reserved1                      : 6;
+    } smear_opt_cfg0;
+
+    /* 0x00002014 reg2053 */
+    struct {
+        RK_U32 dist0_frm_avg               : 14;
+        RK_U32 thre_dsp_static             : 5;
+        RK_U32 thre_dsp_mov                : 5;
+        RK_U32 thre_dist_mv_confor_cime    : 7;
+        RK_U32 reserved                    : 1;
+    } smear_opt_cfg1;
+
+    /* 0x00002018 reg2054 */
+    struct {
+        RK_U32 thre_madp_stc_dep0    : 4;
+        RK_U32 thre_madp_stc_dep1    : 4;
+        RK_U32 thre_madp_stc_dep2    : 4;
+        RK_U32 thre_madp_mov_dep0    : 6;
+        RK_U32 thre_madp_mov_dep1    : 6;
+        RK_U32 thre_madp_mov_dep2    : 6;
+        RK_U32 reserved              : 2;
+    } smear_madp_thd;
+
+    /* 0x0000201c reg2055 */
+    struct {
+        RK_U32 thre_num_pt_stc_dep0    : 6;
+        RK_U32 thre_num_pt_stc_dep1    : 4;
+        RK_U32 thre_num_pt_stc_dep2    : 2;
+        RK_U32 reserved                : 4;
+        RK_U32 thre_num_pt_mov_dep0    : 6;
+        RK_U32 thre_num_pt_mov_dep1    : 4;
+        RK_U32 thre_num_pt_mov_dep2    : 2;
+        RK_U32 reserved1               : 4;
+    } smear_stat_thd;
+
+    /* 0x00002020 reg2056 */
+    struct {
+        RK_U32 confor_cime_gmv0      : 5;
+        RK_U32 reserved              : 3;
+        RK_U32 confor_cime_gmv1      : 5;
+        RK_U32 reserved1             : 3;
+        RK_U32 inconfor_cime_gmv0    : 6;
+        RK_U32 reserved2             : 2;
+        RK_U32 inconfor_cime_gmv1    : 6;
+        RK_U32 reserved3             : 2;
+    } smear_bmv_dist_thd0;
+
+    /* 0x00002024 reg2057 */
+    struct {
+        RK_U32 inconfor_cime_gmv2    : 6;
+        RK_U32 reserved              : 2;
+        RK_U32 inconfor_cime_gmv3    : 6;
+        RK_U32 reserved1             : 2;
+        RK_U32 inconfor_cime_gmv4    : 6;
+        RK_U32 reserved2             : 10;
+    } smear_bmv_dist_thd1;
+
+    /* 0x00002028 reg2058 */
+    struct {
+        RK_U32 thre_min_num_confor_csu0_bndry_cime_gmv      : 2;
+        RK_U32 thre_max_num_confor_csu0_bndry_cime_gmv      : 2;
+        RK_U32 thre_min_num_inconfor_csu0_bndry_cime_gmv    : 2;
+        RK_U32 thre_max_num_inconfor_csu0_bndry_cime_gmv    : 2;
+        RK_U32 thre_split_dep0                              : 2;
+        RK_U32 thre_zero_srgn                               : 5;
+        RK_U32 reserved                                     : 1;
+        RK_U32 madi_thre_dep0                               : 8;
+        RK_U32 madi_thre_dep1                               : 8;
+    } smear_min_bndry_gmv;
+
+    /* 0x0000202c reg2059 */
+    struct {
+        RK_U32 thre_madp_stc_cover0    : 6;
+        RK_U32 thre_madp_stc_cover1    : 6;
+        RK_U32 thre_madp_mov_cover0    : 5;
+        RK_U32 thre_madp_mov_cover1    : 5;
+        RK_U32 smear_qp_strength       : 4;
+        RK_U32 smear_thre_qp           : 6;
+    } smear_madp_cov_thd;
+
+    /* 0x00002030 reg2060 */
+    struct {
+        RK_U32 skin_en                        : 1;
+        RK_U32 skin_strength                  : 3;
+        RK_U32 thre_uvsqr16_skin              : 8;
+        RK_U32 skin_thre_cst_best_mad         : 10;
+        RK_U32 skin_thre_cst_best_grdn_blk    : 7;
+        RK_U32 reserved                       : 1;
+        RK_U32 frame_skin_ratio               : 2;
+    } skin_opt_cfg;
+
+    /* 0x00002034 reg2061 */
+    struct {
+        RK_U32 thre_sum_mad_intra         : 2;
+        RK_U32 thre_sum_grdn_blk_intra    : 2;
+        RK_U32 vld_thre_skin_v            : 3;
+        RK_U32 reserved                   : 1;
+        RK_U32 thre_min_skin_u            : 8;
+        RK_U32 thre_max_skin_u            : 8;
+        RK_U32 thre_min_skin_v            : 8;
+    } skin_chrm_thd;
+
+    /* 0x00002038 reg2062 */
+    struct {
+        RK_U32 block_en                        : 1;
+        RK_U32 reserved                        : 1;
+        RK_U32 block_thre_cst_best_mad         : 10;
+        RK_U32 reserved1                       : 4;
+        RK_U32 block_thre_cst_best_grdn_blk    : 6;
+        RK_U32 reserved2                       : 2;
+        RK_U32 thre_num_grdnt_point_cmplx      : 2;
+        RK_U32 block_delta_qp_flag             : 2;
+        RK_U32 reserved3                       : 4;
+    } block_opt_cfg;
+
+    /* 0x0000203c reg2063 */
+    struct {
+        RK_U32 cmplx_thre_cst_best_mad_dep0    : 13;
+        RK_U32 reserved                        : 3;
+        RK_U32 cmplx_thre_cst_best_mad_dep1    : 13;
+        RK_U32 reserved1                       : 2;
+        RK_U32 cmplx_en                        : 1;
+    } cmplx_opt_cfg;
+
+    /* 0x00002040 reg2064 */
+    struct {
+        RK_U32 cmplx_thre_cst_best_mad_dep2         : 13;
+        RK_U32 reserved                             : 3;
+        RK_U32 cmplx_thre_cst_best_grdn_blk_dep0    : 11;
+        RK_U32 reserved1                            : 5;
+    } cmplx_bst_mad_thd;
+
+    /* 0x00002044 reg2065 */
+    struct {
+        RK_U32 cmplx_thre_cst_best_grdn_blk_dep1    : 11;
+        RK_U32 reserved                             : 5;
+        RK_U32 cmplx_thre_cst_best_grdn_blk_dep2    : 11;
+        RK_U32 reserved1                            : 5;
+    } cmplx_bst_grdn_thd;
+
+    /* 0x00002048 reg2066 */
+    struct {
+        RK_U32 line_en                                 : 1;
+        RK_U32 line_thre_min_cst_best_grdn_blk_dep0    : 5;
+        RK_U32 line_thre_min_cst_best_grdn_blk_dep1    : 8;
+        RK_U32 line_thre_min_cst_best_grdn_blk_dep2    : 8;
+        RK_U32 line_thre_ratio_best_grdn_blk_dep0      : 4;
+        RK_U32 line_thre_ratio_best_grdn_blk_dep1      : 4;
+        RK_U32 reserved                                : 2;
+    } line_opt_cfg;
+
+    /* 0x0000204c reg2067 */
+    struct {
+        RK_U32 line_thre_max_cst_best_grdn_blk_dep0    : 7;
+        RK_U32 reserved                                : 1;
+        RK_U32 line_thre_max_cst_best_grdn_blk_dep1    : 8;
+        RK_U32 line_thre_max_cst_best_grdn_blk_dep2    : 8;
+        RK_U32 reserved1                               : 8;
+    } line_cst_bst_grdn;
+
+    /* 0x00002050 reg2068 */
+    struct {
+        RK_U32 line_thre_qp               : 6;
+        RK_U32 block_strength             : 3;
+        RK_U32 block_thre_qp              : 6;
+        RK_U32 cmplx_strength             : 3;
+        RK_U32 cmplx_thre_qp              : 6;
+        RK_U32 cmplx_thre_max_grdn_blk    : 6;
+        RK_U32 reserved                   : 2;
+    } subj_opt_dqp0;
+
+    /* 0x00002054 reg2069 */
+    struct {
+        RK_U32 skin_thre_qp                     : 6;
+        RK_U32 smear_frame_thre_qp              : 6;
+        RK_U32 bndry_rdo_mode_intra_jcoef_d0    : 6;
+        RK_U32 bndry_rdo_mode_intra_jcoef_d1    : 6;
+        RK_U32 skin_thre_madp                   : 8;
+    } subj_opt_dqp1;
+
+    /* 0x00002058 reg2070 */
+    struct {
+        RK_U32 line_rdo_split_rcoef_d0    : 5;
+        RK_U32 line_rdo_split_rcoef_d1    : 5;
+        RK_U32 choose_cu32_split_jcoef    : 6;
+        RK_U32 choose_cu16_split_jcoef    : 5;
+        RK_U32 reserved                   : 11;
+    } subj_opt_rdo_split;
+
+    /* 0x0000205c reg2071 */
+    struct {
+        RK_U32 lid_grdn_blk_cu16_th       : 8;
+        RK_U32 lid_rmd_intra_jcoef_ang    : 5;
+        RK_U32 lid_rdo_intra_rcoef_ang    : 5;
+        RK_U32 lid_rmd_intra_jcoef_dp     : 6;
+        RK_U32 lid_rdo_intra_rcoef_dp     : 6;
+        RK_U32 lid_en                     : 1;
+        RK_U32 reserved                   : 1;
+    } line_intra_dir_cfg;
+
+    /* 0x00002060 reg2072 -  0x0000206c reg 2076*/
+    rdo_b32_skip_par rdo_b32_skip;
+
+    /* 0x00002070 reg2076 - 0x0000207c reg2079*/
+    rdo_skip_par rdo_b16_skip;
+
+    /* 0x00002080 reg2080 - 0x00002088 reg2082 */
+    rdo_b32_noskip_par rdo_b32_inter;
+
+    /* 0x0000208c reg2083 - 0x00002094 reg2085 */
+    rdo_noskip_par rdo_b16_inter;
+
+    /* 0x00002098 reg2086 - 0x000020a0 reg2087 */
+    rdo_noskip_par rdo_b32_intra;
+
+    /* 0x000020a4 reg2088 - 0x000020ac reg2091 */
+    rdo_noskip_par rdo_b16_intra;
+
+    /* 0x000020b0 reg2092 */
+    struct {
+        RK_U32 ref1_rmd_mode_lr_jcoef_d0    : 5;
+        RK_U32 ref1_rmd_mode_lr_jcoef_d1    : 5;
+        RK_U32 ref1_rdo_mode_lr_jcoef_d0    : 5;
+        RK_U32 ref1_rdo_mode_lr_jcoef_d1    : 5;
+        RK_U32 ref1_rmd_mv_lr_jcoef_d0      : 5;
+        RK_U32 ref1_rmd_mv_lr_jcoef_d1      : 5;
+        RK_U32 reserved                     : 2;
+    } smear_ref1_cfg0;
+
+    /* 0x000020b4 reg2093 */
+    struct {
+        RK_U32 ref1_rdo_inter_tu_res_joef_d0    : 5;
+        RK_U32 ref1_rdo_inter_tu_res_joef_d1    : 5;
+        RK_U32 ref1_rdoq_zero_mv_rcoef_d0       : 5;
+        RK_U32 ref1_rdoq_zero_mv_rcoef_d1       : 5;
+        RK_U32 ref1_rmd_inter_lr_jcoef_d0       : 5;
+        RK_U32 ref1_rmd_inter_lr_jcoef_d1       : 5;
+        RK_U32 reserved                         : 2;
+    } smear_ref1_cfg1;
+
+    /* 0x000020b8 reg2094 - 0x000020bc reg2095*/
+    RK_U32 reserved_2094_2095[2];
+
+    /* 0x000020c0 reg2096 */
+    struct {
+        RK_U32 thre_max_luma_dark        : 8;
+        RK_U32 thre_min_luma_bright      : 8;
+        RK_U32 thre_ratio_dark_bright    : 6;
+        RK_U32 reserved                  : 2;
+        RK_U32 thre_qp_dark_bright       : 6;
+        RK_U32 reserved1                 : 1;
+        RK_U32 dark_bright_en            : 1;
+    } dark_brgt_opt_cfg;
+
+    /* 0x000020c4 reg2097 */
+    struct {
+        RK_U32 madp_th_dep0_dark_bright    : 8;
+        RK_U32 madp_th_dep1_dark_bright    : 8;
+        RK_U32 madi_th_dep0_dark_bright    : 6;
+        RK_U32 reserved                    : 2;
+        RK_U32 madi_th_dep1_dark_bright    : 6;
+        RK_U32 reserved1                   : 2;
+    } dark_brgt_madi_thd;
+
+    /* 0x000020c8 reg2098 */
+    struct {
+        RK_U32 dark_bright_inter_res_j_coef_wgt_dep0    : 8;
+        RK_U32 dark_bright_inter_res_j_coef_wgt_dep1    : 8;
+        RK_U32 dark_bright_intra_j_coef_wgt_dep0        : 8;
+        RK_U32 dark_bright_intra_j_coef_wgt_dep1        : 8;
+    } dark_brgt_wgt0;
+
+    /* 0x000020cc reg2099 */
+    struct {
+        RK_U32 dark_bright_split_rcoef_d0    : 6;
+        RK_U32 reserved                      : 2;
+        RK_U32 dark_bright_split_rcoef_d1    : 6;
+        RK_U32 reserved1                     : 18;
+    } dark_brgt_wgt1;
+
+    /* 0x000020d0 reg2100 */
+    struct {
+        RK_U32 cmplx_static_en               : 1;
+        RK_U32 cmplx_static_lgt_chng_en      : 1;
+        RK_U32 thre_qp_cmplx_static          : 6;
+        RK_U32 madp_th0_dep0_cmplx_static    : 6;
+        RK_U32 madp_th1_dep0_cmplx_static    : 8;
+        RK_U32 madp_th2_dep0_cmplx_static    : 10;
+    } cmplx_statc_cfg;
+
+    /* 0x000020d4 reg2101 */
+    struct {
+        RK_U32 num_grdn_point_th1_dep0_cmplx_static    : 8;
+        RK_U32 num_grdn_point_th2_dep0_cmplx_static    : 8;
+        RK_U32 madi_th1_dep0_cmplx_static              : 6;
+        RK_U32 reserved                                : 2;
+        RK_U32 madi_th2_dep0_cmplx_static              : 6;
+        RK_U32 reserved1                               : 2;
+    } cmplx_statc_thd0;
+
+    /* 0x000020d8 reg2102 */
+    struct {
+        RK_U32 madp_th0_dep1_cmplx_static           : 6;
+        RK_U32 madp_th1_dep1_cmplx_static           : 8;
+        RK_U32 madp_th2_dep1_cmplx_static           : 10;
+        RK_U32 static_num_thre_dep1_cmplx_static    : 2;
+        RK_U32 srch_rgn_mv_th_cmplx_static          : 5;
+        RK_U32 reserved                             : 1;
+    } cmplx_statc_thd1;
+
+    /* 0x000020dc reg2103 */
+    struct {
+        RK_U32 num_grdn_point_th1_dep1_cmplx_static    : 6;
+        RK_U32 num_grdn_point_th2_dep1_cmplx_static    : 6;
+        RK_U32 madi_th1_dep1_cmplx_static              : 6;
+        RK_U32 madi_th2_dep1_cmplx_static              : 6;
+        RK_U32 num_cu16_th                : 3;
+        RK_U32 frame_qp_en                : 1;
+        RK_U32 ratio_light_madp_th        : 2;
+        RK_U32 reserved                   : 2;
+    } cmplx_statc_thd2;
+
+    /* 0x000020e0 reg2104 */
+    struct {
+        RK_U32 inter_res_j_coef_wgt1_dep0    : 8;
+        RK_U32 inter_res_j_coef_wgt2_dep0    : 8;
+        RK_U32 inter_res_j_coef_wgt1_dep1    : 8;
+        RK_U32 inter_res_j_coef_wgt2_dep1    : 8;
+    } cmplx_statc_wgt0;
+
+    /* 0x000020e4 reg2105 */
+    struct {
+        RK_U32 intra_j_coef_wgt1_dep0    : 8;
+        RK_U32 intra_j_coef_wgt2_dep0    : 8;
+        RK_U32 intra_j_coef_wgt1_dep1    : 8;
+        RK_U32 intra_j_coef_wgt2_dep1    : 8;
+    } cmplx_statc_wgt1;
+
+    /* 0x000020e8 reg2106 */
+    struct {
+        RK_U32 split_rcoef_w1d0    : 6;
+        RK_U32 split_rcoef_w1d1    : 6;
+        RK_U32 split_rcoef_w2d0    : 6;
+        RK_U32 split_rcoef_w2d1    : 6;
+        RK_U32 reserved            : 8;
+    } cmplx_statc_wgt2;
+
+    /* 0x20ec - 0x20fc */
+    RK_U32 reserved2107_2111[5];
+
+    /* 0x00002100 reg2112 */
+    struct {
+        RK_U32 blur_low_madi_thd     : 7;
+        RK_U32 reserved              : 1;
+        RK_U32 blur_high_madi_thd    : 7;
+        RK_U32 reserved1             : 1;
+        RK_U32 blur_low_cnt_thd      : 4;
+        RK_U32 blur_hight_cnt_thd    : 4;
+        RK_U32 blur_sum_cnt_thd      : 4;
+        RK_U32 anti_blur_en          : 1;
+        RK_U32 scene_mode            : 1;
+        RK_U32 reserved2             : 2;
+    } subj_anti_blur_thd;
+
+    /* 0x00002104 reg2113 */
+    struct {
+        RK_U32 blur_motion_thd           : 12;
+        RK_U32 sao_ofst_thd_eo_luma      : 3;
+        RK_U32 reserved                  : 1;
+        RK_U32 sao_ofst_thd_bo_luma      : 3;
+        RK_U32 reserved1                 : 1;
+        RK_U32 sao_ofst_thd_eo_chroma    : 3;
+        RK_U32 reserved2                 : 1;
+        RK_U32 sao_ofst_thd_bo_chroma    : 3;
+        RK_U32 reserved3                 : 5;
+    } subj_anti_blur_sao;
+
+    /* 0x00002108 reg2114 */
+    struct {
+        RK_U32 notmerge_ofst_dist_eo_wgt0    : 8;
+        RK_U32 notmerge_ofst_dist_bo_wgt0    : 8;
+        RK_U32 notmerge_ofst_dist_eo_wgt1    : 8;
+        RK_U32 notmerge_ofst_dist_bo_wgt1    : 8;
+    } subj_anti_blur_wgt0;
+
+    /* 0x0000210c reg2115 */
+    struct {
+        RK_U32 notmerge_ofst_lambda_eo_wgt0     : 8;
+        RK_U32 notmerge_ofst_lambda_bo_wgt0     : 8;
+        RK_U32 notmerge_compare_dist_eo_wgt0    : 8;
+        RK_U32 notmerge_compare_dist_bo_wgt0    : 8;
+    } subj_anti_blur_wgt1;
+
+    /* 0x00002110 reg2116 */
+    struct {
+        RK_U32 notmerge_compare_dist_eo_wgt1    : 8;
+        RK_U32 notmerge_compare_dist_bo_wgt1    : 8;
+        RK_U32 notmerge_compare_rate_eo_wgt0    : 8;
+        RK_U32 notmerge_compare_rate_bo_wgt0    : 8;
+    } subj_anti_blur_wgt2;
+
+    /* 0x00002114 reg2117 */
+    struct {
+        RK_U32 sao_mode_compare_dist_eo_wgt0    : 8;
+        RK_U32 sao_mode_compare_dist_bo_wgt0    : 8;
+        RK_U32 merge_cost_dist_eo_wgt0          : 8;
+        RK_U32 merge_cost_dist_bo_wgt0          : 8;
+    } subj_anti_blur_wgt3;
+
+    /* 0x00002118 reg2118 */
+    struct {
+        RK_U32 merge_cost_dist_eo_wgt1    : 8;
+        RK_U32 merge_cost_dist_bo_wgt1    : 8;
+        RK_U32 merge_cost_bit_eo_wgt0     : 8;
+        RK_U32 merge_cost_bit_bo_wgt0     : 8;
+    } subj_anti_blur_wgt4;
+
+    /* 0x211c */
+    RK_U32 reserved_2119;
+
+    /* 0x00002120 reg2120 - 0x0000213c reg2127 */
+    pre_cst_par preintra32_cst;
+
+    /* 0x00002140 reg2128 - 0x0000215c reg2135 */
+    pre_cst_par preintra16_cst;
+
+    /* 0x00002160 reg2136 */
+    struct {
+        RK_U32 offset_thd                      : 4;
+        RK_U32 offset_diff_thd                 : 4;
+        RK_U32 weak_texture_offset_thd         : 3;
+        RK_U32 weak_texture_offset_diff_thd    : 3;
+        RK_U32 reserved                        : 18;
+    } atr_thd_hevc;
+} H265eVepu511Sqi;
+
+/* class: scaling list  */
+/* 0x00002200 reg2176- 0x00002c9c reg2855*/
+typedef struct H265eVepu511SclCfg_t {
+    /* 0x2200 - 0x2584 iq_scal_y8_intra_ac0 ~ iq_scal_list_dc1 only HEVC*/
+    RK_U32 tu8_intra_y[16];
+    RK_U32 tu8_intra_u[16];
+    RK_U32 tu8_intra_v[16];
+    RK_U32 tu8_inter_y[16];
+    RK_U32 tu8_inter_u[16];
+    RK_U32 tu8_inter_v[16];
+    RK_U32 tu16_intra_y_ac[16];
+    RK_U32 tu16_intra_u_ac[16];
+    RK_U32 tu16_intra_v_ac[16];
+    RK_U32 tu16_inter_y_ac[16];
+    RK_U32 tu16_inter_u_ac[16];
+    RK_U32 tu16_inter_v_ac[16];
+    RK_U32 tu32_intra_y_ac[16];
+    RK_U32 tu32_inter_y_ac[16];
+
+    /* 0x2580 */
+    struct {
+        RK_U32 tu16_intra_y_dc  : 8;
+        RK_U32 tu16_intra_u_dc  : 8;
+        RK_U32 tu16_intra_v_dc  : 8;
+        RK_U32 tu16_inter_y_dc  : 8;
+    } tu_dc0;
+
+    /* 0x2584 reg 2401*/
+    struct {
+        RK_U32 tu16_inter_u_dc  : 8;
+        RK_U32 tu16_inter_v_dc  : 8;
+        RK_U32 tu32_intra_y_dc  : 8;
+        RK_U32 tu32_inter_y_dc  : 8;
+    } tu_dc1;
+
+    /* 0x2588 reg 2402 - 0x258c reg 2403*/
+    RK_U32 reserved2402_2403[2];
+
+    /* 0x2590 reg 2404 - 0x2c9c reg 2855*/
+    RK_U32 q_y8_intra[32];
+    RK_U32 q_u8_intra[32];
+    RK_U32 q_v8_intra[32];
+    RK_U32 q_y8_inter[32];
+    RK_U32 q_u8_inter[32];
+    RK_U32 q_v8_inter[32];
+    RK_U32 q_y16_intra[32];
+    RK_U32 q_u16_intra[32];
+    RK_U32 q_v16_intra[32];
+    RK_U32 q_y16_inter[32];
+    RK_U32 q_u16_inter[32];
+    RK_U32 q_v16_inter[32];
+    RK_U32 q_y32_intra[32];
+    RK_U32 q_y32_inter[32];
+
+    RK_U32 q_list[4];
+} H265eVepu511SclCfg;
+
+typedef struct H265eV511RegSet_t {
+    Vepu511ControlCfg         reg_ctl;
+    H265eVepu511Frame         reg_frm;
+    Vepu511RcRoi              reg_rc_roi;
+    H265eVepu511Param         reg_param;
+    H265eVepu511Sqi           reg_sqi;
+    H265eVepu511SclCfg        reg_scl;
+    Vepu511OsdRegs            reg_osd;
+    Vepu511Dbg                reg_dbg;
+} H265eV511RegSet;
+
+typedef struct H265eV511StatusElem_t {
+    RK_U32 hw_status;
+    Vepu511Status st;
+} H265eV511StatusElem;
+
+#endif
diff --git a/mpp/hal/rkenc/jpege/CMakeLists.txt b/mpp/hal/rkenc/jpege/CMakeLists.txt
index a78f38cf..92e81ce3 100644
--- a/mpp/hal/rkenc/jpege/CMakeLists.txt
+++ b/mpp/hal/rkenc/jpege/CMakeLists.txt
@@ -6,6 +6,7 @@ include_directories(../common/)
 # hal jpeg header
 set(HAL_JPEGE_HDR
     hal_jpege_vepu540c_reg.h
+    hal_jpege_vepu511_reg.h
     hal_jpege_vpu720_reg.h
     hal_jpege_vpu720.h
     )
@@ -13,6 +14,7 @@ set(HAL_JPEGE_HDR
 # hal jpeg encoder sourse
 set(HAL_JPEGE_SRC
     hal_jpege_vepu540c.c
+    hal_jpege_vepu511.c
     hal_jpege_vpu720.c
     )
 
diff --git a/mpp/hal/rkenc/jpege/hal_jpege_vepu511.c b/mpp/hal/rkenc/jpege/hal_jpege_vepu511.c
new file mode 100644
index 00000000..a2dc3579
--- /dev/null
+++ b/mpp/hal/rkenc/jpege/hal_jpege_vepu511.c
@@ -0,0 +1,680 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG  "hal_jpege_v511"
+
+#include <linux/string.h>
+
+#include <string.h>
+#include <math.h>
+#include <limits.h>
+
+#include "mpp_env.h"
+#include "mpp_mem.h"
+#include "mpp_soc.h"
+#include "mpp_common.h"
+#include "mpp_frame_impl.h"
+
+#include "hal_jpege_debug.h"
+#include "jpege_syntax.h"
+#include "hal_bufs.h"
+#include "rkv_enc_def.h"
+#include "vepu541_common.h"
+#include "vepu511_common.h"
+#include "hal_jpege_vepu511.h"
+#include "hal_jpege_vepu511_reg.h"
+#include "hal_jpege_hdr.h"
+
+typedef struct JpegeV511HalContext_t {
+    MppEncHalApi        api;
+    MppDev              dev;
+    void                *regs;
+    void                *reg_out;
+
+    void                *dump_files;
+
+    RK_S32              frame_type;
+    RK_S32              last_frame_type;
+
+    /* @frame_cnt starts from ZERO */
+    RK_U32              frame_cnt;
+    void                *roi_data;
+    MppEncCfgSet        *cfg;
+    Vepu511OsdCfg       osd_cfg;
+
+    RK_U32              enc_mode;
+    RK_U32              frame_size;
+    RK_S32              max_buf_cnt;
+    RK_S32              hdr_status;
+    void                *input_fmt;
+    RK_U8               *src_buf;
+    RK_U8               *dst_buf;
+    RK_S32              buf_size;
+    RK_U32              frame_num;
+    RK_S32              fbc_header_len;
+    RK_U32              title_num;
+
+    JpegeBits           bits;
+    JpegeSyntax         syntax;
+} JpegeV511HalContext;
+
+MPP_RET hal_jpege_vepu511_init(void *hal, MppEncHalCfg *cfg)
+{
+    MPP_RET ret = MPP_OK;
+    JpegeV511HalContext *ctx = (JpegeV511HalContext *)hal;
+
+    mpp_env_get_u32("hal_jpege_debug", &hal_jpege_debug, 0);
+    hal_jpege_enter();
+
+    ctx->reg_out  = mpp_calloc(JpegV511Status, 1);
+    ctx->regs           = mpp_calloc(JpegV511RegSet, 1);
+    ctx->input_fmt      = mpp_calloc(VepuFmtCfg, 1);
+    ctx->cfg            = cfg->cfg;
+    ctx->frame_cnt = 0;
+    ctx->enc_mode = 1;
+    cfg->type = VPU_CLIENT_RKVENC;
+    ret = mpp_dev_init(&cfg->dev, cfg->type);
+    if (ret) {
+        mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
+        return ret;
+    }
+
+    ctx->dev = cfg->dev;
+    jpege_bits_init(&ctx->bits);
+    mpp_assert(ctx->bits);
+
+    hal_jpege_leave();
+    return ret;
+}
+
+MPP_RET hal_jpege_vepu511_deinit(void *hal)
+{
+    JpegeV511HalContext *ctx = (JpegeV511HalContext *)hal;
+
+    hal_jpege_enter();
+    jpege_bits_deinit(ctx->bits);
+
+    MPP_FREE(ctx->regs);
+    MPP_FREE(ctx->reg_out);
+    MPP_FREE(ctx->input_fmt);
+
+    if (ctx->dev) {
+        mpp_dev_deinit(ctx->dev);
+        ctx->dev = NULL;
+    }
+    hal_jpege_leave();
+    return MPP_OK;
+}
+
+static MPP_RET hal_jpege_vepu511_prepare(void *hal)
+{
+    JpegeV511HalContext *ctx = (JpegeV511HalContext *)hal;
+
+    hal_jpege_dbg_func("enter %p\n", hal);
+    VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
+    vepu541_set_fmt(fmt, ctx->cfg->prep.format);
+
+    hal_jpege_dbg_func("leave %p\n", hal);
+
+    return MPP_OK;
+}
+
+static MPP_RET vepu511_jpeg_set_patch_info(MppDev dev, JpegeSyntax *syn,
+                                           Vepu541Fmt input_fmt,
+                                           HalEncTask *task)
+{
+    RK_U32 hor_stride = syn->hor_stride;
+    RK_U32 ver_stride = syn->ver_stride ? syn->ver_stride : syn->height;
+    RK_U32 frame_size = hor_stride * ver_stride;
+    RK_U32 u_offset = 0, v_offset = 0;
+    MPP_RET ret = MPP_OK;
+
+    if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(task->frame))) {
+        u_offset = mpp_frame_get_fbc_offset(task->frame);
+        v_offset = u_offset;
+    } else {
+        switch (input_fmt) {
+        case VEPU541_FMT_YUV420P: {
+            u_offset = frame_size;
+            v_offset = frame_size * 5 / 4;
+        } break;
+        case VEPU541_FMT_YUV420SP:
+        case VEPU541_FMT_YUV422SP: {
+            u_offset = frame_size;
+            v_offset = frame_size;
+        } break;
+        case VEPU541_FMT_YUV422P: {
+            u_offset = frame_size;
+            v_offset = frame_size * 3 / 2;
+        } break;
+        case VEPU540_FMT_YUV400 :
+        case VEPU541_FMT_YUYV422:
+        case VEPU541_FMT_UYVY422: {
+            u_offset = 0;
+            v_offset = 0;
+        } break;
+        case VEPU580_FMT_YUV444SP : {
+            u_offset = frame_size;
+            v_offset = frame_size;
+        } break;
+        case VEPU580_FMT_YUV444P : {
+            u_offset = frame_size;
+            v_offset = frame_size * 2;
+        } break;
+        case VEPU541_FMT_BGR565:
+        case VEPU541_FMT_BGR888:
+        case VEPU541_FMT_BGRA8888: {
+            u_offset = 0;
+            v_offset = 0;
+        } break;
+        default: {
+            mpp_err("unknown color space: %d\n", input_fmt);
+            u_offset = frame_size;
+            v_offset = frame_size * 5 / 4;
+        }
+        }
+    }
+
+    /* input cb addr */
+    if (u_offset)
+        mpp_dev_set_reg_offset(dev, 265, u_offset);
+
+    /* input cr addr */
+    if (v_offset)
+        mpp_dev_set_reg_offset(dev, 266, v_offset);
+
+    return ret;
+}
+
+MPP_RET vepu511_set_jpeg_reg(Vepu511JpegCfg *cfg)
+{
+    HalEncTask *task = ( HalEncTask *)cfg->enc_task;
+    JpegeSyntax *syn = (JpegeSyntax *)task->syntax.data;
+    Vepu511JpegReg *regs = (Vepu511JpegReg *)cfg->jpeg_reg_base;
+    VepuFmtCfg *fmt = (VepuFmtCfg *)cfg->input_fmt;
+    RK_U32 pic_width_align8, pic_height_align8;
+    RK_S32 stridey = 0;
+    RK_S32 stridec = 0;
+
+    pic_width_align8 = (syn->width + 7) & (~7);
+    pic_height_align8 = (syn->height + 7) & (~7);
+
+    regs->adr_src0 =  mpp_buffer_get_fd(task->input);
+    regs->adr_src1 = regs->adr_src0;
+    regs->adr_src2 = regs->adr_src0;
+
+    vepu511_jpeg_set_patch_info(cfg->dev, syn, (Vepu541Fmt) fmt->format, task);
+
+    regs->adr_bsbt = mpp_buffer_get_fd(task->output);
+    regs->adr_bsbb = regs->adr_bsbt;
+    regs->adr_bsbs = regs->adr_bsbt;
+    regs->adr_bsbr = regs->adr_bsbt;
+
+    mpp_dev_set_reg_offset(cfg->dev, 258, mpp_packet_get_length(task->packet));
+    mpp_dev_set_reg_offset(cfg->dev, 256, mpp_buffer_get_size(task->output));
+
+    regs->enc_rsl.pic_wd8_m1    = pic_width_align8 / 8 - 1;
+    regs->src_fill.pic_wfill    = (syn->width & 0x7)
+                                  ? (8 - (syn->width & 0x7)) : 0;
+    regs->enc_rsl.pic_hd8_m1    = pic_height_align8 / 8 - 1;
+    regs->src_fill.pic_hfill    = (syn->height & 0x7)
+                                  ? (8 - (syn->height & 0x7)) : 0;
+
+    regs->src_fmt.src_cfmt = fmt->format;
+    regs->src_fmt.alpha_swap = fmt->alpha_swap;
+    regs->src_fmt.rbuv_swap  = fmt->rbuv_swap;
+    regs->src_fmt.src_range_trns_en  = 0;
+    regs->src_fmt.src_range_trns_sel = 0;
+    regs->src_fmt.chroma_ds_mode     = 0;
+    regs->src_proc.src_mirr = syn->mirroring > 0;
+    regs->src_proc.src_rot = syn->rotation;
+
+    if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(task->frame))) {
+        regs->src_proc.rkfbcd_en = 1;
+
+        stridey = mpp_frame_get_fbc_hdr_stride(task->frame);
+        if (!stridey)
+            stridey = MPP_ALIGN(syn->hor_stride, 16) >> 2;
+    } else if (syn->hor_stride) {
+        stridey = syn->hor_stride;
+    } else {
+        if (regs->src_fmt.src_cfmt == VEPU541_FMT_BGRA8888 )
+            stridey = syn->width * 4;
+        else if (regs->src_fmt.src_cfmt == VEPU541_FMT_BGR888 ||
+                 regs->src_fmt.src_cfmt == VEPU580_FMT_YUV444P ||
+                 regs->src_fmt.src_cfmt == VEPU580_FMT_YUV444SP)
+            stridey = syn->width * 3;
+        else if (regs->src_fmt.src_cfmt == VEPU541_FMT_BGR565 ||
+                 regs->src_fmt.src_cfmt == VEPU541_FMT_YUYV422 ||
+                 regs->src_fmt.src_cfmt == VEPU541_FMT_UYVY422)
+            stridey = syn->width * 2;
+    }
+
+    stridec = (regs->src_fmt.src_cfmt == VEPU541_FMT_YUV422SP ||
+               regs->src_fmt.src_cfmt == VEPU541_FMT_YUV420SP ||
+               regs->src_fmt.src_cfmt == VEPU580_FMT_YUV444P) ?
+              stridey : stridey / 2;
+
+    if (regs->src_fmt.src_cfmt == VEPU580_FMT_YUV444SP)
+        stridec = stridey * 2;
+
+    if (regs->src_fmt.src_cfmt < VEPU541_FMT_NONE) {
+        regs->src_udfy.csc_wgt_r2y = 66;
+        regs->src_udfy.csc_wgt_g2y = 129;
+        regs->src_udfy.csc_wgt_b2y = 25;
+
+        regs->src_udfu.csc_wgt_r2u = -38;
+        regs->src_udfu.csc_wgt_g2u = -74;
+        regs->src_udfu.csc_wgt_b2u = 112;
+
+        regs->src_udfv.csc_wgt_r2v = 112;
+        regs->src_udfv.csc_wgt_g2v = -94;
+        regs->src_udfv.csc_wgt_b2v = -18;
+
+        regs->src_udfo.csc_ofst_y = 16;
+        regs->src_udfo.csc_ofst_u = 128;
+        regs->src_udfo.csc_ofst_v = 128;
+    }
+
+    regs->src_strd0.src_strd0  = stridey;
+    regs->src_strd1.src_strd1  = stridec;
+    regs->pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
+    regs->pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
+
+    regs->y_cfg.bias_y = 0;
+    regs->u_cfg.bias_u = 0;
+    regs->v_cfg.bias_v = 0;
+
+    regs->base_cfg.ri  = syn->restart_ri;
+    regs->base_cfg.out_mode = 0;
+    regs->base_cfg.start_rst_m = 0;
+    regs->base_cfg.pic_last_ecs = 1;
+    regs->base_cfg.stnd = 1;
+
+    regs->uvc_cfg.uvc_partition0_len = 0;
+    regs->uvc_cfg.uvc_partition_len = 0;
+    regs->uvc_cfg.uvc_skip_len = 0;
+    return MPP_OK;
+}
+
+static MPP_RET hal_jpege_vepu510_set_roi(void *roi_reg_base, MppEncROICfg * roi,
+                                         RK_S32 w, RK_S32 h)
+{
+    MppEncROIRegion *region = roi->regions;
+    Vepu511JpegReg *roi_reg = (Vepu511JpegReg *)roi_reg_base;
+    Vepu511JpegRoiRegion *reg_regions = &roi_reg->roi_regions[0];
+    RK_S32 i;
+    MPP_RET ret = MPP_NOK;
+
+    if (NULL == reg_regions) {
+        mpp_err_f("invalid reg_regions %p\n", reg_regions);
+        goto DONE;
+    }
+
+    memset(reg_regions, 0, sizeof(Vepu511RoiRegion) * 8);
+
+    if (NULL == roi) {
+        mpp_err_f("invalid buf %p roi %p\n", roi);
+        goto DONE;
+    }
+
+    if (roi->number > MPP_MAX_JPEG_ROI_NUM) {
+        mpp_err_f("invalid region number %d\n", roi->number);
+        goto DONE;
+    }
+    mpp_log_f("set roi vepu511: roi->number %d\n", roi->number);
+
+    /* check region config */
+    ret = MPP_OK;
+    for (i = 0; i < (RK_S32) roi->number; i++, region++) {
+        if (region->x + region->w > w || region->y + region->h > h)
+            ret = MPP_NOK;
+
+        if (region->intra > 1
+            || region->qp_area_idx >= MPP_MAX_JPEG_ROI_NUM
+            || region->area_map_en > 1 || region->abs_qp_en > 1)
+            ret = MPP_NOK;
+
+        if ((region->abs_qp_en && region->quality > 51) ||
+            (!region->abs_qp_en
+             && (region->quality > 51 || region->quality < -51)))
+            ret = MPP_NOK;
+
+        if (ret) {
+            mpp_err_f("region %d invalid param:\n", i);
+            mpp_err_f("position [%d:%d:%d:%d] vs [%d:%d]\n",
+                      region->x, region->y, region->w, region->h, w,
+                      h);
+            mpp_err_f("force intra %d qp area index %d\n",
+                      region->intra, region->qp_area_idx);
+            mpp_err_f("abs qp mode %d value %d\n",
+                      region->abs_qp_en, region->quality);
+            goto DONE;
+        }
+        reg_regions->roi_cfg0.roi0_rdoq_en = 1;
+        reg_regions->roi_cfg0.roi0_rdoq_level = region->quality;
+        reg_regions->roi_cfg0.roi0_rdoq_start_x = MPP_ALIGN(region->x, 16) >> 3;
+        reg_regions->roi_cfg0.roi0_rdoq_start_y = MPP_ALIGN(region->y, 16) >> 3;
+        reg_regions->roi_cfg1.roi0_rdoq_width_m1 = (MPP_ALIGN(region->w, 16) >> 3) - 1;
+        reg_regions->roi_cfg1.roi0_rdoq_height_m1 = (MPP_ALIGN(region->h, 16) >> 3) - 1;
+
+        reg_regions++;
+    }
+DONE:
+    return ret;
+}
+
+MPP_RET hal_jpege_vepu511_gen_regs(void *hal, HalEncTask *task)
+{
+    JpegeV511HalContext *ctx = (JpegeV511HalContext *)hal;
+    JpegV511RegSet *regs = ctx->regs;
+    Vepu511ControlCfg *reg_ctl = &regs->reg_ctl;
+    JpegVepu511Base *reg_base = &regs->reg_base;
+    JpegeBits bits = ctx->bits;
+    const RK_U8 *qtable[2] = {NULL};
+    size_t length = mpp_packet_get_length(task->packet);
+    RK_U8  *buf = mpp_buffer_get_ptr(task->output);
+    size_t size = mpp_buffer_get_size(task->output);
+    JpegeSyntax *syntax = &ctx->syntax;
+    VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
+    Vepu511JpegCfg cfg;
+    RK_S32 bitpos;
+
+    hal_jpege_enter();
+    cfg.enc_task = task;
+    cfg.jpeg_reg_base = &reg_base->jpegReg;
+    cfg.dev = ctx->dev;
+    cfg.input_fmt = ctx->input_fmt;
+
+    memset(regs, 0, sizeof(JpegV511RegSet));
+
+    /* write header to output buffer */
+    jpege_bits_setup(bits, buf, (RK_U32)size);
+    /* seek length bytes data */
+    jpege_seek_bits(bits, length << 3);
+    /* NOTE: write header will update qtable */
+    write_jpeg_header(bits, syntax, qtable);
+
+    bitpos = jpege_bits_get_bitpos(bits);
+    task->length = (bitpos + 7) >> 3;
+    mpp_buffer_sync_partial_end(task->output, 0, task->length);
+    mpp_packet_set_length(task->packet, task->length);
+    reg_ctl->enc_strt.lkt_num      = 0;
+    reg_ctl->enc_strt.vepu_cmd     = ctx->enc_mode;
+    reg_ctl->enc_clr.safe_clr      = 0x0;
+    reg_ctl->enc_clr.force_clr     = 0x0;
+
+    reg_ctl->int_en.enc_done_en         = 1;
+    reg_ctl->int_en.lkt_node_done_en    = 1;
+    reg_ctl->int_en.sclr_done_en        = 1;
+    reg_ctl->int_en.vslc_done_en         = 1;
+    reg_ctl->int_en.vbsf_oflw_en         = 1;
+
+    reg_ctl->int_en.jbuf_lens_en        = 1;
+    reg_ctl->int_en.enc_err_en          = 1;
+    reg_ctl->int_en.vsrc_err_en         = 1;
+    reg_ctl->int_en.wdg_en              = 1;
+    reg_ctl->int_en.lkt_err_int_en      = 0;
+    reg_ctl->int_en.lkt_err_stop_en     = 0;
+    reg_ctl->int_en.lkt_force_stop_en   = 0;
+    reg_ctl->int_en.jslc_done_en        = 0;
+    reg_ctl->int_en.jbsf_oflw_en        = 0;
+    reg_ctl->int_en.dvbm_err_en         = 0;
+
+    reg_ctl->dtrns_map.jpeg_bus_edin    = 0x7;
+    reg_ctl->dtrns_map.src_bus_edin     = 0x0;
+    reg_ctl->dtrns_map.meiw_bus_edin    = 0x0;
+    reg_ctl->dtrns_map.bsw_bus_edin     = 0x0;
+    reg_ctl->dtrns_map.lktr_bus_edin    = 0x0;
+    reg_ctl->dtrns_map.roir_bus_edin    = 0x0;
+    reg_ctl->dtrns_map.lktw_bus_edin    = 0x0;
+    reg_ctl->dtrns_map.rec_nfbc_bus_edin   = 0x0;
+    reg_ctl->dtrns_cfg.jsrc_bus_edin = fmt->src_endian;
+    reg_base->common.enc_pic.enc_stnd = 2; // disable h264 or hevc
+
+    reg_ctl->dtrns_cfg.axi_brsp_cke     = 0x0;
+    reg_ctl->enc_wdg.vs_load_thd        = 0x1fffff;
+    reg_base->common.enc_pic.jpeg_slen_fifo = 0;
+
+    vepu511_set_jpeg_reg(&cfg);
+
+    if (ctx->roi_data) {
+        mpp_log_f("set roi data2\n");
+        hal_jpege_vepu510_set_roi(&regs->reg_base.jpegReg, ctx->roi_data,
+                                  ctx->cfg->prep.width, ctx->cfg->prep.height);
+    }
+
+    if (ctx->osd_cfg.osd_data3 || ctx->osd_cfg.osd_data)
+        vepu511_set_osd(&ctx->osd_cfg, &regs->reg_osd.osd_jpeg_cfg);
+
+    {
+        RK_U16 *tbl = &regs->jpeg_table.qua_tab0[0];
+        RK_U32 i, j;
+
+        for ( i = 0; i < 8; i++) {
+            for ( j = 0; j < 8; j++) {
+                tbl[i * 8 + j] = 0x8000 / qtable[0][j * 8 + i];
+            }
+        }
+        tbl += 64;
+        for ( i = 0; i < 8; i++) {
+            for ( j = 0; j < 8; j++) {
+                tbl[i * 8 + j] = 0x8000 / qtable[1][j * 8 + i];
+            }
+        }
+        tbl += 64;
+        for ( i = 0; i < 8; i++) {
+            for ( j = 0; j < 8; j++) {
+                tbl[i * 8 + j] = 0x8000 / qtable[1][j * 8 + i];
+            }
+        }
+    }
+    ctx->frame_num++;
+
+    hal_jpege_leave();
+    return MPP_OK;
+}
+
+MPP_RET hal_jpege_vepu511_start(void *hal, HalEncTask *enc_task)
+{
+    MPP_RET ret = MPP_OK;
+    JpegeV511HalContext *ctx = (JpegeV511HalContext *)hal;
+    JpegV511RegSet *hw_regs = ctx->regs;
+    JpegV511Status *reg_out = ctx->reg_out;
+    MppDevRegWrCfg cfg;
+    MppDevRegRdCfg cfg1;
+    hal_jpege_enter();
+
+    if (enc_task->flags.err) {
+        mpp_err_f("enc_task->flags.err %08x, return e arly",
+                  enc_task->flags.err);
+        return MPP_NOK;
+    }
+
+    cfg.reg = (RK_U32*)&hw_regs->reg_ctl;
+    cfg.size = sizeof(Vepu511ControlCfg);
+    cfg.offset = VEPU511_CTL_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    cfg.reg = &hw_regs->jpeg_table;
+    cfg.size = sizeof(JpegVepu511Tab);
+    cfg.offset = VEPU511_JPEGTAB_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    cfg.reg = &hw_regs->reg_base;
+    cfg.size = sizeof(JpegVepu511Base);
+    cfg.offset = VEPU511_FRAME_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    cfg.reg = &hw_regs->reg_osd;
+    cfg.size = sizeof(Vepu511OsdRegs);
+    cfg.offset = VEPU511_OSD_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    cfg1.reg = &reg_out->hw_status;
+    cfg1.size = sizeof(RK_U32);
+    cfg1.offset = VEPU511_REG_BASE_HW_STATUS;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
+    if (ret) {
+        mpp_err_f("set register read failed %d\n", ret);
+        return ret;
+    }
+
+    cfg1.reg = &reg_out->st;
+    cfg1.size = sizeof(JpegV511Status) - 4;
+    cfg1.offset = VEPU511_STATUS_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
+    if (ret) {
+        mpp_err_f("set register read failed %d\n", ret);
+        return ret;
+    }
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
+    if (ret) {
+        mpp_err_f("send cmd failed %d\n", ret);
+    }
+    hal_jpege_leave();
+    return ret;
+}
+
+static MPP_RET hal_jpege_vepu511_status_check(void *hal)
+{
+    JpegeV511HalContext *ctx = (JpegeV511HalContext *)hal;
+    JpegV511Status *elem = (JpegV511Status *)ctx->reg_out;
+
+    RK_U32 hw_status = elem->hw_status;
+
+    if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH)
+        mpp_err_f("RKV_ENC_INT_LINKTABLE_FINISH");
+
+    if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH)
+        mpp_err_f("RKV_ENC_INT_ONE_SLICE_FINISH");
+
+    if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH)
+        mpp_err_f("RKV_ENC_INT_SAFE_CLEAR_FINISH");
+
+    if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW)
+        mpp_err_f("RKV_ENC_INT_BIT_STREAM_OVERFLOW");
+
+    if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL)
+        mpp_err_f("RKV_ENC_INT_BUS_WRITE_FULL");
+
+    if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR)
+        mpp_err_f("RKV_ENC_INT_BUS_WRITE_ERROR");
+
+    if (hw_status & RKV_ENC_INT_BUS_READ_ERROR)
+        mpp_err_f("RKV_ENC_INT_BUS_READ_ERROR");
+
+    if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR)
+        mpp_err_f("RKV_ENC_INT_TIMEOUT_ERROR");
+
+    return MPP_OK;
+}
+
+MPP_RET hal_jpege_vepu511_wait(void *hal, HalEncTask *task)
+{
+    MPP_RET ret = MPP_OK;
+    JpegeV511HalContext *ctx = (JpegeV511HalContext *)hal;
+    HalEncTask *enc_task = task;
+    JpegV511Status *elem = (JpegV511Status *)ctx->reg_out;
+    hal_jpege_enter();
+
+    if (enc_task->flags.err) {
+        mpp_err_f("enc_task->flags.err %08x, return early",
+                  enc_task->flags.err);
+        return MPP_NOK;
+    }
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
+    if (ret) {
+        mpp_err_f("poll cmd failed %d\n", ret);
+        ret = MPP_ERR_VPUHW;
+    } else {
+        hal_jpege_vepu511_status_check(hal);
+        task->hw_length += elem->st.jpeg_head_bits_l32;
+    }
+
+    hal_jpege_leave();
+    return ret;
+}
+
+MPP_RET hal_jpege_vepu511_get_task(void *hal, HalEncTask *task)
+{
+    JpegeV511HalContext *ctx = (JpegeV511HalContext *)hal;
+    MppFrame frame = task->frame;
+    EncFrmStatus  *frm_status = &task->rc_task->frm;
+    JpegeSyntax *syntax = (JpegeSyntax *)task->syntax.data;
+
+    hal_jpege_enter();
+
+    memcpy(&ctx->syntax, syntax, sizeof(ctx->syntax));
+    ctx->last_frame_type = ctx->frame_type;
+
+    if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
+        MppMeta meta = mpp_frame_get_meta(frame);
+
+        mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
+        mpp_meta_get_ptr(meta, KEY_OSD_DATA3, (void **)&ctx->osd_cfg.osd_data3);
+
+    }
+
+    hal_jpege_leave();
+    return MPP_OK;
+}
+
+MPP_RET hal_jpege_vepu511_ret_task(void *hal, HalEncTask *task)
+{
+    (void)hal;
+    EncRcTaskInfo *rc_info = &task->rc_task->info;
+    hal_jpege_enter();
+
+    task->length += task->hw_length;
+
+    // setup bit length for rate control
+    rc_info->bit_real = task->hw_length * 8;
+    rc_info->quality_real = rc_info->quality_target;
+
+    hal_jpege_leave();
+    return MPP_OK;
+}
+
+const MppEncHalApi hal_jpege_vepu511 = {
+    .name       = "hal_jpege_v511",
+    .coding     = MPP_VIDEO_CodingMJPEG,
+    .ctx_size   = sizeof(JpegeV511HalContext),
+    .flag       = 0,
+    .init       = hal_jpege_vepu511_init,
+    .deinit     = hal_jpege_vepu511_deinit,
+    .prepare    = hal_jpege_vepu511_prepare,
+    .get_task   = hal_jpege_vepu511_get_task,
+    .gen_regs   = hal_jpege_vepu511_gen_regs,
+    .start      = hal_jpege_vepu511_start,
+    .wait       = hal_jpege_vepu511_wait,
+    .part_start = NULL,
+    .part_wait  = NULL,
+    .ret_task   = hal_jpege_vepu511_ret_task,
+};
diff --git a/mpp/hal/rkenc/jpege/hal_jpege_vepu511.h b/mpp/hal/rkenc/jpege/hal_jpege_vepu511.h
new file mode 100644
index 00000000..0745006a
--- /dev/null
+++ b/mpp/hal/rkenc/jpege/hal_jpege_vepu511.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_JPEGE_VEPU511_H__
+#define __HAL_JPEGE_VEPU511_H__
+
+#include "mpp_enc_hal.h"
+
+extern const MppEncHalApi hal_jpege_vepu511;
+#define MPP_MAX_JPEG_ROI_NUM       16
+#define MPP_MAX_JPEG_ROI_LEVEL     63
+
+#endif /* __HAL_JPEGE_VEPU511_H__ */
diff --git a/mpp/hal/rkenc/jpege/hal_jpege_vepu511_reg.h b/mpp/hal/rkenc/jpege/hal_jpege_vepu511_reg.h
new file mode 100644
index 00000000..9ddff593
--- /dev/null
+++ b/mpp/hal/rkenc/jpege/hal_jpege_vepu511_reg.h
@@ -0,0 +1,384 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_JPEGE_VEPU511_REG_H__
+#define __HAL_JPEGE_VEPU511_REG_H__
+
+#include "rk_type.h"
+#include "vepu511_common.h"
+
+typedef struct Vepu511JpegRoiRegion_t {
+    struct {
+        RK_U32 roi0_rdoq_start_x    : 11;
+        RK_U32 roi0_rdoq_start_y    : 11;
+        RK_U32 reserved             : 3;
+        RK_U32 roi0_rdoq_level      : 6;
+        RK_U32 roi0_rdoq_en         : 1;
+    } roi_cfg0;
+
+    struct {
+        RK_U32 roi0_rdoq_width_m1     : 11;
+        RK_U32 roi0_rdoq_height_m1    : 11;
+        /* the below 10 bits only for roi0 */
+        RK_U32 reserved               : 3;
+        RK_U32 frm_rdoq_level         : 6;
+        RK_U32 frm_rdoq_en            : 1;
+    } roi_cfg1;
+} Vepu511JpegRoiRegion;
+
+/* 0x00000400 reg256 - 0x0000050c reg323*/
+typedef struct Vepu511JpegReg_t {
+    /* 0x00000400 reg256 */
+    RK_U32  adr_bsbt;
+
+    /* 0x00000404 reg257 */
+    RK_U32  adr_bsbb;
+
+    /* 0x00000408 reg258 */
+    RK_U32 adr_bsbs;
+
+    /* 0x0000040c reg259 */
+    RK_U32 adr_bsbr;
+
+    /* 0x00000410 reg260 */
+    RK_U32 adr_vsy_b;
+
+    /* 0x00000414 reg261 */
+    RK_U32 adr_vsc_b;
+
+    /* 0x00000418 reg262 */
+    RK_U32 adr_vsy_t;
+
+    /* 0x0000041c reg263 */
+    RK_U32 adr_vsc_t;
+
+    /* 0x00000420 reg264 */
+    RK_U32 adr_src0;
+
+    /* 0x00000424 reg265 */
+    RK_U32 adr_src1;
+
+    /* 0x00000428 reg266 */
+    RK_U32 adr_src2;
+
+    /* 0x0000042c reg267 */
+    RK_U32 bsp_size;
+
+    /* 0x430 - 0x43c */
+    RK_U32 reserved268_271[4];
+
+    /* 0x00000440 reg272 */
+    struct {
+        RK_U32 pic_wd8_m1    : 11;
+        RK_U32 reserved      : 1;
+        RK_U32 pp0_vnum_m1   : 4;
+        RK_U32 pic_hd8_m1    : 11;
+        RK_U32 reserved1     : 1;
+        RK_U32 pp0_jnum_m1   : 4;
+    } enc_rsl;
+
+    /* 0x00000444 reg273 */
+    struct {
+        RK_U32 pic_wfill    : 6;
+        RK_U32 reserved     : 10;
+        RK_U32 pic_hfill    : 6;
+        RK_U32 reserved1    : 10;
+    } src_fill;
+
+    /* 0x00000448 reg274 */
+    struct {
+        RK_U32 alpha_swap            : 1;
+        RK_U32 rbuv_swap             : 1;
+        RK_U32 src_cfmt              : 4;
+        RK_U32 reserved              : 2;
+        RK_U32 src_range_trns_en     : 1;
+        RK_U32 src_range_trns_sel    : 1;
+        RK_U32 chroma_ds_mode        : 1;
+        RK_U32 reserved1             : 21;
+    } src_fmt;
+
+    /* 0x0000044c reg275 */
+    struct {
+        RK_U32 csc_wgt_b2y    : 9;
+        RK_U32 csc_wgt_g2y    : 9;
+        RK_U32 csc_wgt_r2y    : 9;
+        RK_U32 reserved       : 5;
+    } src_udfy;
+
+    /* 0x00000450 reg276 */
+    struct {
+        RK_U32 csc_wgt_b2u    : 9;
+        RK_U32 csc_wgt_g2u    : 9;
+        RK_U32 csc_wgt_r2u    : 9;
+        RK_U32 reserved       : 5;
+    } src_udfu;
+
+    /* 0x00000454 reg277 */
+    struct {
+        RK_U32 csc_wgt_b2v    : 9;
+        RK_U32 csc_wgt_g2v    : 9;
+        RK_U32 csc_wgt_r2v    : 9;
+        RK_U32 reserved       : 5;
+    } src_udfv;
+
+    /* 0x00000458 reg278 */
+    struct {
+        RK_U32 csc_ofst_v    : 8;
+        RK_U32 csc_ofst_u    : 8;
+        RK_U32 csc_ofst_y    : 5;
+        RK_U32 reserved      : 11;
+    } src_udfo;
+
+    /* 0x0000045c reg279 */
+    struct {
+        RK_U32 cr_force_value     : 8;
+        RK_U32 cb_force_value     : 8;
+        RK_U32 chroma_force_en    : 1;
+        RK_U32 reserved           : 9;
+        RK_U32 src_mirr           : 1;
+        RK_U32 src_rot            : 2;
+        RK_U32 reserved1          : 1;
+        RK_U32 rkfbcd_en          : 1;
+        RK_U32 reserved2          : 1;
+    } src_proc;
+
+    /* 0x00000460 reg280 */
+    struct {
+        RK_U32 pic_ofst_x    : 14;
+        RK_U32 reserved      : 2;
+        RK_U32 pic_ofst_y    : 14;
+        RK_U32 reserved1     : 2;
+    } pic_ofst;
+
+    /* 0x00000464 reg281 */
+    struct {
+        RK_U32 src_strd0    : 21;
+        RK_U32 reserved     : 11;
+    } src_strd0;
+
+    /* 0x00000468 reg282 */
+    struct {
+        RK_U32 src_strd1    : 16;
+        RK_U32 reserved     : 16;
+    } src_strd1;
+
+    /* 0x0000046c reg283 */
+    struct {
+        RK_U32 pp_corner_filter_strength      : 2;
+        RK_U32 reserved                       : 2;
+        RK_U32 pp_edge_filter_strength        : 2;
+        RK_U32 reserved1                      : 2;
+        RK_U32 pp_internal_filter_strength    : 2;
+        RK_U32 reserved2                      : 22;
+    } src_flt_cfg;
+
+    /* 0x00000470 reg284 */
+    struct {
+        RK_U32 bias_y    : 15;
+        RK_U32 reserved  : 17;
+    } y_cfg;
+
+    /* 0x00000474 reg285 */
+    struct {
+        RK_U32 bias_u    : 15;
+        RK_U32 reserved  : 17;
+    } u_cfg;
+
+    /* 0x00000478 reg286 */
+    struct {
+        RK_U32 bias_v    : 15;
+        RK_U32 reserved  : 17;
+    } v_cfg;
+
+    /* 0x0000047c reg287 */
+    struct {
+        RK_U32 ri              : 25;
+        RK_U32 out_mode        : 1;
+        RK_U32 start_rst_m     : 3;
+        RK_U32 pic_last_ecs    : 1;
+        RK_U32 reserved        : 1;
+        RK_U32 stnd            : 1;
+    } base_cfg;
+
+    /* 0x00000480 reg288 */
+    struct {
+        RK_U32 uvc_partition0_len    : 12;
+        RK_U32 uvc_partition_len     : 12;
+        RK_U32 uvc_skip_len          : 6;
+        RK_U32 reserved              : 2;
+    } uvc_cfg;
+
+    /* 0x00000484 reg289 */
+    struct {
+        RK_U32 reserved     : 4;
+        RK_U32 eslf_badr    : 28;
+    } adr_eslf;
+
+    /* 0x00000488 reg290 */
+    struct {
+        RK_U32 eslf_rptr    : 10;
+        RK_U32 eslf_wptr    : 10;
+        RK_U32 eslf_blen    : 10;
+        RK_U32 eslf_updt    : 2;
+    } eslf_buf;
+
+    /* 0x48c */
+    RK_U32 reserved_291;
+
+    /* 0x00000490 reg292 - 0x0000050c reg323*/
+    Vepu511JpegRoiRegion roi_regions[16];
+} Vepu511JpegReg;
+
+/* 0x00002ca0 reg2856 - - 0x00002e1c reg2951 */
+typedef struct JpegVepu511Tab_t {
+    RK_U16 qua_tab0[64];
+    RK_U16 qua_tab1[64];
+    RK_U16 qua_tab2[64];
+} JpegVepu511Tab;
+
+typedef struct Vepu511JpegOsdCfg_t {
+    /* 0x00003138 reg3150 */
+    struct {
+        RK_U32 osd_en                : 1;
+        RK_U32 reserved              : 4;
+        RK_U32 osd_qp_adj_en         : 1;
+        RK_U32 osd_range_trns_en     : 1;
+        RK_U32 osd_range_trns_sel    : 1;
+        RK_U32 osd_fmt               : 4;
+        RK_U32 osd_alpha_swap        : 1;
+        RK_U32 osd_rbuv_swap         : 1;
+        RK_U32 reserved1             : 8;
+        RK_U32 osd_fg_alpha          : 8;
+        RK_U32 osd_fg_alpha_sel      : 2;
+    } osd_cfg0;
+
+    /* 0x0000313c reg3151 */
+    struct {
+        RK_U32 osd_lt_xcrd    : 14;
+        RK_U32 osd_lt_ycrd    : 14;
+        RK_U32 osd_endn       : 4;
+    } osd_cfg1;
+
+    /* 0x00003140 reg3152 */
+    struct {
+        RK_U32 osd_rb_xcrd    : 14;
+        RK_U32 osd_rb_ycrd    : 14;
+        RK_U32 reserved       : 4;
+    } osd_cfg2;
+
+    /* 0x00003144 reg3153 */
+    RK_U32 osd_st_addr;
+
+    /* 0x3148 */
+    RK_U32 reserved_3154;
+
+    /* 0x0000314c reg3155 */
+    struct {
+        RK_U32 osd_stride        : 17;
+        RK_U32 reserved          : 8;
+        RK_U32 osd_ch_ds_mode    : 1;
+        RK_U32 reserved1         : 6;
+    } osd_cfg5;
+
+    /* 0x00003150 reg3156 */
+    struct {
+        RK_U32 osd_v_b_lut0    : 8;
+        RK_U32 osd_u_g_lut0    : 8;
+        RK_U32 osd_y_r_lut0    : 8;
+        RK_U32 osd_v_b_lut1    : 8;
+    } osd_cfg6;
+
+    /* 0x00003154 reg3157 */
+    struct {
+        RK_U32 osd0_u_g_lut1      : 8;
+        RK_U32 osd0_y_r_lut1      : 8;
+        RK_U32 osd0_alpha_lut0    : 8;
+        RK_U32 osd0_alpha_lut1    : 8;
+    } osd_cfg7;
+
+    /* 0x3158 */
+    RK_U32 reserved_3158;
+} JpegVepu511Osd_cfg;
+
+/* 0x00003138 reg3150 - - 0x00003264 reg3225 */
+typedef struct Vepu511JpegOsd_t {
+    JpegVepu511Osd_cfg osd_cfg[8];
+    /* 0x00003258 reg3222 */
+    struct {
+        RK_U32 osd_csc_yr    : 9;
+        RK_U32 osd_csc_yg    : 9;
+        RK_U32 osd_csc_yb    : 9;
+        RK_U32 reserved      : 5;
+    } osd_whi_cfg0;
+
+    /* 0x0000325c reg3223 */
+    struct {
+        RK_U32 osd_csc_ur    : 9;
+        RK_U32 osd_csc_ug    : 9;
+        RK_U32 osd_csc_ub    : 9;
+        RK_U32 reserved      : 5;
+    } osd_whi_cfg1;
+
+    /* 0x00003260 reg3224 */
+    struct {
+        RK_U32 osd_csc_vr    : 9;
+        RK_U32 osd_csc_vg    : 9;
+        RK_U32 osd_csc_vb    : 9;
+        RK_U32 reserved      : 5;
+    } osd_whi_cfg2;
+
+    /* 0x00003264 reg3225 */
+    struct {
+        RK_U32 osd_csc_ofst_y    : 8;
+        RK_U32 osd_csc_ofst_u    : 8;
+        RK_U32 osd_csc_ofst_v    : 8;
+        RK_U32 reserved          : 8;
+    } osd_whi_cfg3;
+} JpegVepu511Osd;
+
+/* class: buffer/video syntax */
+/* 0x00000270 reg156 - 0x0000050c reg323 */
+typedef struct JpegVepu511Base_t {
+    /* 0x00000270 reg156  - 0x0000039c reg231 */
+    Vepu511FrmCommon    common;
+
+    /* 0x000003a0 reg232 - 0x000003f4 reg253*/
+    RK_U32 reserved232_253[22];
+
+    /* 0x000003f8 reg254 */
+    struct {
+        RK_U32 slice_sta_x      : 9;
+        RK_U32 reserved1        : 7;
+        RK_U32 slice_sta_y      : 10;
+        RK_U32 reserved2        : 5;
+        RK_U32 slice_enc_ena    : 1;
+    } slice_enc_cfg0;
+
+    /* 0x000003fc reg255 */
+    struct {
+        RK_U32 slice_end_x    : 9;
+        RK_U32 reserved       : 7;
+        RK_U32 slice_end_y    : 10;
+        RK_U32 reserved1      : 6;
+    } slice_enc_cfg1;
+
+    /* 0x00000400 reg256 - 0x0000050c reg323 */
+    Vepu511JpegReg jpegReg;
+} JpegVepu511Base;
+
+typedef struct JpegV511RegSet_t {
+    Vepu511ControlCfg   reg_ctl;
+    JpegVepu511Base     reg_base;
+    JpegVepu511Tab      jpeg_table;
+    Vepu511OsdRegs      reg_osd;
+    Vepu511Dbg          reg_dbg;
+} JpegV511RegSet;
+
+typedef struct JpegV511Status_t {
+    RK_U32 hw_status;
+    Vepu511Status st;
+} JpegV511Status;
+
+#endif