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[hal_h264e_rkv]: support osd configuration
1. add osd control interface 2. remove h264e_hal_rkv_coveragetest_cfg.osd 3. add h264e_hal_test & mpi_enc_test for osd 4. use tool to format code Change-Id: Iadb3453d8e6976e5f718253f762d144864419e94 Signed-off-by: Lin Kesheng <lks@rock-chips.com>
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@@ -36,6 +36,15 @@
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#define CMD_CTX_ID_ISP (0x00030000)
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#define CMD_ID_MASK (0x0000FFFF)
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#define MPP_ENC_OSD_PLT_WHITE ((255<<24)|(128<<16)|(128<<8)|235)
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#define MPP_ENC_OSD_PLT_YELLOW ((255<<24)|(146<<16)|( 16<<8 )|210)
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#define MPP_ENC_OSD_PLT_CYAN ((255<<24)|( 16<<16 )|(166<<8)|170)
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#define MPP_ENC_OSD_PLT_GREEN ((255<<24)|( 34<<16 )|( 54<<8 )|145)
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#define MPP_ENC_OSD_PLT_TRANS (( 0<<24)|(222<<16)|(202<<8)|106)
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#define MPP_ENC_OSD_PLT_RED ((255<<24)|(240<<16)|( 90<<8 )|81)
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#define MPP_ENC_OSD_PLT_BLUE ((255<<24)|(110<<16)|(240<<8)|41)
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#define MPP_ENC_OSD_PLT_BLACK ((255<<24)|(128<<16)|(128<<8)|16)
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typedef enum {
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MPP_OSAL_CMD_BASE = CMD_MODULE_OSAL,
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MPP_OSAL_CMD_END,
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@@ -68,7 +77,8 @@ typedef enum {
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MPP_ENC_GET_RC_CFG,
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MPP_ENC_SET_PREP_CFG,
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MPP_ENC_GET_PREP_CFG,
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MPP_ENC_SET_OSD_CFG,
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MPP_ENC_SET_OSD_PLT_CFG,
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MPP_ENC_SET_OSD_DATA_CFG,
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MPP_ENC_GET_OSD_CFG,
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MPP_ENC_SET_CFG,
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MPP_ENC_GET_CFG,
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@@ -326,20 +336,41 @@ typedef struct MppEncROICfg_t {
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* When palette is set.
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* 2. fixed OSD palette
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* When palette is NULL.
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*
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* if MppEncOSDPlt.buf != NULL , palette includes maximun 256 levels,
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* every level composed of 32 bits defined below:
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* Y : 8 bits
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* U : 8 bits
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* V : 8 bits
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* alpha : 8 bits
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*/
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typedef struct MppEncOSDPlt_t {
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RK_U32 buf[256];
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} MppEncOSDPlt;
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/* position info is unit in 16 pixels(one MB), and
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* x-directon range in pixels = (rd_pos_x - lt_pos_x + 1) * 16;
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* y-directon range in pixels = (rd_pos_y - lt_pos_y + 1) * 16;
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*/
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typedef struct MppEncOSDRegion_t {
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RK_U16 x;
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RK_U16 y;
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RK_U16 w;
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RK_U16 h;
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RK_U8 *data;
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RK_U32 enable;
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RK_U32 inverse;
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RK_U32 start_mb_x;
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RK_U32 start_mb_y;
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RK_U32 num_mb_x;
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RK_U32 num_mb_y;
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RK_U32 buf_offset;
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} MppEncOSDRegion;
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typedef struct MppEncOSDCfg_t {
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RK_U32 number;
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RK_U8 *palette;
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MppEncOSDRegion *regions;
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} MppEncOSDCfg;
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/* if num_region > 0 && region==NULL
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* use old osd data
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*/
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typedef struct MppEncOSDData_t {
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MppBuffer buf;
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RK_U32 num_region;
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MppEncOSDRegion region[8];
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} MppEncOSDData;
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/*
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* Mpp Motion Detection parameter
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@@ -363,9 +394,9 @@ typedef struct MppEncOSDCfg_t {
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* 4. Buffer must be ion buffer and 1024 byte aligned.
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*/
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typedef struct MppEncMDBlkInfo_t {
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RK_U32 sad :15; /* bit 0~14 - SAD */
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RK_S32 mvx :9; /* bit 15~23 - signed horizontal mv */
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RK_S32 mvy :8; /* bit 24~31 - signed vertical mv */
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RK_U32 sad : 15; /* bit 0~14 - SAD */
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RK_S32 mvx : 9; /* bit 15~23 - signed horizontal mv */
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RK_S32 mvy : 8; /* bit 24~31 - signed vertical mv */
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} MppEncMDBlkInfo;
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#endif /*__RK_MPI_CMD_H__*/
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