From 089660baa8bc0806ab5140c6458fb4b1def7b25f Mon Sep 17 00:00:00 2001 From: Lin Kesheng Date: Fri, 30 Sep 2016 09:31:05 +0800 Subject: [PATCH] [hal_h264e_rkv]: support osd configuration 1. add osd control interface 2. remove h264e_hal_rkv_coveragetest_cfg.osd 3. add h264e_hal_test & mpi_enc_test for osd 4. use tool to format code Change-Id: Iadb3453d8e6976e5f718253f762d144864419e94 Signed-off-by: Lin Kesheng --- inc/rk_mpi_cmd.h | 59 ++++-- mpp/codec/mpp_dec.cpp | 2 +- mpp/codec/mpp_enc.cpp | 6 + mpp/hal/rkenc/h264e/hal_h264e.h | 4 +- mpp/hal/rkenc/h264e/hal_h264e_rkv.c | 232 +++++++++++----------- mpp/hal/rkenc/h264e/hal_h264e_rkv.h | 5 - mpp/hal/rkenc/h264e/hal_h264e_vpu.c | 1 - mpp/hal/rkenc/h264e/test/h264e_hal_test.c | 62 +++++- mpp/legacy/vpu_api_legacy.cpp | 2 +- mpp/mpp.cpp | 15 +- test/mpi_enc_test.c | 82 +++++++- 11 files changed, 306 insertions(+), 164 deletions(-) diff --git a/inc/rk_mpi_cmd.h b/inc/rk_mpi_cmd.h index bc24fbfe..33307a9b 100644 --- a/inc/rk_mpi_cmd.h +++ b/inc/rk_mpi_cmd.h @@ -36,6 +36,15 @@ #define CMD_CTX_ID_ISP (0x00030000) #define CMD_ID_MASK (0x0000FFFF) +#define MPP_ENC_OSD_PLT_WHITE ((255<<24)|(128<<16)|(128<<8)|235) +#define MPP_ENC_OSD_PLT_YELLOW ((255<<24)|(146<<16)|( 16<<8 )|210) +#define MPP_ENC_OSD_PLT_CYAN ((255<<24)|( 16<<16 )|(166<<8)|170) +#define MPP_ENC_OSD_PLT_GREEN ((255<<24)|( 34<<16 )|( 54<<8 )|145) +#define MPP_ENC_OSD_PLT_TRANS (( 0<<24)|(222<<16)|(202<<8)|106) +#define MPP_ENC_OSD_PLT_RED ((255<<24)|(240<<16)|( 90<<8 )|81) +#define MPP_ENC_OSD_PLT_BLUE ((255<<24)|(110<<16)|(240<<8)|41) +#define MPP_ENC_OSD_PLT_BLACK ((255<<24)|(128<<16)|(128<<8)|16) + typedef enum { MPP_OSAL_CMD_BASE = CMD_MODULE_OSAL, MPP_OSAL_CMD_END, @@ -68,7 +77,8 @@ typedef enum { MPP_ENC_GET_RC_CFG, MPP_ENC_SET_PREP_CFG, MPP_ENC_GET_PREP_CFG, - MPP_ENC_SET_OSD_CFG, + MPP_ENC_SET_OSD_PLT_CFG, + MPP_ENC_SET_OSD_DATA_CFG, MPP_ENC_GET_OSD_CFG, MPP_ENC_SET_CFG, MPP_ENC_GET_CFG, @@ -326,20 +336,41 @@ typedef struct MppEncROICfg_t { * When palette is set. * 2. fixed OSD palette * When palette is NULL. + * + * if MppEncOSDPlt.buf != NULL , palette includes maximun 256 levels, + * every level composed of 32 bits defined below: + * Y : 8 bits + * U : 8 bits + * V : 8 bits + * alpha : 8 bits + */ +typedef struct MppEncOSDPlt_t { + RK_U32 buf[256]; +} MppEncOSDPlt; + +/* position info is unit in 16 pixels(one MB), and + * x-directon range in pixels = (rd_pos_x - lt_pos_x + 1) * 16; + * y-directon range in pixels = (rd_pos_y - lt_pos_y + 1) * 16; */ typedef struct MppEncOSDRegion_t { - RK_U16 x; - RK_U16 y; - RK_U16 w; - RK_U16 h; - RK_U8 *data; + RK_U32 enable; + RK_U32 inverse; + RK_U32 start_mb_x; + RK_U32 start_mb_y; + RK_U32 num_mb_x; + RK_U32 num_mb_y; + RK_U32 buf_offset; } MppEncOSDRegion; -typedef struct MppEncOSDCfg_t { - RK_U32 number; - RK_U8 *palette; - MppEncOSDRegion *regions; -} MppEncOSDCfg; + +/* if num_region > 0 && region==NULL + * use old osd data + */ +typedef struct MppEncOSDData_t { + MppBuffer buf; + RK_U32 num_region; + MppEncOSDRegion region[8]; +} MppEncOSDData; /* * Mpp Motion Detection parameter @@ -363,9 +394,9 @@ typedef struct MppEncOSDCfg_t { * 4. Buffer must be ion buffer and 1024 byte aligned. */ typedef struct MppEncMDBlkInfo_t { - RK_U32 sad :15; /* bit 0~14 - SAD */ - RK_S32 mvx :9; /* bit 15~23 - signed horizontal mv */ - RK_S32 mvy :8; /* bit 24~31 - signed vertical mv */ + RK_U32 sad : 15; /* bit 0~14 - SAD */ + RK_S32 mvx : 9; /* bit 15~23 - signed horizontal mv */ + RK_S32 mvy : 8; /* bit 24~31 - signed vertical mv */ } MppEncMDBlkInfo; #endif /*__RK_MPI_CMD_H__*/ diff --git a/mpp/codec/mpp_dec.cpp b/mpp/codec/mpp_dec.cpp index 0fa64cb4..39d6fc8c 100644 --- a/mpp/codec/mpp_dec.cpp +++ b/mpp/codec/mpp_dec.cpp @@ -908,7 +908,7 @@ void *mpp_dec_advanced_thread(void *data) * then enqueue task back to input port * final user will release the mpp_frame they had input */ -DEC_OUT: + DEC_OUT: mpp_task_meta_set_packet(mpp_task, KEY_INPUT_PACKET, packet); mpp_port_enqueue(input, mpp_task); mpp_task = NULL; diff --git a/mpp/codec/mpp_enc.cpp b/mpp/codec/mpp_enc.cpp index fbf4e3fc..e957921c 100644 --- a/mpp/codec/mpp_enc.cpp +++ b/mpp/codec/mpp_enc.cpp @@ -429,6 +429,12 @@ MPP_RET mpp_enc_control(MppEnc *enc, MpiCmd cmd, void *param) case MPP_ENC_GET_RC_CFG : { ret = mpp_hal_control(enc->hal, cmd, param); } break; + case MPP_ENC_SET_OSD_PLT_CFG : { + ret = mpp_hal_control(enc->hal, cmd, param); + } break; + case MPP_ENC_SET_OSD_DATA_CFG : { + ret = mpp_hal_control(enc->hal, cmd, param); + } break; default : { } break; } diff --git a/mpp/hal/rkenc/h264e/hal_h264e.h b/mpp/hal/rkenc/h264e/hal_h264e.h index ae55d789..27804f2d 100644 --- a/mpp/hal/rkenc/h264e/hal_h264e.h +++ b/mpp/hal/rkenc/h264e/hal_h264e.h @@ -354,7 +354,6 @@ typedef struct h264e_hal_context_t { RK_U32 frame_cnt; h264e_hal_param param; RK_U32 enc_mode; - HalEncTask enc_task; void *dump_files; void *param_buf; @@ -362,6 +361,9 @@ typedef struct h264e_hal_context_t { MppPacket packeted_param; void *test_cfg; h264e_control_extra_info_cfg extra_info_cfg; + + RK_U32 osd_plt_type; //0:user define, 1:default + MppEncOSDData osd_data; } h264e_hal_context; #endif diff --git a/mpp/hal/rkenc/h264e/hal_h264e_rkv.c b/mpp/hal/rkenc/h264e/hal_h264e_rkv.c index c50ec8f7..089ab398 100644 --- a/mpp/hal/rkenc/h264e/hal_h264e_rkv.c +++ b/mpp/hal/rkenc/h264e/hal_h264e_rkv.c @@ -14,10 +14,11 @@ * limitations under the License. */ -#define MODULE_TAG "hal_h264e_rk" +#define MODULE_TAG "hal_h264e_rkv" #include #include +#include #include "vpu.h" #include "mpp_common.h" @@ -40,6 +41,11 @@ #define RKVENC_IS_TYPE_B(x) ((x)==RKVENC_FRAME_TYPE_B || (x)==RKVENC_FRAME_TYPE_BREF) #define RKVENC_IS_DISPOSABLE(type) ( type == RKVENC_FRAME_TYPE_B ) +#define H264E_IOC_MAGIC 'l' +#define H264E_IOC_CUSTOM_BASE 0x1000 +#define H264E_IOC_SET_OSD_PLT _IOW(H264E_IOC_MAGIC, H264E_IOC_CUSTOM_BASE+1, MppEncOSDPlt) + + const RK_S32 h264e_csp_idx_map[H264E_RKV_CSP_BUTT] = {RKV_H264E_CSP2_BGRA, RKV_H264E_CSP2_BGR, RKV_H264E_CSP2_RGB, 0, RKV_H264E_CSP2_NV16, RKV_H264E_CSP2_I422, RKV_H264E_CSP2_NV12, RKV_H264E_CSP2_I420, RKV_H264E_CSP2_RGB, RKV_H264E_CSP2_RGB }; @@ -290,6 +296,24 @@ static RK_U32 reg_idx2addr_map[132] = { }; #endif +static MPP_RET hal_h264e_rkv_cfg_hardware(RK_S32 socket, RK_U32 cmd, void *param) +{ + RK_S32 ret = 0; + + if (param == NULL) { + h264e_hal_log_err("input param is NULL"); + return MPP_ERR_NULL_PTR; + } + + ret = (RK_S32)ioctl(socket, cmd, param); + if (ret) { + h264e_hal_log_err("ioctl H264E_IOC_SET_OSDL_PLT failed ret %d", ret); + return MPP_NOK; + } + + return MPP_OK; +} + static h264e_hal_rkv_csp_info hal_h264e_rkv_convert_csp(RK_S32 src_type) { MppFrameFormat src_fmt = (MppFrameFormat)src_type; @@ -1428,12 +1452,6 @@ static MPP_RET hal_h264e_rkv_free_buffers(h264e_hal_context *ctx) return MPP_NOK; } } - if (buffers->hw_osd_buf[k]) { - if (MPP_OK != mpp_buffer_put(buffers->hw_osd_buf[k])) { - h264e_hal_log_err("hw_osd_buf[%d] put failed", k); - return MPP_NOK; - } - } } { @@ -1568,17 +1586,6 @@ static MPP_RET hal_h264e_rkv_allocate_buffers(h264e_hal_context *ctx, h264e_synt } } - if (syn->osd_mode || (test_cfg && test_cfg->osd)) { - for (k = 0; k < RKV_H264E_LINKTABLE_FRAME_NUM; k++) { - if (MPP_OK != mpp_buffer_get(buffers->hw_buf_grp[H264E_HAL_RKV_BUF_GRP_REC], &buffers->hw_osd_buf[k], num_mbs_oneframe * 256)) { - h264e_hal_log_err("hw_osd_buf[%d] get failed", buffers->hw_osd_buf[k]); - return MPP_ERR_MALLOC; - } else { - h264e_hal_log_dpb("hw_osd_buf[%d] %p done, fd %d", k, buffers->hw_osd_buf[k], mpp_buffer_get_fd(buffers->hw_osd_buf[k])); - } - } - } - h264e_hal_debug_leave(); return MPP_OK; } @@ -2496,6 +2503,48 @@ static MPP_RET hal_h264e_rkv_set_extra_info(h264e_hal_context *ctx, void *param) return MPP_OK; } +static MPP_RET hal_h264e_rkv_set_osd_plt(h264e_hal_context *ctx, void *param) +{ + MppEncOSDPlt *plt = (MppEncOSDPlt *)param; + h264e_hal_debug_enter(); + if (plt->buf) { + ctx->osd_plt_type = 0; + if (MPP_OK != hal_h264e_rkv_cfg_hardware(ctx->vpu_socket, H264E_IOC_SET_OSD_PLT, param)) { + h264e_hal_log_err("set osd plt error"); + return MPP_NOK; + } + } else { + ctx->osd_plt_type = 1; + } + + h264e_hal_debug_leave(); + return MPP_OK; +} + +static MPP_RET hal_h264e_rkv_set_osd_data(h264e_hal_context *ctx, void *param) +{ + MppEncOSDData *src = (MppEncOSDData *)param; + MppEncOSDData *dst = &ctx->osd_data; + RK_U32 num = src->num_region; + + h264e_hal_debug_enter(); + if (num > 8) { + h264e_hal_log_err("number of region %d exceed maxinum 8"); + return MPP_NOK; + } + + dst->num_region = num; + + if (num) { + if (src->buf) { + dst->buf = src->buf; + memcpy(dst->region, src->region, num * sizeof(MppEncOSDRegion)); + } + } + + h264e_hal_debug_leave(); + return MPP_OK; +} static void hal_h264e_rkv_reference_deinit( h264e_hal_rkv_dpb_ctx *dpb_ctx) { @@ -2612,10 +2661,7 @@ MPP_RET hal_h264e_rkv_deinit(void *hal) ctx->packeted_param = NULL; } - if (ctx->param_buf) { - mpp_free(ctx->param_buf); - ctx->param_buf = NULL; - } + MPP_FREE(ctx->param_buf); ctx->param_size = 0; @@ -2833,108 +2879,49 @@ MPP_RET hal_h264e_rkv_set_roi_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn, M return MPP_OK; } -MPP_RET hal_h264e_rkv_set_osd_regs(h264e_rkv_reg_set *regs, h264e_syntax *syn, MppBuffer osd_idx_buf, - h264e_hal_rkv_coveragetest_cfg *test) +MPP_RET hal_h264e_rkv_set_osd_regs(h264e_hal_context *ctx, h264e_rkv_reg_set *regs) { - if (test && test->osd) { -#define OSD_SIZE_MBS 4 //size of osd in mb - RK_S32 k = 0; - RK_U32 osd_r0_en = 1; - RK_U32 osd_r1_en = 1; - RK_U32 osd_r2_en = 1; - RK_U32 osd_r3_en = 1; - RK_U32 osd_r4_en = 1; - RK_U32 osd_r5_en = 1; - RK_U32 osd_r6_en = 1; - RK_U32 osd_r7_en = 1; +#define H264E_DEFAULT_OSD_INV_THR 15 //TODO: open interface later + RK_U32 k = 0; + MppEncOSDData *osd_data = &ctx->osd_data; + RK_U32 num = osd_data->num_region; + MppEncOSDRegion *region = osd_data->region; + RK_U32 buf_fd = mpp_buffer_get_fd(osd_data->buf); - RK_U32 osd_r0_inv_en = 0; - RK_U32 osd_r1_inv_en = 0; - RK_U32 osd_r2_inv_en = 0; - RK_U32 osd_r3_inv_en = 0; - RK_U32 osd_r4_inv_en = 0; - RK_U32 osd_r5_inv_en = 0; - RK_U32 osd_r6_inv_en = 0; - RK_U32 osd_r7_inv_en = 0; + regs->swreg65.osd_clk_sel = 1; + regs->swreg65.osd_plt_type = ctx->osd_plt_type; - RK_U32 osd_size_pixels = 16 * OSD_SIZE_MBS * 16 * OSD_SIZE_MBS; - h264e_hal_log_detail("---- test-osd ----"); + for (k = 0; k < num; k++) { + regs->swreg65.osd_en |= region[k].enable << k; + regs->swreg65.osd_inv |= region[k].inverse << k; + if (region[k].enable) { + regs->swreg67_osd_pos[k].lt_pos_x = region[k].start_mb_x; + regs->swreg67_osd_pos[k].lt_pos_y = region[k].start_mb_y; + regs->swreg67_osd_pos[k].rd_pos_x = region[k].start_mb_x + region[k].num_mb_x - 1; + regs->swreg67_osd_pos[k].rd_pos_y = region[k].start_mb_y + region[k].num_mb_y - 1; - regs->swreg65.osd_en = (osd_r0_en << 0) + (osd_r1_en << 1) + (osd_r2_en << 2) + (osd_r3_en << 3) + (osd_r4_en << 4) + (osd_r5_en << 5) + (osd_r6_en << 6) + (osd_r7_en << 7); - regs->swreg65.osd_inv = (osd_r0_inv_en << 0) + (osd_r1_inv_en << 1) + (osd_r2_inv_en << 2) + (osd_r3_inv_en << 3) + - (osd_r4_inv_en << 4) + (osd_r5_inv_en << 5) + (osd_r6_inv_en << 6) + (osd_r7_inv_en << 7); - - regs->swreg65.osd_clk_sel = 1; - regs->swreg65.osd_plt_type = 0; //OSD_plt_type; - - regs->swreg66.osd_inv_r1 = 0; //OSD_r1_inv_range; - regs->swreg66.osd_inv_r2 = 0; //OSD_r2_inv_range; - regs->swreg66.osd_inv_r3 = 0; //OSD_r3_inv_range; - regs->swreg66.osd_inv_r4 = 0; //OSD_r4_inv_range; - regs->swreg66.osd_inv_r5 = 0; //OSD_r5_inv_range; - regs->swreg66.osd_inv_r6 = 0; //OSD_r6_inv_range; - regs->swreg66.osd_inv_r7 = 0; //OSD_r7_inv_range; - - regs->swreg67_osd_pos[0].lt_pos_x = 0 * OSD_SIZE_MBS; //OSD_r0_x_lt_pos; - regs->swreg67_osd_pos[0].lt_pos_y = 0 * OSD_SIZE_MBS; //OSD_r0_y_lt_pos; - regs->swreg67_osd_pos[0].rd_pos_x = 0 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r0_x_rd_pos; - regs->swreg67_osd_pos[0].rd_pos_y = 0 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r0_y_rd_pos; - - regs->swreg67_osd_pos[1].lt_pos_x = 1 * OSD_SIZE_MBS; //OSD_r1_x_lt_pos; - regs->swreg67_osd_pos[1].lt_pos_y = 0 * OSD_SIZE_MBS; //OSD_r1_y_lt_pos; - regs->swreg67_osd_pos[1].rd_pos_x = 1 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r1_x_rd_pos; - regs->swreg67_osd_pos[1].rd_pos_y = 0 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r1_y_rd_pos; - - regs->swreg67_osd_pos[2].lt_pos_x = 2 * OSD_SIZE_MBS; //OSD_r2_x_lt_pos; - regs->swreg67_osd_pos[2].lt_pos_y = 0 * OSD_SIZE_MBS; //OSD_r2_y_lt_pos; - regs->swreg67_osd_pos[2].rd_pos_x = 2 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r2_x_rd_pos; - regs->swreg67_osd_pos[2].rd_pos_y = 0 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r2_y_rd_pos; - - regs->swreg67_osd_pos[3].lt_pos_x = 3 * OSD_SIZE_MBS; //OSD_r3_x_lt_pos; - regs->swreg67_osd_pos[3].lt_pos_y = 0 * OSD_SIZE_MBS; //OSD_r3_y_lt_pos; - regs->swreg67_osd_pos[3].rd_pos_x = 3 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r3_x_rd_pos; - regs->swreg67_osd_pos[3].rd_pos_y = 0 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r3_y_rd_pos; - - regs->swreg67_osd_pos[4].lt_pos_x = 0 * OSD_SIZE_MBS; //OSD_r4_x_lt_pos; - regs->swreg67_osd_pos[4].lt_pos_y = 1 * OSD_SIZE_MBS; //OSD_r4_y_lt_pos; - regs->swreg67_osd_pos[4].rd_pos_x = 0 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r4_x_rd_pos; - regs->swreg67_osd_pos[4].rd_pos_y = 1 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r4_x_rd_pos; - - regs->swreg67_osd_pos[5].lt_pos_x = 1 * OSD_SIZE_MBS; //OSD_r5_x_lt_pos; - regs->swreg67_osd_pos[5].lt_pos_y = 1 * OSD_SIZE_MBS; //OSD_r5_y_lt_pos; - regs->swreg67_osd_pos[5].rd_pos_x = 1 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r5_x_rd_pos; - regs->swreg67_osd_pos[5].rd_pos_y = 1 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r5_y_rd_pos; - - regs->swreg67_osd_pos[6].lt_pos_x = 2 * OSD_SIZE_MBS; //OSD_r6_x_lt_pos; - regs->swreg67_osd_pos[6].lt_pos_y = 1 * OSD_SIZE_MBS; //OSD_r6_y_lt_pos; - regs->swreg67_osd_pos[6].rd_pos_x = 2 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r6_x_rd_pos; - regs->swreg67_osd_pos[6].rd_pos_y = 1 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r6_y_rd_pos; - - regs->swreg67_osd_pos[7].lt_pos_x = 3 * OSD_SIZE_MBS; //OSD_r7_x_lt_pos; - regs->swreg67_osd_pos[7].lt_pos_y = 1 * OSD_SIZE_MBS; //OSD_r7_y_lt_pos; - regs->swreg67_osd_pos[7].rd_pos_x = 3 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r7_x_rd_pos; - regs->swreg67_osd_pos[7].rd_pos_y = 1 * OSD_SIZE_MBS + OSD_SIZE_MBS - 1; //OSD_r7_y_rd_pos; - - for (k = 0; k < 8; k++) { - if (regs->swreg65.osd_plt_type == 0) //configurable - memset((RK_U8 *)mpp_buffer_get_ptr(osd_idx_buf) + k * osd_size_pixels, 32 * k, osd_size_pixels); - else //fixed mode: only support idx 0~7 - memset((RK_U8 *)mpp_buffer_get_ptr(osd_idx_buf) + k * osd_size_pixels, k, osd_size_pixels); - - regs->swreg68_indx_addr_i[k] = mpp_buffer_get_fd(osd_idx_buf) | ((k * osd_size_pixels) << 10); //h->param.indx_addr_i[i]; + regs->swreg68_indx_addr_i[k] = buf_fd | (region[k].buf_offset << 10); } -#if 0 //written in kernel - for (k = 0; k < 256; k++) { - regs->swreg73_osd_indx_tab_i[k] = k | (0x80 << 8) | (0x80 << 16) | (k << 24); - } -#endif - } else { - - (void)test; } - (void)syn; + + if (region[0].inverse) + regs->swreg66.osd_inv_r0 = H264E_DEFAULT_OSD_INV_THR; + if (region[1].inverse) + regs->swreg66.osd_inv_r1 = H264E_DEFAULT_OSD_INV_THR; + if (region[2].inverse) + regs->swreg66.osd_inv_r2 = H264E_DEFAULT_OSD_INV_THR; + if (region[3].inverse) + regs->swreg66.osd_inv_r3 = H264E_DEFAULT_OSD_INV_THR; + if (region[4].inverse) + regs->swreg66.osd_inv_r4 = H264E_DEFAULT_OSD_INV_THR; + if (region[5].inverse) + regs->swreg66.osd_inv_r5 = H264E_DEFAULT_OSD_INV_THR; + if (region[6].inverse) + regs->swreg66.osd_inv_r6 = H264E_DEFAULT_OSD_INV_THR; + if (region[7].inverse) + regs->swreg66.osd_inv_r7 = H264E_DEFAULT_OSD_INV_THR; return MPP_OK; } @@ -3193,14 +3180,13 @@ MPP_RET hal_h264e_rkv_gen_regs(void *hal, HalTaskInfo *task) regs->swreg30_rfpw_addr = mpp_buffer_get_fd(dpb_ctx->fdec->hw_buf);//syn->addr_cfg.rfpw_addr; //TODO: extend recon luma buf if (dpb_ctx->fref[0][0]) regs->swreg31_rfpr_addr = mpp_buffer_get_fd(dpb_ctx->fref[0][0]->hw_buf); //syn->addr_cfg.rfpr_addr; - //regs->swreg32_cmvw_addr = mpp_buffer_get_fd(bufs->hw_cmv_buf[buf2_idx]); if (bufs->hw_dsp_buf[buf2_idx]) regs->swreg34_dspw_addr = mpp_buffer_get_fd(bufs->hw_dsp_buf[buf2_idx]); //syn->addr_cfg.dspw_addr; if (bufs->hw_dsp_buf[1 - buf2_idx]) regs->swreg35_dspr_addr = mpp_buffer_get_fd(bufs->hw_dsp_buf[1 - buf2_idx]); //syn->addr_cfg.dspr_addr; - if(mv_info_buf) { + if (mv_info_buf) { regs->swreg10.mei_stor = 1; //syn->swreg10.mei_stor; regs->swreg36_meiw_addr = mpp_buffer_get_fd(mv_info_buf); //mpp_buffer_get_fd(bufs->hw_mei_buf[mul_buf_idx]); } @@ -3395,7 +3381,7 @@ MPP_RET hal_h264e_rkv_gen_regs(void *hal, HalTaskInfo *task) regs->swreg64.dopn_m1_1 = dpb_ctx->i_mmco_command_count > (mmco4_pre + 1) ? dpb_ctx->mmco[(mmco4_pre + 1)].i_difference_of_pic_nums - 1 : 0; //syn->swreg64.dopn_m1_1; } - hal_h264e_rkv_set_osd_regs(regs, syn, bufs->hw_osd_buf[mul_buf_idx], test_cfg); + hal_h264e_rkv_set_osd_regs(ctx, regs); regs->swreg69.bs_lgth = 0x0; @@ -3725,6 +3711,14 @@ MPP_RET hal_h264e_rkv_control(void *hal, RK_S32 cmd_type, void *param) hal_h264e_rkv_dump_mpp_strm_out_header(ctx, pkt); break; } + case MPP_ENC_SET_OSD_PLT_CFG: { + hal_h264e_rkv_set_osd_plt(ctx, param); + break; + } + case MPP_ENC_SET_OSD_DATA_CFG: { + hal_h264e_rkv_set_osd_data(ctx, param); + break; + } default : { h264e_hal_log_err("unrecognizable cmd type %d", cmd_type); } break; diff --git a/mpp/hal/rkenc/h264e/hal_h264e_rkv.h b/mpp/hal/rkenc/h264e/hal_h264e_rkv.h index c624f7b9..3a9284d9 100644 --- a/mpp/hal/rkenc/h264e/hal_h264e_rkv.h +++ b/mpp/hal/rkenc/h264e/hal_h264e_rkv.h @@ -88,7 +88,6 @@ enc_mode typedef struct h264e_hal_rkv_coveragetest_cfg_t { RK_U32 qp; RK_U32 preproc; - RK_U32 osd; RK_U32 mbrc; RK_U32 roi; } h264e_hal_rkv_coveragetest_cfg; @@ -157,15 +156,11 @@ typedef struct h264e_hal_rkv_roi_cfg_t { typedef struct h264e_hal_rkv_buffers_t { MppBufferGroup hw_buf_grp[H264E_HAL_RKV_BUF_GRP_BUTT]; - //MppBuffer hw_input_buf[RKV_H264E_LINKTABLE_FRAME_NUM]; - //MppBuffer hw_output_buf[RKV_H264E_LINKTABLE_FRAME_NUM]; MppBuffer hw_pp_buf[2]; MppBuffer hw_dsp_buf[2]; //down scale picture MppBuffer hw_mei_buf[RKV_H264E_LINKTABLE_FRAME_NUM]; - //MppBuffer hw_cmv_buf[2]; MppBuffer hw_roi_buf[RKV_H264E_LINKTABLE_FRAME_NUM]; MppBuffer hw_rec_buf[RKV_H264E_NUM_REFS + 1]; //extra 1 frame for current recon - MppBuffer hw_osd_buf[RKV_H264E_LINKTABLE_FRAME_NUM]; } h264e_hal_rkv_buffers; typedef struct h264e_hal_rkv_nal_t { diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vpu.c b/mpp/hal/rkenc/h264e/hal_h264e_vpu.c index acf81a33..ccb4a79d 100644 --- a/mpp/hal/rkenc/h264e/hal_h264e_vpu.c +++ b/mpp/hal/rkenc/h264e/hal_h264e_vpu.c @@ -1830,7 +1830,6 @@ MPP_RET hal_h264e_vpu_gen_regs(void *hal, HalTaskInfo *task) if (MPP_OK != hal_h264e_vpu_validate_syntax(syn, &src_fmt)) { h264e_hal_log_err("hal_h264e_vpu_validate_syntax failed"); } - ctx->enc_task = task->enc; memset(reg, 0, sizeof(h264e_vpu_reg_set)); h264e_hal_log_detail("frame %d generate regs now", ctx->frame_cnt); diff --git a/mpp/hal/rkenc/h264e/test/h264e_hal_test.c b/mpp/hal/rkenc/h264e/test/h264e_hal_test.c index 691330b5..e98abbe6 100644 --- a/mpp/hal/rkenc/h264e/test/h264e_hal_test.c +++ b/mpp/hal/rkenc/h264e/test/h264e_hal_test.c @@ -209,6 +209,31 @@ static RK_U32 h264e_vpu_revert_csp(RK_U32 csp) return (RK_U32)dst_fmt; } +static MPP_RET h264e_rkv_test_gen_osd_data(MppEncOSDData *osd_data, MppBuffer *hw_osd_buf_mul) +{ + RK_U32 k = 0, buf_size = 0; + RK_U8 data = 0; + + osd_data->num_region = 8; + osd_data->buf = hw_osd_buf_mul[g_frame_read_cnt % RKV_H264E_LINKTABLE_FRAME_NUM]; + for (k = 0; k < osd_data->num_region; k++) { + osd_data->region[k].enable = 1; + osd_data->region[k].inverse = 0; + osd_data->region[k].start_mb_x = k * 4; + osd_data->region[k].start_mb_y = k * 4; + osd_data->region[k].num_mb_x = 3; + osd_data->region[k].num_mb_y = 3; + + buf_size = osd_data->region[k].num_mb_x * osd_data->region[k].num_mb_y * 256; + osd_data->region[k].buf_offset = k * buf_size; + + data = k; + memset((RK_U8 *)mpp_buffer_get_ptr(osd_data->buf) + osd_data->region[k].buf_offset, data, buf_size); + } + + return MPP_OK; +} + static MPP_RET h264e_rkv_test_open_files(h264e_hal_test_cfg test_cfg) { @@ -1232,10 +1257,6 @@ static MPP_RET h264e_hal_test_parse_options(int arg_num, char **arg_str, h264e_h cfg->test.preproc = atoi(arg_str[k + 1]); k++; } - if (!strcmp("--test-osd", arg_str[k])) { - cfg->test.osd = atoi(arg_str[k + 1]); - k++; - } if (!strcmp("--test-mbrc", arg_str[k])) { cfg->test.mbrc = atoi(arg_str[k + 1]); k++; @@ -1281,8 +1302,6 @@ static MPP_RET h264e_hal_test_parse_options(int arg_num, char **arg_str, h264e_h mpp_log("cfg->test.qp %d", cfg->test.qp); if (cfg->test.preproc) mpp_log("cfg->test.preproc %d", cfg->test.preproc); - if (cfg->test.osd) - mpp_log("cfg->test.osd %d", cfg->test.osd); if (cfg->test.mbrc) mpp_log("cfg->test.mbrc %d", cfg->test.mbrc); if (cfg->test.roi) @@ -1464,8 +1483,21 @@ MPP_RET h264e_hal_rkv_test(h264e_hal_test_cfg *test_cfg) MppBufferGroup hw_output_buf_grp = NULL; MppBuffer hw_input_buf_mul[RKV_H264E_LINKTABLE_FRAME_NUM] = {NULL}; MppBuffer hw_output_strm_buf_mul[RKV_H264E_LINKTABLE_FRAME_NUM] = {NULL}; + MppBuffer hw_osd_buf_mul[RKV_H264E_LINKTABLE_FRAME_NUM] = {NULL}; RK_U32 frame_luma_stride = 0; + MppEncOSDPlt osd_plt; + MppEncOSDData osd_data; RK_S64 t0; + RK_U32 plt_table[8] = { + MPP_ENC_OSD_PLT_WHITE, + MPP_ENC_OSD_PLT_YELLOW, + MPP_ENC_OSD_PLT_CYAN, + MPP_ENC_OSD_PLT_GREEN, + MPP_ENC_OSD_PLT_TRANS, + MPP_ENC_OSD_PLT_RED, + MPP_ENC_OSD_PLT_BLUE, + MPP_ENC_OSD_PLT_BLACK + }; mpp_packet_init(&extra_info_pkt, (void *)extra_info_buf, H264E_MAX_PACKETED_PARAM_SIZE); @@ -1489,8 +1521,10 @@ MPP_RET h264e_hal_rkv_test(h264e_hal_test_cfg *test_cfg) goto __test_end; } - for (k = 0; k < RKV_H264E_LINKTABLE_FRAME_NUM; k++) + for (k = 0; k < RKV_H264E_LINKTABLE_FRAME_NUM; k++) { mpp_buffer_get(hw_input_buf_grp, &hw_input_buf_mul[k], frame_luma_stride * 3 / 2); + mpp_buffer_get(hw_input_buf_grp, &hw_osd_buf_mul[k], frame_luma_stride); + } for (k = 0; k < RKV_H264E_LINKTABLE_FRAME_NUM; k++) mpp_buffer_get(hw_output_buf_grp, &hw_output_strm_buf_mul[k], syntax_data[0].pic_luma_width * syntax_data[0].pic_luma_height * 3 / 2); @@ -1507,6 +1541,14 @@ MPP_RET h264e_hal_rkv_test(h264e_hal_test_cfg *test_cfg) hal_h264e_rkv_control(&ctx, MPP_ENC_SET_EXTRA_INFO, &extra_info_cfg); hal_h264e_rkv_control(&ctx, MPP_ENC_GET_EXTRA_INFO, &extra_info_pkt); + if (osd_plt.buf) { + for (k = 0; k < 256; k++) { + osd_plt.buf[k] = plt_table[k % 8]; + } + } + + hal_h264e_rkv_control(&ctx, MPP_ENC_SET_OSD_PLT_CFG, (void *)&osd_plt); + do { /* get golden input */ if (g_frame_read_cnt <= g_frame_cnt) { @@ -1514,6 +1556,10 @@ MPP_RET h264e_hal_rkv_test(h264e_hal_test_cfg *test_cfg) RK_S32 frame_num = RKV_H264E_ENC_MODE == 1 ? 1 : RKV_H264E_LINKTABLE_FRAME_NUM; mpp_log("read %d frames input", frame_num); for (k = 0; k < frame_num; k++, g_frame_read_cnt++) { + + h264e_rkv_test_gen_osd_data(&osd_data, hw_osd_buf_mul); + hal_h264e_rkv_control(&ctx, MPP_ENC_SET_OSD_DATA_CFG, (void *)&osd_data); + syn = &syntax_data[g_frame_read_cnt % RKV_H264E_LINKTABLE_FRAME_NUM]; if (MPP_EOS_STREAM_REACHED == get_rkv_syntax_in(syn, hw_input_buf_mul, hw_output_strm_buf_mul, test_cfg)) { mpp_log("syntax input file end, total %d frames are encoded, test is ended", g_frame_cnt); @@ -1571,6 +1617,8 @@ __test_end: mpp_buffer_put(hw_input_buf_mul[k]); if (hw_output_strm_buf_mul[k]) mpp_buffer_put(hw_output_strm_buf_mul[k]); + if (hw_osd_buf_mul[k]) + mpp_buffer_put(hw_osd_buf_mul[k]); } if (hw_input_buf_grp) diff --git a/mpp/legacy/vpu_api_legacy.cpp b/mpp/legacy/vpu_api_legacy.cpp index 8b4729e1..fb35516d 100644 --- a/mpp/legacy/vpu_api_legacy.cpp +++ b/mpp/legacy/vpu_api_legacy.cpp @@ -543,7 +543,7 @@ RK_S32 VpuApiLegacy::decode(VpuCodecContext *ctx, VideoPacket_t *pkt, DecoderOut mpp_log("outputPacket is NULL!"); } -DECODE_OUT: + DECODE_OUT: if (str_buf) { mpp_buffer_put(str_buf); str_buf = NULL; diff --git a/mpp/mpp.cpp b/mpp/mpp.cpp index b75d6de4..c1278f29 100644 --- a/mpp/mpp.cpp +++ b/mpp/mpp.cpp @@ -672,19 +672,8 @@ MPP_RET Mpp::control_dec(MpiCmd cmd, MppParam param) MPP_RET Mpp::control_enc(MpiCmd cmd, MppParam param) { - MPP_RET ret = MPP_NOK; - - switch (cmd) { - case MPP_ENC_SET_CFG : - case MPP_ENC_GET_CFG : - case MPP_ENC_GET_EXTRA_INFO : { - mpp_assert(mEnc); - ret = mpp_enc_control(mEnc, cmd, param); - } break; - default : { - } break; - } - return ret; + mpp_assert(mEnc); + return mpp_enc_control(mEnc, cmd, param); } MPP_RET Mpp::control_isp(MpiCmd cmd, MppParam param) diff --git a/test/mpi_enc_test.c b/test/mpi_enc_test.c index 078b982d..1a9e2d3c 100644 --- a/test/mpi_enc_test.c +++ b/test/mpi_enc_test.c @@ -119,6 +119,41 @@ static MPP_RET fill_yuv_image(RK_U8 *buf, MppEncConfig *mpp_cfg, RK_U32 frame_co return ret; } +static MPP_RET mpi_enc_gen_osd_data(MppEncOSDData *osd_data, MppBuffer osd_buf, RK_U32 frame_cnt) +{ + RK_U32 k = 0, buf_size = 0; + RK_U8 data = 0; + + osd_data->num_region = 8; + osd_data->buf = osd_buf; + for (k = 0; k < osd_data->num_region; k++) { + osd_data->region[k].enable = 1; + osd_data->region[k].inverse = frame_cnt & 1; + osd_data->region[k].start_mb_x = k * 4; + osd_data->region[k].start_mb_y = k * 4; + osd_data->region[k].num_mb_x = 3; + osd_data->region[k].num_mb_y = 3; + + buf_size = osd_data->region[k].num_mb_x * osd_data->region[k].num_mb_y * 256; + osd_data->region[k].buf_offset = k * buf_size; + + data = k; + memset((RK_U8 *)mpp_buffer_get_ptr(osd_data->buf) + osd_data->region[k].buf_offset, data, buf_size); + } + + return MPP_OK; +} + +static MPP_RET mpi_enc_gen_osd_plt(MppEncOSDPlt *osd_plt, RK_U32 *table) +{ + RK_U32 k = 0; + if (osd_plt->buf) { + for (k = 0; k < 256; k++) + osd_plt->buf[k] = table[k % 8]; + } + return MPP_OK; +} + int mpi_enc_test(MpiEncTestCmd *cmd) { MPP_RET ret = MPP_OK; @@ -141,6 +176,8 @@ int mpi_enc_test(MpiEncTestCmd *cmd) MppBuffer frm_buf[MPI_ENC_IO_COUNT] = { NULL }; MppBuffer pkt_buf[MPI_ENC_IO_COUNT] = { NULL }; MppBuffer md_buf[MPI_ENC_IO_COUNT] = { NULL }; + MppBuffer osd_idx_buf[MPI_ENC_IO_COUNT] = { NULL }; + MppEncOSDPlt osd_plt; // paramter for resource malloc RK_U32 width = cmd->width; @@ -154,11 +191,23 @@ int mpi_enc_test(MpiEncTestCmd *cmd) size_t frame_size = hor_stride * ver_stride * 3 / 2; /* NOTE: packet buffer may overflow */ size_t packet_size = width * height; - /* 32 for each 16x16 block */ - size_t mdinfo_size = (((hor_stride + 255)&(~255))/16) * (ver_stride / 16) * 4; //NOTE: hor_stride should be 16-MB aligned + /* 32bits for each 16x16 block */ + size_t mdinfo_size = (((hor_stride + 255) & (~255)) / 16) * (ver_stride / 16) * 4; //NOTE: hor_stride should be 16-MB aligned + /* osd idx size range from 16x16 bytes(pixels) to hor_stride*ver_stride(bytes). for general use, 1/8 Y buffer is enough. */ + size_t osd_idx_size = hor_stride * ver_stride / 8; size_t read_size = 0; RK_U32 frame_count = 0; RK_U64 stream_size = 0; + RK_U32 plt_table[8] = { + MPP_ENC_OSD_PLT_WHITE, + MPP_ENC_OSD_PLT_YELLOW, + MPP_ENC_OSD_PLT_CYAN, + MPP_ENC_OSD_PLT_GREEN, + MPP_ENC_OSD_PLT_TRANS, + MPP_ENC_OSD_PLT_RED, + MPP_ENC_OSD_PLT_BLUE, + MPP_ENC_OSD_PLT_BLACK + }; mpp_log("mpi_enc_test start\n"); @@ -198,6 +247,12 @@ int mpi_enc_test(MpiEncTestCmd *cmd) goto MPP_TEST_OUT; } + ret = mpp_buffer_get(frm_grp, &osd_idx_buf[i], osd_idx_size); + if (ret) { + mpp_err("failed to get buffer for osd idx buf ret %d\n", ret); + goto MPP_TEST_OUT; + } + ret = mpp_buffer_get(pkt_grp, &pkt_buf[i], packet_size); if (ret) { mpp_err("failed to get buffer for input frame ret %d\n", ret); @@ -280,6 +335,14 @@ int mpi_enc_test(MpiEncTestCmd *cmd) mpp_frame_set_hor_stride(frame, hor_stride); mpp_frame_set_ver_stride(frame, ver_stride); + /* gen and cfg osd plt */ + mpi_enc_gen_osd_plt(&osd_plt, plt_table); + ret = mpi->control(ctx, MPP_ENC_SET_OSD_PLT_CFG, &osd_plt); + if (MPP_OK != ret) { + mpp_err("mpi control enc set osd plt failed\n"); + goto MPP_TEST_OUT; + } + i = 0; while (!pkt_eos) { MppTask task = NULL; @@ -287,6 +350,8 @@ int mpi_enc_test(MpiEncTestCmd *cmd) MppBuffer frm_buf_in = frm_buf[index]; MppBuffer pkt_buf_out = pkt_buf[index]; MppBuffer md_info_buf = md_buf[index]; + MppBuffer osd_data_buf = osd_idx_buf[index]; + MppEncOSDData osd_data; void *buf = mpp_buffer_get_ptr(frm_buf_in); if (i == MPI_ENC_IO_COUNT) @@ -334,6 +399,14 @@ int mpi_enc_test(MpiEncTestCmd *cmd) mpp_task_meta_set_packet(task, KEY_OUTPUT_PACKET, packet); mpp_task_meta_set_buffer(task, KEY_MOTION_INFO, md_info_buf); + /* gen and cfg osd plt */ + mpi_enc_gen_osd_data(&osd_data, osd_data_buf, frame_count); + ret = mpi->control(ctx, MPP_ENC_SET_OSD_DATA_CFG, &osd_data); + if (MPP_OK != ret) { + mpp_err("mpi control enc set osd data failed\n"); + goto MPP_TEST_OUT; + } + ret = mpi->enqueue(ctx, MPP_PORT_INPUT, task); if (ret) { mpp_err("mpp task input enqueue failed\n"); @@ -422,6 +495,11 @@ MPP_TEST_OUT: mpp_buffer_put(md_buf[i]); md_buf[i] = NULL; } + + if (osd_idx_buf[i]) { + mpp_buffer_put(osd_idx_buf[i]); + osd_idx_buf[i] = NULL; + } } if (frm_grp) {