Update On Fri Jun 14 20:33:08 CEST 2024

.github/update.log

@@ -672,3 +672,4 @@ Update On Mon Jun 10 20:32:26 CEST 2024
 Update On Tue Jun 11 20:31:29 CEST 2024
 Update On Wed Jun 12 20:32:18 CEST 2024
 Update On Thu Jun 13 20:31:26 CEST 2024
+Update On Fri Jun 14 20:32:58 CEST 2024

clash-meta/adapter/outbound/wireguard.go

@@ -12,6 +12,7 @@ import (
 	"strconv"
 	"strings"
 	"sync"
+	"time"
 
 	"github.com/metacubex/mihomo/common/atomic"
 	CN "github.com/metacubex/mihomo/common/net"
@@ -48,6 +49,10 @@ type WireGuard struct {
 	connectAddr   M.Socksaddr
 	localPrefixes []netip.Prefix
 
+	serverAddrMap   map[M.Socksaddr]netip.AddrPort
+	serverAddrTime  atomic.TypedValue[time.Time]
+	serverAddrMutex sync.Mutex
+
 	closeCh chan struct{} // for test
 }
 
@@ -67,6 +72,8 @@ type WireGuardOption struct {
 
 	RemoteDnsResolve bool     `proxy:"remote-dns-resolve,omitempty"`
 	Dns              []string `proxy:"dns,omitempty"`
+
+	RefreshServerIPInterval int `proxy:"refresh-server-ip-interval,omitempty"`
 }
 
 type WireGuardPeerOption struct {
@@ -287,6 +294,15 @@ func (w *WireGuard) resolve(ctx context.Context, address M.Socksaddr) (netip.Add
 }
 
 func (w *WireGuard) init(ctx context.Context) error {
+	err := w.init0(ctx)
+	if err != nil {
+		return err
+	}
+	w.updateServerAddr(ctx)
+	return nil
+}
+
+func (w *WireGuard) init0(ctx context.Context) error {
 	if w.initOk.Load() {
 		return nil
 	}
@@ -301,44 +317,118 @@ func (w *WireGuard) init(ctx context.Context) error {
 	}
 
 	w.bind.ResetReservedForEndpoint()
-	ipcConf := "private_key=" + w.option.PrivateKey
+	w.serverAddrMap = make(map[M.Socksaddr]netip.AddrPort)
+	ipcConf, err := w.genIpcConf(ctx, false)
+	if err != nil {
+		// !!! do not set initErr here !!!
+		// let us can retry domain resolve in next time
+		return err
+	}
+
+	if debug.Enabled {
+		log.SingLogger.Trace(fmt.Sprintf("[WG](%s) created wireguard ipc conf: \n %s", w.option.Name, ipcConf))
+	}
+	err = w.device.IpcSet(ipcConf)
+	if err != nil {
+		w.initErr = E.Cause(err, "setup wireguard")
+		return w.initErr
+	}
+	w.serverAddrTime.Store(time.Now())
+
+	err = w.tunDevice.Start()
+	if err != nil {
+		w.initErr = err
+		return w.initErr
+	}
+
+	w.initOk.Store(true)
+	return nil
+}
+
+func (w *WireGuard) updateServerAddr(ctx context.Context) {
+	if w.option.RefreshServerIPInterval != 0 && time.Since(w.serverAddrTime.Load()) > time.Second*time.Duration(w.option.RefreshServerIPInterval) {
+		if w.serverAddrMutex.TryLock() {
+			defer w.serverAddrMutex.Unlock()
+			ipcConf, err := w.genIpcConf(ctx, true)
+			if err != nil {
+				log.Warnln("[WG](%s)UpdateServerAddr failed to generate wireguard ipc conf: %s", w.option.Name, err)
+				return
+			}
+			err = w.device.IpcSet(ipcConf)
+			if err != nil {
+				log.Warnln("[WG](%s)UpdateServerAddr failed to update wireguard ipc conf: %s", w.option.Name, err)
+				return
+			}
+			w.serverAddrTime.Store(time.Now())
+		}
+	}
+}
+
+func (w *WireGuard) genIpcConf(ctx context.Context, updateOnly bool) (string, error) {
+	ipcConf := ""
+	if !updateOnly {
+		ipcConf += "private_key=" + w.option.PrivateKey + "\n"
+	}
 	if len(w.option.Peers) > 0 {
 		for i, peer := range w.option.Peers {
-			ipcConf += "\npublic_key=" + peer.PublicKey
-			destination, err := w.resolve(ctx, peer.Addr())
+			peerAddr := peer.Addr()
+			destination, err := w.resolve(ctx, peerAddr)
 			if err != nil {
-				// !!! do not set initErr here !!!
-				// let us can retry domain resolve in next time
-				return E.Cause(err, "resolve endpoint domain for peer ", i)
+				return "", E.Cause(err, "resolve endpoint domain for peer ", i)
 			}
+			if w.serverAddrMap[peerAddr] != destination {
+				w.serverAddrMap[peerAddr] = destination
+			} else if updateOnly {
+				continue
+			}
+
 			if len(w.option.Peers) == 1 { // must call SetConnectAddr if isConnect == true
 				w.bind.SetConnectAddr(destination)
 			}
-			ipcConf += "\nendpoint=" + destination.String()
-			if peer.PreSharedKey != "" {
-				ipcConf += "\npreshared_key=" + peer.PreSharedKey
-			}
-			for _, allowedIP := range peer.AllowedIPs {
-				ipcConf += "\nallowed_ip=" + allowedIP
+			ipcConf += "public_key=" + peer.PublicKey + "\n"
+			if updateOnly {
+				ipcConf += "update_only=true\n"
 			}
+			ipcConf += "endpoint=" + destination.String() + "\n"
 			if len(peer.Reserved) > 0 {
 				var reserved [3]uint8
 				copy(reserved[:], w.option.Reserved)
 				w.bind.SetReservedForEndpoint(destination, reserved)
 			}
+			if updateOnly {
+				continue
+			}
+			if peer.PreSharedKey != "" {
+				ipcConf += "preshared_key=" + peer.PreSharedKey + "\n"
+			}
+			for _, allowedIP := range peer.AllowedIPs {
+				ipcConf += "allowed_ip=" + allowedIP + "\n"
+			}
+			if w.option.PersistentKeepalive != 0 {
+				ipcConf += fmt.Sprintf("persistent_keepalive_interval=%d\n", w.option.PersistentKeepalive)
+			}
 		}
 	} else {
-		ipcConf += "\npublic_key=" + w.option.PublicKey
 		destination, err := w.resolve(ctx, w.connectAddr)
 		if err != nil {
-			// !!! do not set initErr here !!!
-			// let us can retry domain resolve in next time
-			return E.Cause(err, "resolve endpoint domain")
+			return "", E.Cause(err, "resolve endpoint domain")
+		}
+		if w.serverAddrMap[w.connectAddr] != destination {
+			w.serverAddrMap[w.connectAddr] = destination
+		} else if updateOnly {
+			return "", nil
 		}
 		w.bind.SetConnectAddr(destination) // must call SetConnectAddr if isConnect == true
-		ipcConf += "\nendpoint=" + destination.String()
+		ipcConf += "public_key=" + w.option.PublicKey + "\n"
+		if updateOnly {
+			ipcConf += "update_only=true\n"
+		}
+		ipcConf += "endpoint=" + destination.String() + "\n"
+		if updateOnly {
+			return ipcConf, nil
+		}
 		if w.option.PreSharedKey != "" {
-			ipcConf += "\npreshared_key=" + w.option.PreSharedKey
+			ipcConf += "preshared_key=" + w.option.PreSharedKey + "\n"
 		}
 		var has4, has6 bool
 		for _, address := range w.localPrefixes {
@@ -349,34 +439,17 @@ func (w *WireGuard) init(ctx context.Context) error {
 			}
 		}
 		if has4 {
-			ipcConf += "\nallowed_ip=0.0.0.0/0"
+			ipcConf += "allowed_ip=0.0.0.0/0\n"
 		}
 		if has6 {
-			ipcConf += "\nallowed_ip=::/0"
+			ipcConf += "allowed_ip=::/0\n"
+		}
+
+		if w.option.PersistentKeepalive != 0 {
+			ipcConf += fmt.Sprintf("persistent_keepalive_interval=%d\n", w.option.PersistentKeepalive)
 		}
 	}
-
-	if w.option.PersistentKeepalive != 0 {
-		ipcConf += fmt.Sprintf("\npersistent_keepalive_interval=%d", w.option.PersistentKeepalive)
-	}
-
-	if debug.Enabled {
-		log.SingLogger.Trace(fmt.Sprintf("[WG](%s) created wireguard ipc conf: \n %s", w.option.Name, ipcConf))
-	}
-	err := w.device.IpcSet(ipcConf)
-	if err != nil {
-		w.initErr = E.Cause(err, "setup wireguard")
-		return w.initErr
-	}
-
-	err = w.tunDevice.Start()
-	if err != nil {
-		w.initErr = err
-		return w.initErr
-	}
-
-	w.initOk.Store(true)
-	return nil
+	return ipcConf, nil
 }
 
 func closeWireGuard(w *WireGuard) {

clash-meta/dns/client.go

@@ -9,9 +9,7 @@ import (
 	"strings"
 
 	"github.com/metacubex/mihomo/component/ca"
-	"github.com/metacubex/mihomo/component/dialer"
 	"github.com/metacubex/mihomo/component/resolver"
-	C "github.com/metacubex/mihomo/constant"
 	"github.com/metacubex/mihomo/log"
 
 	"github.com/metacubex/randv2"
@@ -20,13 +18,11 @@ import (
 
 type client struct {
 	*D.Client
-	r            *Resolver
-	port         string
-	host         string
-	iface        string
-	proxyAdapter C.ProxyAdapter
-	proxyName    string
-	addr         string
+	r      *Resolver
+	port   string
+	host   string
+	dialer *dnsDialer
+	addr   string
 }
 
 var _ dnsClient = (*client)(nil)
@@ -73,14 +69,8 @@ func (c *client) ExchangeContext(ctx context.Context, m *D.Msg) (*D.Msg, error)
 		network = "tcp"
 	}
 
-	var options []dialer.Option
-	if c.iface != "" {
-		options = append(options, dialer.WithInterface(c.iface))
-	}
-
-	dialHandler := getDialHandler(c.r, c.proxyAdapter, c.proxyName, options...)
 	addr := net.JoinHostPort(ip.String(), c.port)
-	conn, err := dialHandler(ctx, network, addr)
+	conn, err := c.dialer.DialContext(ctx, network, addr)
 	if err != nil {
 		return nil, err
 	}
@@ -115,7 +105,7 @@ func (c *client) ExchangeContext(ctx context.Context, m *D.Msg) (*D.Msg, error)
 			tcpClient.Net = "tcp"
 			network = "tcp"
 			log.Debugln("[DNS] Truncated reply from %s:%s for %s over UDP, retrying over TCP", c.host, c.port, m.Question[0].String())
-			dConn.Conn, err = dialHandler(ctx, network, addr)
+			dConn.Conn, err = c.dialer.DialContext(ctx, network, addr)
 			if err != nil {
 				ch <- result{msg, err}
 				return

clash-meta/dns/dialer.go

@@ -6,7 +6,6 @@ import "github.com/metacubex/mihomo/tunnel"
 
 const RespectRules = tunnel.DnsRespectRules
 
-type dialHandler = tunnel.DnsDialHandler
+type dnsDialer = tunnel.DNSDialer
 
-var getDialHandler = tunnel.GetDnsDialHandler
-var listenPacket = tunnel.DnsListenPacket
+var newDNSDialer = tunnel.NewDNSDialer

clash-meta/dns/doh.go

@@ -62,10 +62,8 @@ type dnsOverHTTPS struct {
 	quicConfig      *quic.Config
 	quicConfigGuard sync.Mutex
 	url             *url.URL
-	r               *Resolver
 	httpVersions    []C.HTTPVersion
-	proxyAdapter    C.ProxyAdapter
-	proxyName       string
+	dialer          *dnsDialer
 	addr            string
 }
 
@@ -85,11 +83,9 @@ func newDoHClient(urlString string, r *Resolver, preferH3 bool, params map[strin
 	}
 
 	doh := &dnsOverHTTPS{
-		url:          u,
-		addr:         u.String(),
-		r:            r,
-		proxyAdapter: proxyAdapter,
-		proxyName:    proxyName,
+		url:    u,
+		addr:   u.String(),
+		dialer: newDNSDialer(r, proxyAdapter, proxyName),
 		quicConfig: &quic.Config{
 			KeepAlivePeriod: QUICKeepAlivePeriod,
 			TokenStore:      newQUICTokenStore(),
@@ -388,13 +384,12 @@ func (doh *dnsOverHTTPS) createTransport(ctx context.Context) (t http.RoundTripp
 		nextProtos = append(nextProtos, string(v))
 	}
 	tlsConfig.NextProtos = nextProtos
-	dialContext := getDialHandler(doh.r, doh.proxyAdapter, doh.proxyName)
 
 	if slices.Contains(doh.httpVersions, C.HTTPVersion3) {
 		// First, we attempt to create an HTTP3 transport.  If the probe QUIC
 		// connection is established successfully, we'll be using HTTP3 for this
 		// upstream.
-		transportH3, err := doh.createTransportH3(ctx, tlsConfig, dialContext)
+		transportH3, err := doh.createTransportH3(ctx, tlsConfig)
 		if err == nil {
 			log.Debugln("[%s] using HTTP/3 for this upstream: QUIC was faster", doh.url.String())
 			return transportH3, nil
@@ -410,7 +405,7 @@ func (doh *dnsOverHTTPS) createTransport(ctx context.Context) (t http.RoundTripp
 	transport := &http.Transport{
 		TLSClientConfig:    tlsConfig,
 		DisableCompression: true,
-		DialContext:        dialContext,
+		DialContext:        doh.dialer.DialContext,
 		IdleConnTimeout:    transportDefaultIdleConnTimeout,
 		MaxConnsPerHost:    dohMaxConnsPerHost,
 		MaxIdleConns:       dohMaxIdleConns,
@@ -490,13 +485,12 @@ func (h *http3Transport) Close() (err error) {
 func (doh *dnsOverHTTPS) createTransportH3(
 	ctx context.Context,
 	tlsConfig *tls.Config,
-	dialContext dialHandler,
 ) (roundTripper http.RoundTripper, err error) {
 	if !doh.supportsH3() {
 		return nil, errors.New("HTTP3 support is not enabled")
 	}
 
-	addr, err := doh.probeH3(ctx, tlsConfig, dialContext)
+	addr, err := doh.probeH3(ctx, tlsConfig)
 	if err != nil {
 		return nil, err
 	}
@@ -534,7 +528,7 @@ func (doh *dnsOverHTTPS) dialQuic(ctx context.Context, addr string, tlsCfg *tls.
 		IP:   net.ParseIP(ip),
 		Port: portInt,
 	}
-	conn, err := listenPacket(ctx, doh.proxyAdapter, doh.proxyName, "udp", addr, doh.r)
+	conn, err := doh.dialer.ListenPacket(ctx, "udp", addr)
 	if err != nil {
 		return nil, err
 	}
@@ -557,12 +551,11 @@ func (doh *dnsOverHTTPS) dialQuic(ctx context.Context, addr string, tlsCfg *tls.
 func (doh *dnsOverHTTPS) probeH3(
 	ctx context.Context,
 	tlsConfig *tls.Config,
-	dialContext dialHandler,
 ) (addr string, err error) {
 	// We're using bootstrapped address instead of what's passed to the function
 	// it does not create an actual connection, but it helps us determine
 	// what IP is actually reachable (when there are v4/v6 addresses).
-	rawConn, err := dialContext(ctx, "udp", doh.url.Host)
+	rawConn, err := doh.dialer.DialContext(ctx, "udp", doh.url.Host)
 	if err != nil {
 		return "", fmt.Errorf("failed to dial: %w", err)
 	}
@@ -592,7 +585,7 @@ func (doh *dnsOverHTTPS) probeH3(
 	chQuic := make(chan error, 1)
 	chTLS := make(chan error, 1)
 	go doh.probeQUIC(ctx, addr, probeTLSCfg, chQuic)
-	go doh.probeTLS(ctx, dialContext, probeTLSCfg, chTLS)
+	go doh.probeTLS(ctx, probeTLSCfg, chTLS)
 
 	select {
 	case quicErr := <-chQuic:
@@ -635,10 +628,10 @@ func (doh *dnsOverHTTPS) probeQUIC(ctx context.Context, addr string, tlsConfig *
 
 // probeTLS attempts to establish a TLS connection to the specified address. We
 // run probeQUIC and probeTLS in parallel and see which one is faster.
-func (doh *dnsOverHTTPS) probeTLS(ctx context.Context, dialContext dialHandler, tlsConfig *tls.Config, ch chan error) {
+func (doh *dnsOverHTTPS) probeTLS(ctx context.Context, tlsConfig *tls.Config, ch chan error) {
 	startTime := time.Now()
 
-	conn, err := doh.tlsDial(ctx, dialContext, "tcp", tlsConfig)
+	conn, err := doh.tlsDial(ctx, "tcp", tlsConfig)
 	if err != nil {
 		ch <- fmt.Errorf("opening TLS connection: %w", err)
 		return
@@ -694,10 +687,10 @@ func isHTTP3(client *http.Client) (ok bool) {
 
 // tlsDial is basically the same as tls.DialWithDialer, but we will call our own
 // dialContext function to get connection.
-func (doh *dnsOverHTTPS) tlsDial(ctx context.Context, dialContext dialHandler, network string, config *tls.Config) (*tls.Conn, error) {
+func (doh *dnsOverHTTPS) tlsDial(ctx context.Context, network string, config *tls.Config) (*tls.Conn, error) {
 	// We're using bootstrapped address instead of what's passed
 	// to the function.
-	rawConn, err := dialContext(ctx, network, doh.url.Host)
+	rawConn, err := doh.dialer.DialContext(ctx, network, doh.url.Host)
 	if err != nil {
 		return nil, err
 	}

clash-meta/dns/doq.go

@@ -60,10 +60,8 @@ type dnsOverQUIC struct {
 	bytesPool      *sync.Pool
 	bytesPoolGuard sync.Mutex
 
-	addr         string
-	proxyAdapter C.ProxyAdapter
-	proxyName    string
-	r            *Resolver
+	addr   string
+	dialer *dnsDialer
 }
 
 // type check
@@ -72,10 +70,8 @@ var _ dnsClient = (*dnsOverQUIC)(nil)
 // newDoQ returns the DNS-over-QUIC Upstream.
 func newDoQ(resolver *Resolver, addr string, proxyAdapter C.ProxyAdapter, proxyName string) (dnsClient, error) {
 	doq := &dnsOverQUIC{
-		addr:         addr,
-		proxyAdapter: proxyAdapter,
-		proxyName:    proxyName,
-		r:            resolver,
+		addr:   addr,
+		dialer: newDNSDialer(resolver, proxyAdapter, proxyName),
 		quicConfig: &quic.Config{
 			KeepAlivePeriod: QUICKeepAlivePeriod,
 			TokenStore:      newQUICTokenStore(),
@@ -300,7 +296,7 @@ func (doq *dnsOverQUIC) openConnection(ctx context.Context) (conn quic.Connectio
 	// we're using bootstrapped address instead of what's passed to the function
 	// it does not create an actual connection, but it helps us determine
 	// what IP is actually reachable (when there're v4/v6 addresses).
-	rawConn, err := getDialHandler(doq.r, doq.proxyAdapter, doq.proxyName)(ctx, "udp", doq.addr)
+	rawConn, err := doq.dialer.DialContext(ctx, "udp", doq.addr)
 	if err != nil {
 		return nil, fmt.Errorf("failed to open a QUIC connection: %w", err)
 	}
@@ -315,7 +311,7 @@ func (doq *dnsOverQUIC) openConnection(ctx context.Context) (conn quic.Connectio
 
 	p, err := strconv.Atoi(port)
 	udpAddr := net.UDPAddr{IP: net.ParseIP(ip), Port: p}
-	udp, err := listenPacket(ctx, doq.proxyAdapter, doq.proxyName, "udp", addr, doq.r)
+	udp, err := doq.dialer.ListenPacket(ctx, "udp", addr)
 	if err != nil {
 		return nil, err
 	}

clash-meta/dns/util.go

@@ -12,6 +12,7 @@ import (
 
 	"github.com/metacubex/mihomo/common/nnip"
 	"github.com/metacubex/mihomo/common/picker"
+	"github.com/metacubex/mihomo/component/dialer"
 	"github.com/metacubex/mihomo/component/resolver"
 	"github.com/metacubex/mihomo/log"
 
@@ -115,6 +116,11 @@ func transform(servers []NameServer, resolver *Resolver) []dnsClient {
 			continue
 		}
 
+		var options []dialer.Option
+		if s.Interface != "" {
+			options = append(options, dialer.WithInterface(s.Interface))
+		}
+
 		host, port, _ := net.SplitHostPort(s.Addr)
 		ret = append(ret, &client{
 			Client: &D.Client{
@@ -125,12 +131,9 @@ func transform(servers []NameServer, resolver *Resolver) []dnsClient {
 				UDPSize: 4096,
 				Timeout: 5 * time.Second,
 			},
-			port:         port,
-			host:         host,
-			iface:        s.Interface,
-			r:            resolver,
-			proxyAdapter: s.ProxyAdapter,
-			proxyName:    s.ProxyName,
+			port:   port,
+			host:   host,
+			dialer: newDNSDialer(resolver, s.ProxyAdapter, s.ProxyName, options...),
 		})
 	}
 	return ret

clash-meta/docs/config.yaml

@@ -728,6 +728,7 @@ proxies: # socks5
     # dialer-proxy: "ss1"
     # remote-dns-resolve: true # 强制 dns 远程解析，默认值为 false
     # dns: [ 1.1.1.1, 8.8.8.8 ] # 仅在 remote-dns-resolve 为 true 时生效
+    # refresh-server-ip-interval: 60 # 重新解析server ip的间隔，单位为秒，默认值为0即仅第一次链接时解析server域名，仅应在server域名对应的IP会发生变化时启用该选项（如家宽ddns）
     # 如果 peers 不为空，该段落中的 allowed-ips 不可为空；前面段落的 server,port,public-key,pre-shared-key 均会被忽略，但 private-key 会被保留且只能在顶层指定
     # peers:
     #   - server: 162.159.192.1

clash-meta/tunnel/dns_dialer.go

@@ -18,110 +18,125 @@ import (
 
 const DnsRespectRules = "RULES"
 
-type DnsDialHandler func(ctx context.Context, network, addr string) (net.Conn, error)
+type DNSDialer struct {
+	r            resolver.Resolver
+	proxyAdapter C.ProxyAdapter
+	proxyName    string
+	opts         []dialer.Option
+}
 
-func GetDnsDialHandler(r resolver.Resolver, proxyAdapter C.ProxyAdapter, proxyName string, opts ...dialer.Option) DnsDialHandler {
-	return func(ctx context.Context, network, addr string) (net.Conn, error) {
-		if len(proxyName) == 0 && proxyAdapter == nil {
-			opts = append(opts, dialer.WithResolver(r))
-			return dialer.DialContext(ctx, network, addr, opts...)
-		} else {
-			metadata := &C.Metadata{
-				NetWork: C.TCP,
-				Type:    C.INNER,
+func NewDNSDialer(r resolver.Resolver, proxyAdapter C.ProxyAdapter, proxyName string, opts ...dialer.Option) *DNSDialer {
+	return &DNSDialer{r: r, proxyAdapter: proxyAdapter, proxyName: proxyName, opts: opts}
+}
+
+func (d *DNSDialer) DialContext(ctx context.Context, network, addr string) (net.Conn, error) {
+	r := d.r
+	proxyName := d.proxyName
+	proxyAdapter := d.proxyAdapter
+	opts := d.opts
+	if len(proxyName) == 0 && proxyAdapter == nil {
+		opts = append(opts, dialer.WithResolver(r))
+		return dialer.DialContext(ctx, network, addr, opts...)
+	} else {
+		metadata := &C.Metadata{
+			NetWork: C.TCP,
+			Type:    C.INNER,
+		}
+		err := metadata.SetRemoteAddress(addr) // tcp can resolve host by remote
+		if err != nil {
+			return nil, err
+		}
+		if !strings.Contains(network, "tcp") {
+			metadata.NetWork = C.UDP
+			if !metadata.Resolved() {
+				// udp must resolve host first
+				dstIP, err := resolver.ResolveIPWithResolver(ctx, metadata.Host, r)
+				if err != nil {
+					return nil, err
+				}
+				metadata.DstIP = dstIP
 			}
-			err := metadata.SetRemoteAddress(addr) // tcp can resolve host by remote
-			if err != nil {
-				return nil, err
-			}
-			if !strings.Contains(network, "tcp") {
-				metadata.NetWork = C.UDP
+		}
+
+		var rule C.Rule
+		if proxyAdapter == nil {
+			if proxyName == DnsRespectRules {
 				if !metadata.Resolved() {
-					// udp must resolve host first
+					// resolve here before resolveMetadata to avoid its inner resolver.ResolveIP
 					dstIP, err := resolver.ResolveIPWithResolver(ctx, metadata.Host, r)
 					if err != nil {
 						return nil, err
 					}
 					metadata.DstIP = dstIP
 				}
+				proxyAdapter, rule, err = resolveMetadata(metadata)
+				if err != nil {
+					return nil, err
+				}
+			} else {
+				var ok bool
+				proxyAdapter, ok = Proxies()[proxyName]
+				if !ok {
+					opts = append(opts, dialer.WithInterface(proxyName))
+				}
+			}
+		}
+
+		if strings.Contains(network, "tcp") {
+			if proxyAdapter == nil {
+				opts = append(opts, dialer.WithResolver(r))
+				return dialer.DialContext(ctx, network, addr, opts...)
 			}
 
-			var rule C.Rule
-			if proxyAdapter == nil {
-				if proxyName == DnsRespectRules {
-					if !metadata.Resolved() {
-						// resolve here before resolveMetadata to avoid its inner resolver.ResolveIP
-						dstIP, err := resolver.ResolveIPWithResolver(ctx, metadata.Host, r)
-						if err != nil {
-							return nil, err
-						}
-						metadata.DstIP = dstIP
-					}
-					proxyAdapter, rule, err = resolveMetadata(metadata)
+			if proxyAdapter.IsL3Protocol(metadata) { // L3 proxy should resolve domain before to avoid loopback
+				if !metadata.Resolved() {
+					dstIP, err := resolver.ResolveIPWithResolver(ctx, metadata.Host, r)
 					if err != nil {
 						return nil, err
 					}
-				} else {
-					var ok bool
-					proxyAdapter, ok = Proxies()[proxyName]
-					if !ok {
-						opts = append(opts, dialer.WithInterface(proxyName))
-					}
+					metadata.DstIP = dstIP
 				}
+				metadata.Host = "" // clear host to avoid double resolve in proxy
 			}
 
-			if strings.Contains(network, "tcp") {
-				if proxyAdapter == nil {
-					opts = append(opts, dialer.WithResolver(r))
-					return dialer.DialContext(ctx, network, addr, opts...)
-				}
-
-				if proxyAdapter.IsL3Protocol(metadata) { // L3 proxy should resolve domain before to avoid loopback
-					if !metadata.Resolved() {
-						dstIP, err := resolver.ResolveIPWithResolver(ctx, metadata.Host, r)
-						if err != nil {
-							return nil, err
-						}
-						metadata.DstIP = dstIP
-					}
-					metadata.Host = "" // clear host to avoid double resolve in proxy
-				}
-
-				conn, err := proxyAdapter.DialContext(ctx, metadata, opts...)
-				if err != nil {
-					logMetadataErr(metadata, rule, proxyAdapter, err)
-					return nil, err
-				}
-				logMetadata(metadata, rule, conn)
-
-				conn = statistic.NewTCPTracker(conn, statistic.DefaultManager, metadata, rule, 0, 0, false)
-
-				return conn, nil
-			} else {
-				if proxyAdapter == nil {
-					return dialer.DialContext(ctx, network, addr, opts...)
-				}
-
-				if !proxyAdapter.SupportUDP() {
-					return nil, fmt.Errorf("proxy adapter [%s] UDP is not supported", proxyAdapter)
-				}
-
-				packetConn, err := proxyAdapter.ListenPacketContext(ctx, metadata, opts...)
-				if err != nil {
-					logMetadataErr(metadata, rule, proxyAdapter, err)
-					return nil, err
-				}
-				logMetadata(metadata, rule, packetConn)
-
-				packetConn = statistic.NewUDPTracker(packetConn, statistic.DefaultManager, metadata, rule, 0, 0, false)
-
-				return N.NewBindPacketConn(packetConn, metadata.UDPAddr()), nil
+			conn, err := proxyAdapter.DialContext(ctx, metadata, opts...)
+			if err != nil {
+				logMetadataErr(metadata, rule, proxyAdapter, err)
+				return nil, err
 			}
+			logMetadata(metadata, rule, conn)
+
+			conn = statistic.NewTCPTracker(conn, statistic.DefaultManager, metadata, rule, 0, 0, false)
+
+			return conn, nil
+		} else {
+			if proxyAdapter == nil {
+				return dialer.DialContext(ctx, network, addr, opts...)
+			}
+
+			if !proxyAdapter.SupportUDP() {
+				return nil, fmt.Errorf("proxy adapter [%s] UDP is not supported", proxyAdapter)
+			}
+
+			packetConn, err := proxyAdapter.ListenPacketContext(ctx, metadata, opts...)
+			if err != nil {
+				logMetadataErr(metadata, rule, proxyAdapter, err)
+				return nil, err
+			}
+			logMetadata(metadata, rule, packetConn)
+
+			packetConn = statistic.NewUDPTracker(packetConn, statistic.DefaultManager, metadata, rule, 0, 0, false)
+
+			return N.NewBindPacketConn(packetConn, metadata.UDPAddr()), nil
 		}
 	}
 }
 
-func DnsListenPacket(ctx context.Context, proxyAdapter C.ProxyAdapter, proxyName string, network string, addr string, r resolver.Resolver, opts ...dialer.Option) (net.PacketConn, error) {
+func (d *DNSDialer) ListenPacket(ctx context.Context, network, addr string) (net.PacketConn, error) {
+	r := d.r
+	proxyAdapter := d.proxyAdapter
+	proxyName := d.proxyName
+	opts := d.opts
 	metadata := &C.Metadata{
 		NetWork: C.UDP,
 		Type:    C.INNER,

clash-nyanpasu/frontend/nyanpasu/package.json

@@ -19,7 +19,7 @@
     "@mui/icons-material": "5.15.20",
     "@mui/lab": "5.0.0-alpha.170",
     "@mui/material": "5.15.20",
-    "@mui/x-data-grid": "7.6.2",
+    "@mui/x-data-grid": "7.7.0",
     "@nyanpasu/interface": "workspace:^",
     "@nyanpasu/ui": "workspace:^",
     "@tauri-apps/api": "1.5.6",

clash-nyanpasu/pnpm-lock.yaml

@@ -195,8 +195,8 @@ importers:
         specifier: 5.15.20
         version: 5.15.20(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(@emotion/styled@11.11.5(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react-dom@19.0.0-rc-9d4fba0788-20240530(react@19.0.0-rc-9d4fba0788-20240530))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0)
       '@mui/x-data-grid':
-        specifier: 7.6.2
-        version: 7.6.2(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(@emotion/styled@11.11.5(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(@mui/material@5.15.20(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(@emotion/styled@11.11.5(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react-dom@19.0.0-rc-9d4fba0788-20240530(react@19.0.0-rc-9d4fba0788-20240530))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react-dom@19.0.0-rc-9d4fba0788-20240530(react@19.0.0-rc-9d4fba0788-20240530))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0)
+        specifier: 7.7.0
+        version: 7.7.0(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(@emotion/styled@11.11.5(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(@mui/material@5.15.20(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(@emotion/styled@11.11.5(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react-dom@19.0.0-rc-9d4fba0788-20240530(react@19.0.0-rc-9d4fba0788-20240530))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react-dom@19.0.0-rc-9d4fba0788-20240530(react@19.0.0-rc-9d4fba0788-20240530))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0)
       '@nyanpasu/interface':
         specifier: workspace:^
         version: link:../interface
@@ -520,6 +520,10 @@ packages:
     resolution: {integrity: sha512-Ja18XcETdEl5mzzACGd+DKgaGJzPTCow7EglgwTmHdwokzDFYh/MHua6lU6DV/hjF2IaOJ4oX2nqnjG7RElKOw==}
     engines: {node: '>=6.9.0'}
 
+  '@babel/runtime@7.24.7':
+    resolution: {integrity: sha512-UwgBRMjJP+xv857DCngvqXI3Iq6J4v0wXmwc6sapg+zyhbwmQX67LUEFrkK5tbyJ30jGuG3ZvWpBiB9LCy1kWw==}
+    engines: {node: '>=6.9.0'}
+
   '@babel/template@7.24.0':
     resolution: {integrity: sha512-Bkf2q8lMB0AFpX0NFEqSbx1OkTHf0f+0j82mkw+ZpzBnkk7e9Ql0891vlfgi+kHwOk8tQjiQHpqh4LaSa0fKEA==}
     engines: {node: '>=6.9.0'}
@@ -1228,8 +1232,8 @@ packages:
       '@types/react':
         optional: true
 
-  '@mui/x-data-grid@7.6.2':
-    resolution: {integrity: sha512-f3t6TU8+f0VgmL4aJ9N/Wm5IeWfICfVb45S469wzzldUhbb/beIO/T3uMyGP13WFhx5f8N5wRRHSYZRHpfzhZw==}
+  '@mui/x-data-grid@7.7.0':
+    resolution: {integrity: sha512-s3Oii9EKcYPnL7M4g5evNley/J0slLL6xWRi0VwYqTHPGntBAMntUktMZ63bD/xko99f5ZcFoRBYTc55+mJ+AQ==}
     engines: {node: '>=14.0.0'}
     peerDependencies:
       '@mui/material': ^5.15.14
@@ -5210,6 +5214,10 @@ snapshots:
     dependencies:
       regenerator-runtime: 0.14.1
 
+  '@babel/runtime@7.24.7':
+    dependencies:
+      regenerator-runtime: 0.14.1
+
   '@babel/template@7.24.0':
     dependencies:
       '@babel/code-frame': 7.24.2
@@ -5780,7 +5788,7 @@ snapshots:
   '@mui/private-theming@5.15.14(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0)':
     dependencies:
       '@babel/runtime': 7.24.6
-      '@mui/utils': 5.15.14(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0)
+      '@mui/utils': 5.15.20(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0)
       prop-types: 15.8.1
       react: 19.0.0-rc-9d4fba0788-20240530
     optionalDependencies:
@@ -5862,12 +5870,12 @@ snapshots:
     optionalDependencies:
       '@types/react': types-react@19.0.0-rc.0
 
-  '@mui/x-data-grid@7.6.2(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(@emotion/styled@11.11.5(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(@mui/material@5.15.20(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(@emotion/styled@11.11.5(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react-dom@19.0.0-rc-9d4fba0788-20240530(react@19.0.0-rc-9d4fba0788-20240530))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react-dom@19.0.0-rc-9d4fba0788-20240530(react@19.0.0-rc-9d4fba0788-20240530))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0)':
+  '@mui/x-data-grid@7.7.0(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(@emotion/styled@11.11.5(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(@mui/material@5.15.20(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(@emotion/styled@11.11.5(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react-dom@19.0.0-rc-9d4fba0788-20240530(react@19.0.0-rc-9d4fba0788-20240530))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react-dom@19.0.0-rc-9d4fba0788-20240530(react@19.0.0-rc-9d4fba0788-20240530))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0)':
     dependencies:
-      '@babel/runtime': 7.24.6
+      '@babel/runtime': 7.24.7
       '@mui/material': 5.15.20(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(@emotion/styled@11.11.5(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react-dom@19.0.0-rc-9d4fba0788-20240530(react@19.0.0-rc-9d4fba0788-20240530))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0)
-      '@mui/system': 5.15.15(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(@emotion/styled@11.11.5(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0)
-      '@mui/utils': 5.15.14(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0)
+      '@mui/system': 5.15.20(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(@emotion/styled@11.11.5(@emotion/react@11.11.4(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0))(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0)
+      '@mui/utils': 5.15.20(react@19.0.0-rc-9d4fba0788-20240530)(types-react@19.0.0-rc.0)
       clsx: 2.1.1
       prop-types: 15.8.1
       react: 19.0.0-rc-9d4fba0788-20240530

clash-verge-rev/package.json

@@ -49,7 +49,8 @@
     "react-router-dom": "^6.23.1",
     "react-transition-group": "^4.4.5",
     "react-virtuoso": "^4.7.11",
-    "swr": "^1.3.0",
+    "sockette": "^2.0.6",
+    "swr": "^2.2.5",
     "tar": "^6.2.1",
     "types-pac": "^1.0.2"
   },

clash-verge-rev/pnpm-lock.yaml

@@ -100,9 +100,12 @@ importers:
       react-virtuoso:
         specifier: ^4.7.11
         version: 4.7.11(react-dom@18.3.1(react@18.3.1))(react@18.3.1)
+      sockette:
+        specifier: ^2.0.6
+        version: 2.0.6
       swr:
-        specifier: ^1.3.0
-        version: 1.3.0(react@18.3.1)
+        specifier: ^2.2.5
+        version: 2.2.5(react@18.3.1)
       tar:
         specifier: ^6.2.1
         version: 6.2.1
@@ -4032,6 +4035,12 @@ packages:
         integrity: sha512-LAOh4z89bGQvl9pFfNF8V146i7o7/CqFPbqzYgP+yYzDIDeS9HaNFtXABamRW+AQzEVODcvE79ljJ+8a9YSdMg==,
       }
 
+  sockette@2.0.6:
+    resolution:
+      {
+        integrity: sha512-W6iG8RGV6Zife3Cj+FhuyHV447E6fqFM2hKmnaQrTvg3OydINV3Msj3WPFbX76blUlUxvQSMMMdrJxce8NqI5Q==,
+      }
+
   source-map-js@1.2.0:
     resolution:
       {
@@ -4110,10 +4119,10 @@ packages:
         integrity: sha512-e4hG1hRwoOdRb37cIMSgzNsxyzKfayW6VOflrwvR+/bzrkyxY/31WkbgnQpgtrNp1SdpJvpUAGTa/ZoiPNDuRQ==,
       }
 
-  swr@1.3.0:
+  swr@2.2.5:
     resolution:
       {
-        integrity: sha512-dkghQrOl2ORX9HYrMDtPa7LTVHJjCTeZoB1dqTbnnEDlSvN8JEKpYIYurDfvbQFUUS8Cg8PceFVZNkW0KNNYPw==,
+        integrity: sha512-QtxqyclFeAsxEUeZIYmsaQ0UjimSq1RZ9Un7I68/0ClKK/U3LoyQunwkQfJZr2fc22DfIXLNDc2wFyTEikCUpg==,
       }
     peerDependencies:
       react: ^16.11.0 || ^17.0.0 || ^18.0.0
@@ -4303,6 +4312,14 @@ packages:
     peerDependencies:
       browserslist: ">= 4.21.0"
 
+  use-sync-external-store@1.2.2:
+    resolution:
+      {
+        integrity: sha512-PElTlVMwpblvbNqQ82d2n6RjStvdSoNe9FG28kNfz3WiXilJm4DdNkEzRhCZuIDwY8U08WVihhGR5iRqAwfDiw==,
+      }
+    peerDependencies:
+      react: ^16.8.0 || ^17.0.0 || ^18.0.0
+
   vfile-message@4.0.2:
     resolution:
       {
@@ -7096,6 +7113,8 @@ snapshots:
       dot-case: 3.0.4
       tslib: 2.6.3
 
+  sockette@2.0.6: {}
+
   source-map-js@1.2.0: {}
 
   source-map-support@0.5.21:
@@ -7130,9 +7149,11 @@ snapshots:
 
   svg-parser@2.0.4: {}
 
-  swr@1.3.0(react@18.3.1):
+  swr@2.2.5(react@18.3.1):
     dependencies:
+      client-only: 0.0.1
       react: 18.3.1
+      use-sync-external-store: 1.2.2(react@18.3.1)
 
   systemjs@6.15.1: {}
 
@@ -7237,6 +7258,10 @@ snapshots:
       escalade: 3.1.2
       picocolors: 1.0.1
 
+  use-sync-external-store@1.2.2(react@18.3.1):
+    dependencies:
+      react: 18.3.1
+
   vfile-message@4.0.2:
     dependencies:
       "@types/unist": 3.0.2

clash-verge-rev/src-tauri/Cargo.lock

@@ -378,7 +378,8 @@ checksum = "1505bd5d3d116872e7271a6d4e16d81d0c8570876c8de68093a09ac269d8aac0"
 [[package]]
 name = "auto-launch"
 version = "0.5.0"
-source = "git+https://github.com/zzzgydi/auto-launch?branch=main#2d94a103ca20652a3baf581ca2c296791c35c09b"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1f012b8cc0c850f34117ec8252a44418f2e34a2cf501de89e29b241ae5f79471"
 dependencies = [
  "dirs 4.0.0",
  "thiserror",

clash-verge-rev/src-tauri/Cargo.toml

@@ -30,13 +30,13 @@ once_cell = "1.19"
 port_scanner = "0.1.5"
 delay_timer = "0.11"
 parking_lot = "0.12"
+auto-launch = "0.5.0"
 percent-encoding = "2.3.1"
 window-shadows = { version = "0.2" }
 tokio = { version = "1", features = ["full"] }
 serde = { version = "1.0", features = ["derive"] }
 reqwest = { version = "0.12", features = ["json", "rustls-tls"] }
 sysproxy = { git="https://github.com/zzzgydi/sysproxy-rs", branch = "main" }
-auto-launch = { git="https://github.com/zzzgydi/auto-launch", branch = "main" }
 tauri = { git="https://github.com/tauri-apps/tauri",branch = "1.x", features = [ "fs-read-file", "fs-exists", "path-all", "protocol-asset", "dialog-open", "notification-all", "icon-png", "icon-ico", "clipboard-all", "global-shortcut-all", "process-all", "shell-all", "system-tray", "updater", "window-all", "devtools"] }
 [target.'cfg(windows)'.dependencies]
 runas = "=1.2.0"

clash-verge-rev/src-tauri/src/feat.rs

@@ -88,16 +88,37 @@ pub fn toggle_system_proxy() {
 pub fn toggle_tun_mode() {
     let enable = Config::verge().data().enable_tun_mode;
     let enable = enable.unwrap_or(false);
-
     tauri::async_runtime::spawn(async move {
-        match patch_verge(IVerge {
-            enable_tun_mode: Some(!enable),
-            ..IVerge::default()
-        })
-        .await
-        {
-            Ok(_) => handle::Handle::refresh_verge(),
-            Err(err) => log::error!(target: "app", "{err}"),
+        if !enable {
+            if let Ok(res) = service::check_service().await {
+                if res.code == 0 {
+                    match patch_verge(IVerge {
+                        enable_tun_mode: Some(!enable),
+                        ..IVerge::default()
+                    })
+                    .await
+                    {
+                        Ok(_) => handle::Handle::refresh_verge(),
+                        Err(err) => log::error!(target: "app", "{err}"),
+                    }
+                    return;
+                }
+            }
+            tauri::api::dialog::message(
+                None::<&tauri::Window>,
+                "Please install and enable service mode",
+                "Service mode is required for Tun mode",
+            );
+        } else {
+            match patch_verge(IVerge {
+                enable_tun_mode: Some(!enable),
+                ..IVerge::default()
+            })
+            .await
+            {
+                Ok(_) => handle::Handle::refresh_verge(),
+                Err(err) => log::error!(target: "app", "{err}"),
+            }
         }
     });
 }
@@ -403,3 +424,19 @@ pub async fn test_delay(url: String) -> Result<u32> {
         }
     }
 }
+
+pub fn check_permission() -> Result<()> {
+    #[cfg(target_os = "windows")]
+    {
+        let hklm = winreg::RegKey::predef(winreg::enums::HKEY_LOCAL_MACHINE);
+
+        if let Ok(reg) = hklm.open_subkey_with_flags(
+            "SOFTWARE\\WOW6432Node\\Microsoft\\Windows\\CurrentVersion\\Run",
+            winreg::enums::KEY_SET_VALUE,
+        ) {
+            reg.delete_value("Clash Verge").unwrap_or_default();
+            return Ok(());
+        }
+    }
+    Err(anyhow::anyhow!("permission denied"))
+}

clash-verge-rev/src-tauri/src/main.rs

@@ -19,6 +19,16 @@ fn main() -> std::io::Result<()> {
         println!("app exists");
         return Ok(());
     }
+    // 权限检测
+    if feat::check_permission().is_ok() {
+        println!("please do not run with admin permission");
+        tauri::api::dialog::blocking::message(
+            None::<&tauri::Window>,
+            "Please do not run with admin permission",
+            "If you want to use Tun mode, please enable service mode instead",
+        );
+        return Ok(());
+    }
 
     #[cfg(target_os = "linux")]
     std::env::set_var("WEBKIT_DISABLE_DMABUF_RENDERER", "1");

clash-verge-rev/src/components/layout/layout-traffic.tsx

@@ -1,4 +1,4 @@
-import { useEffect, useRef, useState } from "react";
+import { useRef } from "react";
 import { Box, Typography } from "@mui/material";
 import {
   ArrowDownward,
@@ -10,8 +10,14 @@ import { useVerge } from "@/hooks/use-verge";
 import { TrafficGraph, type TrafficRef } from "./traffic-graph";
 import { useLogSetup } from "./use-log-setup";
 import { useVisibility } from "@/hooks/use-visibility";
-import { useWebsocket } from "@/hooks/use-websocket";
 import parseTraffic from "@/utils/parse-traffic";
+import useSWRSubscription from "swr/subscription";
+import Sockette from "sockette";
+
+interface MemoryUsage {
+  inuse: number;
+  oslimit?: number;
+}
 
 // setup the traffic
 export const LayoutTraffic = () => {
@@ -22,51 +28,92 @@ export const LayoutTraffic = () => {
   const trafficGraph = verge?.traffic_graph ?? true;
 
   const trafficRef = useRef<TrafficRef>(null);
-  const [traffic, setTraffic] = useState({ up: 0, down: 0 });
-  const [memory, setMemory] = useState({ inuse: 0 });
   const pageVisible = useVisibility();
 
   // setup log ws during layout
   useLogSetup();
 
-  const trafficWs = useWebsocket(
-    (event) => {
-      const data = JSON.parse(event.data) as ITrafficItem;
-      trafficRef.current?.appendData(data);
-      setTraffic(data);
+  const { data: traffic = { up: 0, down: 0 } } = useSWRSubscription<
+    ITrafficItem,
+    any,
+    "getRealtimeTraffic" | null
+  >(
+    clashInfo && pageVisible ? "getRealtimeTraffic" : null,
+    (_key, { next }) => {
+      const { server = "", secret = "" } = clashInfo!;
+
+      let errorCount = 10;
+
+      const s = new Sockette(
+        `ws://${server}/traffic?token=${encodeURIComponent(secret)}`,
+        {
+          onmessage(event) {
+            errorCount = 0; // reset counter
+            const data = JSON.parse(event.data) as ITrafficItem;
+            trafficRef.current?.appendData(data);
+            next(null, data);
+          },
+          onerror(event) {
+            errorCount -= 1;
+
+            if (errorCount <= 0) {
+              this.close();
+              next(event, { up: 0, down: 0 });
+            }
+          },
+        }
+      );
+
+      return () => {
+        s.close();
+      };
     },
-    { onError: () => setTraffic({ up: 0, down: 0 }), errorCount: 10 }
+    {
+      fallbackData: { up: 0, down: 0 },
+      keepPreviousData: true,
+    }
   );
 
-  useEffect(() => {
-    if (!clashInfo || !pageVisible) return;
-
-    const { server = "", secret = "" } = clashInfo;
-    trafficWs.connect(
-      `ws://${server}/traffic?token=${encodeURIComponent(secret)}`
-    );
-    return () => trafficWs.disconnect();
-  }, [clashInfo, pageVisible]);
-
   /* --------- meta memory information --------- */
   const isMetaCore = verge?.clash_core?.includes("clash-meta");
   const displayMemory = isMetaCore && (verge?.enable_memory_usage ?? true);
 
-  const memoryWs = useWebsocket(
-    (event) => {
-      setMemory(JSON.parse(event.data));
-    },
-    { onError: () => setMemory({ inuse: 0 }), errorCount: 10 }
-  );
+  const { data: memory = { inuse: 0 } } = useSWRSubscription<
+    MemoryUsage,
+    any,
+    "getRealtimeMemory" | null
+  >(
+    clashInfo && pageVisible && displayMemory ? "getRealtimeMemory" : null,
+    (_key, { next }) => {
+      const { server = "", secret = "" } = clashInfo!;
+      const ws = new WebSocket(
+        `ws://${server}/memory?token=${encodeURIComponent(secret)}`
+      );
 
-  useEffect(() => {
-    if (!clashInfo || !pageVisible || !displayMemory) return;
-    const { server = "", secret = "" } = clashInfo;
-    memoryWs.connect(
-      `ws://${server}/memory?token=${encodeURIComponent(secret)}`
-    );
-    return () => memoryWs.disconnect();
-  }, [clashInfo, pageVisible, displayMemory]);
+      let errorCount = 10;
+
+      ws.addEventListener("message", (event) => {
+        errorCount = 0; // reset counter
+        next(null, JSON.parse(event.data));
+      });
+      ws.addEventListener("error", (event) => {
+        errorCount -= 1;
+
+        if (errorCount <= 0) {
+          ws.close();
+          next(event, { inuse: 0 });
+        }
+      });
+
+      return () => {
+        ws.close();
+      };
+    },
+    {
+      fallbackData: { inuse: 0 },
+      keepPreviousData: true,
+    }
+  );
 
   const [up, upUnit] = parseTraffic(traffic.up);
   const [down, downUnit] = parseTraffic(traffic.down);

clash-verge-rev/src/components/setting/mods/stack-mode-switch.tsx

@@ -1,12 +1,4 @@
-import { useTranslation } from "react-i18next";
-import { Button, ButtonGroup, Tooltip } from "@mui/material";
-import { checkService } from "@/services/cmds";
-import { useVerge } from "@/hooks/use-verge";
-import getSystem from "@/utils/get-system";
-import useSWR from "swr";
-import { useEffect } from "react";
-
-const isWIN = getSystem() === "windows";
+import { Button, ButtonGroup } from "@mui/material";
 
 interface Props {
   value?: string;
@@ -15,62 +7,31 @@ interface Props {
 
 export const StackModeSwitch = (props: Props) => {
   const { value, onChange } = props;
-  const { verge } = useVerge();
-  const { enable_service_mode } = verge ?? {};
-  // service mode
-  const { data: serviceStatus, mutate: mutateCheck } = useSWR(
-    isWIN ? "checkService" : null,
-    checkService,
-    {
-      revalidateIfStale: false,
-      shouldRetryOnError: false,
-    }
-  );
-
-  const { t } = useTranslation();
-
-  useEffect(() => {
-    mutateCheck();
-  }, []);
 
   return (
-    <Tooltip
-      title={
-        isWIN && (serviceStatus !== "active" || !enable_service_mode)
-          ? t("System and Mixed Can Only be Used in Service Mode")
-          : ""
-      }
-    >
-      <ButtonGroup size="small" sx={{ my: "4px" }}>
-        <Button
-          variant={value?.toLowerCase() === "system" ? "contained" : "outlined"}
-          onClick={() => onChange?.("system")}
-          disabled={
-            isWIN && (serviceStatus !== "active" || !enable_service_mode)
-          }
-          sx={{ textTransform: "capitalize" }}
-        >
-          System
-        </Button>
-        <Button
-          variant={value?.toLowerCase() === "gvisor" ? "contained" : "outlined"}
-          onClick={() => onChange?.("gvisor")}
-          sx={{ textTransform: "capitalize" }}
-        >
-          gVisor
-        </Button>
+    <ButtonGroup size="small" sx={{ my: "4px" }}>
+      <Button
+        variant={value?.toLowerCase() === "system" ? "contained" : "outlined"}
+        onClick={() => onChange?.("system")}
+        sx={{ textTransform: "capitalize" }}
+      >
+        System
+      </Button>
+      <Button
+        variant={value?.toLowerCase() === "gvisor" ? "contained" : "outlined"}
+        onClick={() => onChange?.("gvisor")}
+        sx={{ textTransform: "capitalize" }}
+      >
+        gVisor
+      </Button>
 
-        <Button
-          variant={value?.toLowerCase() === "mixed" ? "contained" : "outlined"}
-          onClick={() => onChange?.("mixed")}
-          disabled={
-            isWIN && (serviceStatus !== "active" || !enable_service_mode)
-          }
-          sx={{ textTransform: "capitalize" }}
-        >
-          Mixed
-        </Button>
-      </ButtonGroup>
-    </Tooltip>
+      <Button
+        variant={value?.toLowerCase() === "mixed" ? "contained" : "outlined"}
+        onClick={() => onChange?.("mixed")}
+        sx={{ textTransform: "capitalize" }}
+      >
+        Mixed
+      </Button>
+    </ButtonGroup>
   );
 };

clash-verge-rev/src/components/setting/mods/sysproxy-viewer.tsx

@@ -29,10 +29,10 @@ export const SysproxyViewer = forwardRef<DialogRef>((props, ref) => {
   let validReg;
   if (getSystem() === "windows") {
     validReg =
-      /^(\*?\w+(\.\w+)*|\d{1,3}(\.\d{1,3}){0,2}\.\*|\d{1,3}(\.\d{1,3}){3})(;(\*?\w+(\.\w+)*|\d{1,3}(\.\d{1,3}){0,2}\.\*|\d{1,3}(\.\d{1,3}){3}))*$/;
+      /^((\*\.)?([a-zA-Z0-9-]+\.)+[a-zA-Z]{2,}|(\d{1,3}\.){1,3}\d{1,3}|\d{1,3}\.\d{1,3}\.\d{1,3}\.\*|\d{1,3}\.\d{1,3}\.\*|\d{1,3}\.\*|([a-fA-F0-9:]+:+)+[a-fA-F0-9]+|localhost|<local>)(;((\*\.)?([a-zA-Z0-9-]+\.)+[a-zA-Z]{2,}|(\d{1,3}\.){1,3}\d{1,3}|\d{1,3}\.\d{1,3}\.\d{1,3}\.\*|\d{1,3}\.\d{1,3}\.\*|\d{1,3}\.\*|([a-fA-F0-9:]+:+)+[a-fA-F0-9]+|localhost|<local>))*;?$/;
   } else {
     validReg =
-      /^((\*\.)?([a-zA-Z0-9-]+\.)+[a-zA-Z]{2,}|(\d{1,3}\.){3}\d{1,3}(\/\d{1,2})?|([a-fA-F0-9:]+:+)+[a-fA-F0-9]+(\/\d{1,3})?)(,((\*\.)?([a-zA-Z0-9-]+\.)+[a-zA-Z]{2,}|(\d{1,3}\.){3}\d{1,3}(\/\d{1,2})?|([a-fA-F0-9:]+:+)+[a-fA-F0-9]+(\/\d{1,3})?))*$/;
+      /^((\*\.)?([a-zA-Z0-9-]+\.)+[a-zA-Z]{2,}|(\d{1,3}\.){1,3}\d{1,3}(\/\d{1,2}|\/3[0-2])?|\d{1,3}\.\d{1,3}\.\d{1,3}\.\*(\/\d{1,2}|\/3[0-2])?|\d{1,3}\.\d{1,3}\.\*(\/\d{1,2}|\/3[0-2])?|\d{1,3}\.\*(\/\d{1,2}|\/3[0-2])?|([a-fA-F0-9:]+:+)+[a-fA-F0-9]+(\/\d{1,3})?|localhost|<local>)(;((\*\.)?([a-zA-Z0-9-]+\.)+[a-zA-Z]{2,}|(\d{1,3}\.){1,3}\d{1,3}(\/\d{1,2}|\/3[0-2])?|\d{1,3}\.\d{1,3}\.\d{1,3}\.\*(\/\d{1,2}|\/3[0-2])?|\d{1,3}\.\d{1,3}\.\*(\/\d{1,2}|\/3[0-2])?|\d{1,3}\.\*(\/\d{1,2}|\/3[0-2])?|([a-fA-F0-9:]+:+)+[a-fA-F0-9]+(\/\d{1,3})?|localhost|<local>))*;?$/;
   }
 
   const [open, setOpen] = useState(false);

clash-verge-rev/src/components/setting/mods/web-ui-viewer.tsx

@@ -23,7 +23,7 @@ export const WebUIViewer = forwardRef<DialogRef>((props, ref) => {
   }));
 
   const webUIList = verge?.web_ui_list || [
-    "https://d.metacubex.one/#?hostname=%host&port=%port&secret=%secret",
+    "https://metacubex.github.io/metacubexd/#/setup?http=true&hostname=%host&port=%port&secret=%secret",
     "https://yacd.metacubex.one/?host=%host&port=%port&secret=%secret",
   ];
 

clash-verge-rev/src/components/setting/setting-system.tsx

@@ -22,11 +22,15 @@ const SettingSystem = ({ onError }: Props) => {
   const { verge, mutateVerge, patchVerge } = useVerge();
 
   // service mode
-  const { data: serviceStatus } = useSWR("checkService", checkService, {
-    revalidateIfStale: false,
-    shouldRetryOnError: false,
-    focusThrottleInterval: 36e5, // 1 hour
-  });
+  const { data: serviceStatus, mutate: mutateCheck } = useSWR(
+    "checkService",
+    checkService,
+    {
+      revalidateIfStale: false,
+      shouldRetryOnError: false,
+      focusThrottleInterval: 36e5, // 1 hour
+    }
+  );
 
   const serviceRef = useRef<DialogRef>(null);
   const sysproxyRef = useRef<DialogRef>(null);
@@ -84,7 +88,7 @@ const SettingSystem = ({ onError }: Props) => {
           onChange={(e) => onChangeData({ enable_tun_mode: e })}
           onGuard={(e) => patchVerge({ enable_tun_mode: e })}
         >
-          <Switch edge="end" />
+          <Switch disabled={serviceStatus !== "active"} edge="end" />
         </GuardState>
       </SettingItem>
 
@@ -109,7 +113,10 @@ const SettingSystem = ({ onError }: Props) => {
           onCatch={onError}
           onFormat={onSwitchFormat}
           onChange={(e) => onChangeData({ enable_service_mode: e })}
-          onGuard={(e) => patchVerge({ enable_service_mode: e })}
+          onGuard={(e) => {
+            setTimeout(() => mutateCheck(), 1000);
+            return patchVerge({ enable_service_mode: e });
+          }}
         >
           <Switch
             edge="end"

lede/package/lean/autocore/Makefile

@@ -47,6 +47,7 @@ define Package/autocore-arm/install
 	$(INSTALL_DIR) $(1)/sbin
 	$(INSTALL_BIN) ./files/arm/sbin/cpuinfo $(1)/sbin/cpuinfo
 	$(INSTALL_BIN) ./files/arm/sbin/ethinfo $(1)/sbin/ethinfo
+	$(INSTALL_BIN) ./files/arm/sbin/usage $(1)/sbin/usage
 endef
 
 define Package/autocore-x86/install

lede/package/lean/autocore/files/arm/index.htm

@@ -15,7 +15,7 @@
 	local has_dhcp = fs.access("/etc/config/dhcp")
 	local has_wifi = ((fs.stat("/etc/config/wireless", "size") or 0) > 0)
 	local has_switch = false
-	
+
 	uci:foreach("network", "switch",
 			function(s)
 				has_switch = true
@@ -32,7 +32,7 @@
 		buffered = 0,
 		shared = 0
 	}
-	
+
 	local mem_cached = luci.sys.exec("sed -e '/^Cached: /!d; s#Cached: *##; s# kB##g' /proc/meminfo")
 
 	local swapinfo = sysinfo.swap or {
@@ -55,15 +55,9 @@
 		):match("%d+")) or 4096
 
 		local user_info = luci.sys.exec("cat /proc/net/arp | grep 'br-lan' | grep '0x2' | wc -l")
-		
-		if fs.access("/sys/kernel/debug/qca-nss-drv/stats/cpu_load_ubi") then
-				nss_usage = "  NSS: "..luci.sys.exec("grep '%' /sys/kernel/debug/qca-nss-drv/stats/cpu_load_ubi | awk -F ' ' '{print $2}'") or ""
-		else
-				nss_usage = ""
-		end
 
-		local cpu_usage = "CPU: "..luci.sys.exec("top -n1 | awk '/^CPU/ { printf(\"%d%%\", 100 - $8) }'")..nss_usage
-		local cpu_info = luci.sys.exec("/sbin/cpuinfo") or "ARM Processor x 0 (233MHz, 2.3°C)"
+		local cpu_usage = luci.sys.exec("/sbin/usage") or "6%"
+		local cpu_info = luci.sys.exec("/sbin/cpuinfo") or "?"
 		local eth_info = luci.sys.exec("ethinfo")
 
 		local rv = {
@@ -168,7 +162,7 @@
 			if (ht)  s += ', MCS %s'.format(mcs);
 			if (sgi) s += ', <%:Short GI%>';
 		}
-		
+
 		if (he) {
 			s += ', HE-MCS %d'.format(mcs);
 			if (nss) s += ', HE-NSS %d'.format(nss);
@@ -271,7 +265,7 @@
 					'<strong><%:Type%>: </strong>%s%s<br />',
 						ifc6.proto, (ifc6.ip6prefix) ? '-pd' : ''
 				);
-				
+
 				if (!ifc6.ip6prefix)
 				{
 					s += String.format(
@@ -658,7 +652,7 @@
 			<% end %>
 
 			var e;
-			
+
 			if (e = document.getElementById('ethinfo'))			{
 				var ports = eval('(' + info.ethinfo + ')');
 				var tmp = "";
@@ -678,10 +672,10 @@
 
 			if (e = document.getElementById('uptime'))
 				e.innerHTML = String.format('%t', info.uptime);
-				
+
 			if (e = document.getElementById('userinfo'))
 				e.innerHTML = info.userinfo;
-				
+
 			if (e = document.getElementById('cpuusage'))
 				e.innerHTML = info.cpuusage;
 

lede/package/lean/autocore/files/arm/sbin/usage

@@ -0,0 +1,14 @@
+#!/bin/sh
+
+NSS_PATH="/sys/kernel/debug/qca-nss-drv/stats"
+
+cpu_usage="$(top -n1 | awk '/^CPU/ {printf("%d%", 100 - $8)}')"
+
+[ ! -d "$NSS_PATH" ] || \
+npu_usage="$(grep '%' "$NSS_PATH"/cpu_load_ubi | awk -F ' ' '{print $2}')"
+
+if [ -d "$NSS_PATH" ]; then
+	echo -n "CPU: ${cpu_usage}%, NPU: ${npu_usage}"
+else
+	echo -n "CPU: ${cpu_usage}%"
+fi

lede/package/lean/default-settings/Makefile

@@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk
 
 PKG_NAME:=default-settings
 PKG_VERSION:=3
-PKG_RELEASE:=13
+PKG_RELEASE:=12
 PKG_LICENSE:=GPLv3
 PKG_LICENSE_FILES:=LICENSE
 

lede/package/lean/default-settings/files/zzz-default-settings

@@ -51,7 +51,7 @@ sed -i '/option disabled/d' /etc/config/wireless
 sed -i '/set wireless.radio${devidx}.disabled/d' /lib/wifi/mac80211.sh
 
 sed -i '/DISTRIB_REVISION/d' /etc/openwrt_release
-echo "DISTRIB_REVISION='R24.6.6'" >> /etc/openwrt_release
+echo "DISTRIB_REVISION='R24.5.1'" >> /etc/openwrt_release
 sed -i '/DISTRIB_DESCRIPTION/d' /etc/openwrt_release
 echo "DISTRIB_DESCRIPTION='OpenWrt '" >> /etc/openwrt_release
 

lede/package/qca/nss-firmware/Makefile

@@ -11,7 +11,7 @@ PKG_NAME:=nss-firmware
 PKG_SOURCE_DATE:=2022-07-14
 PKG_SOURCE_VERSION:=ade6bff594377c9d9c79b45e39bf104303d919bc
 PKG_MIRROR_HASH:=99ca44dd0733cff569308550c6c74febb0e7a03093b14df092d0f53362189647
-PKG_RELEASE:=$(AUTORELEASE)
+PKG_RELEASE:=1
 
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL:=https://github.com/quic/qca-sdk-nss-fw.git
@@ -31,7 +31,7 @@ define Package/nss-firmware-default
   SECTION:=firmware
   CATEGORY:=Firmware
   URL:=$(PKG_SOURCE_URL)
-  DEPENDS:=@(TARGET_ipq807x||TARGET_ipq60xx||TARGET_qualcommax)
+  DEPENDS:=@TARGET_qualcommax
 endef
 
 define Package/nss-firmware-ipq6018

lede/package/qca/qca-mcs/Makefile

@@ -3,9 +3,9 @@ include $(TOPDIR)/rules.mk
 PKG_NAME:=qca-mcs
 PKG_RELEASE:=1
 
-PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-mcs.git
-PKG_SOURCE_DATE:=2023-04-21
 PKG_SOURCE_PROTO:=git
+PKG_SOURCE_DATE:=2023-04-21
+PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-mcs.git
 PKG_SOURCE_VERSION:=8797823e392ac3d9098c090964afd46805a0eb2b
 PKG_MIRROR_HASH:=f0fa76af4545842ebf8b4f0743e1079e190dfa5f3f0d464c063063521d3d30df
 

lede/package/qca/qca-nss-cfi/Makefile

@@ -3,9 +3,9 @@ include $(TOPDIR)/rules.mk
 PKG_NAME:=qca-nss-cfi
 PKG_RELEASE:=1
 
-PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-cfi.git
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_DATE:=2022-12-15
+PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-cfi.git
 PKG_SOURCE_VERSION:=5cd07ce299ee3ce62dbe4f6783ad36361e57583b
 PKG_MIRROR_HASH:=e449eee24fccc09b1cf0f1367bb54cedadcc46a30423934744e78272443197e7
 
@@ -15,11 +15,9 @@ include $(INCLUDE_DIR)/kernel.mk
 include $(INCLUDE_DIR)/package.mk
 
 ifneq (, $(findstring $(CONFIG_TARGET_SUBTARGET), "ipq807x" "ipq60xx"))
-#4.4/5.4 + ipq807x/ipq60xx/ipq50xx
   CFI_OCF_DIR:=ocf/v2.0
   CFI_CRYPTOAPI_DIR:=cryptoapi/v2.0
 else
-#4.4 Kernel + ipq806x
   CFI_CRYPTOAPI_DIR:=cryptoapi/v1.1
   CFI_OCF_DIR:=ocf/v1.0
   CFI_IPSEC_DIR:=ipsec/v1.0
@@ -56,7 +54,6 @@ ifneq (, $(findstring $(CONFIG_TARGET_SUBTARGET), "ipq807x"))
 EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-clients
 endif
 
-# Build individual packages if selected
 ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-cfi-cryptoapi),)
 MAKE_OPTS+= \
 	cryptoapi=y \
@@ -70,8 +67,7 @@ endif
 
 define Build/Compile
 	+$(MAKE) -C "$(LINUX_DIR)" $(strip $(MAKE_OPTS)) \
-		CROSS_COMPILE="$(TARGET_CROSS)" \
-		ARCH="$(LINUX_KARCH)" \
+		$(KERNEL_MAKE_FLAGS) \
 		M="$(PKG_BUILD_DIR)" \
 		EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \
 		CC="$(TARGET_CC)" \
@@ -79,7 +75,6 @@ define Build/Compile
 		CFI_OCF_DIR=$(CFI_OCF_DIR) \
 		CFI_IPSEC_DIR=$(CFI_IPSEC_DIR) \
 		SoC=$(SOC) \
-		$(KERNEL_MAKE_FLAGS) \
 		$(PKG_JOBS) \
 		modules
 endef

lede/package/qca/qca-nss-clients/Makefile

@@ -1,11 +1,11 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=qca-nss-clients
-PKG_RELEASE:=$(AUTORELEASE)
+PKG_RELEASE:=1
 
-PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-clients.git
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_DATE:=2023-10-04
+PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-clients.git
 PKG_SOURCE_VERSION:=f058ae199b42f30be9925b2ed1ce53afb128200c
 PKG_MIRROR_HASH:=90401b577a7750d3b7eadb423700aab7e1da1af392637598e08f6007f23a92e1
 
@@ -22,12 +22,9 @@ else ifeq ($(CONFIG_TARGET_SUBTARGET), "ipq60xx")
   subtarget:=$(CONFIG_TARGET_SUBTARGET)
 endif
 
-ifneq (, $(findstring $(subtarget), "ipq807x" "ipq807x_64" "ipq60xx" "ipq60xx_64"))
-# DTLS Manager v2.0 for Hawkeye/Cypress
+ifneq (, $(findstring $(subtarget), "ipq807x" "ipq60xx"))
   DTLSMGR_DIR:=v2.0
-# IPsec Manager v2.0 for Hawkeye/Cypress
   IPSECMGR_DIR:=v2.0
-# KLIPS plugin
   IPSECMGR_KLIPS:= $(PKG_BUILD_DIR)/ipsecmgr/$(IPSECMGR_DIR)/plugins/klips/qca-nss-ipsec-klips.ko
 endif
 
@@ -36,10 +33,11 @@ define KernelPackage/qca-nss-drv-gre
   CATEGORY:=Kernel modules
   SUBMENU:=Network Devices
   TITLE:=Kernel driver for NSS (connection manager) - GRE
-  DEPENDS:=@(TARGET_ipq_ipq806x||TARGET_ipq806x||TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_ipq807x_64||TARGET_qualcommax||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64||TARGET_ipq_ipq50xx||TARGET_ipq_ipq50xx_64||TARGET_ipq50xx) \
-		   +@NSS_DRV_GRE_ENABLE +kmod-gre6 \
-  		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
-  FILES:=$(PKG_BUILD_DIR)/gre/qca-nss-gre.ko $(PKG_BUILD_DIR)/gre/test/qca-nss-gre-test.ko
+  DEPENDS:=@TARGET_qualcommax +@NSS_DRV_GRE_ENABLE +kmod-gre6 \
+  	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
+  FILES:= \
+	$(PKG_BUILD_DIR)/gre/qca-nss-gre.ko \
+	$(PKG_BUILD_DIR)/gre/test/qca-nss-gre-test.ko
   AUTOLOAD:=$(call AutoLoad,51,qca-nss-gre)
 endef
 
@@ -53,7 +51,7 @@ define KernelPackage/qca-nss-drv-l2tpv2
   SUBMENU:=Network Devices
   TITLE:=Kernel driver for NSS (connection manager) - l2tp
   DEPENDS:=@NSS_DRV_L2TP_ENABLE +kmod-ppp +kmod-l2tp \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
   FILES:=$(PKG_BUILD_DIR)/l2tp/l2tpv2/qca-nss-l2tpv2.ko
   KCONFIG:=CONFIG_L2TP=y
   AUTOLOAD:=$(call AutoLoad,51,qca-nss-l2tpv2)
@@ -69,7 +67,7 @@ define KernelPackage/qca-nss-drv-pptp
   SUBMENU:=Network Devices
   TITLE:=Kernel driver for NSS (connection manager) - PPTP
   DEPENDS:=+@NSS_DRV_PPTP_ENABLE +kmod-pptp \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
   FILES:=$(PKG_BUILD_DIR)/pptp/qca-nss-pptp.ko
   AUTOLOAD:=$(call AutoLoad,51,qca-nss-pptp)
 endef
@@ -84,8 +82,8 @@ define KernelPackage/qca-nss-drv-pppoe
   SUBMENU:=Network Devices
   TITLE:=Kernel driver for NSS (connection manager) - PPPoE
   DEPENDS:=+@NSS_DRV_PPPOE_ENABLE +kmod-ppp +kmod-pppoe \
-		   +PACKAGE_kmod-bonding:kmod-bonding \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
+	   +PACKAGE_kmod-bonding:kmod-bonding \
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
   FILES:=$(PKG_BUILD_DIR)/pppoe/qca-nss-pppoe.ko
   AUTOLOAD:=$(call AutoLoad,51,qca-nss-pppoe)
 endef
@@ -100,8 +98,8 @@ define KernelPackage/qca-nss-drv-map-t
   SUBMENU:=Network Devices
   TITLE:=Kernel driver for NSS (connection manager) - MAP-T
   DEPENDS:=+@NSS_DRV_MAPT_ENABLE \
-		   +PACKAGE_kmod-nat46:kmod-nat46 \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
+	   +PACKAGE_kmod-nat46:kmod-nat46 \
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
   FILES:=$(PKG_BUILD_DIR)/map/map-t/qca-nss-map-t.ko
   AUTOLOAD:=$(call AutoLoad,51,qca-nss-map-t)
 endef
@@ -116,7 +114,7 @@ define KernelPackage/qca-nss-drv-tun6rd
   SUBMENU:=Network Devices
   TITLE:=Kernel driver for NSS (connection manager) - tun6rd
   DEPENDS:=+@NSS_DRV_TUN6RD_ENABLE +kmod-sit +6rd \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
   FILES:=$(PKG_BUILD_DIR)/qca-nss-tun6rd.ko
   AUTOLOAD:=$(call AutoLoad,60,qca-nss-tun6rd)
 endef
@@ -131,7 +129,7 @@ define KernelPackage/qca-nss-drv-tunipip6
   SUBMENU:=Network Devices
   TITLE:=Kernel driver for NSS (connection manager) - DS-lite and ipip6 Tunnel
   DEPENDS:=+@NSS_DRV_TUNIPIP6_ENABLE +kmod-iptunnel6 +kmod-ip6-tunnel \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
   FILES:=$(PKG_BUILD_DIR)/tunipip6/qca-nss-tunipip6.ko
   AUTOLOAD:=$(call AutoLoad,60,qca-nss-tunipip6)
 endef
@@ -146,17 +144,11 @@ define KernelPackage/qca-nss-drv-bridge-mgr
   CATEGORY:=Kernel modules
   SUBMENU:=Network Devices
   TITLE:=Kernel driver for NSS bridge manager
-  DEPENDS:=@(TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_qualcommax||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64||TARGET_ipq60xx) \
-		   +TARGET_ipq_ipq807x:kmod-qca-nss-drv-vlan-mgr \
-		   +TARGET_ipq_ipq807x_64:kmod-qca-nss-drv-vlan-mgr \
-		   +TARGET_ipq807x:kmod-qca-nss-drv-vlan-mgr \
-		   +TARGET_qualcommax:kmod-qca-nss-drv-vlan-mgr \
-		   +TARGET_ipq60xx:kmod-qca-nss-drv-vlan-mgr \
-		   +TARGET_ipq_ipq60xx:kmod-qca-nss-drv-vlan-mgr \
-		   +TARGET_ipq_ipq60xx_64:kmod-qca-nss-drv-vlan-mgr \
-		   +@NSS_DRV_BRIDGE_ENABLE \
-		   +PACKAGE_kmod-bonding:kmod-bonding \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
+  DEPENDS:=@TARGET_qualcommax \
+	   +kmod-qca-nss-drv-vlan-mgr \
+	   +@NSS_DRV_BRIDGE_ENABLE \
+	   +PACKAGE_kmod-bonding:kmod-bonding \
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
 ifneq ($(CONFIG_PACKAGE_kmod-qca-ovsmgr),)
   DEPENDS+=kmod-qca-ovsmgr
 endif
@@ -173,8 +165,8 @@ define KernelPackage/qca-nss-drv-clmapmgr
   CATEGORY:=Kernel modules
   SUBMENU:=Network Devices
   DEPENDS:=+@NSS_DRV_CLMAP_ENABLE \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv \
-		   +kmod-qca-nss-drv-eogremgr
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv \
+	   +kmod-qca-nss-drv-eogremgr
   TITLE:=NSS clmap Manager for QCA NSS driver
   FILES:=$(PKG_BUILD_DIR)/clmapmgr/qca-nss-clmapmgr.ko
 endef
@@ -189,8 +181,8 @@ define KernelPackage/qca-nss-drv-dtlsmgr
   SUBMENU:=Network Devices
   TITLE:=Kernel driver for NSS (connection manager) - dtlsmgr
   DEPENDS:=+@NSS_DRV_DTLS_ENABLE \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv \
-		   +PACKAGE_kmod-qca-nss-cfi-cryptoapi:kmod-qca-nss-cfi-cryptoapi
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv \
+	   +PACKAGE_kmod-qca-nss-cfi-cryptoapi:kmod-qca-nss-cfi-cryptoapi
   FILES:=$(PKG_BUILD_DIR)/dtls/$(DTLSMGR_DIR)/qca-nss-dtlsmgr.ko
 endef
 
@@ -203,10 +195,9 @@ define KernelPackage/qca-nss-drv-tlsmgr
   CATEGORY:=Kernel modules
   SUBMENU:=Network Devices
   TITLE:=Kernel driver for NSS (connection manager) - tlsmgr
-  DEPENDS:=@(TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_ipq807x_64||TARGET_qualcommax||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64||TARGET_ipq60xx) \
-		   +@NSS_DRV_TLS_ENABLE \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv \
-		   +PACKAGE_kmod-qca-nss-cfi-cryptoapi:kmod-qca-nss-cfi-cryptoapi
+  DEPENDS:=@TARGET_qualcommax +@NSS_DRV_TLS_ENABLE \
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv \
+	   +PACKAGE_kmod-qca-nss-cfi-cryptoapi:kmod-qca-nss-cfi-cryptoapi
   FILES:=$(PKG_BUILD_DIR)/tls/qca-nss-tlsmgr.ko
 endef
 
@@ -219,11 +210,11 @@ define KernelPackage/qca-nss-drv-ipsecmgr
   CATEGORY:=Kernel modules
   SUBMENU:=Network Devices
   TITLE:=Kernel driver for NSS (ipsec manager) - ipsecmgr
-  DEPENDS:=@(TARGET_ipq806x||TARGET_ipq807x||TARGET_qualcommax) \
-		   +@NSS_DRV_TSTAMP_ENABLE \
-		   +@NSS_DRV_IPSEC_ENABLE \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv \
-		   +PACKAGE_kmod-qca-nss-cfi-cryptoapi:kmod-qca-nss-cfi-cryptoapi
+  DEPENDS:=@TARGET_qualcommax \
+	   +@NSS_DRV_IPSEC_ENABLE \
+	   +@NSS_DRV_TSTAMP_ENABLE \
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv \
+	   +PACKAGE_kmod-qca-nss-cfi-cryptoapi:kmod-qca-nss-cfi-cryptoapi
 ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-l2tpv2),)
   DEPENDS+=+kmod-qca-nss-drv-l2tpv2
 endif
@@ -240,9 +231,9 @@ define KernelPackage/qca-nss-drv-ovpn-mgr
   CATEGORY:=Kernel modules
   SUBMENU:=Network Devices
   TITLE:=Kernel driver for NSS OpenVPN manager
-  DEPENDS:=@(TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_qualcommax||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64||TARGET_ipq60xx) \
-		   +@NSS_DRV_OVPN_ENABLE +kmod-qca-nss-drv +kmod-tun +kmod-ipt-conntrack \
-		   +PACKAGE_kmod-qca-nss-cfi-cryptoapi:kmod-qca-nss-cfi-cryptoapi
+  DEPENDS:=@TARGET_qualcommax +@NSS_DRV_OVPN_ENABLE \
+	   +kmod-qca-nss-drv +kmod-tun +kmod-ipt-conntrack \
+	   +PACKAGE_kmod-qca-nss-cfi-cryptoapi:kmod-qca-nss-cfi-cryptoapi
   FILES:=$(PKG_BUILD_DIR)/openvpn/src/qca-nss-ovpn-mgr.ko
 endef
 
@@ -255,9 +246,9 @@ define KernelPackage/qca-nss-drv-ovpn-link
   CATEGORY:=Kernel modules
   SUBMENU:=Network Devices
   TITLE:=Kernel driver for interfacing NSS OpenVPN manager with ECM
-  DEPENDS:=@(TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_qualcommax||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64||TARGET_ipq60xx) \
-  		   +kmod-qca-nss-drv-ovpn-mgr \
-  		   +@PACKAGE_kmod-qca-nss-ecm
+  DEPENDS:=@TARGET_qualcommax \
+  	   +kmod-qca-nss-drv-ovpn-mgr \
+  	   +@PACKAGE_kmod-qca-nss-ecm
   FILES:=$(PKG_BUILD_DIR)/openvpn/plugins/qca-nss-ovpn-link.ko
 endef
 
@@ -270,7 +261,7 @@ define KernelPackage/qca-nss-drv-pvxlanmgr
   CATEGORY:=Kernel modules
   SUBMENU:=Network Devices
   DEPENDS:=+@NSS_DRV_PVXLAN_ENABLE \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
   TITLE:=NSS PVXLAN Manager for QCA NSS driver
   FILES:=$(PKG_BUILD_DIR)/pvxlanmgr/qca-nss-pvxlanmgr.ko
 endef
@@ -284,8 +275,8 @@ define KernelPackage/qca-nss-drv-eogremgr
   CATEGORY:=Kernel modules
   SUBMENU:=Network Devices
   DEPENDS:=+@NSS_DRV_GRE_ENABLE \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv \
-		   +kmod-qca-nss-drv-gre
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv \
+	   +kmod-qca-nss-drv-gre
   TITLE:=NSS EOGRE Manager for QCA NSS driver
   FILES:=$(PKG_BUILD_DIR)/eogremgr/qca-nss-eogremgr.ko
 endef
@@ -299,8 +290,8 @@ define KernelPackage/qca-nss-drv-clmapmgr
   CATEGORY:=Kernel modules
   SUBMENU:=Network Devices
   DEPENDS:=+@NSS_DRV_CLMAP_ENABLE \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv \
-		   +kmod-qca-nss-drv-eogremgr
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv \
+	   +kmod-qca-nss-drv-eogremgr
   TITLE:=NSS clmap Manager for QCA NSS driver
   FILES:=$(PKG_BUILD_DIR)/clmapmgr/qca-nss-clmapmgr.ko
 endef
@@ -315,15 +306,9 @@ define KernelPackage/qca-nss-drv-lag-mgr
   SUBMENU:=Network Devices
   TITLE:=Kernel driver for NSS LAG manager
   DEPENDS:=+@NSS_DRV_LAG_ENABLE \
-	   	   +TARGET_ipq_ipq807x:kmod-qca-nss-drv-vlan-mgr \
-	   	   +TARGET_ipq_ipq807x_64:kmod-qca-nss-drv-vlan-mgr \
-		   +TARGET_ipq807x:kmod-qca-nss-drv-vlan-mgr \
-		   +TARGET_qualcommax:kmod-qca-nss-drv-vlan-mgr \
-		   +TARGET_ipq_ipq60xx:kmod-qca-nss-drv-vlan-mgr \
-		   +TARGET_ipq_ipq60xx_64:kmod-qca-nss-drv-vlan-mgr \
-		   +TARGET_ipq60xx:kmod-qca-nss-drv-vlan-mgr \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv \
-		   +PACKAGE_kmod-bonding:kmod-bonding
+	   +kmod-qca-nss-drv-vlan-mgr \
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv \
+	   +PACKAGE_kmod-bonding:kmod-bonding
   FILES:=$(PKG_BUILD_DIR)/lag/qca-nss-lag-mgr.ko
   AUTOLOAD:=$(call AutoLoad,51,qca-nss-lag-mgr)
 endef
@@ -337,7 +322,7 @@ define KernelPackage/qca-nss-drv-vxlanmgr
   CATEGORY:=Kernel modules
   SUBMENU:=Network Devices
   DEPENDS:=+@NSS_DRV_VXLAN_ENABLE +@NSS_DRV_PVXLAN_ENABLE +kmod-vxlan \
-  		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
+  	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
   TITLE:=NSS VxLAN Manager for QCA NSS driver
   FILES:=$(PKG_BUILD_DIR)/vxlanmgr/qca-nss-vxlanmgr.ko
   AUTOLOAD:=$(call AutoLoad,51,qca-nss-vxlanmgr)
@@ -352,10 +337,10 @@ define KernelPackage/qca-nss-drv-vlan-mgr
   CATEGORY:=Kernel modules
   SUBMENU:=Network Devices
   TITLE:=Kernel driver for NSS vlan manager
-  DEPENDS:=@(TARGET_ipq_ipq807x||TARGET_ipq_ipq806x||TARGET_ipq807x||TARGET_qualcommax||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64||TARGET_ipq60xx) \
-		   +@NSS_DRV_VLAN_ENABLE \
-  		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv \
-		   +PACKAGE_kmod-bonding:kmod-bonding
+  DEPENDS:=@TARGET_qualcommax \
+	   +@NSS_DRV_VLAN_ENABLE \
+  	   +PACKAGE_kmod-bonding:kmod-bonding \
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
   FILES:=$(PKG_BUILD_DIR)/vlan/qca-nss-vlan.ko
   AUTOLOAD:=$(call AutoLoad,51,qca-nss-vlan)
 endef
@@ -369,9 +354,9 @@ define KernelPackage/qca-nss-drv-igs
   CATEGORY:=Kernel modules
   SUBMENU:=Network Support
   TITLE:=Action for offloading traffic to an IFB interface to perform ingress shaping.
-  DEPENDS:=@(TARGET_ipq806x||TARGET_ipq_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_qualcommax||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64||TARGET_ipq60xx||TARGET_ipq_ipq50xx||TARGET_ipq_ipq50xx_64||TARGET_ipq50xx) \
-		   +@NSS_DRV_IGS_ENABLE +kmod-sched-core +kmod-nf-conntrack +kmod-ifb +kmod-qca-nss-drv-qdisc \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
+  DEPENDS:=@TARGET_qualcommax +@NSS_DRV_IGS_ENABLE +kmod-qca-nss-drv-qdisc \
+	   +kmod-sched-core +kmod-nf-conntrack +kmod-ifb \
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
   FILES:=$(PKG_BUILD_DIR)/nss_qdisc/igs/act_nssmirred.ko
 endef
 
@@ -384,7 +369,7 @@ define KernelPackage/qca-nss-drv-match
  CATEGORY:=Kernel modules
  SUBMENU:=Network Devices
  DEPENDS:=+@NSS_DRV_MATCH_ENABLE \
-		  +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
+	  +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
  TITLE:=NSS Match for QCA NSS driver
  FILES:=$(PKG_BUILD_DIR)/match/qca-nss-match.ko
 endef
@@ -399,7 +384,7 @@ define KernelPackage/qca-nss-drv-mirror
  SUBMENU:=Network Support
  TITLE:=Module for mirroring packets from NSS to host.
  DEPENDS:=+@NSS_DRV_MIRROR_ENABLE \
-		  +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
+	  +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
  FILES:=$(PKG_BUILD_DIR)/mirror/qca-nss-mirror.ko
 endef
 
@@ -412,10 +397,11 @@ define KernelPackage/qca-nss-drv-netlink
   CATEGORY:=Kernel modules
   SUBMENU:=Network Devices
   TITLE:=NSS NETLINK Manager for QCA NSS driver
-  DEPENDS:=@(TARGET_ipq806x||TARGET_ipq807x||TARGET_ipq_ipq807x_64||TARGET_qualcommax||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64||TARGET_ipq60xx||TARGET_ipq_ipq50xx||TARGET_ipq_ipq50xx_64||TARGET_ipq50xx) \
-  		   +@NSS_DRV_C2C_ENABLE +@NSS_DRV_GRE_REDIR_ENABLE +@NSS_DRV_IPV4_REASM_ENABLE +@NSS_DRV_IPV6_ENABLE +@NSS_DRV_IPV6_REASM_ENABLE +@NSS_DRV_RMNET_ENABLE +@NSS_DRV_OAM_ENABLE +@NSS_DRV_QRFS_ENABLE \
-		   +kmod-pppoe +kmod-qca-nss-drv-dtlsmgr \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
+  DEPENDS:=@TARGET_qualcommax +@NSS_DRV_C2C_ENABLE +@NSS_DRV_GRE_REDIR_ENABLE \
+  	   +@NSS_DRV_IPV4_REASM_ENABLE +@NSS_DRV_IPV6_ENABLE +@NSS_DRV_IPV6_REASM_ENABLE \
+	   +@NSS_DRV_RMNET_ENABLE +@NSS_DRV_OAM_ENABLE +@NSS_DRV_QRFS_ENABLE \
+	   +kmod-pppoe +kmod-qca-nss-drv-dtlsmgr \
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
   FILES:=$(PKG_BUILD_DIR)/netlink/qca-nss-netlink.ko
 endef
 
@@ -429,7 +415,7 @@ define KernelPackage/qca-nss-drv-qdisc
   SUBMENU:=Network Support
   TITLE:=Qdisc for configuring shapers in NSS
   DEPENDS:=+@NSS_DRV_SHAPER_ENABLE +@NSS_DRV_IGS_ENABLE \
-		   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
+	   +PACKAGE_kmod-qca-nss-drv:kmod-qca-nss-drv
   FILES:=$(PKG_BUILD_DIR)/nss_qdisc/qca-nss-qdisc.ko
   KCONFIG:=CONFIG_NET_CLS_ACT=y
   AUTOLOAD:=$(call AutoLoad,58,qca-nss-qdisc)
@@ -513,7 +499,7 @@ endif
 
 ifneq ($(CONFIG_PACKAGE_kmod-qca-nss-drv-ipsecmgr),)
 EXTRA_CFLAGS+= -I$(PKG_BUILD_DIR)/exports \
-			   -I$(STAGING_DIR)/usr/include/qca-nss-ecm
+		-I$(STAGING_DIR)/usr/include/qca-nss-ecm
 NSS_CLIENTS_MAKE_OPTS+=ipsecmgr=y
 endif
 

lede/package/qca/qca-nss-crypto/Makefile

@@ -3,9 +3,9 @@ include $(TOPDIR)/rules.mk
 PKG_NAME:=qca-nss-crypto
 PKG_RELEASE:=1
 
-PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-crypto.git
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_DATE:=2022-12-15
+PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-crypto.git
 PKG_SOURCE_VERSION:=3c5a574ce99d7f0b9f892002020f1bf9bfc57a81
 PKG_MIRROR_HASH:=ff487c5574481f548eef7b61129fa7be1d83ae285dcc3356a06be237440d8782
 
@@ -56,13 +56,11 @@ endif
 define Build/Compile
 	+$(MAKE) -C "$(LINUX_DIR)" \
 		CC="$(TARGET_CC)" \
-		CROSS_COMPILE="$(TARGET_CROSS)" \
-		ARCH="$(LINUX_KARCH)" \
+		$(KERNEL_MAKE_FLAGS) \
 		M="$(PKG_BUILD_DIR)" \
 		EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \
 		NSS_CRYPTO_DIR=$(NSS_CRYPTO_DIR) \
 		SoC=$(SOC) \
-		$(KERNEL_MAKE_FLAGS) \
 		$(PKG_JOBS) \
 		modules
 endef

lede/package/qca/qca-nss-drv/Makefile

@@ -1,11 +1,11 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=qca-nss-drv
-PKG_RELEASE:=$(AUTORELEASE)
+PKG_RELEASE:=1
 
-PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-drv.git
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_DATE:=2023-08-06
+PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-drv.git
 PKG_SOURCE_VERSION:=1ab184034529539f61093184a67d4454cb3eb352
 PKG_MIRROR_HASH:=6aa081c0853d3e3b6d78eee588a0967e540b2317d15aef3c3f6f7129925653f7
 
@@ -67,7 +67,7 @@ define KernelPackage/qca-nss-drv
   SECTION:=kernel
   CATEGORY:=Kernel modules
   SUBMENU:=Network Devices
-  DEPENDS:=@(TARGET_qualcommax||TARGET_ipq60xx) +kmod-qca-nss-dp
+  DEPENDS:=@TARGET_qualcommax +kmod-qca-nss-dp
   TITLE:=Qualcomm NSS core driver
   FILES:=$(PKG_BUILD_DIR)/qca-nss-drv.ko
   AUTOLOAD:=$(call AutoLoad,32,qca-nss-drv)
@@ -89,7 +89,6 @@ define KernelPackage/qca-nss-drv/install
 	$(INSTALL_BIN) ./files/qca-nss-drv.conf $(1)/etc/config/nss
 	$(INSTALL_BIN) ./files/qca-nss-drv.hotplug $(1)/etc/hotplug.d/firmware/10-qca-nss-fw
 	$(INSTALL_BIN) ./files/qca-nss-drv.debug $(1)/lib/debug/qca-nss-drv
-
 endef
 
 define KernelPackage/qca-nss-drv/Description
@@ -107,7 +106,7 @@ endif
 define Build/InstallDev
 	mkdir -p $(1)/usr/include/qca-nss-drv
 	$(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-drv/
-ifneq (, $(findstring $(subtarget), "ipq807x" "ipq807x_64" "ipq60xx" "ipq60xx_64" "ipq50xx" "ipq50xx_64"))
+ifneq (, $(findstring $(subtarget), "ipq807x" "ipq60xx"))
 	$(RM) $(1)/usr/include/qca-nss-drv/nss_ipsecmgr.h
 	# $(INSTALL_DIR) $(1)/usr/include/qca-nss-clients
 	# $(CP) $(NSS_CLIENTS_DIR)/exports/nss_ipsecmgr.h $(1)/usr/include/qca-nss-clients/.
@@ -120,7 +119,7 @@ EXTRA_CFLAGS+= -I$(STAGING_DIR)/usr/include/qca-nss-gmac \
 			   -Wno-unused-variable \
 			   -Wno-error=unused-function
 
-ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "qualcommax" "ipq60xx"))
+ifeq ($(BOARD),qualcommax)
 EXTRA_CFLAGS+= -DNSS_MEM_PROFILE_MEDIUM
 endif
 
@@ -265,11 +264,10 @@ endef
 define Build/Compile
 	+$(MAKE) -C "$(LINUX_DIR)" $(strip $(DRV_MAKE_OPTS)) \
 		CROSS_COMPILE="$(TARGET_CROSS)" \
-		ARCH="$(LINUX_KARCH)" \
+		$(KERNEL_MAKE_FLAGS) \
 		M="$(PKG_BUILD_DIR)" \
 		EXTRA_CFLAGS="$(EXTRA_CFLAGS)" \
 		SoC=$(SOC) \
-		$(KERNEL_MAKE_FLAGS) \
 		$(PKG_JOBS) \
 		modules
 endef

lede/package/qca/qca-nss-drv/patches/0008-add-kernel-6.1-support.patch

@@ -1,20 +1,3 @@
-From aa48e29c88c467ba0b2cf9d1f32a7f3484d88e0e Mon Sep 17 00:00:00 2001
-From: JiaY-shi <shi05275@163.com>
-Date: Fri, 9 Jun 2023 20:51:03 +0800
-Subject: [PATCH] nss-drv: adapt to netif_napi_add() changes
-
-netif_napi_add() removed the weight argument and just uses the default
-NAPI_POLL_WEIGHT in background, so for those requiring custom weight use
-netif_napi_add_weight() instead.
----
- nss_hal/fsm9010/nss_hal_pvt.c |  6 +++-
- nss_hal/ipq50xx/nss_hal_pvt.c |  6 +++-
- nss_hal/ipq60xx/nss_hal_pvt.c | 60 +++++++++++++++++++++++++++++------
- nss_hal/ipq806x/nss_hal_pvt.c |  6 +++-
- nss_hal/ipq807x/nss_hal_pvt.c | 60 +++++++++++++++++++++++++++++------
- nss_hal/ipq95xx/nss_hal_pvt.c |  6 +++-
- 6 files changed, 120 insertions(+), 24 deletions(-)
-
 --- a/nss_hal/fsm9010/nss_hal_pvt.c
 +++ b/nss_hal/fsm9010/nss_hal_pvt.c
 @@ -291,7 +291,11 @@ static int __nss_hal_request_irq(struct

lede/package/qca/qca-nss-ecm/Makefile

@@ -3,9 +3,9 @@ include $(TOPDIR)/rules.mk
 PKG_NAME:=qca-nss-ecm
 PKG_RELEASE=1
 
-PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-nss-ecm.git
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_DATE:=2023-10-20
+PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-nss-ecm.git
 PKG_SOURCE_VERSION:=82b27915fffdbe2cdb2d4eb70e5736ccf92e2560
 PKG_MIRROR_HASH:=643895cb187cacfcde337c19dc5a34512acc225c0db1813a15cc1b66523835c4
 
@@ -19,7 +19,7 @@ define KernelPackage/qca-nss-ecm
   SECTION:=kernel
   CATEGORY:=Kernel modules
   SUBMENU:=Network Support
-  DEPENDS:=@(TARGET_qualcommax||TARGET_ipq60xx) \
+  DEPENDS:=@TARGET_qualcommax \
   		   +@NSS_DRV_IPV6_ENABLE \
 		   +@NSS_DRV_PPE_ENABLE \
 		   +@NSS_DRV_TUN6RD_ENABLE \
@@ -28,8 +28,8 @@ define KernelPackage/qca-nss-ecm
 		   +@NSS_DRV_VIRT_IF_ENABLE \
 		   +@NSS_DRV_WIFI_ENABLE \
 		   +kmod-qca-nss-drv \
-    	   +kmod-nf-conntrack \
-		   +kmod-ppp +kmod-pppoe +kmod-pptp +kmod-bonding \
+    	   +kmod-bonding +kmod-nf-conntrack \
+		   +kmod-ppp +kmod-pppoe +kmod-pptp \
 		   +PACKAGE_kmod-pppol2tp:kmod-pppol2tp \
 		   +PACKAGE_kmod-qca-mcs:kmod-qca-mcs \
 		   +PACKAGE_kmod-nat46:kmod-nat46 \
@@ -63,7 +63,7 @@ EXTRA_CFLAGS+= \
 		 -I$(STAGING_DIR)/usr/include/qca-mcs \
 		 -I$(STAGING_DIR)/usr/include/nat46
 
-ifneq (, $(findstring $(CONFIG_TARGET_BOARD), "qualcommax" "ipq60xx"))
+ifeq ($(BOARD),qualcommax)
 ECM_MAKE_OPTS+=ECM_FRONT_END_NSS_ENABLE=y \
 			   ECM_FRONT_END_SFE_ENABLE=n \
 			   ECM_NON_PORTED_SUPPORT_ENABLE=y \
@@ -150,10 +150,10 @@ define Build/Compile
 	+$(MAKE) -C "$(LINUX_DIR)" $(strip $(ECM_MAKE_OPTS)) \
 		CROSS_COMPILE="$(TARGET_CROSS)" \
 		ARCH="$(LINUX_KARCH)" \
+		$(KERNEL_MAKE_FLAGS) \
 		M="$(PKG_BUILD_DIR)" \
 		EXTRA_CFLAGS="$(EXTRA_CFLAGS) -Wno-error=unused-function " \
 		SoC=$(SOC) \
-		$(KERNEL_MAKE_FLAGS) \
 		$(PKG_JOBS) \
 		modules
 endef

lede/package/qca/qca-nss-ecm/patches/1000-fix-miss-header.patch

@@ -1,24 +0,0 @@
-From 7caef43a66bf9f5bbd3d48db1fc6af26bdca8f63 Mon Sep 17 00:00:00 2001
-From: JiaY-shi <shi05275@163.com>
-Date: Fri, 28 Jul 2023 20:44:45 +0800
-Subject: [PATCH] fix miss header
-
----
- frontends/ecm_front_end_common.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/frontends/ecm_front_end_common.c b/frontends/ecm_front_end_common.c
-index 1339cec..089db07 100644
---- a/frontends/ecm_front_end_common.c
-+++ b/frontends/ecm_front_end_common.c
-@@ -26,6 +26,7 @@
- #include <linux/inetdevice.h>
- #include <linux/sysctl.h>
- #include <net/netfilter/nf_conntrack.h>
-+#include <net/sch_generic.h>
- #ifdef ECM_CLASSIFIER_DSCP_ENABLE
- #include <linux/netfilter/xt_dscp.h>
- #include <net/netfilter/nf_conntrack_dscpremark_ext.h>
--- 
-2.25.1
-

lede/package/qca/qca-nss-ecm/patches/1000-fix-missing-include-header.patch

@@ -0,0 +1,10 @@
+--- a/frontends/ecm_front_end_common.c
++++ b/frontends/ecm_front_end_common.c
+@@ -26,6 +26,7 @@
+ #include <linux/inetdevice.h>
+ #include <linux/sysctl.h>
+ #include <net/netfilter/nf_conntrack.h>
++#include <net/sch_generic.h>
+ #ifdef ECM_CLASSIFIER_DSCP_ENABLE
+ #include <linux/netfilter/xt_dscp.h>
+ #include <net/netfilter/nf_conntrack_dscpremark_ext.h>

lede/package/qca/qca-ssdk-shell/Makefile

@@ -1,11 +1,11 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=qca-ssdk-shell
-PKG_RELEASE:=$(AUTORELEASE)
+PKG_RELEASE:=1
 
-PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/ssdk-shell.git
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_DATE:=2023-10-04
+PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/ssdk-shell.git
 PKG_SOURCE_VERSION:=451c3a26e366ea1acdb4305999a72a0389e74fed
 PKG_MIRROR_HASH:=e2da723c12120096f1c851808b868abe1affa14e4d969eff7bedb1e1eb984418
 
@@ -18,7 +18,6 @@ define Package/qca-ssdk-shell
   TITLE:=Shell application for QCA SSDK
 endef
 
-
 define Package/qca-ssdk-shell/Description
   This package contains a qca-ssdk shell application for QCA chipset
 endef
@@ -27,7 +26,8 @@ ifndef CONFIG_TOOLCHAIN_BIN_PATH
 CONFIG_TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin
 endif
 
-QCASSDK_CONFIG_OPTS+= TOOL_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) \
+QCASSDK_CONFIG_OPTS+= \
+                TOOL_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH) \
                 SYS_PATH=$(LINUX_DIR) \
                 TOOLPREFIX=$(TARGET_CROSS) \
                 KVER=$(LINUX_VERSION) \
@@ -44,5 +44,4 @@ define Package/qca-ssdk-shell/install
 	$(INSTALL_BIN) $(PKG_BUILD_DIR)/build/bin/ssdk_sh $(1)/usr/sbin/
 endef
 
-
 $(eval $(call BuildPackage,qca-ssdk-shell))

lede/target/linux/generic/backport-5.15/728-v6.1-04-net-ethernet-mtk_eth_soc-fix-resource-leak-in-error-.patch

@@ -0,0 +1,35 @@
+From 8110437e59616293228cd781c486d8495a61e36a Mon Sep 17 00:00:00 2001
+From: Yan Cangang <nalanzeyu@gmail.com>
+Date: Sun, 20 Nov 2022 13:52:58 +0800
+Subject: [PATCH] net: ethernet: mtk_eth_soc: fix resource leak in error path
+
+In mtk_probe(), when mtk_ppe_init() or mtk_eth_offload_init() failed,
+mtk_mdio_cleanup() isn't called. Fix it.
+
+Fixes: ba37b7caf1ed ("net: ethernet: mtk_eth_soc: add support for initializing the PPE")
+Fixes: 502e84e2382d ("net: ethernet: mtk_eth_soc: add flow offloading support")
+Signed-off-by: Yan Cangang <nalanzeyu@gmail.com>
+Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -4087,13 +4087,13 @@ static int mtk_probe(struct platform_dev
+ 						   eth->soc->offload_version, i);
+ 			if (!eth->ppe[i]) {
+ 				err = -ENOMEM;
+-				goto err_free_dev;
++				goto err_deinit_mdio;
+ 			}
+ 		}
+ 
+ 		err = mtk_eth_offload_init(eth);
+ 		if (err)
+-			goto err_free_dev;
++			goto err_deinit_mdio;
+ 	}
+ 
+ 	for (i = 0; i < MTK_MAX_DEVS; i++) {

lede/target/linux/generic/backport-5.15/728-v6.1-05-net-ethernet-mtk_eth_soc-fix-memory-leak-in-error-pa.patch

@@ -0,0 +1,107 @@
+From 603ea5e7ffa73c7fac07d8713d97285990695213 Mon Sep 17 00:00:00 2001
+From: Yan Cangang <nalanzeyu@gmail.com>
+Date: Sun, 20 Nov 2022 13:52:59 +0800
+Subject: [PATCH] net: ethernet: mtk_eth_soc: fix memory leak in error path
+
+In mtk_ppe_init(), when dmam_alloc_coherent() or devm_kzalloc() failed,
+the rhashtable ppe->l2_flows isn't destroyed. Fix it.
+
+In mtk_probe(), when mtk_ppe_init() or mtk_eth_offload_init() or
+register_netdev() failed, have the same problem. Fix it.
+
+Fixes: 33fc42de3327 ("net: ethernet: mtk_eth_soc: support creating mac address based offload entries")
+Signed-off-by: Yan Cangang <nalanzeyu@gmail.com>
+Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |  9 +++++----
+ drivers/net/ethernet/mediatek/mtk_ppe.c     | 19 +++++++++++++++++--
+ drivers/net/ethernet/mediatek/mtk_ppe.h     |  1 +
+ 3 files changed, 23 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -4087,13 +4087,13 @@ static int mtk_probe(struct platform_dev
+ 						   eth->soc->offload_version, i);
+ 			if (!eth->ppe[i]) {
+ 				err = -ENOMEM;
+-				goto err_deinit_mdio;
++				goto err_deinit_ppe;
+ 			}
+ 		}
+ 
+ 		err = mtk_eth_offload_init(eth);
+ 		if (err)
+-			goto err_deinit_mdio;
++			goto err_deinit_ppe;
+ 	}
+ 
+ 	for (i = 0; i < MTK_MAX_DEVS; i++) {
+@@ -4103,7 +4103,7 @@ static int mtk_probe(struct platform_dev
+ 		err = register_netdev(eth->netdev[i]);
+ 		if (err) {
+ 			dev_err(eth->dev, "error bringing up device\n");
+-			goto err_deinit_mdio;
++			goto err_deinit_ppe;
+ 		} else
+ 			netif_info(eth, probe, eth->netdev[i],
+ 				   "mediatek frame engine at 0x%08lx, irq %d\n",
+@@ -4123,7 +4123,8 @@ static int mtk_probe(struct platform_dev
+ 
+ 	return 0;
+ 
+-err_deinit_mdio:
++err_deinit_ppe:
++	mtk_ppe_deinit(eth);
+ 	mtk_mdio_cleanup(eth);
+ err_free_dev:
+ 	mtk_free_dev(eth);
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
+@@ -743,7 +743,7 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
+ 				  MTK_PPE_ENTRIES * soc->foe_entry_size,
+ 				  &ppe->foe_phys, GFP_KERNEL);
+ 	if (!foe)
+-		return NULL;
++		goto err_free_l2_flows;
+ 
+ 	ppe->foe_table = foe;
+ 
+@@ -751,11 +751,26 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
+ 			sizeof(*ppe->foe_flow);
+ 	ppe->foe_flow = devm_kzalloc(dev, foe_flow_size, GFP_KERNEL);
+ 	if (!ppe->foe_flow)
+-		return NULL;
++		goto err_free_l2_flows;
+ 
+ 	mtk_ppe_debugfs_init(ppe, index);
+ 
+ 	return ppe;
++
++err_free_l2_flows:
++	rhashtable_destroy(&ppe->l2_flows);
++	return NULL;
++}
++
++void mtk_ppe_deinit(struct mtk_eth *eth)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) {
++		if (!eth->ppe[i])
++			return;
++		rhashtable_destroy(&eth->ppe[i]->l2_flows);
++	}
+ }
+ 
+ static void mtk_ppe_init_foe_table(struct mtk_ppe *ppe)
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.h
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
+@@ -304,6 +304,7 @@ struct mtk_ppe {
+ 
+ struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,
+ 			     int version, int index);
++void mtk_ppe_deinit(struct mtk_eth *eth);
+ void mtk_ppe_start(struct mtk_ppe *ppe);
+ int mtk_ppe_stop(struct mtk_ppe *ppe);
+ 

lede/target/linux/generic/backport-5.15/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch

@@ -237,8 +237,8 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  {
 --- a/drivers/net/ethernet/mediatek/mtk_ppe.h
 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
-@@ -306,6 +306,7 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
- 			     int version, int index);
+@@ -307,6 +307,7 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
+ void mtk_ppe_deinit(struct mtk_eth *eth);
  void mtk_ppe_start(struct mtk_ppe *ppe);
  int mtk_ppe_stop(struct mtk_ppe *ppe);
 +int mtk_ppe_prepare_reset(struct mtk_ppe *ppe);

lede/target/linux/generic/backport-5.15/730-06-v6.3-net-ethernet-mediatek-ppe-assign-per-port-queues-for.patch

@@ -47,7 +47,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #define MTK_FOE_IB2_DEST_PORT_V2	GENMASK(12, 9)
  #define MTK_FOE_IB2_MULTICAST_V2	BIT(13)
  #define MTK_FOE_IB2_WDMA_WINFO_V2	BIT(19)
-@@ -351,6 +353,8 @@ int mtk_foe_entry_set_pppoe(struct mtk_e
+@@ -352,6 +354,8 @@ int mtk_foe_entry_set_pppoe(struct mtk_e
  			    int sid);
  int mtk_foe_entry_set_wdma(struct mtk_eth *eth, struct mtk_foe_entry *entry,
  			   int wdma_idx, int txq, int bss, int wcid);

lede/target/linux/generic/backport-5.15/730-07-v6.3-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch

@@ -1,28 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Thu, 27 Oct 2022 23:39:52 +0200
-Subject: [PATCH] net: ethernet: mtk_eth_soc: compile out netsys v2 code
- on mt7621
-
-Avoid some branches in the hot path on low-end devices with limited CPU power,
-and reduce code size
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -917,7 +917,13 @@ enum mkt_eth_capabilities {
- #define MTK_MUX_GMAC12_TO_GEPHY_SGMII   \
- 	(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
- 
--#define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x)) == (_x))
-+#ifdef CONFIG_SOC_MT7621
-+#define MTK_CAP_MASK MTK_NETSYS_V2
-+#else
-+#define MTK_CAP_MASK 0
-+#endif
-+
-+#define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x) & ~(MTK_CAP_MASK)) == (_x))
- 
- #define MT7621_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
- 		      MTK_GMAC2_RGMII | MTK_SHARED_INT | \

lede/target/linux/generic/backport-5.15/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch

@@ -181,7 +181,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  /* CDMP Ingress Control Register */
  #define MTK_CDMP_IG_CTRL	0x400
  #define MTK_CDMP_STAG_EN	BIT(0)
-@@ -1166,6 +1172,8 @@ struct mtk_eth {
+@@ -1160,6 +1166,8 @@ struct mtk_eth {
  
  	int				ip_align;
  

lede/target/linux/generic/backport-5.15/733-v6.2-12-net-mediatek-sgmii-ensure-the-SGMII-PHY-is-powered-d.patch

@@ -34,7 +34,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -1070,11 +1070,13 @@ struct mtk_soc_data {
+@@ -1064,11 +1064,13 @@ struct mtk_soc_data {
   * @regmap:            The register map pointing at the range used to setup
   *                     SGMII modes
   * @ana_rgc3:          The offset refers to register ANA_RGC3 related to regmap

lede/target/linux/generic/backport-5.15/733-v6.3-21-net-ethernet-mtk_eth_soc-add-missing-ppe-cache-flush.patch

@@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c
 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
-@@ -523,6 +523,7 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp
+@@ -464,6 +464,7 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp
  		hwe->ib1 &= ~MTK_FOE_IB1_STATE;
  		hwe->ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_INVALID);
  		dma_wmb();

lede/target/linux/generic/backport-5.15/733-v6.4-24-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch

@@ -53,7 +53,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4691,8 +4691,8 @@ static int mtk_probe(struct platform_dev
+@@ -4635,8 +4635,8 @@ static int mtk_probe(struct platform_dev
  		for (i = 0; i < num_ppe; i++) {
  			u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
  
@@ -64,7 +64,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  			if (!eth->ppe[i]) {
  				err = -ENOMEM;
  				goto err_deinit_ppe;
-@@ -4818,6 +4818,7 @@ static const struct mtk_soc_data mt7622_
+@@ -4762,6 +4762,7 @@ static const struct mtk_soc_data mt7622_
  	.required_pctl = false,
  	.offload_version = 2,
  	.hash_offset = 2,
@@ -72,7 +72,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
-@@ -4855,6 +4856,7 @@ static const struct mtk_soc_data mt7629_
+@@ -4799,6 +4800,7 @@ static const struct mtk_soc_data mt7629_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7629_CLKS_BITMAP,
  	.required_pctl = false,
@@ -80,7 +80,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4875,6 +4877,7 @@ static const struct mtk_soc_data mt7981_
+@@ -4819,6 +4821,7 @@ static const struct mtk_soc_data mt7981_
  	.offload_version = 2,
  	.hash_offset = 4,
  	.foe_entry_size = sizeof(struct mtk_foe_entry),
@@ -88,7 +88,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma_v2),
  		.rxd_size = sizeof(struct mtk_rx_dma_v2),
-@@ -4895,6 +4898,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4839,6 +4842,7 @@ static const struct mtk_soc_data mt7986_
  	.offload_version = 2,
  	.hash_offset = 4,
  	.foe_entry_size = sizeof(struct mtk_foe_entry),
@@ -98,7 +98,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  		.rxd_size = sizeof(struct mtk_rx_dma_v2),
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -1017,6 +1017,8 @@ struct mtk_reg_map {
+@@ -1008,6 +1008,8 @@ struct mtk_reg_map {
   *				the extra setup for those pins used by GMAC.
   * @hash_offset			Flow table hash offset.
   * @foe_entry_size		Foe table entry size.
@@ -107,7 +107,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
   * @txd_size			Tx DMA descriptor size.
   * @rxd_size			Rx DMA descriptor size.
   * @rx_irq_done_mask		Rx irq done register mask.
-@@ -1034,6 +1036,7 @@ struct mtk_soc_data {
+@@ -1025,6 +1027,7 @@ struct mtk_soc_data {
  	u8		hash_offset;
  	u16		foe_entry_size;
  	netdev_features_t hw_features;
@@ -166,7 +166,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  static void mtk_ppe_cache_clear(struct mtk_ppe *ppe)
  {
  	ppe_set(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);
-@@ -459,6 +501,13 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp
+@@ -465,6 +507,13 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp
  		hwe->ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_INVALID);
  		dma_wmb();
  		mtk_ppe_cache_clear(ppe);
@@ -180,7 +180,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	}
  	entry->hash = 0xffff;
  
-@@ -566,6 +615,9 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
+@@ -572,6 +621,9 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
  	wmb();
  	hwe->ib1 = entry->ib1;
  
@@ -190,7 +190,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	dma_wmb();
  
  	mtk_ppe_cache_clear(ppe);
-@@ -757,11 +809,39 @@ int mtk_ppe_prepare_reset(struct mtk_ppe
+@@ -763,11 +815,39 @@ int mtk_ppe_prepare_reset(struct mtk_ppe
  	return mtk_ppe_wait_busy(ppe);
  }
  
@@ -232,7 +232,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	struct mtk_ppe *ppe;
  	u32 foe_flow_size;
  	void *foe;
-@@ -778,7 +858,8 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
+@@ -784,7 +864,8 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
  	ppe->base = base;
  	ppe->eth = eth;
  	ppe->dev = dev;
@@ -242,7 +242,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  
  	foe = dmam_alloc_coherent(ppe->dev,
  				  MTK_PPE_ENTRIES * soc->foe_entry_size,
-@@ -794,6 +875,23 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
+@@ -800,6 +881,23 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
  	if (!ppe->foe_flow)
  		goto err_free_l2_flows;
  
@@ -266,7 +266,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	mtk_ppe_debugfs_init(ppe, index);
  
  	return ppe;
-@@ -923,6 +1021,16 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
+@@ -929,6 +1027,16 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
  		ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777);
  		ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f);
  	}

lede/target/linux/generic/backport-5.15/733-v6.4-25-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch

@@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c
 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
-@@ -646,6 +646,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
+@@ -605,6 +605,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
  	struct mtk_eth *eth = ppe->eth;
  	u16 timestamp = mtk_eth_timestamp(eth);
  	struct mtk_foe_entry *hwe;
@@ -19,7 +19,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  		entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP_V2;
-@@ -662,8 +663,13 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
+@@ -621,8 +622,13 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
  	wmb();
  	hwe->ib1 = entry->ib1;
  

lede/target/linux/generic/backport-5.15/733-v6.5-27-net-ethernet-mtk_eth_soc-always-mtk_get_ib1_pkt_type.patch

@@ -0,0 +1,31 @@
+From b804f765485109f9644cc05d1e8fc79ca6c6e4aa Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 19 Jul 2023 01:39:36 +0100
+Subject: [PATCH 094/250] net: ethernet: mtk_eth_soc: always
+ mtk_get_ib1_pkt_type
+
+entries and bind debugfs files would display wrong data on NETSYS_V2 and
+later because instead of using mtk_get_ib1_pkt_type the driver would use
+MTK_FOE_IB1_PACKET_TYPE which corresponds to NETSYS_V1(.x) SoCs.
+Use mtk_get_ib1_pkt_type so entries and bind records display correctly.
+
+Fixes: 03a3180e5c09e ("net: ethernet: mtk_eth_soc: introduce flow offloading support for mt7986")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://lore.kernel.org/r/c0ae03d0182f4d27b874cbdf0059bc972c317f3c.1689727134.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c
+@@ -98,7 +98,7 @@ mtk_ppe_debugfs_foe_show(struct seq_file
+ 
+ 		acct = mtk_foe_entry_get_mib(ppe, i, NULL);
+ 
+-		type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
++		type = mtk_get_ib1_pkt_type(ppe->eth, entry->ib1);
+ 		seq_printf(m, "%05x %s %7s", i,
+ 			   mtk_foe_entry_state_str(state),
+ 			   mtk_foe_pkt_type_str(type));

lede/target/linux/generic/backport-5.15/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch

@@ -0,0 +1,78 @@
+From 5ea0e1312bcfebc06b5f91d1bb82b823d6395125 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Wed, 19 Jul 2023 12:29:49 +0200
+Subject: [PATCH 095/250] net: ethernet: mtk_ppe: add MTK_FOE_ENTRY_V{1,2}_SIZE
+ macros
+
+Introduce MTK_FOE_ENTRY_V{1,2}_SIZE macros in order to make more
+explicit foe_entry size for different chipset revisions.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 10 +++++-----
+ drivers/net/ethernet/mediatek/mtk_ppe.h     |  3 +++
+ 2 files changed, 8 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -4711,7 +4711,7 @@ static const struct mtk_soc_data mt7621_
+ 	.required_pctl = false,
+ 	.offload_version = 1,
+ 	.hash_offset = 2,
+-	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
++	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+@@ -4732,7 +4732,7 @@ static const struct mtk_soc_data mt7622_
+ 	.offload_version = 2,
+ 	.hash_offset = 2,
+ 	.has_accounting = true,
+-	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
++	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+@@ -4751,7 +4751,7 @@ static const struct mtk_soc_data mt7623_
+ 	.required_pctl = true,
+ 	.offload_version = 1,
+ 	.hash_offset = 2,
+-	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
++	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+@@ -4789,8 +4789,8 @@ static const struct mtk_soc_data mt7981_
+ 	.required_pctl = false,
+ 	.offload_version = 2,
+ 	.hash_offset = 4,
+-	.foe_entry_size = sizeof(struct mtk_foe_entry),
+ 	.has_accounting = true,
++	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma_v2),
+ 		.rxd_size = sizeof(struct mtk_rx_dma_v2),
+@@ -4810,8 +4810,8 @@ static const struct mtk_soc_data mt7986_
+ 	.required_pctl = false,
+ 	.offload_version = 2,
+ 	.hash_offset = 4,
+-	.foe_entry_size = sizeof(struct mtk_foe_entry),
+ 	.has_accounting = true,
++	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma_v2),
+ 		.rxd_size = sizeof(struct mtk_rx_dma_v2),
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.h
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
+@@ -216,6 +216,9 @@ struct mtk_foe_ipv6_6rd {
+ 	struct mtk_foe_mac_info l2;
+ };
+ 
++#define MTK_FOE_ENTRY_V1_SIZE	80
++#define MTK_FOE_ENTRY_V2_SIZE	96
++
+ struct mtk_foe_entry {
+ 	u32 ib1;
+ 

lede/target/linux/generic/backport-5.15/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch

@@ -0,0 +1,141 @@
+From 8cfa2576d79f9379d167a8994f0fca935c07a8bc Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Sat, 22 Jul 2023 21:32:49 +0100
+Subject: [PATCH 096/250] net: ethernet: mtk_eth_soc: remove incorrect PLL
+ configuration
+
+MT7623 GMAC0 attempts to configure the system clocking according to the
+required speed in the .mac_config callback for non-SGMII, non-baseX and
+non-TRGMII modes.
+
+state->speed setting has never been reliable in the .mac_config
+callback - there are cases where this is not the link speed,
+particularly via ethtool paths, so this has always been unreliable (as
+detailed in phylink's documentation.)
+
+There is the additional issue that mtk_gmac0_rgmii_adjust() will only
+be called if state->interface changes, which means it only configures
+the system clocking on the very first .mac_config call, which will be
+made when the network device is first brought up before any link is
+established.
+
+Essentially, this code is incredibly buggy, and probably never worked.
+
+Moreover, checking the in-kernel DT files, it seems no platform makes
+use of this code path.
+
+Therefore, let's remove it, and disable interface modes for port 0 that
+are not SGMII, 1000base-X, 2500base-X or TRGMII on the MT7623.
+
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Frank Wunderlich <frank-w@public-files.de>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 54 ++++++---------------
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h |  1 +
+ 2 files changed, 17 insertions(+), 38 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -309,7 +309,7 @@ static int mt7621_gmac0_rgmii_adjust(str
+ }
+ 
+ static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
+-				   phy_interface_t interface, int speed)
++				   phy_interface_t interface)
+ {
+ 	u32 val;
+ 	int ret;
+@@ -323,26 +323,7 @@ static void mtk_gmac0_rgmii_adjust(struc
+ 		return;
+ 	}
+ 
+-	val = (speed == SPEED_1000) ?
+-		INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
+-	mtk_w32(eth, val, INTF_MODE);
+-
+-	regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
+-			   ETHSYS_TRGMII_CLK_SEL362_5,
+-			   ETHSYS_TRGMII_CLK_SEL362_5);
+-
+-	val = (speed == SPEED_1000) ? 250000000 : 500000000;
+-	ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
+-	if (ret)
+-		dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
+-
+-	val = (speed == SPEED_1000) ?
+-		RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
+-	mtk_w32(eth, val, TRGMII_RCK_CTRL);
+-
+-	val = (speed == SPEED_1000) ?
+-		TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
+-	mtk_w32(eth, val, TRGMII_TCK_CTRL);
++	dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n");
+ }
+ 
+ static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
+@@ -428,17 +409,8 @@ static void mtk_mac_config(struct phylin
+ 							      state->interface))
+ 					goto err_phy;
+ 			} else {
+-				/* FIXME: this is incorrect. Not only does it
+-				 * use state->speed (which is not guaranteed
+-				 * to be correct) but it also makes use of it
+-				 * in a code path that will only be reachable
+-				 * when the PHY interface mode changes, not
+-				 * when the speed changes. Consequently, RGMII
+-				 * is probably broken.
+-				 */
+ 				mtk_gmac0_rgmii_adjust(mac->hw,
+-						       state->interface,
+-						       state->speed);
++						       state->interface);
+ 
+ 				/* mt7623_pad_clk_setup */
+ 				for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
+@@ -4286,13 +4258,19 @@ static int mtk_add_mac(struct mtk_eth *e
+ 	mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ 		MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
+ 
+-	__set_bit(PHY_INTERFACE_MODE_MII,
+-		  mac->phylink_config.supported_interfaces);
+-	__set_bit(PHY_INTERFACE_MODE_GMII,
+-		  mac->phylink_config.supported_interfaces);
++	/* MT7623 gmac0 is now missing its speed-specific PLL configuration
++	 * in its .mac_config method (since state->speed is not valid there.
++	 * Disable support for MII, GMII and RGMII.
++	 */
++	if (!mac->hw->soc->disable_pll_modes || mac->id != 0) {
++		__set_bit(PHY_INTERFACE_MODE_MII,
++			  mac->phylink_config.supported_interfaces);
++		__set_bit(PHY_INTERFACE_MODE_GMII,
++			  mac->phylink_config.supported_interfaces);
+ 
+-	if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII))
+-		phy_interface_set_rgmii(mac->phylink_config.supported_interfaces);
++		if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII))
++			phy_interface_set_rgmii(mac->phylink_config.supported_interfaces);
++	}
+ 
+ 	if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id)
+ 		__set_bit(PHY_INTERFACE_MODE_TRGMII,
+@@ -4752,6 +4730,7 @@ static const struct mtk_soc_data mt7623_
+ 	.offload_version = 1,
+ 	.hash_offset = 2,
+ 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
++	.disable_pll_modes = true,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -1027,6 +1027,7 @@ struct mtk_soc_data {
+ 	u16		foe_entry_size;
+ 	netdev_features_t hw_features;
+ 	bool		has_accounting;
++	bool		disable_pll_modes;
+ 	struct {
+ 		u32	txd_size;
+ 		u32	rxd_size;

lede/target/linux/generic/backport-5.15/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch

@@ -0,0 +1,81 @@
+From a4c2233b1e4359b6c64b6f9ba98c8718a11fffee Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Sat, 22 Jul 2023 21:32:54 +0100
+Subject: [PATCH 097/250] net: ethernet: mtk_eth_soc: remove mac_pcs_get_state
+ and modernise
+
+Remove the .mac_pcs_get_state function, since as far as I can tell is
+never called - no DT appears to specify an in-band-status management
+nor SFP support for this driver.
+
+Removal of this, along with the previous patch to remove the incorrect
+clocking configuration, means that the driver becomes non-legacy, so
+we can remove the "legacy_pre_march2020" status from this driver.
+
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Frank Wunderlich <frank-w@public-files.de>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 35 ---------------------
+ 1 file changed, 35 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -512,38 +512,6 @@ static int mtk_mac_finish(struct phylink
+ 	return 0;
+ }
+ 
+-static void mtk_mac_pcs_get_state(struct phylink_config *config,
+-				  struct phylink_link_state *state)
+-{
+-	struct mtk_mac *mac = container_of(config, struct mtk_mac,
+-					   phylink_config);
+-	u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id));
+-
+-	state->link = (pmsr & MAC_MSR_LINK);
+-	state->duplex = (pmsr & MAC_MSR_DPX) >> 1;
+-
+-	switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) {
+-	case 0:
+-		state->speed = SPEED_10;
+-		break;
+-	case MAC_MSR_SPEED_100:
+-		state->speed = SPEED_100;
+-		break;
+-	case MAC_MSR_SPEED_1000:
+-		state->speed = SPEED_1000;
+-		break;
+-	default:
+-		state->speed = SPEED_UNKNOWN;
+-		break;
+-	}
+-
+-	state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
+-	if (pmsr & MAC_MSR_RX_FC)
+-		state->pause |= MLO_PAUSE_RX;
+-	if (pmsr & MAC_MSR_TX_FC)
+-		state->pause |= MLO_PAUSE_TX;
+-}
+-
+ static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
+ 			      phy_interface_t interface)
+ {
+@@ -666,7 +634,6 @@ static void mtk_mac_link_up(struct phyli
+ static const struct phylink_mac_ops mtk_phylink_ops = {
+ 	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = mtk_mac_select_pcs,
+-	.mac_pcs_get_state = mtk_mac_pcs_get_state,
+ 	.mac_config = mtk_mac_config,
+ 	.mac_finish = mtk_mac_finish,
+ 	.mac_link_down = mtk_mac_link_down,
+@@ -4253,8 +4220,6 @@ static int mtk_add_mac(struct mtk_eth *e
+ 
+ 	mac->phylink_config.dev = &eth->netdev[id]->dev;
+ 	mac->phylink_config.type = PHYLINK_NETDEV;
+-	/* This driver makes use of state->speed in mac_config */
+-	mac->phylink_config.legacy_pre_march2020 = true;
+ 	mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ 		MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
+ 

lede/target/linux/generic/backport-5.15/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch

@@ -0,0 +1,550 @@
+From 5d8d05fbf804b4485646d39551ac27452e45afd3 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 25 Jul 2023 01:52:02 +0100
+Subject: [PATCH 099/250] net: ethernet: mtk_eth_soc: add version in
+ mtk_soc_data
+
+Introduce version field in mtk_soc_data data structure in order to
+make mtk_eth driver easier to maintain for chipset configuration
+codebase. Get rid of MTK_NETSYS_V2 bit in chip capabilities.
+This is a preliminary patch to introduce support for MT7988 SoC.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/e52fae302ca135436e5cdd26d38d87be2da63055.1690246066.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c   | 55 +++++++++++--------
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h   | 36 +++++++-----
+ drivers/net/ethernet/mediatek/mtk_ppe.c       | 18 +++---
+ .../net/ethernet/mediatek/mtk_ppe_offload.c   |  2 +-
+ drivers/net/ethernet/mediatek/mtk_wed.c       |  4 +-
+ 5 files changed, 66 insertions(+), 49 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -537,7 +537,7 @@ static void mtk_set_queue_speed(struct m
+ 	      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
+ 	      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
+ 	      MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
+-	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v1(eth))
+ 		val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
+ 
+ 	if (IS_ENABLED(CONFIG_SOC_MT7621)) {
+@@ -912,7 +912,7 @@ static bool mtk_rx_get_desc(struct mtk_e
+ 	rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
+ 	rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
+ 	rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
+ 		rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
+ 	}
+@@ -970,7 +970,7 @@ static int mtk_init_fq_dma(struct mtk_et
+ 
+ 		txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
+ 		txd->txd4 = 0;
+-		if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
++		if (mtk_is_netsys_v2_or_greater(eth)) {
+ 			txd->txd5 = 0;
+ 			txd->txd6 = 0;
+ 			txd->txd7 = 0;
+@@ -1159,7 +1159,7 @@ static void mtk_tx_set_dma_desc(struct n
+ 	struct mtk_mac *mac = netdev_priv(dev);
+ 	struct mtk_eth *eth = mac->hw;
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		mtk_tx_set_dma_desc_v2(dev, txd, info);
+ 	else
+ 		mtk_tx_set_dma_desc_v1(dev, txd, info);
+@@ -1466,7 +1466,7 @@ static void mtk_update_rx_cpu_idx(struct
+ 
+ static bool mtk_page_pool_enabled(struct mtk_eth *eth)
+ {
+-	return MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2);
++	return eth->soc->version == 2;
+ }
+ 
+ static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,
+@@ -1806,7 +1806,7 @@ static int mtk_poll_rx(struct napi_struc
+ 			break;
+ 
+ 		/* find out which mac the packet come from. values start at 1 */
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++		if (mtk_is_netsys_v2_or_greater(eth))
+ 			mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
+ 		else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
+ 			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
+@@ -1902,7 +1902,7 @@ static int mtk_poll_rx(struct napi_struc
+ 		skb->dev = netdev;
+ 		bytes += skb->len;
+ 
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++		if (mtk_is_netsys_v2_or_greater(eth)) {
+ 			reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
+ 			hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
+ 			if (hash != MTK_RXD5_FOE_ENTRY)
+@@ -1927,8 +1927,8 @@ static int mtk_poll_rx(struct napi_struc
+ 		/* When using VLAN untagging in combination with DSA, the
+ 		 * hardware treats the MTK special tag as a VLAN and untags it.
+ 		 */
+-		if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) &&
+-		    (trxd.rxd2 & RX_DMA_VTAG) && netdev_uses_dsa(netdev)) {
++		if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) &&
++		    netdev_uses_dsa(netdev)) {
+ 			unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
+ 
+ 			if (port < ARRAY_SIZE(eth->dsa_meta) &&
+@@ -2232,7 +2232,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+ 		txd->txd2 = next_ptr;
+ 		txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
+ 		txd->txd4 = 0;
+-		if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
++		if (mtk_is_netsys_v2_or_greater(eth)) {
+ 			txd->txd5 = 0;
+ 			txd->txd6 = 0;
+ 			txd->txd7 = 0;
+@@ -2285,14 +2285,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+ 			      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
+ 			      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
+ 			      MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
+-			if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++			if (mtk_is_netsys_v1(eth))
+ 				val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
+ 			mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
+ 			ofs += MTK_QTX_OFFSET;
+ 		}
+ 		val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16);
+ 		mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate);
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++		if (mtk_is_netsys_v2_or_greater(eth))
+ 			mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);
+ 	} else {
+ 		mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
+@@ -2419,7 +2419,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+ 
+ 		rxd->rxd3 = 0;
+ 		rxd->rxd4 = 0;
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++		if (mtk_is_netsys_v2_or_greater(eth)) {
+ 			rxd->rxd5 = 0;
+ 			rxd->rxd6 = 0;
+ 			rxd->rxd7 = 0;
+@@ -2967,7 +2967,7 @@ static int mtk_start_dma(struct mtk_eth
+ 		       MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
+ 		       MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
+ 
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++		if (mtk_is_netsys_v2_or_greater(eth))
+ 			val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
+ 			       MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
+ 			       MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN;
+@@ -3111,7 +3111,7 @@ static int mtk_open(struct net_device *d
+ 	phylink_start(mac->phylink);
+ 	netif_tx_start_all_queues(dev);
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return 0;
+ 
+ 	if (mtk_uses_dsa(dev) && !eth->prog) {
+@@ -3376,7 +3376,7 @@ static void mtk_hw_reset(struct mtk_eth
+ {
+ 	u32 val;
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
+ 		val = RSTCTRL_PPE0_V2;
+ 	} else {
+@@ -3388,7 +3388,7 @@ static void mtk_hw_reset(struct mtk_eth
+ 
+ 	ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
+ 			     0x3ffffff);
+ }
+@@ -3414,7 +3414,7 @@ static void mtk_hw_warm_reset(struct mtk
+ 		return;
+ 	}
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
+ 	else
+ 		rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
+@@ -3584,7 +3584,7 @@ static int mtk_hw_init(struct mtk_eth *e
+ 	else
+ 		mtk_hw_reset(eth);
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		/* Set FE to PDMAv2 if necessary */
+ 		val = mtk_r32(eth, MTK_FE_GLO_MISC);
+ 		mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);
+@@ -3621,7 +3621,7 @@ static int mtk_hw_init(struct mtk_eth *e
+ 	 */
+ 	val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
+ 	mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
+-	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v1(eth)) {
+ 		val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
+ 		mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
+ 
+@@ -3643,7 +3643,7 @@ static int mtk_hw_init(struct mtk_eth *e
+ 	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
+ 	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		/* PSE should not drop port8 and port9 packets from WDMA Tx */
+ 		mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
+ 
+@@ -4432,7 +4432,7 @@ static int mtk_probe(struct platform_dev
+ 		}
+ 	}
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 		if (!res) {
+ 			err = -EINVAL;
+@@ -4540,9 +4540,8 @@ static int mtk_probe(struct platform_dev
+ 	}
+ 
+ 	if (eth->soc->offload_version) {
+-		u32 num_ppe;
++		u32 num_ppe = mtk_is_netsys_v2_or_greater(eth) ? 2 : 1;
+ 
+-		num_ppe = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1;
+ 		num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe);
+ 		for (i = 0; i < num_ppe; i++) {
+ 			u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
+@@ -4636,6 +4635,7 @@ static const struct mtk_soc_data mt2701_
+ 	.hw_features = MTK_HW_FEATURES,
+ 	.required_clks = MT7623_CLKS_BITMAP,
+ 	.required_pctl = true,
++	.version = 1,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+@@ -4652,6 +4652,7 @@ static const struct mtk_soc_data mt7621_
+ 	.hw_features = MTK_HW_FEATURES,
+ 	.required_clks = MT7621_CLKS_BITMAP,
+ 	.required_pctl = false,
++	.version = 1,
+ 	.offload_version = 1,
+ 	.hash_offset = 2,
+ 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
+@@ -4672,6 +4673,7 @@ static const struct mtk_soc_data mt7622_
+ 	.hw_features = MTK_HW_FEATURES,
+ 	.required_clks = MT7622_CLKS_BITMAP,
+ 	.required_pctl = false,
++	.version = 1,
+ 	.offload_version = 2,
+ 	.hash_offset = 2,
+ 	.has_accounting = true,
+@@ -4692,6 +4694,7 @@ static const struct mtk_soc_data mt7623_
+ 	.hw_features = MTK_HW_FEATURES,
+ 	.required_clks = MT7623_CLKS_BITMAP,
+ 	.required_pctl = true,
++	.version = 1,
+ 	.offload_version = 1,
+ 	.hash_offset = 2,
+ 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
+@@ -4714,6 +4717,7 @@ static const struct mtk_soc_data mt7629_
+ 	.required_clks = MT7629_CLKS_BITMAP,
+ 	.required_pctl = false,
+ 	.has_accounting = true,
++	.version = 1,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+@@ -4731,6 +4735,7 @@ static const struct mtk_soc_data mt7981_
+ 	.hw_features = MTK_HW_FEATURES,
+ 	.required_clks = MT7981_CLKS_BITMAP,
+ 	.required_pctl = false,
++	.version = 2,
+ 	.offload_version = 2,
+ 	.hash_offset = 4,
+ 	.has_accounting = true,
+@@ -4752,6 +4757,7 @@ static const struct mtk_soc_data mt7986_
+ 	.hw_features = MTK_HW_FEATURES,
+ 	.required_clks = MT7986_CLKS_BITMAP,
+ 	.required_pctl = false,
++	.version = 2,
+ 	.offload_version = 2,
+ 	.hash_offset = 4,
+ 	.has_accounting = true,
+@@ -4772,6 +4778,7 @@ static const struct mtk_soc_data rt5350_
+ 	.hw_features = MTK_HW_FEATURES_MT7628,
+ 	.required_clks = MT7628_CLKS_BITMAP,
+ 	.required_pctl = false,
++	.version = 1,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -817,7 +817,6 @@ enum mkt_eth_capabilities {
+ 	MTK_SHARED_INT_BIT,
+ 	MTK_TRGMII_MT7621_CLK_BIT,
+ 	MTK_QDMA_BIT,
+-	MTK_NETSYS_V2_BIT,
+ 	MTK_SOC_MT7628_BIT,
+ 	MTK_RSTCTRL_PPE1_BIT,
+ 	MTK_U3_COPHY_V2_BIT,
+@@ -852,7 +851,6 @@ enum mkt_eth_capabilities {
+ #define MTK_SHARED_INT		BIT(MTK_SHARED_INT_BIT)
+ #define MTK_TRGMII_MT7621_CLK	BIT(MTK_TRGMII_MT7621_CLK_BIT)
+ #define MTK_QDMA		BIT(MTK_QDMA_BIT)
+-#define MTK_NETSYS_V2		BIT(MTK_NETSYS_V2_BIT)
+ #define MTK_SOC_MT7628		BIT(MTK_SOC_MT7628_BIT)
+ #define MTK_RSTCTRL_PPE1	BIT(MTK_RSTCTRL_PPE1_BIT)
+ #define MTK_U3_COPHY_V2		BIT(MTK_U3_COPHY_V2_BIT)
+@@ -931,11 +929,11 @@ enum mkt_eth_capabilities {
+ #define MT7981_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
+ 		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
+ 		      MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
+-		      MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
++		      MTK_RSTCTRL_PPE1)
+ 
+ #define MT7986_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
+ 		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
+-		      MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
++		      MTK_RSTCTRL_PPE1)
+ 
+ struct mtk_tx_dma_desc_info {
+ 	dma_addr_t	addr;
+@@ -1006,6 +1004,7 @@ struct mtk_reg_map {
+  * @required_pctl		A bool value to show whether the SoC requires
+  *				the extra setup for those pins used by GMAC.
+  * @hash_offset			Flow table hash offset.
++ * @version			SoC version.
+  * @foe_entry_size		Foe table entry size.
+  * @has_accounting		Bool indicating support for accounting of
+  *				offloaded flows.
+@@ -1024,6 +1023,7 @@ struct mtk_soc_data {
+ 	bool		required_pctl;
+ 	u8		offload_version;
+ 	u8		hash_offset;
++	u8		version;
+ 	u16		foe_entry_size;
+ 	netdev_features_t hw_features;
+ 	bool		has_accounting;
+@@ -1180,6 +1180,16 @@ struct mtk_mac {
+ /* the struct describing the SoC. these are declared in the soc_xyz.c files */
+ extern const struct of_device_id of_mtk_match[];
+ 
++static inline bool mtk_is_netsys_v1(struct mtk_eth *eth)
++{
++	return eth->soc->version == 1;
++}
++
++static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth)
++{
++	return eth->soc->version > 1;
++}
++
+ static inline struct mtk_foe_entry *
+ mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash)
+ {
+@@ -1190,7 +1200,7 @@ mtk_foe_get_entry(struct mtk_ppe *ppe, u
+ 
+ static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return MTK_FOE_IB1_BIND_TIMESTAMP_V2;
+ 
+ 	return MTK_FOE_IB1_BIND_TIMESTAMP;
+@@ -1198,7 +1208,7 @@ static inline u32 mtk_get_ib1_ts_mask(st
+ 
+ static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return MTK_FOE_IB1_BIND_PPPOE_V2;
+ 
+ 	return MTK_FOE_IB1_BIND_PPPOE;
+@@ -1206,7 +1216,7 @@ static inline u32 mtk_get_ib1_ppoe_mask(
+ 
+ static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return MTK_FOE_IB1_BIND_VLAN_TAG_V2;
+ 
+ 	return MTK_FOE_IB1_BIND_VLAN_TAG;
+@@ -1214,7 +1224,7 @@ static inline u32 mtk_get_ib1_vlan_tag_m
+ 
+ static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return MTK_FOE_IB1_BIND_VLAN_LAYER_V2;
+ 
+ 	return MTK_FOE_IB1_BIND_VLAN_LAYER;
+@@ -1222,7 +1232,7 @@ static inline u32 mtk_get_ib1_vlan_layer
+ 
+ static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);
+ 
+ 	return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
+@@ -1230,7 +1240,7 @@ static inline u32 mtk_prep_ib1_vlan_laye
+ 
+ static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);
+ 
+ 	return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
+@@ -1238,7 +1248,7 @@ static inline u32 mtk_get_ib1_vlan_layer
+ 
+ static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return MTK_FOE_IB1_PACKET_TYPE_V2;
+ 
+ 	return MTK_FOE_IB1_PACKET_TYPE;
+@@ -1246,7 +1256,7 @@ static inline u32 mtk_get_ib1_pkt_type_m
+ 
+ static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val);
+ 
+ 	return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val);
+@@ -1254,7 +1264,7 @@ static inline u32 mtk_get_ib1_pkt_type(s
+ 
+ static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return MTK_FOE_IB2_MULTICAST_V2;
+ 
+ 	return MTK_FOE_IB2_MULTICAST;
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
+@@ -207,7 +207,7 @@ int mtk_foe_entry_prepare(struct mtk_eth
+ 
+ 	memset(entry, 0, sizeof(*entry));
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		val = FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_BIND) |
+ 		      FIELD_PREP(MTK_FOE_IB1_PACKET_TYPE_V2, type) |
+ 		      FIELD_PREP(MTK_FOE_IB1_UDP, l4proto == IPPROTO_UDP) |
+@@ -271,7 +271,7 @@ int mtk_foe_entry_set_pse_port(struct mt
+ 	u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
+ 	u32 val = *ib2;
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		val &= ~MTK_FOE_IB2_DEST_PORT_V2;
+ 		val |= FIELD_PREP(MTK_FOE_IB2_DEST_PORT_V2, port);
+ 	} else {
+@@ -422,7 +422,7 @@ int mtk_foe_entry_set_wdma(struct mtk_et
+ 	struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry);
+ 	u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		*ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
+ 		*ib2 |=  FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |
+ 			 MTK_FOE_IB2_WDMA_WINFO_V2;
+@@ -452,7 +452,7 @@ int mtk_foe_entry_set_queue(struct mtk_e
+ {
+ 	u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		*ib2 &= ~MTK_FOE_IB2_QID_V2;
+ 		*ib2 |= FIELD_PREP(MTK_FOE_IB2_QID_V2, queue);
+ 		*ib2 |= MTK_FOE_IB2_PSE_QOS_V2;
+@@ -607,7 +607,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
+ 	struct mtk_foe_entry *hwe;
+ 	u32 val;
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP_V2;
+ 		entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP_V2,
+ 					 timestamp);
+@@ -623,7 +623,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
+ 	hwe->ib1 = entry->ib1;
+ 
+ 	if (ppe->accounting) {
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++		if (mtk_is_netsys_v2_or_greater(eth))
+ 			val = MTK_FOE_IB2_MIB_CNT_V2;
+ 		else
+ 			val = MTK_FOE_IB2_MIB_CNT;
+@@ -971,7 +971,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
+ 			 MTK_PPE_SCAN_MODE_KEEPALIVE_AGE) |
+ 	      FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM,
+ 			 MTK_PPE_ENTRIES_SHIFT);
+-	if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(ppe->eth))
+ 		val |= MTK_PPE_TB_CFG_INFO_SEL;
+ 	ppe_w32(ppe, MTK_PPE_TB_CFG, val);
+ 
+@@ -987,7 +987,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
+ 	      MTK_PPE_FLOW_CFG_IP4_NAPT |
+ 	      MTK_PPE_FLOW_CFG_IP4_DSLITE |
+ 	      MTK_PPE_FLOW_CFG_IP4_NAT_FRAG;
+-	if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(ppe->eth))
+ 		val |= MTK_PPE_MD_TOAP_BYP_CRSN0 |
+ 		       MTK_PPE_MD_TOAP_BYP_CRSN1 |
+ 		       MTK_PPE_MD_TOAP_BYP_CRSN2 |
+@@ -1029,7 +1029,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
+ 
+ 	ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0);
+ 
+-	if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(ppe->eth)) {
+ 		ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777);
+ 		ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f);
+ 	}
+--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
+@@ -193,7 +193,7 @@ mtk_flow_set_output_device(struct mtk_et
+ 	if (mtk_flow_get_wdma_info(dev, dest_mac, &info) == 0) {
+ 		mtk_foe_entry_set_wdma(eth, foe, info.wdma_idx, info.queue,
+ 				       info.bss, info.wcid);
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++		if (mtk_is_netsys_v2_or_greater(eth)) {
+ 			switch (info.wdma_idx) {
+ 			case 0:
+ 				pse_port = 8;
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -1091,7 +1091,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+ 	} else {
+ 		struct mtk_eth *eth = dev->hw->eth;
+ 
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++		if (mtk_is_netsys_v2_or_greater(eth))
+ 			wed_set(dev, MTK_WED_RESET_IDX,
+ 				MTK_WED_RESET_IDX_RX_V2);
+ 		else
+@@ -1813,7 +1813,7 @@ void mtk_wed_add_hw(struct device_node *
+ 	hw->wdma = wdma;
+ 	hw->index = index;
+ 	hw->irq = irq;
+-	hw->version = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1;
++	hw->version = mtk_is_netsys_v1(eth) ? 1 : 2;
+ 
+ 	if (hw->version == 1) {
+ 		hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,

lede/target/linux/generic/backport-5.15/750-v6.5-06-net-ethernet-mtk_eth_soc-increase-MAX_DEVS-to-3.patch

@@ -0,0 +1,29 @@
+From f8fb8dbd158c585be7574faf92db7d614b6722ff Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 25 Jul 2023 01:52:27 +0100
+Subject: [PATCH 100/250] net: ethernet: mtk_eth_soc: increase MAX_DEVS to 3
+
+This is a preliminary patch to add MT7988 SoC support since it runs 3
+macs instead of 2.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/3563e5fab367e7d79a7f1296fabaa5c20f202d7a.1690246066.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -1040,8 +1040,8 @@ struct mtk_soc_data {
+ 
+ #define MTK_DMA_MONITOR_TIMEOUT		msecs_to_jiffies(1000)
+ 
+-/* currently no SoC has more than 2 macs */
+-#define MTK_MAX_DEVS			2
++/* currently no SoC has more than 3 macs */
++#define MTK_MAX_DEVS	3
+ 
+ /* struct mtk_eth -	This is the main datasructure for holding the state
+  *			of the driver

lede/target/linux/generic/backport-5.15/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch

@@ -1,143 +1,176 @@
-From 4e35e80750b33727e606be9e7ce447bde2e0deb7 Mon Sep 17 00:00:00 2001
+From 856be974290f28d7943be2ac5a382c4139486196 Mon Sep 17 00:00:00 2001
 From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Tue, 7 Mar 2023 15:55:35 +0000
-Subject: [PATCH 3/7] net: ethernet: mtk_eth_soc: rely on num_devs and remove
- MTK_MAC_COUNT
+Date: Tue, 25 Jul 2023 01:52:44 +0100
+Subject: [PATCH 101/250] net: ethernet: mtk_eth_soc: rely on MTK_MAX_DEVS and
+ remove MTK_MAC_COUNT
 
-Get rid of MTK_MAC_COUNT since it is a duplicated of eth->soc->num_devs.
+Get rid of MTK_MAC_COUNT since it is a duplicated of MTK_MAX_DEVS.
 
 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/1856f4266f2fc80677807b1bad867659e7b00c65.1690246066.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 ---
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 ++++++++++-----------
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 49 ++++++++++++---------
  drivers/net/ethernet/mediatek/mtk_eth_soc.h |  1 -
- 2 files changed, 15 insertions(+), 16 deletions(-)
+ 2 files changed, 27 insertions(+), 23 deletions(-)
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -899,7 +899,7 @@ static void mtk_stats_update(struct mtk_
+@@ -838,7 +838,7 @@ static void mtk_stats_update(struct mtk_
  {
  	int i;
  
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		if (!eth->mac[i] || !eth->mac[i]->hw_stats)
  			continue;
  		if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
-@@ -1402,7 +1402,7 @@ static int mtk_queue_stopped(struct mtk_
+@@ -1341,7 +1341,7 @@ static int mtk_queue_stopped(struct mtk_
  {
  	int i;
  
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		if (!eth->netdev[i])
  			continue;
  		if (netif_queue_stopped(eth->netdev[i]))
-@@ -1416,7 +1416,7 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1355,7 +1355,7 @@ static void mtk_wake_queue(struct mtk_et
  {
  	int i;
  
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		if (!eth->netdev[i])
  			continue;
  		netif_tx_wake_all_queues(eth->netdev[i]);
-@@ -1907,7 +1907,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1812,7 +1812,7 @@ static int mtk_poll_rx(struct napi_struc
  			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
  			mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
  
 -		if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
-+		if (unlikely(mac < 0 || mac >= eth->soc->num_devs ||
++		if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS ||
  			     !eth->netdev[mac]))
  			goto release_desc;
  
-@@ -2939,7 +2939,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -2841,7 +2841,7 @@ static void mtk_dma_free(struct mtk_eth
  	const struct mtk_soc_data *soc = eth->soc;
  	int i;
  
 -	for (i = 0; i < MTK_MAC_COUNT; i++)
-+	for (i = 0; i < soc->num_devs; i++)
++	for (i = 0; i < MTK_MAX_DEVS; i++)
  		if (eth->netdev[i])
  			netdev_reset_queue(eth->netdev[i]);
  	if (eth->scratch_ring) {
-@@ -3093,7 +3093,7 @@ static void mtk_gdm_config(struct mtk_et
+@@ -2995,8 +2995,13 @@ static void mtk_gdm_config(struct mtk_et
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
  		return;
  
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
- 		u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
+-		u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
++		u32 val;
++
++		if (!eth->netdev[i])
++			continue;
++
++		val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
  
  		/* default setup the forward port to send frame to PDMA */
-@@ -3706,7 +3706,7 @@ static int mtk_hw_init(struct mtk_eth *e
+ 		val &= ~0xffff;
+@@ -3006,7 +3011,7 @@ static void mtk_gdm_config(struct mtk_et
+ 
+ 		val |= config;
+ 
+-		if (eth->netdev[i] && netdev_uses_dsa(eth->netdev[i]))
++		if (netdev_uses_dsa(eth->netdev[i]))
+ 			val |= MTK_GDMA_SPECIAL_TAG;
+ 
+ 		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
+@@ -3605,15 +3610,15 @@ static int mtk_hw_init(struct mtk_eth *e
  	 * up with the more appropriate value when mtk_mac_config call is being
  	 * invoked.
  	 */
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		struct net_device *dev = eth->netdev[i];
  
- 		mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
-@@ -3894,7 +3894,7 @@ static void mtk_pending_work(struct work
+-		mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
+-		if (dev) {
+-			struct mtk_mac *mac = netdev_priv(dev);
++		if (!dev)
++			continue;
+ 
+-			mtk_set_mcr_max_rx(mac, dev->mtu + MTK_RX_ETH_HLEN);
+-		}
++		mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
++		mtk_set_mcr_max_rx(netdev_priv(dev),
++				   dev->mtu + MTK_RX_ETH_HLEN);
+ 	}
+ 
+ 	/* Indicates CDM to parse the MTK special tag from CPU
+@@ -3793,7 +3798,7 @@ static void mtk_pending_work(struct work
  	mtk_prepare_for_reset(eth);
  
  	/* stop all devices to make sure that dma is properly shut down */
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		if (!eth->netdev[i] || !netif_running(eth->netdev[i]))
  			continue;
  
-@@ -3910,7 +3910,7 @@ static void mtk_pending_work(struct work
+@@ -3809,8 +3814,8 @@ static void mtk_pending_work(struct work
  	mtk_hw_init(eth, true);
  
  	/* restart DMA and enable IRQs */
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
- 		if (!test_bit(i, &restart))
+-		if (!test_bit(i, &restart))
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
++		if (!eth->netdev[i] || !test_bit(i, &restart))
  			continue;
  
-@@ -3938,7 +3938,7 @@ static int mtk_free_dev(struct mtk_eth *
+ 		if (mtk_open(eth->netdev[i])) {
+@@ -3837,7 +3842,7 @@ static int mtk_free_dev(struct mtk_eth *
  {
  	int i;
  
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		if (!eth->netdev[i])
  			continue;
  		free_netdev(eth->netdev[i]);
-@@ -3957,7 +3957,7 @@ static int mtk_unreg_dev(struct mtk_eth
+@@ -3856,7 +3861,7 @@ static int mtk_unreg_dev(struct mtk_eth
  {
  	int i;
  
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		struct mtk_mac *mac;
  		if (!eth->netdev[i])
  			continue;
-@@ -4261,7 +4261,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4157,7 +4162,7 @@ static int mtk_add_mac(struct mtk_eth *e
  	}
  
  	id = be32_to_cpup(_id);
 -	if (id >= MTK_MAC_COUNT) {
-+	if (id >= eth->soc->num_devs) {
++	if (id >= MTK_MAX_DEVS) {
  		dev_err(eth->dev, "%d is not a valid mac id\n", id);
  		return -EINVAL;
  	}
-@@ -4402,7 +4402,7 @@ void mtk_eth_set_dma_device(struct mtk_e
+@@ -4302,7 +4307,7 @@ void mtk_eth_set_dma_device(struct mtk_e
  
  	rtnl_lock();
  
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		dev = eth->netdev[i];
  
  		if (!dev || !(dev->flags & IFF_UP))
-@@ -4729,7 +4729,7 @@ static int mtk_remove(struct platform_de
+@@ -4610,7 +4615,7 @@ static int mtk_remove(struct platform_de
  	int i;
  
  	/* stop all devices to make sure that dma is properly shut down */
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		if (!eth->netdev[i])
  			continue;
  		mtk_stop(eth->netdev[i]);

lede/target/linux/generic/backport-5.15/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch

@@ -1,22 +1,24 @@
-From ab817f559d505329d8a413c7d29250f6d87d77a0 Mon Sep 17 00:00:00 2001
+From a41d535855976838d246c079143c948dcf0f7931 Mon Sep 17 00:00:00 2001
 From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Tue, 7 Mar 2023 15:55:47 +0000
-Subject: [PATCH 4/7] net: ethernet: mtk_eth_soc: add MTK_NETSYS_V3 capability
- bit
+Date: Tue, 25 Jul 2023 01:52:59 +0100
+Subject: [PATCH 102/250] net: ethernet: mtk_eth_soc: add NETSYS_V3 version
+ support
 
-Introduce MTK_NETSYS_V3 bit in the device capabilities.
+Introduce NETSYS_V3 chipset version support.
 This is a preliminary patch to introduce support for MT7988 SoC.
 
 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/0db2260910755d76fa48e303b9f9bdf4e5a82340.1690246066.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 ---
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 115 ++++++++++++++++----
- drivers/net/ethernet/mediatek/mtk_eth_soc.h |  44 +++++++-
- 2 files changed, 134 insertions(+), 25 deletions(-)
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 105 ++++++++++++++------
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h |  48 +++++++--
+ 2 files changed, 116 insertions(+), 37 deletions(-)
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -923,17 +923,32 @@ void mtk_stats_update_mac(struct mtk_mac
+@@ -818,17 +818,32 @@ void mtk_stats_update_mac(struct mtk_mac
  			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);
  		hw_stats->rx_flow_control_packets +=
  			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);
@@ -32,7 +34,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 -		hw_stats->tx_packets +=
 -			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs);
 +
-+		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
++		if (mtk_is_netsys_v3_or_greater(eth)) {
 +			hw_stats->tx_skip +=
 +				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs);
 +			hw_stats->tx_collisions +=
@@ -60,7 +62,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	}
  
  	u64_stats_update_end(&hw_stats->syncp);
-@@ -1237,7 +1252,10 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1130,7 +1145,10 @@ static void mtk_tx_set_dma_desc_v2(struc
  		data |= TX_DMA_LS0;
  	WRITE_ONCE(desc->txd3, data);
  
@@ -72,57 +74,53 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
  	WRITE_ONCE(desc->txd4, data);
  
-@@ -1248,6 +1266,9 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1141,6 +1159,8 @@ static void mtk_tx_set_dma_desc_v2(struc
  		/* tx checksum offload */
  		if (info->csum)
  			data |= TX_DMA_CHKSUM_V2;
-+		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) &&
-+		    netdev_uses_dsa(dev))
++		if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev))
 +			data |= TX_DMA_SPTAG_V3;
  	}
  	WRITE_ONCE(desc->txd5, data);
  
-@@ -1313,8 +1334,13 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1206,8 +1226,7 @@ static int mtk_tx_map(struct sk_buff *sk
  	mtk_tx_set_dma_desc(dev, itxd, &txd_info);
  
  	itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
 -	itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
 -			  MTK_TX_FLAGS_FPORT1;
-+	if (mac->id == MTK_GMAC1_ID)
-+		itx_buf->flags |= MTK_TX_FLAGS_FPORT0;
-+	else if (mac->id == MTK_GMAC2_ID)
-+		itx_buf->flags |= MTK_TX_FLAGS_FPORT1;
-+	else
-+		itx_buf->flags |= MTK_TX_FLAGS_FPORT2;
-+
++	itx_buf->mac_id = mac->id;
  	setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size,
  		     k++);
  
-@@ -1362,8 +1388,13 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1255,8 +1274,7 @@ static int mtk_tx_map(struct sk_buff *sk
  				memset(tx_buf, 0, sizeof(*tx_buf));
  			tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
  			tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
 -			tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
 -					 MTK_TX_FLAGS_FPORT1;
-+
-+			if (mac->id == MTK_GMAC1_ID)
-+				tx_buf->flags |= MTK_TX_FLAGS_FPORT0;
-+			else if (mac->id == MTK_GMAC2_ID)
-+				tx_buf->flags |= MTK_TX_FLAGS_FPORT1;
-+			else
-+				tx_buf->flags |= MTK_TX_FLAGS_FPORT2;
++			tx_buf->mac_id = mac->id;
  
  			setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr,
  				     txd_info.size, k++);
-@@ -1949,11 +1980,24 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1558,7 +1576,7 @@ static int mtk_xdp_frame_map(struct mtk_
+ 	}
+ 	mtk_tx_set_dma_desc(dev, txd, txd_info);
+ 
+-	tx_buf->flags |= !mac->id ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1;
++	tx_buf->mac_id = mac->id;
+ 	tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX;
+ 	tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
+ 
+@@ -1806,11 +1824,24 @@ static int mtk_poll_rx(struct napi_struc
  			break;
  
  		/* find out which mac the packet come from. values start at 1 */
--		if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
+-		if (mtk_is_netsys_v2_or_greater(eth))
 -			mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
 -		else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
 -			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
-+		if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
++		if (mtk_is_netsys_v2_or_greater(eth)) {
 +			u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
 +
 +			switch (val) {
@@ -137,29 +135,44 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +				break;
 +			}
 +		} else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
-+			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) {
++			   !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) {
  			mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
 +		}
  
- 		if (unlikely(mac < 0 || mac >= eth->soc->num_devs ||
+ 		if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS ||
  			     !eth->netdev[mac]))
-@@ -2184,7 +2228,9 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2030,7 +2061,6 @@ static int mtk_poll_tx_qdma(struct mtk_e
+ 
+ 	while ((cpu != dma) && budget) {
+ 		u32 next_cpu = desc->txd2;
+-		int mac = 0;
+ 
+ 		desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
+ 		if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
+@@ -2038,15 +2068,13 @@ static int mtk_poll_tx_qdma(struct mtk_e
+ 
  		tx_buf = mtk_desc_to_tx_buf(ring, desc,
  					    eth->soc->txrx.txd_size);
- 		if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
+-		if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
 -			mac = 1;
-+			mac = MTK_GMAC2_ID;
-+		else if (tx_buf->flags & MTK_TX_FLAGS_FPORT2)
-+			mac = MTK_GMAC3_ID;
- 
+-
  		if (!tx_buf->data)
  			break;
-@@ -3798,7 +3844,26 @@ static int mtk_hw_init(struct mtk_eth *e
+ 
+ 		if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
+ 			if (tx_buf->type == MTK_TYPE_SKB)
+-				mtk_poll_tx_done(eth, state, mac, tx_buf->data);
++				mtk_poll_tx_done(eth, state, tx_buf->mac_id,
++						 tx_buf->data);
+ 
+ 			budget--;
+ 		}
+@@ -3648,7 +3676,24 @@ static int mtk_hw_init(struct mtk_eth *e
  	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
  	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
  
--	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
-+	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
+-	if (mtk_is_netsys_v2_or_greater(eth)) {
++	if (mtk_is_netsys_v3_or_greater(eth)) {
 +		/* PSE should not drop port1, port8 and port9 packets */
 +		mtk_w32(eth, 0x00000302, PSE_DROP_CFG);
 +
@@ -168,9 +181,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +		mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
 +
 +		/* Disable GDM1 RX CRC stripping */
-+		val = mtk_r32(eth, MTK_GDMA_FWD_CFG(0));
-+		val &= ~MTK_GDMA_STRP_CRC;
-+		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(0));
++		mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0));
 +
 +		/* PSE GDM3 MIB counter has incorrect hw default values,
 +		 * so the driver ought to read clear the values beforehand
@@ -178,17 +189,17 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +		 */
 +		for (i = 0; i < 0x80; i += 0x4)
 +			mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i);
-+	} else if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	} else if (!mtk_is_netsys_v1(eth)) {
  		/* PSE should not drop port8 and port9 packets from WDMA Tx */
  		mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
  
-@@ -4363,7 +4428,11 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4210,7 +4255,11 @@ static int mtk_add_mac(struct mtk_eth *e
  	}
  	spin_lock_init(&mac->hw_stats->stats_lock);
  	u64_stats_init(&mac->hw_stats->syncp);
 -	mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
 +
-+	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3))
++	if (mtk_is_netsys_v3_or_greater(eth))
 +		mac->hw_stats->reg_offset = id * 0x80;
 +	else
 +		mac->hw_stats->reg_offset = id * 0x40;
@@ -197,7 +208,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	err = of_get_phy_mode(np, &phy_mode);
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -121,6 +121,7 @@
+@@ -122,6 +122,7 @@
  #define MTK_GDMA_ICS_EN		BIT(22)
  #define MTK_GDMA_TCS_EN		BIT(21)
  #define MTK_GDMA_UCS_EN		BIT(20)
@@ -205,7 +216,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  #define MTK_GDMA_TO_PDMA	0x0
  #define MTK_GDMA_DROP_ALL       0x7777
  
-@@ -286,8 +287,6 @@
+@@ -287,8 +288,6 @@
  /* QDMA Interrupt grouping registers */
  #define MTK_RLS_DONE_INT	BIT(0)
  
@@ -214,7 +225,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  /* QDMA TX NUM */
  #define QID_BITS_V2(x)		(((x) & 0x3f) << 16)
  #define MTK_QDMA_GMAC2_QID	8
-@@ -300,6 +299,8 @@
+@@ -301,6 +300,8 @@
  #define TX_DMA_CHKSUM_V2	(0x7 << 28)
  #define TX_DMA_TSO_V2		BIT(31)
  
@@ -223,15 +234,20 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  /* QDMA V2 descriptor txd4 */
  #define TX_DMA_FPORT_SHIFT_V2	8
  #define TX_DMA_FPORT_MASK_V2	0xf
-@@ -639,6 +640,7 @@ enum mtk_tx_flags {
+@@ -631,12 +632,6 @@ enum mtk_tx_flags {
  	 */
- 	MTK_TX_FLAGS_FPORT0	= 0x04,
- 	MTK_TX_FLAGS_FPORT1	= 0x08,
-+	MTK_TX_FLAGS_FPORT2	= 0x10,
+ 	MTK_TX_FLAGS_SINGLE0	= 0x01,
+ 	MTK_TX_FLAGS_PAGE0	= 0x02,
+-
+-	/* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted
+-	 * SKB out instead of looking up through hardware TX descriptor.
+-	 */
+-	MTK_TX_FLAGS_FPORT0	= 0x04,
+-	MTK_TX_FLAGS_FPORT1	= 0x08,
  };
  
  /* This enum allows us to identify how the clock is defined on the array of the
-@@ -724,6 +726,42 @@ enum mtk_dev_state {
+@@ -722,6 +717,35 @@ enum mtk_dev_state {
  	MTK_RESETTING
  };
  
@@ -263,30 +279,29 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	MTK_GMAC3_ID,
 +	MTK_GMAC_ID_MAX
 +};
-+
-+/* GDM Type */
-+enum mtk_gdm_type {
-+	MTK_GDM_TYPE = 0,
-+	MTK_XGDM_TYPE,
-+	MTK_GDM_TYPE_MAX
-+};
 +
  enum mtk_tx_buf_type {
  	MTK_TYPE_SKB,
  	MTK_TYPE_XDP_TX,
-@@ -820,6 +858,7 @@ enum mkt_eth_capabilities {
- 	MTK_QDMA_BIT,
- 	MTK_NETSYS_V1_BIT,
- 	MTK_NETSYS_V2_BIT,
-+	MTK_NETSYS_V3_BIT,
- 	MTK_SOC_MT7628_BIT,
- 	MTK_RSTCTRL_PPE1_BIT,
- 	MTK_U3_COPHY_V2_BIT,
-@@ -856,6 +895,7 @@ enum mkt_eth_capabilities {
- #define MTK_QDMA		BIT(MTK_QDMA_BIT)
- #define MTK_NETSYS_V1		BIT(MTK_NETSYS_V1_BIT)
- #define MTK_NETSYS_V2		BIT(MTK_NETSYS_V2_BIT)
-+#define MTK_NETSYS_V3		BIT(MTK_NETSYS_V3_BIT)
- #define MTK_SOC_MT7628		BIT(MTK_SOC_MT7628_BIT)
- #define MTK_RSTCTRL_PPE1	BIT(MTK_RSTCTRL_PPE1_BIT)
- #define MTK_U3_COPHY_V2		BIT(MTK_U3_COPHY_V2_BIT)
+@@ -740,7 +764,8 @@ struct mtk_tx_buf {
+ 	enum mtk_tx_buf_type type;
+ 	void *data;
+ 
+-	u32 flags;
++	u16 mac_id;
++	u16 flags;
+ 	DEFINE_DMA_UNMAP_ADDR(dma_addr0);
+ 	DEFINE_DMA_UNMAP_LEN(dma_len0);
+ 	DEFINE_DMA_UNMAP_ADDR(dma_addr1);
+@@ -1189,6 +1214,11 @@ static inline bool mtk_is_netsys_v2_or_g
+ 	return eth->soc->version > 1;
+ }
+ 
++static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth)
++{
++	return eth->soc->version > 2;
++}
++
+ static inline struct mtk_foe_entry *
+ mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash)
+ {

lede/target/linux/generic/backport-5.15/750-v6.5-09-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch

@@ -1,17 +1,19 @@
-From 45b575fd9e6a455090820248bf1b98b1f2c7b6c8 Mon Sep 17 00:00:00 2001
+From db797ae0542220a98658229397da464c383c991c Mon Sep 17 00:00:00 2001
 From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Tue, 7 Mar 2023 15:56:00 +0000
-Subject: [PATCH 5/7] net: ethernet: mtk_eth_soc: convert caps in mtk_soc_data
- struct to u64
+Date: Tue, 25 Jul 2023 01:53:13 +0100
+Subject: [PATCH 103/250] net: ethernet: mtk_eth_soc: convert caps in
+ mtk_soc_data struct to u64
 
 This is a preliminary patch to introduce support for MT7988 SoC.
 
 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/9499ac3670b2fc5b444404b84e8a4a169beabbf2.1690246066.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 ---
- drivers/net/ethernet/mediatek/mtk_eth_path.c | 22 +++----
- drivers/net/ethernet/mediatek/mtk_eth_soc.h  | 62 ++++++++++----------
- 2 files changed, 42 insertions(+), 42 deletions(-)
+ drivers/net/ethernet/mediatek/mtk_eth_path.c | 22 ++++----
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h  | 56 ++++++++++----------
+ 2 files changed, 39 insertions(+), 39 deletions(-)
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
@@ -111,7 +113,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  				MTK_ETH_PATH_GMAC2_RGMII;
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -878,44 +878,44 @@ enum mkt_eth_capabilities {
+@@ -863,41 +863,41 @@ enum mkt_eth_capabilities {
  };
  
  /* Supported hardware group on SoCs */
@@ -127,9 +129,6 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 -#define MTK_SHARED_INT		BIT(MTK_SHARED_INT_BIT)
 -#define MTK_TRGMII_MT7621_CLK	BIT(MTK_TRGMII_MT7621_CLK_BIT)
 -#define MTK_QDMA		BIT(MTK_QDMA_BIT)
--#define MTK_NETSYS_V1		BIT(MTK_NETSYS_V1_BIT)
--#define MTK_NETSYS_V2		BIT(MTK_NETSYS_V2_BIT)
--#define MTK_NETSYS_V3		BIT(MTK_NETSYS_V3_BIT)
 -#define MTK_SOC_MT7628		BIT(MTK_SOC_MT7628_BIT)
 -#define MTK_RSTCTRL_PPE1	BIT(MTK_RSTCTRL_PPE1_BIT)
 -#define MTK_U3_COPHY_V2		BIT(MTK_U3_COPHY_V2_BIT)
@@ -145,9 +144,6 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +#define MTK_SHARED_INT		BIT_ULL(MTK_SHARED_INT_BIT)
 +#define MTK_TRGMII_MT7621_CLK	BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT)
 +#define MTK_QDMA		BIT_ULL(MTK_QDMA_BIT)
-+#define MTK_NETSYS_V1		BIT_ULL(MTK_NETSYS_V1_BIT)
-+#define MTK_NETSYS_V2		BIT_ULL(MTK_NETSYS_V2_BIT)
-+#define MTK_NETSYS_V3		BIT_ULL(MTK_NETSYS_V3_BIT)
 +#define MTK_SOC_MT7628		BIT_ULL(MTK_SOC_MT7628_BIT)
 +#define MTK_RSTCTRL_PPE1	BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
 +#define MTK_U3_COPHY_V2		BIT_ULL(MTK_U3_COPHY_V2_BIT)
@@ -186,7 +182,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  #define MTK_GMAC1_RGMII		(MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
  #define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
-@@ -1071,7 +1071,7 @@ struct mtk_reg_map {
+@@ -1042,7 +1042,7 @@ struct mtk_reg_map {
  struct mtk_soc_data {
  	const struct mtk_reg_map *reg_map;
  	u32             ana_rgc3;

lede/target/linux/generic/backport-5.15/750-v6.5-10-net-ethernet-mtk_eth_soc-convert-clock-bitmap-to-u64.patch

@@ -0,0 +1,132 @@
+From a1c9f7d1d24e90294f6a6755b137fcf306851e93 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 25 Jul 2023 01:53:28 +0100
+Subject: [PATCH 104/250] net: ethernet: mtk_eth_soc: convert clock bitmap to
+ u64
+
+The to-be-added MT7988 SoC adds many new clocks which need to be
+controlled by the Ethernet driver, which will result in their total
+number exceeding 32.
+Prepare by converting clock bitmaps into 64-bit types.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/6960a39bb0078cf84d7642a9558e6a91c6cc9df3.1690246066.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 96 +++++++++++----------
+ 1 file changed, 49 insertions(+), 47 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -663,54 +663,56 @@ enum mtk_clks_map {
+ 	MTK_CLK_MAX
+ };
+ 
+-#define MT7623_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \
+-				 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
+-				 BIT(MTK_CLK_TRGPLL))
+-#define MT7622_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \
+-				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
+-				 BIT(MTK_CLK_GP2) | \
+-				 BIT(MTK_CLK_SGMII_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII_CK) | \
+-				 BIT(MTK_CLK_ETH2PLL))
++#define MT7623_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \
++				 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
++				 BIT_ULL(MTK_CLK_TRGPLL))
++#define MT7622_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \
++				 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
++				 BIT_ULL(MTK_CLK_GP2) | \
++				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII_CK) | \
++				 BIT_ULL(MTK_CLK_ETH2PLL))
+ #define MT7621_CLKS_BITMAP	(0)
+ #define MT7628_CLKS_BITMAP	(0)
+-#define MT7629_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \
+-				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
+-				 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
+-				 BIT(MTK_CLK_SGMII_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII2_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII_CK) | \
+-				 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
+-#define MT7981_CLKS_BITMAP	(BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
+-				 BIT(MTK_CLK_WOCPU0) | \
+-				 BIT(MTK_CLK_SGMII_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII2_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII_CK))
+-#define MT7986_CLKS_BITMAP	(BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
+-				 BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
+-				 BIT(MTK_CLK_SGMII_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII2_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_FB))
++#define MT7629_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \
++				 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
++				 BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \
++				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII_CK) | \
++				 BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP))
++#define MT7981_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
++				 BIT_ULL(MTK_CLK_GP1) | \
++				 BIT_ULL(MTK_CLK_WOCPU0) | \
++				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII_CK))
++#define MT7986_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
++				 BIT_ULL(MTK_CLK_GP1) | \
++				 BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \
++				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
+ 
+ enum mtk_dev_state {
+ 	MTK_HW_INIT,
+@@ -1043,7 +1045,7 @@ struct mtk_soc_data {
+ 	const struct mtk_reg_map *reg_map;
+ 	u32             ana_rgc3;
+ 	u64		caps;
+-	u32		required_clks;
++	u64		required_clks;
+ 	bool		required_pctl;
+ 	u8		offload_version;
+ 	u8		hash_offset;

lede/target/linux/generic/backport-5.15/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch

@@ -0,0 +1,477 @@
+From 94f825a7eadfc8b4c8828efdb7705d9703f9c73e Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 25 Jul 2023 01:57:42 +0100
+Subject: [PATCH 105/250] net: ethernet: mtk_eth_soc: add basic support for
+ MT7988 SoC
+
+Introduce support for ethernet chip available in MT7988 SoC to
+mtk_eth_soc driver. As a first step support only the first GMAC which
+is hard-wired to the internal DSA switch having 4 built-in gigabit
+Ethernet PHYs.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/25c8377095b95d186872eeda7aa055da83e8f0ca.1690246605.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_path.c |  14 +-
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c  | 201 +++++++++++++++++--
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h  |  86 +++++++-
+ 3 files changed, 273 insertions(+), 28 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
+@@ -43,7 +43,7 @@ static const char *mtk_eth_path_name(u64
+ static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path)
+ {
+ 	bool updated = true;
+-	u32 val, mask, set;
++	u32 mask, set, reg;
+ 
+ 	switch (path) {
+ 	case MTK_ETH_PATH_GMAC1_SGMII:
+@@ -59,11 +59,13 @@ static int set_mux_gdm1_to_gmac1_esw(str
+ 		break;
+ 	}
+ 
+-	if (updated) {
+-		val = mtk_r32(eth, MTK_MAC_MISC);
+-		val = (val & mask) | set;
+-		mtk_w32(eth, val, MTK_MAC_MISC);
+-	}
++	if (mtk_is_netsys_v3_or_greater(eth))
++		reg = MTK_MAC_MISC_V3;
++	else
++		reg = MTK_MAC_MISC;
++
++	if (updated)
++		mtk_m32(eth, mask, set, reg);
+ 
+ 	dev_dbg(eth->dev, "path %s in %s updated = %d\n",
+ 		mtk_eth_path_name(path), __func__, updated);
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -152,6 +152,54 @@ static const struct mtk_reg_map mt7986_r
+ 	.pse_oq_sta		= 0x01a0,
+ };
+ 
++static const struct mtk_reg_map mt7988_reg_map = {
++	.tx_irq_mask		= 0x461c,
++	.tx_irq_status		= 0x4618,
++	.pdma = {
++		.rx_ptr		= 0x6900,
++		.rx_cnt_cfg	= 0x6904,
++		.pcrx_ptr	= 0x6908,
++		.glo_cfg	= 0x6a04,
++		.rst_idx	= 0x6a08,
++		.delay_irq	= 0x6a0c,
++		.irq_status	= 0x6a20,
++		.irq_mask	= 0x6a28,
++		.adma_rx_dbg0	= 0x6a38,
++		.int_grp	= 0x6a50,
++	},
++	.qdma = {
++		.qtx_cfg	= 0x4400,
++		.qtx_sch	= 0x4404,
++		.rx_ptr		= 0x4500,
++		.rx_cnt_cfg	= 0x4504,
++		.qcrx_ptr	= 0x4508,
++		.glo_cfg	= 0x4604,
++		.rst_idx	= 0x4608,
++		.delay_irq	= 0x460c,
++		.fc_th		= 0x4610,
++		.int_grp	= 0x4620,
++		.hred		= 0x4644,
++		.ctx_ptr	= 0x4700,
++		.dtx_ptr	= 0x4704,
++		.crx_ptr	= 0x4710,
++		.drx_ptr	= 0x4714,
++		.fq_head	= 0x4720,
++		.fq_tail	= 0x4724,
++		.fq_count	= 0x4728,
++		.fq_blen	= 0x472c,
++		.tx_sch_rate	= 0x4798,
++	},
++	.gdm1_cnt		= 0x1c00,
++	.gdma_to_ppe0		= 0x3333,
++	.ppe_base		= 0x2000,
++	.wdma_base = {
++		[0]		= 0x4800,
++		[1]		= 0x4c00,
++	},
++	.pse_iq_sta		= 0x0180,
++	.pse_oq_sta		= 0x01a0,
++};
++
+ /* strings used by ethtool */
+ static const struct mtk_ethtool_stats {
+ 	char str[ETH_GSTRING_LEN];
+@@ -179,10 +227,54 @@ static const struct mtk_ethtool_stats {
+ };
+ 
+ static const char * const mtk_clks_source_name[] = {
+-	"ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
+-	"sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
+-	"sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
+-	"sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1"
++	"ethif",
++	"sgmiitop",
++	"esw",
++	"gp0",
++	"gp1",
++	"gp2",
++	"gp3",
++	"xgp1",
++	"xgp2",
++	"xgp3",
++	"crypto",
++	"fe",
++	"trgpll",
++	"sgmii_tx250m",
++	"sgmii_rx250m",
++	"sgmii_cdr_ref",
++	"sgmii_cdr_fb",
++	"sgmii2_tx250m",
++	"sgmii2_rx250m",
++	"sgmii2_cdr_ref",
++	"sgmii2_cdr_fb",
++	"sgmii_ck",
++	"eth2pll",
++	"wocpu0",
++	"wocpu1",
++	"netsys0",
++	"netsys1",
++	"ethwarp_wocpu2",
++	"ethwarp_wocpu1",
++	"ethwarp_wocpu0",
++	"top_usxgmii0_sel",
++	"top_usxgmii1_sel",
++	"top_sgm0_sel",
++	"top_sgm1_sel",
++	"top_xfi_phy0_xtal_sel",
++	"top_xfi_phy1_xtal_sel",
++	"top_eth_gmii_sel",
++	"top_eth_refck_50m_sel",
++	"top_eth_sys_200m_sel",
++	"top_eth_sys_sel",
++	"top_eth_xgmii_sel",
++	"top_eth_mii_sel",
++	"top_netsys_sel",
++	"top_netsys_500m_sel",
++	"top_netsys_pao_2x_sel",
++	"top_netsys_sync_250m_sel",
++	"top_netsys_ppefb_250m_sel",
++	"top_netsys_warp_sel",
+ };
+ 
+ void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
+@@ -195,7 +287,7 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
+ 	return __raw_readl(eth->base + reg);
+ }
+ 
+-static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg)
++u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg)
+ {
+ 	u32 val;
+ 
+@@ -326,6 +418,19 @@ static void mtk_gmac0_rgmii_adjust(struc
+ 	dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n");
+ }
+ 
++static void mtk_setup_bridge_switch(struct mtk_eth *eth)
++{
++	/* Force Port1 XGMAC Link Up */
++	mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID),
++		MTK_XGMAC_STS(MTK_GMAC1_ID));
++
++	/* Adjust GSW bridge IPG to 11 */
++	mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK,
++		(GSW_IPG_11 << GSWTX_IPG_SHIFT) |
++		(GSW_IPG_11 << GSWRX_IPG_SHIFT),
++		MTK_GSW_CFG);
++}
++
+ static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
+ 					      phy_interface_t interface)
+ {
+@@ -395,6 +500,8 @@ static void mtk_mac_config(struct phylin
+ 					goto init_err;
+ 			}
+ 			break;
++		case PHY_INTERFACE_MODE_INTERNAL:
++			break;
+ 		default:
+ 			goto err_phy;
+ 		}
+@@ -472,6 +579,15 @@ static void mtk_mac_config(struct phylin
+ 		return;
+ 	}
+ 
++	/* Setup gmac */
++	if (mtk_is_netsys_v3_or_greater(eth) &&
++	    mac->interface == PHY_INTERFACE_MODE_INTERNAL) {
++		mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
++		mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
++
++		mtk_setup_bridge_switch(eth);
++	}
++
+ 	return;
+ 
+ err_phy:
+@@ -682,11 +798,15 @@ static int mtk_mdio_init(struct mtk_eth
+ 	}
+ 	divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
+ 
++	/* Configure MDC Turbo Mode */
++	if (mtk_is_netsys_v3_or_greater(eth))
++		mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3);
++
+ 	/* Configure MDC Divider */
+-	val = mtk_r32(eth, MTK_PPSC);
+-	val &= ~PPSC_MDC_CFG;
+-	val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO;
+-	mtk_w32(eth, val, MTK_PPSC);
++	val = FIELD_PREP(PPSC_MDC_CFG, divider);
++	if (!mtk_is_netsys_v3_or_greater(eth))
++		val |= PPSC_MDC_TURBO;
++	mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC);
+ 
+ 	dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
+ 
+@@ -1145,10 +1265,19 @@ static void mtk_tx_set_dma_desc_v2(struc
+ 		data |= TX_DMA_LS0;
+ 	WRITE_ONCE(desc->txd3, data);
+ 
+-	if (mac->id == MTK_GMAC3_ID)
+-		data = PSE_GDM3_PORT;
+-	else
+-		data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
++	 /* set forward port */
++	switch (mac->id) {
++	case MTK_GMAC1_ID:
++		data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2;
++		break;
++	case MTK_GMAC2_ID:
++		data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2;
++		break;
++	case MTK_GMAC3_ID:
++		data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2;
++		break;
++	}
++
+ 	data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
+ 	WRITE_ONCE(desc->txd4, data);
+ 
+@@ -4304,6 +4433,17 @@ static int mtk_add_mac(struct mtk_eth *e
+ 			  mac->phylink_config.supported_interfaces);
+ 	}
+ 
++	if (mtk_is_netsys_v3_or_greater(mac->hw) &&
++	    MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) &&
++	    id == MTK_GMAC1_ID) {
++		mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
++						       MAC_SYM_PAUSE |
++						       MAC_10000FD;
++		phy_interface_zero(mac->phylink_config.supported_interfaces);
++		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
++			  mac->phylink_config.supported_interfaces);
++	}
++
+ 	phylink = phylink_create(&mac->phylink_config,
+ 				 of_fwnode_handle(mac->of_node),
+ 				 phy_mode, &mtk_phylink_ops);
+@@ -4826,6 +4966,24 @@ static const struct mtk_soc_data mt7986_
+ 	},
+ };
+ 
++static const struct mtk_soc_data mt7988_data = {
++	.reg_map = &mt7988_reg_map,
++	.ana_rgc3 = 0x128,
++	.caps = MT7988_CAPS,
++	.hw_features = MTK_HW_FEATURES,
++	.required_clks = MT7988_CLKS_BITMAP,
++	.required_pctl = false,
++	.version = 3,
++	.txrx = {
++		.txd_size = sizeof(struct mtk_tx_dma_v2),
++		.rxd_size = sizeof(struct mtk_rx_dma_v2),
++		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
++		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
++		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
++		.dma_len_offset = 8,
++	},
++};
++
+ static const struct mtk_soc_data rt5350_data = {
+ 	.reg_map = &mt7628_reg_map,
+ 	.caps = MT7628_CAPS,
+@@ -4844,14 +5002,15 @@ static const struct mtk_soc_data rt5350_
+ };
+ 
+ const struct of_device_id of_mtk_match[] = {
+-	{ .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
+-	{ .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
+-	{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
+-	{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
+-	{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
+-	{ .compatible = "mediatek,mt7981-eth", .data = &mt7981_data},
+-	{ .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
+-	{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
++	{ .compatible = "mediatek,mt2701-eth", .data = &mt2701_data },
++	{ .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
++	{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data },
++	{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data },
++	{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
++	{ .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
++	{ .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },
++	{ .compatible = "mediatek,mt7988-eth", .data = &mt7988_data },
++	{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, of_mtk_match);
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -117,7 +117,8 @@
+ #define MTK_CDMP_EG_CTRL	0x404
+ 
+ /* GDM Exgress Control Register */
+-#define MTK_GDMA_FWD_CFG(x)	(0x500 + (x * 0x1000))
++#define MTK_GDMA_FWD_CFG(x)	({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ?	\
++				   0x540 : 0x500 + (_x * 0x1000); })
+ #define MTK_GDMA_SPECIAL_TAG	BIT(24)
+ #define MTK_GDMA_ICS_EN		BIT(22)
+ #define MTK_GDMA_TCS_EN		BIT(21)
+@@ -126,6 +127,11 @@
+ #define MTK_GDMA_TO_PDMA	0x0
+ #define MTK_GDMA_DROP_ALL       0x7777
+ 
++/* GDM Egress Control Register */
++#define MTK_GDMA_EG_CTRL(x)	({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ?	\
++				   0x544 : 0x504 + (_x * 0x1000); })
++#define MTK_GDMA_XGDM_SEL	BIT(31)
++
+ /* Unicast Filter MAC Address Register - Low */
+ #define MTK_GDMA_MAC_ADRL(x)	(0x508 + (x * 0x1000))
+ 
+@@ -386,7 +392,26 @@
+ #define PHY_IAC_TIMEOUT		HZ
+ 
+ #define MTK_MAC_MISC		0x1000c
++#define MTK_MAC_MISC_V3		0x10010
+ #define MTK_MUX_TO_ESW		BIT(0)
++#define MISC_MDC_TURBO		BIT(4)
++
++/* XMAC status registers */
++#define MTK_XGMAC_STS(x)	(((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C)
++#define MTK_XGMAC_FORCE_LINK(x)	(((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15))
++#define MTK_USXGMII_PCS_LINK	BIT(8)
++#define MTK_XGMAC_RX_FC		BIT(5)
++#define MTK_XGMAC_TX_FC		BIT(4)
++#define MTK_USXGMII_PCS_MODE	GENMASK(3, 1)
++#define MTK_XGMAC_LINK_STS	BIT(0)
++
++/* GSW bridge registers */
++#define MTK_GSW_CFG		(0x10080)
++#define GSWTX_IPG_MASK		GENMASK(19, 16)
++#define GSWTX_IPG_SHIFT		16
++#define GSWRX_IPG_MASK		GENMASK(3, 0)
++#define GSWRX_IPG_SHIFT		0
++#define GSW_IPG_11		11
+ 
+ /* Mac control registers */
+ #define MTK_MAC_MCR(x)		(0x10100 + (x * 0x100))
+@@ -644,6 +669,11 @@ enum mtk_clks_map {
+ 	MTK_CLK_GP0,
+ 	MTK_CLK_GP1,
+ 	MTK_CLK_GP2,
++	MTK_CLK_GP3,
++	MTK_CLK_XGP1,
++	MTK_CLK_XGP2,
++	MTK_CLK_XGP3,
++	MTK_CLK_CRYPTO,
+ 	MTK_CLK_FE,
+ 	MTK_CLK_TRGPLL,
+ 	MTK_CLK_SGMII_TX_250M,
+@@ -660,6 +690,27 @@ enum mtk_clks_map {
+ 	MTK_CLK_WOCPU1,
+ 	MTK_CLK_NETSYS0,
+ 	MTK_CLK_NETSYS1,
++	MTK_CLK_ETHWARP_WOCPU2,
++	MTK_CLK_ETHWARP_WOCPU1,
++	MTK_CLK_ETHWARP_WOCPU0,
++	MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
++	MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
++	MTK_CLK_TOP_SGM_0_SEL,
++	MTK_CLK_TOP_SGM_1_SEL,
++	MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
++	MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
++	MTK_CLK_TOP_ETH_GMII_SEL,
++	MTK_CLK_TOP_ETH_REFCK_50M_SEL,
++	MTK_CLK_TOP_ETH_SYS_200M_SEL,
++	MTK_CLK_TOP_ETH_SYS_SEL,
++	MTK_CLK_TOP_ETH_XGMII_SEL,
++	MTK_CLK_TOP_ETH_MII_SEL,
++	MTK_CLK_TOP_NETSYS_SEL,
++	MTK_CLK_TOP_NETSYS_500M_SEL,
++	MTK_CLK_TOP_NETSYS_PAO_2X_SEL,
++	MTK_CLK_TOP_NETSYS_SYNC_250M_SEL,
++	MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL,
++	MTK_CLK_TOP_NETSYS_WARP_SEL,
+ 	MTK_CLK_MAX
+ };
+ 
+@@ -713,6 +764,36 @@ enum mtk_clks_map {
+ 				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
+ 				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
+ 				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
++#define MT7988_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \
++				 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
++				 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
++				 BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
++				 BIT_ULL(MTK_CLK_CRYPTO) | \
++				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
++				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
++				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
++				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
++				 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL))
+ 
+ enum mtk_dev_state {
+ 	MTK_HW_INIT,
+@@ -961,6 +1042,8 @@ enum mkt_eth_capabilities {
+ 		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
+ 		      MTK_RSTCTRL_PPE1)
+ 
++#define MT7988_CAPS  (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1)
++
+ struct mtk_tx_dma_desc_info {
+ 	dma_addr_t	addr;
+ 	u32		size;
+@@ -1306,6 +1389,7 @@ void mtk_stats_update_mac(struct mtk_mac
+ 
+ void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
+ u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
++u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
+ 
+ int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
+ int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);

lede/target/linux/generic/backport-5.15/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch

@@ -0,0 +1,27 @@
+From 38a7eb76220731eff40602cf433f24880be0a6c2 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Thu, 27 Jul 2023 09:02:26 +0200
+Subject: [PATCH 106/250] net: ethernet: mtk_eth_soc: enable page_pool support
+ for MT7988 SoC
+
+In order to recycle pages, enable page_pool allocator for MT7988 SoC.
+
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://lore.kernel.org/r/fd4e8693980e47385a543e7b002eec0b88bd09df.1690440675.git.lorenzo@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -1613,7 +1613,7 @@ static void mtk_update_rx_cpu_idx(struct
+ 
+ static bool mtk_page_pool_enabled(struct mtk_eth *eth)
+ {
+-	return eth->soc->version == 2;
++	return mtk_is_netsys_v2_or_greater(eth);
+ }
+ 
+ static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,

lede/target/linux/generic/backport-5.15/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch

@@ -0,0 +1,135 @@
+From 199e7d5a7f03dd377f3a7a458360dbedd71d50ba Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Thu, 27 Jul 2023 09:07:28 +0200
+Subject: [PATCH 107/250] net: ethernet: mtk_eth_soc: enable nft hw
+ flowtable_offload for MT7988 SoC
+
+Enable hw Packet Process Engine (PPE) for MT7988 SoC.
+
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://lore.kernel.org/r/5e86341b0220a49620dadc02d77970de5ded9efc.1690441576.git.lorenzo@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |  3 +++
+ drivers/net/ethernet/mediatek/mtk_ppe.c     | 19 +++++++++++++++----
+ drivers/net/ethernet/mediatek/mtk_ppe.h     | 19 ++++++++++++++++++-
+ 3 files changed, 36 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -4974,6 +4974,9 @@ static const struct mtk_soc_data mt7988_
+ 	.required_clks = MT7988_CLKS_BITMAP,
+ 	.required_pctl = false,
+ 	.version = 3,
++	.offload_version = 2,
++	.hash_offset = 4,
++	.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma_v2),
+ 		.rxd_size = sizeof(struct mtk_rx_dma_v2),
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
+@@ -422,13 +422,22 @@ int mtk_foe_entry_set_wdma(struct mtk_et
+ 	struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry);
+ 	u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
+ 
+-	if (mtk_is_netsys_v2_or_greater(eth)) {
++	switch (eth->soc->version) {
++	case 3:
++		*ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
++		*ib2 |=  FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |
++			 MTK_FOE_IB2_WDMA_WINFO_V2;
++		l2->w3info = FIELD_PREP(MTK_FOE_WINFO_WCID_V3, wcid) |
++			     FIELD_PREP(MTK_FOE_WINFO_BSS_V3, bss);
++		break;
++	case 2:
+ 		*ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
+ 		*ib2 |=  FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |
+ 			 MTK_FOE_IB2_WDMA_WINFO_V2;
+ 		l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) |
+ 			    FIELD_PREP(MTK_FOE_WINFO_BSS, bss);
+-	} else {
++		break;
++	default:
+ 		*ib2 &= ~MTK_FOE_IB2_PORT_MG;
+ 		*ib2 |= MTK_FOE_IB2_WDMA_WINFO;
+ 		if (wdma_idx)
+@@ -436,6 +445,7 @@ int mtk_foe_entry_set_wdma(struct mtk_et
+ 		l2->vlan2 = FIELD_PREP(MTK_FOE_VLAN2_WINFO_BSS, bss) |
+ 			    FIELD_PREP(MTK_FOE_VLAN2_WINFO_WCID, wcid) |
+ 			    FIELD_PREP(MTK_FOE_VLAN2_WINFO_RING, txq);
++		break;
+ 	}
+ 
+ 	return 0;
+@@ -956,8 +966,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
+ 	mtk_ppe_init_foe_table(ppe);
+ 	ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys);
+ 
+-	val = MTK_PPE_TB_CFG_ENTRY_80B |
+-	      MTK_PPE_TB_CFG_AGE_NON_L4 |
++	val = MTK_PPE_TB_CFG_AGE_NON_L4 |
+ 	      MTK_PPE_TB_CFG_AGE_UNBIND |
+ 	      MTK_PPE_TB_CFG_AGE_TCP |
+ 	      MTK_PPE_TB_CFG_AGE_UDP |
+@@ -973,6 +982,8 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
+ 			 MTK_PPE_ENTRIES_SHIFT);
+ 	if (mtk_is_netsys_v2_or_greater(ppe->eth))
+ 		val |= MTK_PPE_TB_CFG_INFO_SEL;
++	if (!mtk_is_netsys_v3_or_greater(ppe->eth))
++		val |= MTK_PPE_TB_CFG_ENTRY_80B;
+ 	ppe_w32(ppe, MTK_PPE_TB_CFG, val);
+ 
+ 	ppe_w32(ppe, MTK_PPE_IP_PROTO_CHK,
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.h
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
+@@ -85,6 +85,17 @@ enum {
+ #define MTK_FOE_WINFO_BSS		GENMASK(5, 0)
+ #define MTK_FOE_WINFO_WCID		GENMASK(15, 6)
+ 
++#define MTK_FOE_WINFO_BSS_V3		GENMASK(23, 16)
++#define MTK_FOE_WINFO_WCID_V3		GENMASK(15, 0)
++
++#define MTK_FOE_WINFO_PAO_USR_INFO	GENMASK(15, 0)
++#define MTK_FOE_WINFO_PAO_TID		GENMASK(19, 16)
++#define MTK_FOE_WINFO_PAO_IS_FIXEDRATE	BIT(20)
++#define MTK_FOE_WINFO_PAO_IS_PRIOR	BIT(21)
++#define MTK_FOE_WINFO_PAO_IS_SP		BIT(22)
++#define MTK_FOE_WINFO_PAO_HF		BIT(23)
++#define MTK_FOE_WINFO_PAO_AMSDU_EN	BIT(24)
++
+ enum {
+ 	MTK_FOE_STATE_INVALID,
+ 	MTK_FOE_STATE_UNBIND,
+@@ -106,8 +117,13 @@ struct mtk_foe_mac_info {
+ 	u16 pppoe_id;
+ 	u16 src_mac_lo;
+ 
++	/* netsys_v2 */
+ 	u16 minfo;
+ 	u16 winfo;
++
++	/* netsys_v3 */
++	u32 w3info;
++	u32 wpao;
+ };
+ 
+ /* software-only entry type */
+@@ -218,6 +234,7 @@ struct mtk_foe_ipv6_6rd {
+ 
+ #define MTK_FOE_ENTRY_V1_SIZE	80
+ #define MTK_FOE_ENTRY_V2_SIZE	96
++#define MTK_FOE_ENTRY_V3_SIZE	128
+ 
+ struct mtk_foe_entry {
+ 	u32 ib1;
+@@ -228,7 +245,7 @@ struct mtk_foe_entry {
+ 		struct mtk_foe_ipv4_dslite dslite;
+ 		struct mtk_foe_ipv6 ipv6;
+ 		struct mtk_foe_ipv6_6rd ipv6_6rd;
+-		u32 data[23];
++		u32 data[31];
+ 	};
+ };
+ 

lede/target/linux/generic/backport-5.15/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch

@@ -0,0 +1,78 @@
+From 0c024632c1e7ff69914329bfd87bec749b9c0aed Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 2 Aug 2023 04:31:09 +0100
+Subject: [PATCH 108/250] net: ethernet: mtk_eth_soc: support per-flow
+ accounting on MT7988
+
+NETSYS_V3 uses 64 bits for each counters while older SoCs are using
+48/40 bits for each counter.
+Support reading per-flow byte and package counters on NETSYS_V3.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Link: https://lore.kernel.org/r/37a0928fa8c1253b197884c68ce1f54239421ac5.1690946442.git.daniel@makrotopia.org
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c  |  1 +
+ drivers/net/ethernet/mediatek/mtk_ppe.c      | 21 +++++++++++++-------
+ drivers/net/ethernet/mediatek/mtk_ppe_regs.h |  2 ++
+ 3 files changed, 17 insertions(+), 7 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -4976,6 +4976,7 @@ static const struct mtk_soc_data mt7988_
+ 	.version = 3,
+ 	.offload_version = 2,
+ 	.hash_offset = 4,
++	.has_accounting = true,
+ 	.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma_v2),
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
+@@ -91,7 +91,6 @@ static int mtk_ppe_mib_wait_busy(struct
+ 
+ static int mtk_mib_entry_read(struct mtk_ppe *ppe, u16 index, u64 *bytes, u64 *packets)
+ {
+-	u32 byte_cnt_low, byte_cnt_high, pkt_cnt_low, pkt_cnt_high;
+ 	u32 val, cnt_r0, cnt_r1, cnt_r2;
+ 	int ret;
+ 
+@@ -106,12 +105,20 @@ static int mtk_mib_entry_read(struct mtk
+ 	cnt_r1 = readl(ppe->base + MTK_PPE_MIB_SER_R1);
+ 	cnt_r2 = readl(ppe->base + MTK_PPE_MIB_SER_R2);
+ 
+-	byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0);
+-	byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1);
+-	pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1);
+-	pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2);
+-	*bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low;
+-	*packets = (pkt_cnt_high << 16) | pkt_cnt_low;
++	if (mtk_is_netsys_v3_or_greater(ppe->eth)) {
++		/* 64 bit for each counter */
++		u32 cnt_r3 = readl(ppe->base + MTK_PPE_MIB_SER_R3);
++		*bytes = ((u64)cnt_r1 << 32) | cnt_r0;
++		*packets = ((u64)cnt_r3 << 32) | cnt_r2;
++	} else {
++		/* 48 bit byte counter, 40 bit packet counter */
++		u32 byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0);
++		u32 byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1);
++		u32 pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1);
++		u32 pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2);
++		*bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low;
++		*packets = (pkt_cnt_high << 16) | pkt_cnt_low;
++	}
+ 
+ 	return 0;
+ }
+--- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
++++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
+@@ -163,6 +163,8 @@ enum {
+ #define MTK_PPE_MIB_SER_R2			0x348
+ #define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH		GENMASK(23, 0)
+ 
++#define MTK_PPE_MIB_SER_R3			0x34c
++
+ #define MTK_PPE_MIB_CACHE_CTL			0x350
+ #define MTK_PPE_MIB_CACHE_CTL_EN		BIT(0)
+ #define MTK_PPE_MIB_CACHE_CTL_FLUSH		BIT(2)

lede/target/linux/generic/backport-5.15/750-v6.5-15-net-ethernet-mtk_eth_soc-fix-NULL-pointer-on-hw-rese.patch

@@ -0,0 +1,52 @@
+From 3b12f42772c26869d60398c1710aa27b27cd945c Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 21 Aug 2023 17:12:44 +0100
+Subject: [PATCH 109/250] net: ethernet: mtk_eth_soc: fix NULL pointer on hw
+ reset
+
+When a hardware reset is triggered on devices not initializing WED the
+calls to mtk_wed_fe_reset and mtk_wed_fe_reset_complete dereference a
+pointer on uninitialized stack memory.
+Break out of both functions in case a hw_list entry is 0.
+
+Fixes: 08a764a7c51b ("net: ethernet: mtk_wed: add reset/reset_complete callbacks")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://lore.kernel.org/r/5465c1609b464cc7407ae1530c40821dcdf9d3e6.1692634266.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_wed.c | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -214,9 +214,13 @@ void mtk_wed_fe_reset(void)
+ 
+ 	for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
+ 		struct mtk_wed_hw *hw = hw_list[i];
+-		struct mtk_wed_device *dev = hw->wed_dev;
++		struct mtk_wed_device *dev;
+ 		int err;
+ 
++		if (!hw)
++			break;
++
++		dev = hw->wed_dev;
+ 		if (!dev || !dev->wlan.reset)
+ 			continue;
+ 
+@@ -237,8 +241,12 @@ void mtk_wed_fe_reset_complete(void)
+ 
+ 	for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
+ 		struct mtk_wed_hw *hw = hw_list[i];
+-		struct mtk_wed_device *dev = hw->wed_dev;
++		struct mtk_wed_device *dev;
++
++		if (!hw)
++			break;
+ 
++		dev = hw->wed_dev;
+ 		if (!dev || !dev->wlan.reset_complete)
+ 			continue;
+ 

lede/target/linux/generic/backport-5.15/750-v6.5-16-net-ethernet-mtk_eth_soc-fix-register-definitions-fo.patch

@@ -0,0 +1,44 @@
+From 489aea123d74a846ce746bfdb3efe1e7ad512e0d Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 22 Aug 2023 17:31:24 +0100
+Subject: [PATCH 110/250] net: ethernet: mtk_eth_soc: fix register definitions
+ for MT7988
+
+More register macros need to be adjusted for the 3rd GMAC on MT7988.
+Account for added bit in SYSCFG0_SGMII_MASK.
+
+Fixes: 445eb6448ed3 ("net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Link: https://lore.kernel.org/r/1c8da012e2ca80939906d85f314138c552139f0f.1692721443.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -133,10 +133,12 @@
+ #define MTK_GDMA_XGDM_SEL	BIT(31)
+ 
+ /* Unicast Filter MAC Address Register - Low */
+-#define MTK_GDMA_MAC_ADRL(x)	(0x508 + (x * 0x1000))
++#define MTK_GDMA_MAC_ADRL(x)	({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ?	\
++				   0x548 : 0x508 + (_x * 0x1000); })
+ 
+ /* Unicast Filter MAC Address Register - High */
+-#define MTK_GDMA_MAC_ADRH(x)	(0x50C + (x * 0x1000))
++#define MTK_GDMA_MAC_ADRH(x)	({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ?	\
++				   0x54C : 0x50C + (_x * 0x1000); })
+ 
+ /* FE global misc reg*/
+ #define MTK_FE_GLO_MISC         0x124
+@@ -500,7 +502,7 @@
+ #define ETHSYS_SYSCFG0		0x14
+ #define SYSCFG0_GE_MASK		0x3
+ #define SYSCFG0_GE_MODE(x, y)	(x << (12 + (y * 2)))
+-#define SYSCFG0_SGMII_MASK     GENMASK(9, 8)
++#define SYSCFG0_SGMII_MASK     GENMASK(9, 7)
+ #define SYSCFG0_SGMII_GMAC1    ((2 << 8) & SYSCFG0_SGMII_MASK)
+ #define SYSCFG0_SGMII_GMAC2    ((3 << 8) & SYSCFG0_SGMII_MASK)
+ #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)

lede/target/linux/generic/backport-5.15/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch

@@ -0,0 +1,188 @@
+From 15a84d1c44ae8c1451c265ee60500588a24e8cd6 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 22 Aug 2023 17:32:03 +0100
+Subject: [PATCH 111/250] net: ethernet: mtk_eth_soc: add reset bits for MT7988
+
+Add bits needed to reset the frame engine on MT7988.
+
+Fixes: 445eb6448ed3 ("net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/89b6c38380e7a3800c1362aa7575600717bc7543.1692721443.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 76 +++++++++++++++------
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 16 +++--
+ 2 files changed, 68 insertions(+), 24 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -3538,19 +3538,34 @@ static void mtk_hw_reset(struct mtk_eth
+ {
+ 	u32 val;
+ 
+-	if (mtk_is_netsys_v2_or_greater(eth)) {
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
++
++	if (mtk_is_netsys_v3_or_greater(eth)) {
++		val = RSTCTRL_PPE0_V3;
++
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
++			val |= RSTCTRL_PPE1_V3;
++
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
++			val |= RSTCTRL_PPE2;
++
++		val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
++	} else if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		val = RSTCTRL_PPE0_V2;
++
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
++			val |= RSTCTRL_PPE1;
+ 	} else {
+ 		val = RSTCTRL_PPE0;
+ 	}
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
+-		val |= RSTCTRL_PPE1;
+-
+ 	ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
+ 
+-	if (mtk_is_netsys_v2_or_greater(eth))
++	if (mtk_is_netsys_v3_or_greater(eth))
++		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
++			     0x6f8ff);
++	else if (mtk_is_netsys_v2_or_greater(eth))
+ 		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
+ 			     0x3ffffff);
+ }
+@@ -3576,13 +3591,21 @@ static void mtk_hw_warm_reset(struct mtk
+ 		return;
+ 	}
+ 
+-	if (mtk_is_netsys_v2_or_greater(eth))
++	if (mtk_is_netsys_v3_or_greater(eth)) {
++		rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3;
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
++			rst_mask |= RSTCTRL_PPE1_V3;
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
++			rst_mask |= RSTCTRL_PPE2;
++
++		rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
++	} else if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
+-	else
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
++			rst_mask |= RSTCTRL_PPE1;
++	} else {
+ 		rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
+-
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
+-		rst_mask |= RSTCTRL_PPE1;
++	}
+ 
+ 	regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
+ 
+@@ -3934,11 +3957,17 @@ static void mtk_prepare_for_reset(struct
+ 	u32 val;
+ 	int i;
+ 
+-	/* disabe FE P3 and P4 */
+-	val = mtk_r32(eth, MTK_FE_GLO_CFG) | MTK_FE_LINK_DOWN_P3;
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
+-		val |= MTK_FE_LINK_DOWN_P4;
+-	mtk_w32(eth, val, MTK_FE_GLO_CFG);
++	/* set FE PPE ports link down */
++	for (i = MTK_GMAC1_ID;
++	     i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID);
++	     i += 2) {
++		val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
++			val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT);
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
++			val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT);
++		mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
++	}
+ 
+ 	/* adjust PPE configurations to prepare for reset */
+ 	for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
+@@ -3999,11 +4028,18 @@ static void mtk_pending_work(struct work
+ 		}
+ 	}
+ 
+-	/* enabe FE P3 and P4 */
+-	val = mtk_r32(eth, MTK_FE_GLO_CFG) & ~MTK_FE_LINK_DOWN_P3;
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
+-		val &= ~MTK_FE_LINK_DOWN_P4;
+-	mtk_w32(eth, val, MTK_FE_GLO_CFG);
++	/* set FE PPE ports link up */
++	for (i = MTK_GMAC1_ID;
++	     i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID);
++	     i += 2) {
++		val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
++			val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT);
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
++			val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT);
++
++		mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
++	}
+ 
+ 	clear_bit(MTK_RESETTING, &eth->state);
+ 
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -76,9 +76,8 @@
+ #define	MTK_HW_LRO_SDL_REMAIN_ROOM	1522
+ 
+ /* Frame Engine Global Configuration */
+-#define MTK_FE_GLO_CFG		0x00
+-#define MTK_FE_LINK_DOWN_P3	BIT(11)
+-#define MTK_FE_LINK_DOWN_P4	BIT(12)
++#define MTK_FE_GLO_CFG(x)	(((x) == MTK_GMAC3_ID) ? 0x24 : 0x00)
++#define MTK_FE_LINK_DOWN_P(x)	BIT(((x) + 8) % 16)
+ 
+ /* Frame Engine Global Reset Register */
+ #define MTK_RST_GL		0x04
+@@ -519,9 +518,15 @@
+ /* ethernet reset control register */
+ #define ETHSYS_RSTCTRL			0x34
+ #define RSTCTRL_FE			BIT(6)
++#define RSTCTRL_WDMA0			BIT(24)
++#define RSTCTRL_WDMA1			BIT(25)
++#define RSTCTRL_WDMA2			BIT(26)
+ #define RSTCTRL_PPE0			BIT(31)
+ #define RSTCTRL_PPE0_V2			BIT(30)
+ #define RSTCTRL_PPE1			BIT(31)
++#define RSTCTRL_PPE0_V3			BIT(29)
++#define RSTCTRL_PPE1_V3			BIT(30)
++#define RSTCTRL_PPE2			BIT(31)
+ #define RSTCTRL_ETH			BIT(23)
+ 
+ /* ethernet reset check idle register */
+@@ -928,6 +933,7 @@ enum mkt_eth_capabilities {
+ 	MTK_QDMA_BIT,
+ 	MTK_SOC_MT7628_BIT,
+ 	MTK_RSTCTRL_PPE1_BIT,
++	MTK_RSTCTRL_PPE2_BIT,
+ 	MTK_U3_COPHY_V2_BIT,
+ 
+ 	/* MUX BITS*/
+@@ -962,6 +968,7 @@ enum mkt_eth_capabilities {
+ #define MTK_QDMA		BIT_ULL(MTK_QDMA_BIT)
+ #define MTK_SOC_MT7628		BIT_ULL(MTK_SOC_MT7628_BIT)
+ #define MTK_RSTCTRL_PPE1	BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
++#define MTK_RSTCTRL_PPE2	BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
+ #define MTK_U3_COPHY_V2		BIT_ULL(MTK_U3_COPHY_V2_BIT)
+ 
+ #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW		\
+@@ -1044,7 +1051,8 @@ enum mkt_eth_capabilities {
+ 		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
+ 		      MTK_RSTCTRL_PPE1)
+ 
+-#define MT7988_CAPS  (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1)
++#define MT7988_CAPS  (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1 | \
++		      MTK_RSTCTRL_PPE2)
+ 
+ struct mtk_tx_dma_desc_info {
+ 	dma_addr_t	addr;

lede/target/linux/generic/backport-5.15/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch

@@ -0,0 +1,254 @@
+From 25ce45fe40b574e5d7ffa407f7f2db03e7d5a910 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 22 Aug 2023 17:32:54 +0100
+Subject: [PATCH 112/250] net: ethernet: mtk_eth_soc: add support for in-SoC
+ SRAM
+
+MT7981, MT7986 and MT7988 come with in-SoC SRAM dedicated for Ethernet
+DMA rings. Support using the SRAM without breaking existing device tree
+bindings, ie. only new SoC starting from MT7988 will have the SRAM
+declared as additional resource in device tree. For MT7981 and MT7986
+an offset on top of the main I/O base is used.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/e45e0f230c63ad58869e8fe35b95a2fb8925b625.1692721443.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 88 ++++++++++++++++-----
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 12 ++-
+ 2 files changed, 78 insertions(+), 22 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -1075,10 +1075,13 @@ static int mtk_init_fq_dma(struct mtk_et
+ 	dma_addr_t dma_addr;
+ 	int i;
+ 
+-	eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
+-					       cnt * soc->txrx.txd_size,
+-					       &eth->phy_scratch_ring,
+-					       GFP_KERNEL);
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM))
++		eth->scratch_ring = eth->sram_base;
++	else
++		eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
++						       cnt * soc->txrx.txd_size,
++						       &eth->phy_scratch_ring,
++						       GFP_KERNEL);
+ 	if (unlikely(!eth->scratch_ring))
+ 		return -ENOMEM;
+ 
+@@ -2376,8 +2379,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+ 	if (!ring->buf)
+ 		goto no_tx_mem;
+ 
+-	ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
+-				       &ring->phys, GFP_KERNEL);
++	if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) {
++		ring->dma = eth->sram_base + ring_size * sz;
++		ring->phys = eth->phy_scratch_ring + ring_size * (dma_addr_t)sz;
++	} else {
++		ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
++					       &ring->phys, GFP_KERNEL);
++	}
++
+ 	if (!ring->dma)
+ 		goto no_tx_mem;
+ 
+@@ -2476,8 +2485,7 @@ static void mtk_tx_clean(struct mtk_eth
+ 		kfree(ring->buf);
+ 		ring->buf = NULL;
+ 	}
+-
+-	if (ring->dma) {
++	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
+ 		dma_free_coherent(eth->dma_dev,
+ 				  ring->dma_size * soc->txrx.txd_size,
+ 				  ring->dma, ring->phys);
+@@ -2496,9 +2504,14 @@ static int mtk_rx_alloc(struct mtk_eth *
+ {
+ 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
+ 	struct mtk_rx_ring *ring;
+-	int rx_data_len, rx_dma_size;
++	int rx_data_len, rx_dma_size, tx_ring_size;
+ 	int i;
+ 
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
++		tx_ring_size = MTK_QDMA_RING_SIZE;
++	else
++		tx_ring_size = MTK_DMA_SIZE;
++
+ 	if (rx_flag == MTK_RX_FLAGS_QDMA) {
+ 		if (ring_no)
+ 			return -EINVAL;
+@@ -2533,9 +2546,20 @@ static int mtk_rx_alloc(struct mtk_eth *
+ 		ring->page_pool = pp;
+ 	}
+ 
+-	ring->dma = dma_alloc_coherent(eth->dma_dev,
+-				       rx_dma_size * eth->soc->txrx.rxd_size,
+-				       &ring->phys, GFP_KERNEL);
++	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
++	    rx_flag != MTK_RX_FLAGS_NORMAL) {
++		ring->dma = dma_alloc_coherent(eth->dma_dev,
++					       rx_dma_size * eth->soc->txrx.rxd_size,
++					       &ring->phys, GFP_KERNEL);
++	} else {
++		struct mtk_tx_ring *tx_ring = &eth->tx_ring;
++
++		ring->dma = tx_ring->dma + tx_ring_size *
++			    eth->soc->txrx.txd_size * (ring_no + 1);
++		ring->phys = tx_ring->phys + tx_ring_size *
++			     eth->soc->txrx.txd_size * (ring_no + 1);
++	}
++
+ 	if (!ring->dma)
+ 		return -ENOMEM;
+ 
+@@ -2618,7 +2642,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+ 	return 0;
+ }
+ 
+-static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
++static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram)
+ {
+ 	int i;
+ 
+@@ -2641,7 +2665,7 @@ static void mtk_rx_clean(struct mtk_eth
+ 		ring->data = NULL;
+ 	}
+ 
+-	if (ring->dma) {
++	if (!in_sram && ring->dma) {
+ 		dma_free_coherent(eth->dma_dev,
+ 				  ring->dma_size * eth->soc->txrx.rxd_size,
+ 				  ring->dma, ring->phys);
+@@ -3001,7 +3025,7 @@ static void mtk_dma_free(struct mtk_eth
+ 	for (i = 0; i < MTK_MAX_DEVS; i++)
+ 		if (eth->netdev[i])
+ 			netdev_reset_queue(eth->netdev[i]);
+-	if (eth->scratch_ring) {
++	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
+ 		dma_free_coherent(eth->dma_dev,
+ 				  MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
+ 				  eth->scratch_ring, eth->phy_scratch_ring);
+@@ -3009,13 +3033,13 @@ static void mtk_dma_free(struct mtk_eth
+ 		eth->phy_scratch_ring = 0;
+ 	}
+ 	mtk_tx_clean(eth);
+-	mtk_rx_clean(eth, &eth->rx_ring[0]);
+-	mtk_rx_clean(eth, &eth->rx_ring_qdma);
++	mtk_rx_clean(eth, &eth->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM));
++	mtk_rx_clean(eth, &eth->rx_ring_qdma, false);
+ 
+ 	if (eth->hwlro) {
+ 		mtk_hwlro_rx_uninit(eth);
+ 		for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
+-			mtk_rx_clean(eth, &eth->rx_ring[i]);
++			mtk_rx_clean(eth, &eth->rx_ring[i], false);
+ 	}
+ 
+ 	kfree(eth->scratch_head);
+@@ -4585,7 +4609,7 @@ static int mtk_sgmii_init(struct mtk_eth
+ 
+ static int mtk_probe(struct platform_device *pdev)
+ {
+-	struct resource *res = NULL;
++	struct resource *res = NULL, *res_sram;
+ 	struct device_node *mac_np;
+ 	struct mtk_eth *eth;
+ 	int err, i;
+@@ -4605,6 +4629,20 @@ static int mtk_probe(struct platform_dev
+ 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
+ 		eth->ip_align = NET_IP_ALIGN;
+ 
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
++		/* SRAM is actual memory and supports transparent access just like DRAM.
++		 * Hence we don't require __iomem being set and don't need to use accessor
++		 * functions to read from or write to SRAM.
++		 */
++		if (mtk_is_netsys_v3_or_greater(eth)) {
++			eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1);
++			if (IS_ERR(eth->sram_base))
++				return PTR_ERR(eth->sram_base);
++		} else {
++			eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET;
++		}
++	}
++
+ 	spin_lock_init(&eth->page_lock);
+ 	spin_lock_init(&eth->tx_irq_lock);
+ 	spin_lock_init(&eth->rx_irq_lock);
+@@ -4668,6 +4706,18 @@ static int mtk_probe(struct platform_dev
+ 			err = -EINVAL;
+ 			goto err_destroy_sgmii;
+ 		}
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
++			if (mtk_is_netsys_v3_or_greater(eth)) {
++				res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++				if (!res_sram) {
++					err = -EINVAL;
++					goto err_destroy_sgmii;
++				}
++				eth->phy_scratch_ring = res_sram->start;
++			} else {
++				eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET;
++			}
++		}
+ 	}
+ 
+ 	if (eth->soc->offload_version) {
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -139,6 +139,9 @@
+ #define MTK_GDMA_MAC_ADRH(x)	({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ?	\
+ 				   0x54C : 0x50C + (_x * 0x1000); })
+ 
++/* Internal SRAM offset */
++#define MTK_ETH_SRAM_OFFSET	0x40000
++
+ /* FE global misc reg*/
+ #define MTK_FE_GLO_MISC         0x124
+ 
+@@ -935,6 +938,7 @@ enum mkt_eth_capabilities {
+ 	MTK_RSTCTRL_PPE1_BIT,
+ 	MTK_RSTCTRL_PPE2_BIT,
+ 	MTK_U3_COPHY_V2_BIT,
++	MTK_SRAM_BIT,
+ 
+ 	/* MUX BITS*/
+ 	MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
+@@ -970,6 +974,7 @@ enum mkt_eth_capabilities {
+ #define MTK_RSTCTRL_PPE1	BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
+ #define MTK_RSTCTRL_PPE2	BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
+ #define MTK_U3_COPHY_V2		BIT_ULL(MTK_U3_COPHY_V2_BIT)
++#define MTK_SRAM		BIT_ULL(MTK_SRAM_BIT)
+ 
+ #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW		\
+ 	BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
+@@ -1045,14 +1050,14 @@ enum mkt_eth_capabilities {
+ #define MT7981_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
+ 		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
+ 		      MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
+-		      MTK_RSTCTRL_PPE1)
++		      MTK_RSTCTRL_PPE1 | MTK_SRAM)
+ 
+ #define MT7986_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
+ 		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
+-		      MTK_RSTCTRL_PPE1)
++		      MTK_RSTCTRL_PPE1 | MTK_SRAM)
+ 
+ #define MT7988_CAPS  (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1 | \
+-		      MTK_RSTCTRL_PPE2)
++		      MTK_RSTCTRL_PPE2 | MTK_SRAM)
+ 
+ struct mtk_tx_dma_desc_info {
+ 	dma_addr_t	addr;
+@@ -1212,6 +1217,7 @@ struct mtk_eth {
+ 	struct device			*dev;
+ 	struct device			*dma_dev;
+ 	void __iomem			*base;
++	void				*sram_base;
+ 	spinlock_t			page_lock;
+ 	spinlock_t			tx_irq_lock;
+ 	spinlock_t			rx_irq_lock;

lede/target/linux/generic/backport-5.15/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch

@@ -0,0 +1,166 @@
+From 0b0d606eb9650fa01dd5621e072aa29a10544399 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 22 Aug 2023 17:33:12 +0100
+Subject: [PATCH 113/250] net: ethernet: mtk_eth_soc: support 36-bit DMA
+ addressing on MT7988
+
+Systems having 4 GiB of RAM and more require DMA addressing beyond the
+current 32-bit limit. Starting from MT7988 the hardware now supports
+36-bit DMA addressing, let's use that new capability in the driver to
+avoid running into swiotlb on systems with 4 GiB of RAM or more.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/95b919c98876c9e49761e44662e7c937479eecb8.1692721443.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 +++++++++++++++++++--
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 22 +++++++++++++--
+ 2 files changed, 48 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -1266,6 +1266,10 @@ static void mtk_tx_set_dma_desc_v2(struc
+ 	data = TX_DMA_PLEN0(info->size);
+ 	if (info->last)
+ 		data |= TX_DMA_LS0;
++
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
++		data |= TX_DMA_PREP_ADDR64(info->addr);
++
+ 	WRITE_ONCE(desc->txd3, data);
+ 
+ 	 /* set forward port */
+@@ -1933,6 +1937,7 @@ static int mtk_poll_rx(struct napi_struc
+ 	bool xdp_flush = false;
+ 	int idx;
+ 	struct sk_buff *skb;
++	u64 addr64 = 0;
+ 	u8 *data, *new_data;
+ 	struct mtk_rx_dma_v2 *rxd, trxd;
+ 	int done = 0, bytes = 0;
+@@ -2048,7 +2053,10 @@ static int mtk_poll_rx(struct napi_struc
+ 				goto release_desc;
+ 			}
+ 
+-			dma_unmap_single(eth->dma_dev, trxd.rxd1,
++			if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
++				addr64 = RX_DMA_GET_ADDR64(trxd.rxd2);
++
++			dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64),
+ 					 ring->buf_size, DMA_FROM_DEVICE);
+ 
+ 			skb = build_skb(data, ring->frag_size);
+@@ -2114,6 +2122,9 @@ release_desc:
+ 		else
+ 			rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
+ 
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
++			rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr);
++
+ 		ring->calc_idx = idx;
+ 		done++;
+ 	}
+@@ -2598,6 +2609,9 @@ static int mtk_rx_alloc(struct mtk_eth *
+ 		else
+ 			rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
+ 
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
++			rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr);
++
+ 		rxd->rxd3 = 0;
+ 		rxd->rxd4 = 0;
+ 		if (mtk_is_netsys_v2_or_greater(eth)) {
+@@ -2644,6 +2658,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+ 
+ static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram)
+ {
++	u64 addr64 = 0;
+ 	int i;
+ 
+ 	if (ring->data && ring->dma) {
+@@ -2657,7 +2672,10 @@ static void mtk_rx_clean(struct mtk_eth
+ 			if (!rxd->rxd1)
+ 				continue;
+ 
+-			dma_unmap_single(eth->dma_dev, rxd->rxd1,
++			if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
++				addr64 = RX_DMA_GET_ADDR64(rxd->rxd2);
++
++			dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64),
+ 					 ring->buf_size, DMA_FROM_DEVICE);
+ 			mtk_rx_put_buff(ring, ring->data[i], false);
+ 		}
+@@ -4643,6 +4661,14 @@ static int mtk_probe(struct platform_dev
+ 		}
+ 	}
+ 
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
++		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36));
++		if (err) {
++			dev_err(&pdev->dev, "Wrong DMA config\n");
++			return -EINVAL;
++		}
++	}
++
+ 	spin_lock_init(&eth->page_lock);
+ 	spin_lock_init(&eth->tx_irq_lock);
+ 	spin_lock_init(&eth->rx_irq_lock);
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -331,6 +331,14 @@
+ #define TX_DMA_PLEN1(x)		((x) & eth->soc->txrx.dma_max_len)
+ #define TX_DMA_SWC		BIT(14)
+ #define TX_DMA_PQID		GENMASK(3, 0)
++#define TX_DMA_ADDR64_MASK	GENMASK(3, 0)
++#if IS_ENABLED(CONFIG_64BIT)
++# define TX_DMA_GET_ADDR64(x)	(((u64)FIELD_GET(TX_DMA_ADDR64_MASK, (x))) << 32)
++# define TX_DMA_PREP_ADDR64(x)	FIELD_PREP(TX_DMA_ADDR64_MASK, ((x) >> 32))
++#else
++# define TX_DMA_GET_ADDR64(x)	(0)
++# define TX_DMA_PREP_ADDR64(x)	(0)
++#endif
+ 
+ /* PDMA on MT7628 */
+ #define TX_DMA_DONE		BIT(31)
+@@ -343,6 +351,14 @@
+ #define RX_DMA_PREP_PLEN0(x)	(((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
+ #define RX_DMA_GET_PLEN0(x)	(((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len)
+ #define RX_DMA_VTAG		BIT(15)
++#define RX_DMA_ADDR64_MASK	GENMASK(3, 0)
++#if IS_ENABLED(CONFIG_64BIT)
++# define RX_DMA_GET_ADDR64(x)	(((u64)FIELD_GET(RX_DMA_ADDR64_MASK, (x))) << 32)
++# define RX_DMA_PREP_ADDR64(x)	FIELD_PREP(RX_DMA_ADDR64_MASK, ((x) >> 32))
++#else
++# define RX_DMA_GET_ADDR64(x)	(0)
++# define RX_DMA_PREP_ADDR64(x)	(0)
++#endif
+ 
+ /* QDMA descriptor rxd3 */
+ #define RX_DMA_VID(x)		((x) & VLAN_VID_MASK)
+@@ -939,6 +955,7 @@ enum mkt_eth_capabilities {
+ 	MTK_RSTCTRL_PPE2_BIT,
+ 	MTK_U3_COPHY_V2_BIT,
+ 	MTK_SRAM_BIT,
++	MTK_36BIT_DMA_BIT,
+ 
+ 	/* MUX BITS*/
+ 	MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
+@@ -975,6 +992,7 @@ enum mkt_eth_capabilities {
+ #define MTK_RSTCTRL_PPE2	BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
+ #define MTK_U3_COPHY_V2		BIT_ULL(MTK_U3_COPHY_V2_BIT)
+ #define MTK_SRAM		BIT_ULL(MTK_SRAM_BIT)
++#define MTK_36BIT_DMA	BIT_ULL(MTK_36BIT_DMA_BIT)
+ 
+ #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW		\
+ 	BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
+@@ -1056,8 +1074,8 @@ enum mkt_eth_capabilities {
+ 		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
+ 		      MTK_RSTCTRL_PPE1 | MTK_SRAM)
+ 
+-#define MT7988_CAPS  (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1 | \
+-		      MTK_RSTCTRL_PPE2 | MTK_SRAM)
++#define MT7988_CAPS  (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \
++		      MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
+ 
+ struct mtk_tx_dma_desc_info {
+ 	dma_addr_t	addr;

lede/target/linux/generic/backport-5.15/792-01-v6.0-net-phylink-disable-PCS-polling-over-major-configura.patch

@@ -0,0 +1,81 @@
+From bfac8c490d605bea03b1f1927582b6f396462164 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Mon, 27 Jun 2022 12:44:43 +0100
+Subject: [PATCH] net: phylink: disable PCS polling over major configuration
+
+While we are performing a major configuration, there is no point having
+the PCS polling timer running. Stop it before we begin preparing for
+the configuration change, and restart it only once we've successfully
+completed the change.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 30 ++++++++++++++++++++----------
+ 1 file changed, 20 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -756,6 +756,18 @@ static void phylink_resolve_flow(struct
+ 	}
+ }
+ 
++static void phylink_pcs_poll_stop(struct phylink *pl)
++{
++	if (pl->cfg_link_an_mode == MLO_AN_INBAND)
++		del_timer(&pl->link_poll);
++}
++
++static void phylink_pcs_poll_start(struct phylink *pl)
++{
++	if (pl->pcs->poll && pl->cfg_link_an_mode == MLO_AN_INBAND)
++		mod_timer(&pl->link_poll, jiffies + HZ);
++}
++
+ static void phylink_mac_config(struct phylink *pl,
+ 			       const struct phylink_link_state *state)
+ {
+@@ -787,6 +799,7 @@ static void phylink_major_config(struct
+ 				  const struct phylink_link_state *state)
+ {
+ 	struct phylink_pcs *pcs = NULL;
++	bool pcs_changed = false;
+ 	int err;
+ 
+ 	phylink_dbg(pl, "major config %s\n", phy_modes(state->interface));
+@@ -799,8 +812,12 @@ static void phylink_major_config(struct
+ 				    pcs);
+ 			return;
+ 		}
++
++		pcs_changed = pcs && pl->pcs != pcs;
+ 	}
+ 
++	phylink_pcs_poll_stop(pl);
++
+ 	if (pl->mac_ops->mac_prepare) {
+ 		err = pl->mac_ops->mac_prepare(pl->config, pl->cur_link_an_mode,
+ 					       state->interface);
+@@ -814,8 +831,10 @@ static void phylink_major_config(struct
+ 	/* If we have a new PCS, switch to the new PCS after preparing the MAC
+ 	 * for the change.
+ 	 */
+-	if (pcs)
+-		phylink_set_pcs(pl, pcs);
++	if (pcs_changed) {
++		pl->pcs = pcs;
++		pl->pcs_ops = pcs->ops;
++	}
+ 
+ 	phylink_mac_config(pl, state);
+ 
+@@ -841,6 +860,8 @@ static void phylink_major_config(struct
+ 			phylink_err(pl, "mac_finish failed: %pe\n",
+ 				    ERR_PTR(err));
+ 	}
++
++	phylink_pcs_poll_start(pl);
+ }
+ 
+ /*

lede/target/linux/generic/backport-5.15/792-02-v6.0-net-phylink-fix-NULL-pl-pcs-dereference-during-phyli.patch

@@ -0,0 +1,38 @@
+From b7d78b46d5e8dc77c656c13885d31e931923b915 Mon Sep 17 00:00:00 2001
+From: Vladimir Oltean <vladimir.oltean@nxp.com>
+Date: Wed, 29 Jun 2022 22:33:58 +0300
+Subject: [PATCH] net: phylink: fix NULL pl->pcs dereference during
+ phylink_pcs_poll_start
+
+The current link mode of the phylink instance may not require an
+attached PCS. However, phylink_major_config() unconditionally
+dereferences this potentially NULL pointer when restarting the link poll
+timer, which will panic the kernel.
+
+Fix the problem by checking whether a PCS exists in phylink_pcs_poll_start(),
+otherwise do nothing. The code prior to the blamed patch also only
+looked at pcs->poll within an "if (pcs)" block.
+
+Fixes: bfac8c490d60 ("net: phylink: disable PCS polling over major configuration")
+Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Tested-by: Gerhard Engleder <gerhard@engleder-embedded.com>
+Tested-by: Michael Walle <michael@walle.cc> # on kontron-kbox-a-230-ls
+Tested-by: Nicolas Ferre <nicolas.ferre@microchip.com> # on sam9x60ek
+Link: https://lore.kernel.org/r/20220629193358.4007923-1-vladimir.oltean@nxp.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -764,7 +764,7 @@ static void phylink_pcs_poll_stop(struct
+ 
+ static void phylink_pcs_poll_start(struct phylink *pl)
+ {
+-	if (pl->pcs->poll && pl->cfg_link_an_mode == MLO_AN_INBAND)
++	if (pl->pcs && pl->pcs->poll && pl->cfg_link_an_mode == MLO_AN_INBAND)
+ 		mod_timer(&pl->link_poll, jiffies + HZ);
+ }
+ 

lede/target/linux/generic/backport-5.15/792-03-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch

@@ -0,0 +1,172 @@
+From 90ef0a7b0622c62758b2638604927867775479ea Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Thu, 13 Jul 2023 09:42:07 +0100
+Subject: [PATCH] net: phylink: add pcs_enable()/pcs_disable() methods
+
+Add phylink PCS enable/disable callbacks that will allow us to place
+IEEE 802.3 register compliant PCS in power-down mode while not being
+used.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phylink.c | 48 +++++++++++++++++++++++++++++++--------
+ include/linux/phylink.h   | 16 +++++++++++++
+ 2 files changed, 55 insertions(+), 9 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -34,6 +34,10 @@ enum {
+ 	PHYLINK_DISABLE_STOPPED,
+ 	PHYLINK_DISABLE_LINK,
+ 	PHYLINK_DISABLE_MAC_WOL,
++
++	PCS_STATE_DOWN = 0,
++	PCS_STATE_STARTING,
++	PCS_STATE_STARTED,
+ };
+ 
+ /**
+@@ -72,6 +76,7 @@ struct phylink {
+ 	struct mutex state_mutex;
+ 	struct phylink_link_state phy_state;
+ 	struct work_struct resolve;
++	unsigned int pcs_state;
+ 
+ 	bool mac_link_dropped;
+ 	bool using_mac_select_pcs;
+@@ -795,6 +800,22 @@ static void phylink_mac_pcs_an_restart(s
+ 	}
+ }
+ 
++static void phylink_pcs_disable(struct phylink_pcs *pcs)
++{
++	if (pcs && pcs->ops->pcs_disable)
++		pcs->ops->pcs_disable(pcs);
++}
++
++static int phylink_pcs_enable(struct phylink_pcs *pcs)
++{
++	int err = 0;
++
++	if (pcs && pcs->ops->pcs_enable)
++		err = pcs->ops->pcs_enable(pcs);
++
++	return err;
++}
++
+ static void phylink_major_config(struct phylink *pl, bool restart,
+ 				  const struct phylink_link_state *state)
+ {
+@@ -832,12 +853,16 @@ static void phylink_major_config(struct
+ 	 * for the change.
+ 	 */
+ 	if (pcs_changed) {
++		phylink_pcs_disable(pl->pcs);
+ 		pl->pcs = pcs;
+ 		pl->pcs_ops = pcs->ops;
+ 	}
+ 
+ 	phylink_mac_config(pl, state);
+ 
++	if (pl->pcs_state == PCS_STATE_STARTING || pcs_changed)
++		phylink_pcs_enable(pl->pcs);
++
+ 	if (pl->pcs_ops) {
+ 		err = pl->pcs_ops->pcs_config(pl->pcs, pl->cur_link_an_mode,
+ 					      state->interface,
+@@ -1260,6 +1285,7 @@ struct phylink *phylink_create(struct ph
+ 	pl->link_config.speed = SPEED_UNKNOWN;
+ 	pl->link_config.duplex = DUPLEX_UNKNOWN;
+ 	pl->link_config.an_enabled = true;
++	pl->pcs_state = PCS_STATE_DOWN;
+ 	pl->mac_ops = mac_ops;
+ 	__set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state);
+ 	timer_setup(&pl->link_poll, phylink_fixed_poll, 0);
+@@ -1651,6 +1677,8 @@ void phylink_start(struct phylink *pl)
+ 	if (pl->netdev)
+ 		netif_carrier_off(pl->netdev);
+ 
++	pl->pcs_state = PCS_STATE_STARTING;
++
+ 	/* Apply the link configuration to the MAC when starting. This allows
+ 	 * a fixed-link to start with the correct parameters, and also
+ 	 * ensures that we set the appropriate advertisement for Serdes links.
+@@ -1661,6 +1689,8 @@ void phylink_start(struct phylink *pl)
+ 	 */
+ 	phylink_mac_initial_config(pl, true);
+ 
++	pl->pcs_state = PCS_STATE_STARTED;
++
+ 	clear_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state);
+ 	phylink_run_resolve(pl);
+ 
+@@ -1680,16 +1710,9 @@ void phylink_start(struct phylink *pl)
+ 			poll = true;
+ 	}
+ 
+-	switch (pl->cfg_link_an_mode) {
+-	case MLO_AN_FIXED:
++	if (pl->cfg_link_an_mode == MLO_AN_FIXED)
+ 		poll |= pl->config->poll_fixed_state;
+-		break;
+-	case MLO_AN_INBAND:
+-		poll |= pl->config->pcs_poll;
+-		if (pl->pcs)
+-			poll |= pl->pcs->poll;
+-		break;
+-	}
++
+ 	if (poll)
+ 		mod_timer(&pl->link_poll, jiffies + HZ);
+ 	if (pl->phydev)
+@@ -1726,6 +1749,10 @@ void phylink_stop(struct phylink *pl)
+ 	}
+ 
+ 	phylink_run_resolve_and_disable(pl, PHYLINK_DISABLE_STOPPED);
++
++	pl->pcs_state = PCS_STATE_DOWN;
++
++	phylink_pcs_disable(pl->pcs);
+ }
+ EXPORT_SYMBOL_GPL(phylink_stop);
+ 
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -419,6 +419,8 @@ struct phylink_pcs {
+ /**
+  * struct phylink_pcs_ops - MAC PCS operations structure.
+  * @pcs_validate: validate the link configuration.
++ * @pcs_enable: enable the PCS.
++ * @pcs_disable: disable the PCS.
+  * @pcs_get_state: read the current MAC PCS link state from the hardware.
+  * @pcs_config: configure the MAC PCS for the selected mode and state.
+  * @pcs_an_restart: restart 802.3z BaseX autonegotiation.
+@@ -428,6 +430,8 @@ struct phylink_pcs {
+ struct phylink_pcs_ops {
+ 	int (*pcs_validate)(struct phylink_pcs *pcs, unsigned long *supported,
+ 			    const struct phylink_link_state *state);
++	int (*pcs_enable)(struct phylink_pcs *pcs);
++	void (*pcs_disable)(struct phylink_pcs *pcs);
+ 	void (*pcs_get_state)(struct phylink_pcs *pcs,
+ 			      struct phylink_link_state *state);
+ 	int (*pcs_config)(struct phylink_pcs *pcs, unsigned int mode,
+@@ -458,6 +462,18 @@ int pcs_validate(struct phylink_pcs *pcs
+ 		 const struct phylink_link_state *state);
+ 
+ /**
++ * pcs_enable() - enable the PCS.
++ * @pcs: a pointer to a &struct phylink_pcs.
++ */
++int pcs_enable(struct phylink_pcs *pcs);
++
++/**
++ * pcs_disable() - disable the PCS.
++ * @pcs: a pointer to a &struct phylink_pcs.
++ */
++void pcs_disable(struct phylink_pcs *pcs);
++
++/**
+  * pcs_get_state() - Read the current inband link state from the hardware
+  * @pcs: a pointer to a &struct phylink_pcs.
+  * @state: a pointer to a &struct phylink_link_state.

lede/target/linux/generic/backport-5.15/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch

@@ -0,0 +1,44 @@
+From e4ccdfb78a47132f2d215658aab8902fc457c4b4 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 18 Aug 2023 04:07:46 +0100
+Subject: [PATCH 082/125] net: pcs: lynxi: implement pcs_disable op
+
+When switching from 10GBase-R/5GBase-R/USXGMII to one of the interface
+modes provided by mtk-pcs-lynxi we need to make sure to always perform
+a full configuration of the PHYA.
+
+Implement pcs_disable op which resets the stored interface mode to
+PHY_INTERFACE_MODE_NA to trigger a full reconfiguration once the LynxI
+PCS driver had previously been deselected in favor of another PCS
+driver such as the to-be-added driver for the USXGMII PCS found in
+MT7988.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/f23d1a60d2c9d2fb72e32dcb0eaa5f7e867a3d68.1692327891.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/pcs/pcs-mtk-lynxi.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/net/pcs/pcs-mtk-lynxi.c
++++ b/drivers/net/pcs/pcs-mtk-lynxi.c
+@@ -241,11 +241,19 @@ static void mtk_pcs_lynxi_link_up(struct
+ 	}
+ }
+ 
++static void mtk_pcs_lynxi_disable(struct phylink_pcs *pcs)
++{
++	struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
++
++	mpcs->interface = PHY_INTERFACE_MODE_NA;
++}
++
+ static const struct phylink_pcs_ops mtk_pcs_lynxi_ops = {
+ 	.pcs_get_state = mtk_pcs_lynxi_get_state,
+ 	.pcs_config = mtk_pcs_lynxi_config,
+ 	.pcs_an_restart = mtk_pcs_lynxi_restart_an,
+ 	.pcs_link_up = mtk_pcs_lynxi_link_up,
++	.pcs_disable = mtk_pcs_lynxi_disable,
+ };
+ 
+ struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,

lede/target/linux/generic/backport-6.1/730-07-v6.3-net-ethernet-mtk_eth_soc-compile-out-netsys-v2-code-.patch

@@ -1,28 +0,0 @@
-From: Felix Fietkau <nbd@nbd.name>
-Date: Thu, 27 Oct 2022 23:39:52 +0200
-Subject: [PATCH] net: ethernet: mtk_eth_soc: compile out netsys v2 code
- on mt7621
-
-Avoid some branches in the hot path on low-end devices with limited CPU power,
-and reduce code size
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -921,7 +921,13 @@ enum mkt_eth_capabilities {
- #define MTK_MUX_GMAC12_TO_GEPHY_SGMII   \
- 	(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
- 
--#define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x)) == (_x))
-+#ifdef CONFIG_SOC_MT7621
-+#define MTK_CAP_MASK MTK_NETSYS_V2
-+#else
-+#define MTK_CAP_MASK 0
-+#endif
-+
-+#define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x) & ~(MTK_CAP_MASK)) == (_x))
- 
- #define MT7621_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
- 		      MTK_GMAC2_RGMII | MTK_SHARED_INT | \

lede/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch

@@ -181,7 +181,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  /* CDMP Ingress Control Register */
  #define MTK_CDMP_IG_CTRL	0x400
  #define MTK_CDMP_STAG_EN	BIT(0)
-@@ -1170,6 +1176,8 @@ struct mtk_eth {
+@@ -1164,6 +1170,8 @@ struct mtk_eth {
  
  	int				ip_align;
  

lede/target/linux/generic/backport-6.1/733-v6.2-12-net-mediatek-sgmii-ensure-the-SGMII-PHY-is-powered-d.patch

@@ -34,7 +34,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -1073,11 +1073,13 @@ struct mtk_soc_data {
+@@ -1067,11 +1067,13 @@ struct mtk_soc_data {
   * @regmap:            The register map pointing at the range used to setup
   *                     SGMII modes
   * @ana_rgc3:          The offset refers to register ANA_RGC3 related to regmap

lede/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch

@@ -14,6 +14,12 @@ new device-tree attribute 'mediatek,pn_swap' to support them.
 
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_path.c | 14 +++++++--
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c  | 21 +++++++++++++
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h  | 31 ++++++++++++++++++++
+ drivers/net/ethernet/mediatek/mtk_sgmii.c    | 10 +++++++
+ 4 files changed, 73 insertions(+), 3 deletions(-)
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
@@ -145,7 +151,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW		\
  	BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
-@@ -966,6 +990,11 @@ enum mkt_eth_capabilities {
+@@ -960,6 +984,11 @@ enum mkt_eth_capabilities {
  		      MTK_MUX_U3_GMAC2_TO_QPHY | \
  		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
  
@@ -157,7 +163,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  #define MT7986_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
  		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
  		      MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
-@@ -1079,12 +1108,14 @@ struct mtk_soc_data {
+@@ -1073,12 +1102,14 @@ struct mtk_soc_data {
   * @ana_rgc3:          The offset refers to register ANA_RGC3 related to regmap
   * @interface:         Currently configured interface mode
   * @pcs:               Phylink PCS structure

lede/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch

@@ -228,7 +228,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  /* Infrasys subsystem config registers */
  #define INFRA_MISC2            0x70c
  #define CO_QPHY_SEL            BIT(0)
-@@ -1108,31 +1049,6 @@ struct mtk_soc_data {
+@@ -1102,31 +1043,6 @@ struct mtk_soc_data {
  /* currently no SoC has more than 2 macs */
  #define MTK_MAX_DEVS			2
  
@@ -260,7 +260,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  /* struct mtk_eth -	This is the main datasructure for holding the state
   *			of the driver
   * @dev:		The device pointer
-@@ -1152,6 +1068,7 @@ struct mtk_sgmii {
+@@ -1146,6 +1062,7 @@ struct mtk_sgmii {
   *			MII modes
   * @infra:              The register map pointing at the range used to setup
   *                      SGMII and GePHY path
@@ -268,7 +268,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
   * @pctl:		The register map pointing at the range used to setup
   *			GMAC port drive/slew values
   * @dma_refcnt:		track how many netdevs are using the DMA engine
-@@ -1192,8 +1109,8 @@ struct mtk_eth {
+@@ -1186,8 +1103,8 @@ struct mtk_eth {
  	u32				msg_enable;
  	unsigned long			sysclk;
  	struct regmap			*ethsys;
@@ -279,7 +279,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct regmap			*pctl;
  	bool				hwlro;
  	refcount_t			dma_refcnt;
-@@ -1355,10 +1272,6 @@ void mtk_stats_update_mac(struct mtk_mac
+@@ -1349,10 +1266,6 @@ void mtk_stats_update_mac(struct mtk_mac
  void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
  u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
  

lede/target/linux/generic/backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch

@@ -1,59 +1,33 @@
-From patchwork Wed Nov  2 00:58:01 2022
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
-X-Patchwork-Id: 13027653
-X-Patchwork-Delegate: kuba@kernel.org
-Return-Path: <netdev-owner@kernel.org>
-Date: Wed, 2 Nov 2022 00:58:01 +0000
+From f601293f37c4be618c5efaef85d2ee21f97e82e0 Mon Sep 17 00:00:00 2001
 From: Daniel Golle <daniel@makrotopia.org>
-To: Felix Fietkau <nbd@nbd.name>, John Crispin <john@phrozen.org>,
-        Sean Wang <sean.wang@mediatek.com>,
-        Mark Lee <Mark-MC.Lee@mediatek.com>,
-        "David S. Miller" <davem@davemloft.net>,
-        Eric Dumazet <edumazet@google.com>,
-        Jakub Kicinski <kuba@kernel.org>,
-        Paolo Abeni <pabeni@redhat.com>,
-        Matthias Brugger <matthias.bgg@gmail.com>,
-        netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
-        linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org
-Subject: [PATCH v4] net: ethernet: mediatek: ppe: add support for flow
+Date: Sun, 19 Mar 2023 12:57:35 +0000
+Subject: [PATCH 092/250] net: ethernet: mtk_eth_soc: ppe: add support for flow
  accounting
-Message-ID: <Y2HAmYYPd77dz+K5@makrotopia.org>
 MIME-Version: 1.0
-Content-Disposition: inline
-Precedence: bulk
-List-ID: <netdev.vger.kernel.org>
-X-Mailing-List: netdev@vger.kernel.org
-X-Patchwork-Delegate: kuba@kernel.org
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
 
 The PPE units found in MT7622 and newer support packet and byte
-accounting of hw-offloaded flows. Add support for reading those
-counters as found in MediaTek's SDK[1].
+accounting of hw-offloaded flows. Add support for reading those counters
+as found in MediaTek's SDK[1].
 
 [1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/bc6a6a375c800dc2b80e1a325a2c732d1737df92
+Tested-by: Bjørn Mork <bjorn@mork.no>
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 ---
-v4: declare function mtk_mib_entry_read as static
-v3: don't bother to set 'false' values in any zero-initialized struct
-    use mtk_foe_entry_ib2
-    both changes were requested by Felix Fietkau
-
-v2: fix wrong variable name in return value check spotted by Denis Kirjanov
-
- drivers/net/ethernet/mediatek/mtk_eth_soc.c   |   7 +-
- drivers/net/ethernet/mediatek/mtk_eth_soc.h   |   1 +
- drivers/net/ethernet/mediatek/mtk_ppe.c       | 110 +++++++++++++++++-
- drivers/net/ethernet/mediatek/mtk_ppe.h       |  23 +++-
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c   |   8 +-
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h   |   3 +
+ drivers/net/ethernet/mediatek/mtk_ppe.c       | 114 +++++++++++++++++-
+ drivers/net/ethernet/mediatek/mtk_ppe.h       |  25 +++-
  .../net/ethernet/mediatek/mtk_ppe_debugfs.c   |   9 +-
- .../net/ethernet/mediatek/mtk_ppe_offload.c   |   7 ++
+ .../net/ethernet/mediatek/mtk_ppe_offload.c   |   8 ++
  drivers/net/ethernet/mediatek/mtk_ppe_regs.h  |  14 +++
- 7 files changed, 166 insertions(+), 5 deletions(-)
+ 7 files changed, 172 insertions(+), 9 deletions(-)
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4637,8 +4637,8 @@ static int mtk_probe(struct platform_dev
+@@ -4689,8 +4689,8 @@ static int mtk_probe(struct platform_dev
  		for (i = 0; i < num_ppe; i++) {
  			u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
  
@@ -63,8 +37,8 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
 +
  			if (!eth->ppe[i]) {
  				err = -ENOMEM;
- 				goto err_free_dev;
-@@ -4765,6 +4765,7 @@ static const struct mtk_soc_data mt7622_
+ 				goto err_deinit_ppe;
+@@ -4814,6 +4814,7 @@ static const struct mtk_soc_data mt7622_
  	.required_pctl = false,
  	.offload_version = 2,
  	.hash_offset = 2,
@@ -72,7 +46,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
-@@ -4802,6 +4803,7 @@ static const struct mtk_soc_data mt7629_
+@@ -4851,6 +4852,7 @@ static const struct mtk_soc_data mt7629_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7629_CLKS_BITMAP,
  	.required_pctl = false,
@@ -80,7 +54,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4822,6 +4824,7 @@ static const struct mtk_soc_data mt7981_
+@@ -4871,6 +4873,7 @@ static const struct mtk_soc_data mt7981_
  	.offload_version = 2,
  	.hash_offset = 4,
  	.foe_entry_size = sizeof(struct mtk_foe_entry),
@@ -88,7 +62,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma_v2),
  		.rxd_size = sizeof(struct mtk_rx_dma_v2),
-@@ -4842,6 +4845,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4891,6 +4894,7 @@ static const struct mtk_soc_data mt7986_
  	.offload_version = 2,
  	.hash_offset = 4,
  	.foe_entry_size = sizeof(struct mtk_foe_entry),
@@ -98,7 +72,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  		.rxd_size = sizeof(struct mtk_rx_dma_v2),
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -1014,6 +1014,8 @@ struct mtk_reg_map {
+@@ -1011,6 +1011,8 @@ struct mtk_reg_map {
   *				the extra setup for those pins used by GMAC.
   * @hash_offset			Flow table hash offset.
   * @foe_entry_size		Foe table entry size.
@@ -107,7 +81,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
   * @txd_size			Tx DMA descriptor size.
   * @rxd_size			Rx DMA descriptor size.
   * @rx_irq_done_mask		Rx irq done register mask.
-@@ -1031,6 +1033,7 @@ struct mtk_soc_data {
+@@ -1028,6 +1030,7 @@ struct mtk_soc_data {
  	u8		hash_offset;
  	u16		foe_entry_size;
  	netdev_features_t hw_features;
@@ -166,10 +140,10 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  static void mtk_ppe_cache_clear(struct mtk_ppe *ppe)
  {
  	ppe_set(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);
-@@ -464,6 +506,13 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp
- 		hwe->ib1 &= ~MTK_FOE_IB1_STATE;
+@@ -459,6 +501,13 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp
  		hwe->ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_INVALID);
  		dma_wmb();
+ 		mtk_ppe_cache_clear(ppe);
 +		if (ppe->accounting) {
 +			struct mtk_foe_accounting *acct;
 +
@@ -180,7 +154,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	}
  	entry->hash = 0xffff;
  
-@@ -571,6 +620,9 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
+@@ -566,6 +615,9 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
  	wmb();
  	hwe->ib1 = entry->ib1;
  
@@ -190,7 +164,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	dma_wmb();
  
  	mtk_ppe_cache_clear(ppe);
-@@ -762,11 +814,39 @@ int mtk_ppe_prepare_reset(struct mtk_ppe
+@@ -757,11 +809,39 @@ int mtk_ppe_prepare_reset(struct mtk_ppe
  	return mtk_ppe_wait_busy(ppe);
  }
  
@@ -232,7 +206,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	struct mtk_ppe *ppe;
  	u32 foe_flow_size;
  	void *foe;
-@@ -783,7 +863,8 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
+@@ -778,7 +858,8 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
  	ppe->base = base;
  	ppe->eth = eth;
  	ppe->dev = dev;
@@ -242,9 +216,9 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  
  	foe = dmam_alloc_coherent(ppe->dev,
  				  MTK_PPE_ENTRIES * soc->foe_entry_size,
-@@ -799,6 +880,23 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
+@@ -794,6 +875,23 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
  	if (!ppe->foe_flow)
- 		return NULL;
+ 		goto err_free_l2_flows;
  
 +	if (accounting) {
 +		mib = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * sizeof(*mib),
@@ -266,7 +240,7 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	mtk_ppe_debugfs_init(ppe, index);
  
  	return ppe;
-@@ -913,6 +1011,16 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
+@@ -923,6 +1021,16 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
  		ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777);
  		ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f);
  	}
@@ -328,17 +302,18 @@ v2: fix wrong variable name in return value check spotted by Denis Kirjanov
  	u16 foe_check_time[MTK_PPE_ENTRIES];
  	struct hlist_head *foe_flow;
  
-@@ -303,8 +322,7 @@ struct mtk_ppe {
+@@ -303,8 +322,8 @@ struct mtk_ppe {
  	void *acct_table;
  };
  
 -struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,
 -			     int version, int index);
 +struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, int index);
++
+ void mtk_ppe_deinit(struct mtk_eth *eth);
  void mtk_ppe_start(struct mtk_ppe *ppe);
  int mtk_ppe_stop(struct mtk_ppe *ppe);
- int mtk_ppe_prepare_reset(struct mtk_ppe *ppe);
-@@ -358,5 +376,7 @@ int mtk_foe_entry_commit(struct mtk_ppe
+@@ -359,5 +378,7 @@ int mtk_foe_entry_commit(struct mtk_ppe
  void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);
  int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);
  int mtk_ppe_debugfs_init(struct mtk_ppe *ppe, int index);

lede/target/linux/generic/backport-6.1/733-v6.4-24-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch

@@ -1,17 +1,24 @@
+From 88a0fd5927b7c2c7aecd6dc747d898eb38043d2b Mon Sep 17 00:00:00 2001
 From: Felix Fietkau <nbd@nbd.name>
-Date: Thu, 23 Mar 2023 21:45:43 +0100
-Subject: [PATCH] net: ethernet: mediatek: fix ppe flow accounting for v1
- hardware
+Date: Thu, 20 Apr 2023 22:06:42 +0100
+Subject: [PATCH 093/250] net: mtk_eth_soc: mediatek: fix ppe flow accounting
+ for v1 hardware
 
 Older chips (like MT7622) use a different bit in ib2 to enable hardware
-counter support.
+counter support. Add macros for both and select the appropriate bit.
 
+Fixes: 3fbe4d8c0e53 ("net: ethernet: mtk_eth_soc: ppe: add support for flow accounting")
 Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
 ---
+ drivers/net/ethernet/mediatek/mtk_ppe.c | 10 ++++++++--
+ drivers/net/ethernet/mediatek/mtk_ppe.h |  3 ++-
+ 2 files changed, 10 insertions(+), 3 deletions(-)
 
 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c
 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
-@@ -640,6 +640,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
+@@ -599,6 +599,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
  	struct mtk_eth *eth = ppe->eth;
  	u16 timestamp = mtk_eth_timestamp(eth);
  	struct mtk_foe_entry *hwe;
@@ -19,7 +26,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  		entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP_V2;
-@@ -656,8 +657,13 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
+@@ -615,8 +616,13 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
  	wmb();
  	hwe->ib1 = entry->ib1;
  

lede/target/linux/generic/backport-6.1/733-v6.5-26-net-ethernet-mtk_eth_soc-always-mtk_get_ib1_pkt_type.patch

@@ -0,0 +1,31 @@
+From b804f765485109f9644cc05d1e8fc79ca6c6e4aa Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 19 Jul 2023 01:39:36 +0100
+Subject: [PATCH 094/250] net: ethernet: mtk_eth_soc: always
+ mtk_get_ib1_pkt_type
+
+entries and bind debugfs files would display wrong data on NETSYS_V2 and
+later because instead of using mtk_get_ib1_pkt_type the driver would use
+MTK_FOE_IB1_PACKET_TYPE which corresponds to NETSYS_V1(.x) SoCs.
+Use mtk_get_ib1_pkt_type so entries and bind records display correctly.
+
+Fixes: 03a3180e5c09e ("net: ethernet: mtk_eth_soc: introduce flow offloading support for mt7986")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://lore.kernel.org/r/c0ae03d0182f4d27b874cbdf0059bc972c317f3c.1689727134.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c
+@@ -98,7 +98,7 @@ mtk_ppe_debugfs_foe_show(struct seq_file
+ 
+ 		acct = mtk_foe_entry_get_mib(ppe, i, NULL);
+ 
+-		type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
++		type = mtk_get_ib1_pkt_type(ppe->eth, entry->ib1);
+ 		seq_printf(m, "%05x %s %7s", i,
+ 			   mtk_foe_entry_state_str(state),
+ 			   mtk_foe_pkt_type_str(type));

lede/target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch

@@ -0,0 +1,78 @@
+From 5ea0e1312bcfebc06b5f91d1bb82b823d6395125 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Wed, 19 Jul 2023 12:29:49 +0200
+Subject: [PATCH 095/250] net: ethernet: mtk_ppe: add MTK_FOE_ENTRY_V{1,2}_SIZE
+ macros
+
+Introduce MTK_FOE_ENTRY_V{1,2}_SIZE macros in order to make more
+explicit foe_entry size for different chipset revisions.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 10 +++++-----
+ drivers/net/ethernet/mediatek/mtk_ppe.h     |  3 +++
+ 2 files changed, 8 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -4763,7 +4763,7 @@ static const struct mtk_soc_data mt7621_
+ 	.required_pctl = false,
+ 	.offload_version = 1,
+ 	.hash_offset = 2,
+-	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
++	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+@@ -4784,7 +4784,7 @@ static const struct mtk_soc_data mt7622_
+ 	.offload_version = 2,
+ 	.hash_offset = 2,
+ 	.has_accounting = true,
+-	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
++	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+@@ -4803,7 +4803,7 @@ static const struct mtk_soc_data mt7623_
+ 	.required_pctl = true,
+ 	.offload_version = 1,
+ 	.hash_offset = 2,
+-	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
++	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+@@ -4841,8 +4841,8 @@ static const struct mtk_soc_data mt7981_
+ 	.required_pctl = false,
+ 	.offload_version = 2,
+ 	.hash_offset = 4,
+-	.foe_entry_size = sizeof(struct mtk_foe_entry),
+ 	.has_accounting = true,
++	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma_v2),
+ 		.rxd_size = sizeof(struct mtk_rx_dma_v2),
+@@ -4862,8 +4862,8 @@ static const struct mtk_soc_data mt7986_
+ 	.required_pctl = false,
+ 	.offload_version = 2,
+ 	.hash_offset = 4,
+-	.foe_entry_size = sizeof(struct mtk_foe_entry),
+ 	.has_accounting = true,
++	.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma_v2),
+ 		.rxd_size = sizeof(struct mtk_rx_dma_v2),
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.h
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
+@@ -216,6 +216,9 @@ struct mtk_foe_ipv6_6rd {
+ 	struct mtk_foe_mac_info l2;
+ };
+ 
++#define MTK_FOE_ENTRY_V1_SIZE	80
++#define MTK_FOE_ENTRY_V2_SIZE	96
++
+ struct mtk_foe_entry {
+ 	u32 ib1;
+ 

lede/target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch

@@ -0,0 +1,141 @@
+From 8cfa2576d79f9379d167a8994f0fca935c07a8bc Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Sat, 22 Jul 2023 21:32:49 +0100
+Subject: [PATCH 096/250] net: ethernet: mtk_eth_soc: remove incorrect PLL
+ configuration
+
+MT7623 GMAC0 attempts to configure the system clocking according to the
+required speed in the .mac_config callback for non-SGMII, non-baseX and
+non-TRGMII modes.
+
+state->speed setting has never been reliable in the .mac_config
+callback - there are cases where this is not the link speed,
+particularly via ethtool paths, so this has always been unreliable (as
+detailed in phylink's documentation.)
+
+There is the additional issue that mtk_gmac0_rgmii_adjust() will only
+be called if state->interface changes, which means it only configures
+the system clocking on the very first .mac_config call, which will be
+made when the network device is first brought up before any link is
+established.
+
+Essentially, this code is incredibly buggy, and probably never worked.
+
+Moreover, checking the in-kernel DT files, it seems no platform makes
+use of this code path.
+
+Therefore, let's remove it, and disable interface modes for port 0 that
+are not SGMII, 1000base-X, 2500base-X or TRGMII on the MT7623.
+
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Frank Wunderlich <frank-w@public-files.de>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 54 ++++++---------------
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h |  1 +
+ 2 files changed, 17 insertions(+), 38 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -352,7 +352,7 @@ static int mt7621_gmac0_rgmii_adjust(str
+ }
+ 
+ static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
+-				   phy_interface_t interface, int speed)
++				   phy_interface_t interface)
+ {
+ 	u32 val;
+ 	int ret;
+@@ -366,26 +366,7 @@ static void mtk_gmac0_rgmii_adjust(struc
+ 		return;
+ 	}
+ 
+-	val = (speed == SPEED_1000) ?
+-		INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
+-	mtk_w32(eth, val, INTF_MODE);
+-
+-	regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
+-			   ETHSYS_TRGMII_CLK_SEL362_5,
+-			   ETHSYS_TRGMII_CLK_SEL362_5);
+-
+-	val = (speed == SPEED_1000) ? 250000000 : 500000000;
+-	ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
+-	if (ret)
+-		dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
+-
+-	val = (speed == SPEED_1000) ?
+-		RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
+-	mtk_w32(eth, val, TRGMII_RCK_CTRL);
+-
+-	val = (speed == SPEED_1000) ?
+-		TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
+-	mtk_w32(eth, val, TRGMII_TCK_CTRL);
++	dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n");
+ }
+ 
+ static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
+@@ -471,17 +452,8 @@ static void mtk_mac_config(struct phylin
+ 							      state->interface))
+ 					goto err_phy;
+ 			} else {
+-				/* FIXME: this is incorrect. Not only does it
+-				 * use state->speed (which is not guaranteed
+-				 * to be correct) but it also makes use of it
+-				 * in a code path that will only be reachable
+-				 * when the PHY interface mode changes, not
+-				 * when the speed changes. Consequently, RGMII
+-				 * is probably broken.
+-				 */
+ 				mtk_gmac0_rgmii_adjust(mac->hw,
+-						       state->interface,
+-						       state->speed);
++						       state->interface);
+ 
+ 				/* mt7623_pad_clk_setup */
+ 				for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
+@@ -4340,13 +4312,19 @@ static int mtk_add_mac(struct mtk_eth *e
+ 	mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ 		MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
+ 
+-	__set_bit(PHY_INTERFACE_MODE_MII,
+-		  mac->phylink_config.supported_interfaces);
+-	__set_bit(PHY_INTERFACE_MODE_GMII,
+-		  mac->phylink_config.supported_interfaces);
++	/* MT7623 gmac0 is now missing its speed-specific PLL configuration
++	 * in its .mac_config method (since state->speed is not valid there.
++	 * Disable support for MII, GMII and RGMII.
++	 */
++	if (!mac->hw->soc->disable_pll_modes || mac->id != 0) {
++		__set_bit(PHY_INTERFACE_MODE_MII,
++			  mac->phylink_config.supported_interfaces);
++		__set_bit(PHY_INTERFACE_MODE_GMII,
++			  mac->phylink_config.supported_interfaces);
+ 
+-	if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII))
+-		phy_interface_set_rgmii(mac->phylink_config.supported_interfaces);
++		if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII))
++			phy_interface_set_rgmii(mac->phylink_config.supported_interfaces);
++	}
+ 
+ 	if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id)
+ 		__set_bit(PHY_INTERFACE_MODE_TRGMII,
+@@ -4804,6 +4782,7 @@ static const struct mtk_soc_data mt7623_
+ 	.offload_version = 1,
+ 	.hash_offset = 2,
+ 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
++	.disable_pll_modes = true,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -1030,6 +1030,7 @@ struct mtk_soc_data {
+ 	u16		foe_entry_size;
+ 	netdev_features_t hw_features;
+ 	bool		has_accounting;
++	bool		disable_pll_modes;
+ 	struct {
+ 		u32	txd_size;
+ 		u32	rxd_size;

lede/target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch

@@ -0,0 +1,81 @@
+From a4c2233b1e4359b6c64b6f9ba98c8718a11fffee Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Sat, 22 Jul 2023 21:32:54 +0100
+Subject: [PATCH 097/250] net: ethernet: mtk_eth_soc: remove mac_pcs_get_state
+ and modernise
+
+Remove the .mac_pcs_get_state function, since as far as I can tell is
+never called - no DT appears to specify an in-band-status management
+nor SFP support for this driver.
+
+Removal of this, along with the previous patch to remove the incorrect
+clocking configuration, means that the driver becomes non-legacy, so
+we can remove the "legacy_pre_march2020" status from this driver.
+
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Frank Wunderlich <frank-w@public-files.de>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 35 ---------------------
+ 1 file changed, 35 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -555,38 +555,6 @@ static int mtk_mac_finish(struct phylink
+ 	return 0;
+ }
+ 
+-static void mtk_mac_pcs_get_state(struct phylink_config *config,
+-				  struct phylink_link_state *state)
+-{
+-	struct mtk_mac *mac = container_of(config, struct mtk_mac,
+-					   phylink_config);
+-	u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id));
+-
+-	state->link = (pmsr & MAC_MSR_LINK);
+-	state->duplex = (pmsr & MAC_MSR_DPX) >> 1;
+-
+-	switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) {
+-	case 0:
+-		state->speed = SPEED_10;
+-		break;
+-	case MAC_MSR_SPEED_100:
+-		state->speed = SPEED_100;
+-		break;
+-	case MAC_MSR_SPEED_1000:
+-		state->speed = SPEED_1000;
+-		break;
+-	default:
+-		state->speed = SPEED_UNKNOWN;
+-		break;
+-	}
+-
+-	state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
+-	if (pmsr & MAC_MSR_RX_FC)
+-		state->pause |= MLO_PAUSE_RX;
+-	if (pmsr & MAC_MSR_TX_FC)
+-		state->pause |= MLO_PAUSE_TX;
+-}
+-
+ static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
+ 			      phy_interface_t interface)
+ {
+@@ -709,7 +677,6 @@ static void mtk_mac_link_up(struct phyli
+ static const struct phylink_mac_ops mtk_phylink_ops = {
+ 	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = mtk_mac_select_pcs,
+-	.mac_pcs_get_state = mtk_mac_pcs_get_state,
+ 	.mac_config = mtk_mac_config,
+ 	.mac_finish = mtk_mac_finish,
+ 	.mac_link_down = mtk_mac_link_down,
+@@ -4307,8 +4274,6 @@ static int mtk_add_mac(struct mtk_eth *e
+ 
+ 	mac->phylink_config.dev = &eth->netdev[id]->dev;
+ 	mac->phylink_config.type = PHYLINK_NETDEV;
+-	/* This driver makes use of state->speed in mac_config */
+-	mac->phylink_config.legacy_pre_march2020 = true;
+ 	mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ 		MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
+ 

lede/target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch

@@ -0,0 +1,550 @@
+From 5d8d05fbf804b4485646d39551ac27452e45afd3 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 25 Jul 2023 01:52:02 +0100
+Subject: [PATCH 099/250] net: ethernet: mtk_eth_soc: add version in
+ mtk_soc_data
+
+Introduce version field in mtk_soc_data data structure in order to
+make mtk_eth driver easier to maintain for chipset configuration
+codebase. Get rid of MTK_NETSYS_V2 bit in chip capabilities.
+This is a preliminary patch to introduce support for MT7988 SoC.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/e52fae302ca135436e5cdd26d38d87be2da63055.1690246066.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c   | 55 +++++++++++--------
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h   | 36 +++++++-----
+ drivers/net/ethernet/mediatek/mtk_ppe.c       | 18 +++---
+ .../net/ethernet/mediatek/mtk_ppe_offload.c   |  2 +-
+ drivers/net/ethernet/mediatek/mtk_wed.c       |  4 +-
+ 5 files changed, 66 insertions(+), 49 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -580,7 +580,7 @@ static void mtk_set_queue_speed(struct m
+ 	      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
+ 	      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
+ 	      MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
+-	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v1(eth))
+ 		val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
+ 
+ 	if (IS_ENABLED(CONFIG_SOC_MT7621)) {
+@@ -956,7 +956,7 @@ static bool mtk_rx_get_desc(struct mtk_e
+ 	rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
+ 	rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
+ 	rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
+ 		rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
+ 	}
+@@ -1014,7 +1014,7 @@ static int mtk_init_fq_dma(struct mtk_et
+ 
+ 		txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
+ 		txd->txd4 = 0;
+-		if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
++		if (mtk_is_netsys_v2_or_greater(eth)) {
+ 			txd->txd5 = 0;
+ 			txd->txd6 = 0;
+ 			txd->txd7 = 0;
+@@ -1205,7 +1205,7 @@ static void mtk_tx_set_dma_desc(struct n
+ 	struct mtk_mac *mac = netdev_priv(dev);
+ 	struct mtk_eth *eth = mac->hw;
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		mtk_tx_set_dma_desc_v2(dev, txd, info);
+ 	else
+ 		mtk_tx_set_dma_desc_v1(dev, txd, info);
+@@ -1512,7 +1512,7 @@ static void mtk_update_rx_cpu_idx(struct
+ 
+ static bool mtk_page_pool_enabled(struct mtk_eth *eth)
+ {
+-	return MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2);
++	return eth->soc->version == 2;
+ }
+ 
+ static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,
+@@ -1854,7 +1854,7 @@ static int mtk_poll_rx(struct napi_struc
+ 			break;
+ 
+ 		/* find out which mac the packet come from. values start at 1 */
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++		if (mtk_is_netsys_v2_or_greater(eth))
+ 			mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
+ 		else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
+ 			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
+@@ -1950,7 +1950,7 @@ static int mtk_poll_rx(struct napi_struc
+ 		skb->dev = netdev;
+ 		bytes += skb->len;
+ 
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++		if (mtk_is_netsys_v2_or_greater(eth)) {
+ 			reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
+ 			hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
+ 			if (hash != MTK_RXD5_FOE_ENTRY)
+@@ -1975,8 +1975,8 @@ static int mtk_poll_rx(struct napi_struc
+ 		/* When using VLAN untagging in combination with DSA, the
+ 		 * hardware treats the MTK special tag as a VLAN and untags it.
+ 		 */
+-		if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) &&
+-		    (trxd.rxd2 & RX_DMA_VTAG) && netdev_uses_dsa(netdev)) {
++		if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) &&
++		    netdev_uses_dsa(netdev)) {
+ 			unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
+ 
+ 			if (port < ARRAY_SIZE(eth->dsa_meta) &&
+@@ -2286,7 +2286,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+ 		txd->txd2 = next_ptr;
+ 		txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
+ 		txd->txd4 = 0;
+-		if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
++		if (mtk_is_netsys_v2_or_greater(eth)) {
+ 			txd->txd5 = 0;
+ 			txd->txd6 = 0;
+ 			txd->txd7 = 0;
+@@ -2339,14 +2339,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+ 			      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
+ 			      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
+ 			      MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
+-			if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++			if (mtk_is_netsys_v1(eth))
+ 				val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
+ 			mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
+ 			ofs += MTK_QTX_OFFSET;
+ 		}
+ 		val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16);
+ 		mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate);
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++		if (mtk_is_netsys_v2_or_greater(eth))
+ 			mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);
+ 	} else {
+ 		mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
+@@ -2475,7 +2475,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+ 
+ 		rxd->rxd3 = 0;
+ 		rxd->rxd4 = 0;
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++		if (mtk_is_netsys_v2_or_greater(eth)) {
+ 			rxd->rxd5 = 0;
+ 			rxd->rxd6 = 0;
+ 			rxd->rxd7 = 0;
+@@ -3023,7 +3023,7 @@ static int mtk_start_dma(struct mtk_eth
+ 		       MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
+ 		       MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
+ 
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++		if (mtk_is_netsys_v2_or_greater(eth))
+ 			val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
+ 			       MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
+ 			       MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN;
+@@ -3165,7 +3165,7 @@ static int mtk_open(struct net_device *d
+ 	phylink_start(mac->phylink);
+ 	netif_tx_start_all_queues(dev);
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return 0;
+ 
+ 	if (mtk_uses_dsa(dev) && !eth->prog) {
+@@ -3430,7 +3430,7 @@ static void mtk_hw_reset(struct mtk_eth
+ {
+ 	u32 val;
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
+ 		val = RSTCTRL_PPE0_V2;
+ 	} else {
+@@ -3442,7 +3442,7 @@ static void mtk_hw_reset(struct mtk_eth
+ 
+ 	ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
+ 			     0x3ffffff);
+ }
+@@ -3468,7 +3468,7 @@ static void mtk_hw_warm_reset(struct mtk
+ 		return;
+ 	}
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
+ 	else
+ 		rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
+@@ -3638,7 +3638,7 @@ static int mtk_hw_init(struct mtk_eth *e
+ 	else
+ 		mtk_hw_reset(eth);
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		/* Set FE to PDMAv2 if necessary */
+ 		val = mtk_r32(eth, MTK_FE_GLO_MISC);
+ 		mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);
+@@ -3675,7 +3675,7 @@ static int mtk_hw_init(struct mtk_eth *e
+ 	 */
+ 	val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
+ 	mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
+-	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v1(eth)) {
+ 		val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
+ 		mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
+ 
+@@ -3697,7 +3697,7 @@ static int mtk_hw_init(struct mtk_eth *e
+ 	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
+ 	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		/* PSE should not drop port8 and port9 packets from WDMA Tx */
+ 		mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
+ 
+@@ -4486,7 +4486,7 @@ static int mtk_probe(struct platform_dev
+ 		}
+ 	}
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 		if (!res) {
+ 			err = -EINVAL;
+@@ -4594,9 +4594,8 @@ static int mtk_probe(struct platform_dev
+ 	}
+ 
+ 	if (eth->soc->offload_version) {
+-		u32 num_ppe;
++		u32 num_ppe = mtk_is_netsys_v2_or_greater(eth) ? 2 : 1;
+ 
+-		num_ppe = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1;
+ 		num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe);
+ 		for (i = 0; i < num_ppe; i++) {
+ 			u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
+@@ -4688,6 +4687,7 @@ static const struct mtk_soc_data mt2701_
+ 	.hw_features = MTK_HW_FEATURES,
+ 	.required_clks = MT7623_CLKS_BITMAP,
+ 	.required_pctl = true,
++	.version = 1,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+@@ -4704,6 +4704,7 @@ static const struct mtk_soc_data mt7621_
+ 	.hw_features = MTK_HW_FEATURES,
+ 	.required_clks = MT7621_CLKS_BITMAP,
+ 	.required_pctl = false,
++	.version = 1,
+ 	.offload_version = 1,
+ 	.hash_offset = 2,
+ 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
+@@ -4724,6 +4725,7 @@ static const struct mtk_soc_data mt7622_
+ 	.hw_features = MTK_HW_FEATURES,
+ 	.required_clks = MT7622_CLKS_BITMAP,
+ 	.required_pctl = false,
++	.version = 1,
+ 	.offload_version = 2,
+ 	.hash_offset = 2,
+ 	.has_accounting = true,
+@@ -4744,6 +4746,7 @@ static const struct mtk_soc_data mt7623_
+ 	.hw_features = MTK_HW_FEATURES,
+ 	.required_clks = MT7623_CLKS_BITMAP,
+ 	.required_pctl = true,
++	.version = 1,
+ 	.offload_version = 1,
+ 	.hash_offset = 2,
+ 	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
+@@ -4766,6 +4769,7 @@ static const struct mtk_soc_data mt7629_
+ 	.required_clks = MT7629_CLKS_BITMAP,
+ 	.required_pctl = false,
+ 	.has_accounting = true,
++	.version = 1,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+@@ -4783,6 +4787,7 @@ static const struct mtk_soc_data mt7981_
+ 	.hw_features = MTK_HW_FEATURES,
+ 	.required_clks = MT7981_CLKS_BITMAP,
+ 	.required_pctl = false,
++	.version = 2,
+ 	.offload_version = 2,
+ 	.hash_offset = 4,
+ 	.has_accounting = true,
+@@ -4804,6 +4809,7 @@ static const struct mtk_soc_data mt7986_
+ 	.hw_features = MTK_HW_FEATURES,
+ 	.required_clks = MT7986_CLKS_BITMAP,
+ 	.required_pctl = false,
++	.version = 2,
+ 	.offload_version = 2,
+ 	.hash_offset = 4,
+ 	.has_accounting = true,
+@@ -4824,6 +4830,7 @@ static const struct mtk_soc_data rt5350_
+ 	.hw_features = MTK_HW_FEATURES_MT7628,
+ 	.required_clks = MT7628_CLKS_BITMAP,
+ 	.required_pctl = false,
++	.version = 1,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma),
+ 		.rxd_size = sizeof(struct mtk_rx_dma),
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -820,7 +820,6 @@ enum mkt_eth_capabilities {
+ 	MTK_SHARED_INT_BIT,
+ 	MTK_TRGMII_MT7621_CLK_BIT,
+ 	MTK_QDMA_BIT,
+-	MTK_NETSYS_V2_BIT,
+ 	MTK_SOC_MT7628_BIT,
+ 	MTK_RSTCTRL_PPE1_BIT,
+ 	MTK_U3_COPHY_V2_BIT,
+@@ -855,7 +854,6 @@ enum mkt_eth_capabilities {
+ #define MTK_SHARED_INT		BIT(MTK_SHARED_INT_BIT)
+ #define MTK_TRGMII_MT7621_CLK	BIT(MTK_TRGMII_MT7621_CLK_BIT)
+ #define MTK_QDMA		BIT(MTK_QDMA_BIT)
+-#define MTK_NETSYS_V2		BIT(MTK_NETSYS_V2_BIT)
+ #define MTK_SOC_MT7628		BIT(MTK_SOC_MT7628_BIT)
+ #define MTK_RSTCTRL_PPE1	BIT(MTK_RSTCTRL_PPE1_BIT)
+ #define MTK_U3_COPHY_V2		BIT(MTK_U3_COPHY_V2_BIT)
+@@ -934,11 +932,11 @@ enum mkt_eth_capabilities {
+ #define MT7981_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
+ 		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
+ 		      MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
+-		      MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
++		      MTK_RSTCTRL_PPE1)
+ 
+ #define MT7986_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
+ 		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
+-		      MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
++		      MTK_RSTCTRL_PPE1)
+ 
+ struct mtk_tx_dma_desc_info {
+ 	dma_addr_t	addr;
+@@ -1009,6 +1007,7 @@ struct mtk_reg_map {
+  * @required_pctl		A bool value to show whether the SoC requires
+  *				the extra setup for those pins used by GMAC.
+  * @hash_offset			Flow table hash offset.
++ * @version			SoC version.
+  * @foe_entry_size		Foe table entry size.
+  * @has_accounting		Bool indicating support for accounting of
+  *				offloaded flows.
+@@ -1027,6 +1026,7 @@ struct mtk_soc_data {
+ 	bool		required_pctl;
+ 	u8		offload_version;
+ 	u8		hash_offset;
++	u8		version;
+ 	u16		foe_entry_size;
+ 	netdev_features_t hw_features;
+ 	bool		has_accounting;
+@@ -1183,6 +1183,16 @@ struct mtk_mac {
+ /* the struct describing the SoC. these are declared in the soc_xyz.c files */
+ extern const struct of_device_id of_mtk_match[];
+ 
++static inline bool mtk_is_netsys_v1(struct mtk_eth *eth)
++{
++	return eth->soc->version == 1;
++}
++
++static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth)
++{
++	return eth->soc->version > 1;
++}
++
+ static inline struct mtk_foe_entry *
+ mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash)
+ {
+@@ -1193,7 +1203,7 @@ mtk_foe_get_entry(struct mtk_ppe *ppe, u
+ 
+ static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return MTK_FOE_IB1_BIND_TIMESTAMP_V2;
+ 
+ 	return MTK_FOE_IB1_BIND_TIMESTAMP;
+@@ -1201,7 +1211,7 @@ static inline u32 mtk_get_ib1_ts_mask(st
+ 
+ static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return MTK_FOE_IB1_BIND_PPPOE_V2;
+ 
+ 	return MTK_FOE_IB1_BIND_PPPOE;
+@@ -1209,7 +1219,7 @@ static inline u32 mtk_get_ib1_ppoe_mask(
+ 
+ static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return MTK_FOE_IB1_BIND_VLAN_TAG_V2;
+ 
+ 	return MTK_FOE_IB1_BIND_VLAN_TAG;
+@@ -1217,7 +1227,7 @@ static inline u32 mtk_get_ib1_vlan_tag_m
+ 
+ static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return MTK_FOE_IB1_BIND_VLAN_LAYER_V2;
+ 
+ 	return MTK_FOE_IB1_BIND_VLAN_LAYER;
+@@ -1225,7 +1235,7 @@ static inline u32 mtk_get_ib1_vlan_layer
+ 
+ static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);
+ 
+ 	return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
+@@ -1233,7 +1243,7 @@ static inline u32 mtk_prep_ib1_vlan_laye
+ 
+ static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);
+ 
+ 	return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
+@@ -1241,7 +1251,7 @@ static inline u32 mtk_get_ib1_vlan_layer
+ 
+ static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return MTK_FOE_IB1_PACKET_TYPE_V2;
+ 
+ 	return MTK_FOE_IB1_PACKET_TYPE;
+@@ -1249,7 +1259,7 @@ static inline u32 mtk_get_ib1_pkt_type_m
+ 
+ static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val);
+ 
+ 	return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val);
+@@ -1257,7 +1267,7 @@ static inline u32 mtk_get_ib1_pkt_type(s
+ 
+ static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth)
+ {
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		return MTK_FOE_IB2_MULTICAST_V2;
+ 
+ 	return MTK_FOE_IB2_MULTICAST;
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
+@@ -207,7 +207,7 @@ int mtk_foe_entry_prepare(struct mtk_eth
+ 
+ 	memset(entry, 0, sizeof(*entry));
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		val = FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_BIND) |
+ 		      FIELD_PREP(MTK_FOE_IB1_PACKET_TYPE_V2, type) |
+ 		      FIELD_PREP(MTK_FOE_IB1_UDP, l4proto == IPPROTO_UDP) |
+@@ -271,7 +271,7 @@ int mtk_foe_entry_set_pse_port(struct mt
+ 	u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
+ 	u32 val = *ib2;
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		val &= ~MTK_FOE_IB2_DEST_PORT_V2;
+ 		val |= FIELD_PREP(MTK_FOE_IB2_DEST_PORT_V2, port);
+ 	} else {
+@@ -422,7 +422,7 @@ int mtk_foe_entry_set_wdma(struct mtk_et
+ 	struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry);
+ 	u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		*ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
+ 		*ib2 |=  FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |
+ 			 MTK_FOE_IB2_WDMA_WINFO_V2;
+@@ -446,7 +446,7 @@ int mtk_foe_entry_set_queue(struct mtk_e
+ {
+ 	u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		*ib2 &= ~MTK_FOE_IB2_QID_V2;
+ 		*ib2 |= FIELD_PREP(MTK_FOE_IB2_QID_V2, queue);
+ 		*ib2 |= MTK_FOE_IB2_PSE_QOS_V2;
+@@ -601,7 +601,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
+ 	struct mtk_foe_entry *hwe;
+ 	u32 val;
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP_V2;
+ 		entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP_V2,
+ 					 timestamp);
+@@ -617,7 +617,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
+ 	hwe->ib1 = entry->ib1;
+ 
+ 	if (ppe->accounting) {
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++		if (mtk_is_netsys_v2_or_greater(eth))
+ 			val = MTK_FOE_IB2_MIB_CNT_V2;
+ 		else
+ 			val = MTK_FOE_IB2_MIB_CNT;
+@@ -965,7 +965,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
+ 			 MTK_PPE_SCAN_MODE_KEEPALIVE_AGE) |
+ 	      FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM,
+ 			 MTK_PPE_ENTRIES_SHIFT);
+-	if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(ppe->eth))
+ 		val |= MTK_PPE_TB_CFG_INFO_SEL;
+ 	ppe_w32(ppe, MTK_PPE_TB_CFG, val);
+ 
+@@ -981,7 +981,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
+ 	      MTK_PPE_FLOW_CFG_IP4_NAPT |
+ 	      MTK_PPE_FLOW_CFG_IP4_DSLITE |
+ 	      MTK_PPE_FLOW_CFG_IP4_NAT_FRAG;
+-	if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2))
++	if (mtk_is_netsys_v2_or_greater(ppe->eth))
+ 		val |= MTK_PPE_MD_TOAP_BYP_CRSN0 |
+ 		       MTK_PPE_MD_TOAP_BYP_CRSN1 |
+ 		       MTK_PPE_MD_TOAP_BYP_CRSN2 |
+@@ -1023,7 +1023,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
+ 
+ 	ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0);
+ 
+-	if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2)) {
++	if (mtk_is_netsys_v2_or_greater(ppe->eth)) {
+ 		ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777);
+ 		ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f);
+ 	}
+--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
+@@ -193,7 +193,7 @@ mtk_flow_set_output_device(struct mtk_et
+ 	if (mtk_flow_get_wdma_info(dev, dest_mac, &info) == 0) {
+ 		mtk_foe_entry_set_wdma(eth, foe, info.wdma_idx, info.queue,
+ 				       info.bss, info.wcid);
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++		if (mtk_is_netsys_v2_or_greater(eth)) {
+ 			switch (info.wdma_idx) {
+ 			case 0:
+ 				pse_port = 8;
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -1084,7 +1084,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+ 	} else {
+ 		struct mtk_eth *eth = dev->hw->eth;
+ 
+-		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
++		if (mtk_is_netsys_v2_or_greater(eth))
+ 			wed_set(dev, MTK_WED_RESET_IDX,
+ 				MTK_WED_RESET_IDX_RX_V2);
+ 		else
+@@ -1806,7 +1806,7 @@ void mtk_wed_add_hw(struct device_node *
+ 	hw->wdma = wdma;
+ 	hw->index = index;
+ 	hw->irq = irq;
+-	hw->version = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1;
++	hw->version = mtk_is_netsys_v1(eth) ? 1 : 2;
+ 
+ 	if (hw->version == 1) {
+ 		hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,

lede/target/linux/generic/backport-6.1/750-v6.5-06-net-ethernet-mtk_eth_soc-increase-MAX_DEVS-to-3.patch

@@ -0,0 +1,29 @@
+From f8fb8dbd158c585be7574faf92db7d614b6722ff Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 25 Jul 2023 01:52:27 +0100
+Subject: [PATCH 100/250] net: ethernet: mtk_eth_soc: increase MAX_DEVS to 3
+
+This is a preliminary patch to add MT7988 SoC support since it runs 3
+macs instead of 2.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/3563e5fab367e7d79a7f1296fabaa5c20f202d7a.1690246066.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -1043,8 +1043,8 @@ struct mtk_soc_data {
+ 
+ #define MTK_DMA_MONITOR_TIMEOUT		msecs_to_jiffies(1000)
+ 
+-/* currently no SoC has more than 2 macs */
+-#define MTK_MAX_DEVS			2
++/* currently no SoC has more than 3 macs */
++#define MTK_MAX_DEVS	3
+ 
+ /* struct mtk_eth -	This is the main datasructure for holding the state
+  *			of the driver

lede/target/linux/generic/backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch

@@ -1,143 +1,176 @@
-From 4e35e80750b33727e606be9e7ce447bde2e0deb7 Mon Sep 17 00:00:00 2001
+From 856be974290f28d7943be2ac5a382c4139486196 Mon Sep 17 00:00:00 2001
 From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Tue, 7 Mar 2023 15:55:35 +0000
-Subject: [PATCH 3/7] net: ethernet: mtk_eth_soc: rely on num_devs and remove
- MTK_MAC_COUNT
+Date: Tue, 25 Jul 2023 01:52:44 +0100
+Subject: [PATCH 101/250] net: ethernet: mtk_eth_soc: rely on MTK_MAX_DEVS and
+ remove MTK_MAC_COUNT
 
-Get rid of MTK_MAC_COUNT since it is a duplicated of eth->soc->num_devs.
+Get rid of MTK_MAC_COUNT since it is a duplicated of MTK_MAX_DEVS.
 
 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/1856f4266f2fc80677807b1bad867659e7b00c65.1690246066.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 ---
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 ++++++++++-----------
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 49 ++++++++++++---------
  drivers/net/ethernet/mediatek/mtk_eth_soc.h |  1 -
- 2 files changed, 15 insertions(+), 16 deletions(-)
+ 2 files changed, 27 insertions(+), 23 deletions(-)
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -943,7 +943,7 @@ static void mtk_stats_update(struct mtk_
+@@ -882,7 +882,7 @@ static void mtk_stats_update(struct mtk_
  {
  	int i;
  
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		if (!eth->mac[i] || !eth->mac[i]->hw_stats)
  			continue;
  		if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
-@@ -1448,7 +1448,7 @@ static int mtk_queue_stopped(struct mtk_
+@@ -1387,7 +1387,7 @@ static int mtk_queue_stopped(struct mtk_
  {
  	int i;
  
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		if (!eth->netdev[i])
  			continue;
  		if (netif_queue_stopped(eth->netdev[i]))
-@@ -1462,7 +1462,7 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1401,7 +1401,7 @@ static void mtk_wake_queue(struct mtk_et
  {
  	int i;
  
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		if (!eth->netdev[i])
  			continue;
  		netif_tx_wake_all_queues(eth->netdev[i]);
-@@ -1955,7 +1955,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1860,7 +1860,7 @@ static int mtk_poll_rx(struct napi_struc
  			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
  			mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
  
 -		if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
-+		if (unlikely(mac < 0 || mac >= eth->soc->num_devs ||
++		if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS ||
  			     !eth->netdev[mac]))
  			goto release_desc;
  
-@@ -2995,7 +2995,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -2897,7 +2897,7 @@ static void mtk_dma_free(struct mtk_eth
  	const struct mtk_soc_data *soc = eth->soc;
  	int i;
  
 -	for (i = 0; i < MTK_MAC_COUNT; i++)
-+	for (i = 0; i < soc->num_devs; i++)
++	for (i = 0; i < MTK_MAX_DEVS; i++)
  		if (eth->netdev[i])
  			netdev_reset_queue(eth->netdev[i]);
  	if (eth->scratch_ring) {
-@@ -3149,7 +3149,7 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3051,8 +3051,13 @@ static void mtk_gdm_config(struct mtk_et
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
  		return;
  
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
- 		u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
+-		u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
++		u32 val;
++
++		if (!eth->netdev[i])
++			continue;
++
++		val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
  
  		/* default setup the forward port to send frame to PDMA */
-@@ -3760,7 +3760,7 @@ static int mtk_hw_init(struct mtk_eth *e
+ 		val &= ~0xffff;
+@@ -3062,7 +3067,7 @@ static void mtk_gdm_config(struct mtk_et
+ 
+ 		val |= config;
+ 
+-		if (eth->netdev[i] && netdev_uses_dsa(eth->netdev[i]))
++		if (netdev_uses_dsa(eth->netdev[i]))
+ 			val |= MTK_GDMA_SPECIAL_TAG;
+ 
+ 		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
+@@ -3659,15 +3664,15 @@ static int mtk_hw_init(struct mtk_eth *e
  	 * up with the more appropriate value when mtk_mac_config call is being
  	 * invoked.
  	 */
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		struct net_device *dev = eth->netdev[i];
  
- 		mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
-@@ -3948,7 +3948,7 @@ static void mtk_pending_work(struct work
+-		mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
+-		if (dev) {
+-			struct mtk_mac *mac = netdev_priv(dev);
++		if (!dev)
++			continue;
+ 
+-			mtk_set_mcr_max_rx(mac, dev->mtu + MTK_RX_ETH_HLEN);
+-		}
++		mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
++		mtk_set_mcr_max_rx(netdev_priv(dev),
++				   dev->mtu + MTK_RX_ETH_HLEN);
+ 	}
+ 
+ 	/* Indicates CDM to parse the MTK special tag from CPU
+@@ -3847,7 +3852,7 @@ static void mtk_pending_work(struct work
  	mtk_prepare_for_reset(eth);
  
  	/* stop all devices to make sure that dma is properly shut down */
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		if (!eth->netdev[i] || !netif_running(eth->netdev[i]))
  			continue;
  
-@@ -3964,7 +3964,7 @@ static void mtk_pending_work(struct work
+@@ -3863,8 +3868,8 @@ static void mtk_pending_work(struct work
  	mtk_hw_init(eth, true);
  
  	/* restart DMA and enable IRQs */
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
- 		if (!test_bit(i, &restart))
+-		if (!test_bit(i, &restart))
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
++		if (!eth->netdev[i] || !test_bit(i, &restart))
  			continue;
  
-@@ -3992,7 +3992,7 @@ static int mtk_free_dev(struct mtk_eth *
+ 		if (mtk_open(eth->netdev[i])) {
+@@ -3891,7 +3896,7 @@ static int mtk_free_dev(struct mtk_eth *
  {
  	int i;
  
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		if (!eth->netdev[i])
  			continue;
  		free_netdev(eth->netdev[i]);
-@@ -4011,7 +4011,7 @@ static int mtk_unreg_dev(struct mtk_eth
+@@ -3910,7 +3915,7 @@ static int mtk_unreg_dev(struct mtk_eth
  {
  	int i;
  
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		struct mtk_mac *mac;
  		if (!eth->netdev[i])
  			continue;
-@@ -4315,7 +4315,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4211,7 +4216,7 @@ static int mtk_add_mac(struct mtk_eth *e
  	}
  
  	id = be32_to_cpup(_id);
 -	if (id >= MTK_MAC_COUNT) {
-+	if (id >= eth->soc->num_devs) {
++	if (id >= MTK_MAX_DEVS) {
  		dev_err(eth->dev, "%d is not a valid mac id\n", id);
  		return -EINVAL;
  	}
-@@ -4456,7 +4456,7 @@ void mtk_eth_set_dma_device(struct mtk_e
+@@ -4356,7 +4361,7 @@ void mtk_eth_set_dma_device(struct mtk_e
  
  	rtnl_lock();
  
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		dev = eth->netdev[i];
  
  		if (!dev || !(dev->flags & IFF_UP))
-@@ -4782,7 +4782,7 @@ static int mtk_remove(struct platform_de
+@@ -4662,7 +4667,7 @@ static int mtk_remove(struct platform_de
  	int i;
  
  	/* stop all devices to make sure that dma is properly shut down */
 -	for (i = 0; i < MTK_MAC_COUNT; i++) {
-+	for (i = 0; i < eth->soc->num_devs; i++) {
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
  		if (!eth->netdev[i])
  			continue;
  		mtk_stop(eth->netdev[i]);

lede/target/linux/generic/backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch

@@ -1,22 +1,24 @@
-From ab817f559d505329d8a413c7d29250f6d87d77a0 Mon Sep 17 00:00:00 2001
+From a41d535855976838d246c079143c948dcf0f7931 Mon Sep 17 00:00:00 2001
 From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Tue, 7 Mar 2023 15:55:47 +0000
-Subject: [PATCH 4/7] net: ethernet: mtk_eth_soc: add MTK_NETSYS_V3 capability
- bit
+Date: Tue, 25 Jul 2023 01:52:59 +0100
+Subject: [PATCH 102/250] net: ethernet: mtk_eth_soc: add NETSYS_V3 version
+ support
 
-Introduce MTK_NETSYS_V3 bit in the device capabilities.
+Introduce NETSYS_V3 chipset version support.
 This is a preliminary patch to introduce support for MT7988 SoC.
 
 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/0db2260910755d76fa48e303b9f9bdf4e5a82340.1690246066.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 ---
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 115 ++++++++++++++++----
- drivers/net/ethernet/mediatek/mtk_eth_soc.h |  44 +++++++-
- 2 files changed, 134 insertions(+), 25 deletions(-)
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 105 ++++++++++++++------
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h |  48 +++++++--
+ 2 files changed, 116 insertions(+), 37 deletions(-)
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -879,17 +879,32 @@ void mtk_stats_update_mac(struct mtk_mac
+@@ -862,17 +862,32 @@ void mtk_stats_update_mac(struct mtk_mac
  			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);
  		hw_stats->rx_flow_control_packets +=
  			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);
@@ -32,7 +34,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 -		hw_stats->tx_packets +=
 -			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs);
 +
-+		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
++		if (mtk_is_netsys_v3_or_greater(eth)) {
 +			hw_stats->tx_skip +=
 +				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs);
 +			hw_stats->tx_collisions +=
@@ -60,7 +62,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	}
  
  	u64_stats_update_end(&hw_stats->syncp);
-@@ -1191,7 +1206,10 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1176,7 +1191,10 @@ static void mtk_tx_set_dma_desc_v2(struc
  		data |= TX_DMA_LS0;
  	WRITE_ONCE(desc->txd3, data);
  
@@ -72,57 +74,53 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
  	WRITE_ONCE(desc->txd4, data);
  
-@@ -1202,6 +1220,9 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1187,6 +1205,8 @@ static void mtk_tx_set_dma_desc_v2(struc
  		/* tx checksum offload */
  		if (info->csum)
  			data |= TX_DMA_CHKSUM_V2;
-+		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) &&
-+		    netdev_uses_dsa(dev))
++		if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev))
 +			data |= TX_DMA_SPTAG_V3;
  	}
  	WRITE_ONCE(desc->txd5, data);
  
-@@ -1267,8 +1288,13 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1252,8 +1272,7 @@ static int mtk_tx_map(struct sk_buff *sk
  	mtk_tx_set_dma_desc(dev, itxd, &txd_info);
  
  	itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
 -	itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
 -			  MTK_TX_FLAGS_FPORT1;
-+	if (mac->id == MTK_GMAC1_ID)
-+		itx_buf->flags |= MTK_TX_FLAGS_FPORT0;
-+	else if (mac->id == MTK_GMAC2_ID)
-+		itx_buf->flags |= MTK_TX_FLAGS_FPORT1;
-+	else
-+		itx_buf->flags |= MTK_TX_FLAGS_FPORT2;
-+
++	itx_buf->mac_id = mac->id;
  	setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size,
  		     k++);
  
-@@ -1316,8 +1342,13 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1301,8 +1320,7 @@ static int mtk_tx_map(struct sk_buff *sk
  				memset(tx_buf, 0, sizeof(*tx_buf));
  			tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
  			tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
 -			tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
 -					 MTK_TX_FLAGS_FPORT1;
-+
-+			if (mac->id == MTK_GMAC1_ID)
-+				tx_buf->flags |= MTK_TX_FLAGS_FPORT0;
-+			else if (mac->id == MTK_GMAC2_ID)
-+				tx_buf->flags |= MTK_TX_FLAGS_FPORT1;
-+			else
-+				tx_buf->flags |= MTK_TX_FLAGS_FPORT2;
++			tx_buf->mac_id = mac->id;
  
  			setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr,
  				     txd_info.size, k++);
-@@ -1901,11 +1932,24 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1604,7 +1622,7 @@ static int mtk_xdp_frame_map(struct mtk_
+ 	}
+ 	mtk_tx_set_dma_desc(dev, txd, txd_info);
+ 
+-	tx_buf->flags |= !mac->id ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1;
++	tx_buf->mac_id = mac->id;
+ 	tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX;
+ 	tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
+ 
+@@ -1854,11 +1872,24 @@ static int mtk_poll_rx(struct napi_struc
  			break;
  
  		/* find out which mac the packet come from. values start at 1 */
--		if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
+-		if (mtk_is_netsys_v2_or_greater(eth))
 -			mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
 -		else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
 -			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
-+		if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
++		if (mtk_is_netsys_v2_or_greater(eth)) {
 +			u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
 +
 +			switch (val) {
@@ -137,29 +135,44 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +				break;
 +			}
 +		} else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
-+			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) {
++			   !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) {
  			mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
 +		}
  
- 		if (unlikely(mac < 0 || mac >= eth->soc->num_devs ||
+ 		if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS ||
  			     !eth->netdev[mac]))
-@@ -2134,7 +2178,9 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2080,7 +2111,6 @@ static int mtk_poll_tx_qdma(struct mtk_e
+ 
+ 	while ((cpu != dma) && budget) {
+ 		u32 next_cpu = desc->txd2;
+-		int mac = 0;
+ 
+ 		desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
+ 		if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
+@@ -2088,15 +2118,13 @@ static int mtk_poll_tx_qdma(struct mtk_e
+ 
  		tx_buf = mtk_desc_to_tx_buf(ring, desc,
  					    eth->soc->txrx.txd_size);
- 		if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
+-		if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
 -			mac = 1;
-+			mac = MTK_GMAC2_ID;
-+		else if (tx_buf->flags & MTK_TX_FLAGS_FPORT2)
-+			mac = MTK_GMAC3_ID;
- 
+-
  		if (!tx_buf->data)
  			break;
-@@ -3744,7 +3790,26 @@ static int mtk_hw_init(struct mtk_eth *e
+ 
+ 		if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
+ 			if (tx_buf->type == MTK_TYPE_SKB)
+-				mtk_poll_tx_done(eth, state, mac, tx_buf->data);
++				mtk_poll_tx_done(eth, state, tx_buf->mac_id,
++						 tx_buf->data);
+ 
+ 			budget--;
+ 		}
+@@ -3702,7 +3730,24 @@ static int mtk_hw_init(struct mtk_eth *e
  	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
  	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
  
--	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
-+	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
+-	if (mtk_is_netsys_v2_or_greater(eth)) {
++	if (mtk_is_netsys_v3_or_greater(eth)) {
 +		/* PSE should not drop port1, port8 and port9 packets */
 +		mtk_w32(eth, 0x00000302, PSE_DROP_CFG);
 +
@@ -168,9 +181,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +		mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
 +
 +		/* Disable GDM1 RX CRC stripping */
-+		val = mtk_r32(eth, MTK_GDMA_FWD_CFG(0));
-+		val &= ~MTK_GDMA_STRP_CRC;
-+		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(0));
++		mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0));
 +
 +		/* PSE GDM3 MIB counter has incorrect hw default values,
 +		 * so the driver ought to read clear the values beforehand
@@ -178,17 +189,17 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +		 */
 +		for (i = 0; i < 0x80; i += 0x4)
 +			mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i);
-+	} else if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
++	} else if (!mtk_is_netsys_v1(eth)) {
  		/* PSE should not drop port8 and port9 packets from WDMA Tx */
  		mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
  
-@@ -4309,7 +4374,11 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4264,7 +4309,11 @@ static int mtk_add_mac(struct mtk_eth *e
  	}
  	spin_lock_init(&mac->hw_stats->stats_lock);
  	u64_stats_init(&mac->hw_stats->syncp);
 -	mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
 +
-+	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3))
++	if (mtk_is_netsys_v3_or_greater(eth))
 +		mac->hw_stats->reg_offset = id * 0x80;
 +	else
 +		mac->hw_stats->reg_offset = id * 0x40;
@@ -197,7 +208,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	err = of_get_phy_mode(np, &phy_mode);
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -121,6 +121,7 @@
+@@ -122,6 +122,7 @@
  #define MTK_GDMA_ICS_EN		BIT(22)
  #define MTK_GDMA_TCS_EN		BIT(21)
  #define MTK_GDMA_UCS_EN		BIT(20)
@@ -205,7 +216,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  #define MTK_GDMA_TO_PDMA	0x0
  #define MTK_GDMA_DROP_ALL       0x7777
  
-@@ -286,8 +287,6 @@
+@@ -287,8 +288,6 @@
  /* QDMA Interrupt grouping registers */
  #define MTK_RLS_DONE_INT	BIT(0)
  
@@ -214,7 +225,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  /* QDMA TX NUM */
  #define QID_BITS_V2(x)		(((x) & 0x3f) << 16)
  #define MTK_QDMA_GMAC2_QID	8
-@@ -300,6 +299,8 @@
+@@ -301,6 +300,8 @@
  #define TX_DMA_CHKSUM_V2	(0x7 << 28)
  #define TX_DMA_TSO_V2		BIT(31)
  
@@ -223,15 +234,20 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  /* QDMA V2 descriptor txd4 */
  #define TX_DMA_FPORT_SHIFT_V2	8
  #define TX_DMA_FPORT_MASK_V2	0xf
-@@ -636,6 +637,7 @@ enum mtk_tx_flags {
+@@ -634,12 +635,6 @@ enum mtk_tx_flags {
  	 */
- 	MTK_TX_FLAGS_FPORT0	= 0x04,
- 	MTK_TX_FLAGS_FPORT1	= 0x08,
-+	MTK_TX_FLAGS_FPORT2	= 0x10,
+ 	MTK_TX_FLAGS_SINGLE0	= 0x01,
+ 	MTK_TX_FLAGS_PAGE0	= 0x02,
+-
+-	/* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted
+-	 * SKB out instead of looking up through hardware TX descriptor.
+-	 */
+-	MTK_TX_FLAGS_FPORT0	= 0x04,
+-	MTK_TX_FLAGS_FPORT1	= 0x08,
  };
  
  /* This enum allows us to identify how the clock is defined on the array of the
-@@ -721,6 +723,42 @@ enum mtk_dev_state {
+@@ -725,6 +720,35 @@ enum mtk_dev_state {
  	MTK_RESETTING
  };
  
@@ -263,30 +279,29 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	MTK_GMAC3_ID,
 +	MTK_GMAC_ID_MAX
 +};
-+
-+/* GDM Type */
-+enum mtk_gdm_type {
-+	MTK_GDM_TYPE = 0,
-+	MTK_XGDM_TYPE,
-+	MTK_GDM_TYPE_MAX
-+};
 +
  enum mtk_tx_buf_type {
  	MTK_TYPE_SKB,
  	MTK_TYPE_XDP_TX,
-@@ -817,6 +855,7 @@ enum mkt_eth_capabilities {
- 	MTK_QDMA_BIT,
- 	MTK_NETSYS_V1_BIT,
- 	MTK_NETSYS_V2_BIT,
-+	MTK_NETSYS_V3_BIT,
- 	MTK_SOC_MT7628_BIT,
- 	MTK_RSTCTRL_PPE1_BIT,
- 	MTK_U3_COPHY_V2_BIT,
-@@ -853,6 +892,7 @@ enum mkt_eth_capabilities {
- #define MTK_QDMA		BIT(MTK_QDMA_BIT)
- #define MTK_NETSYS_V1		BIT(MTK_NETSYS_V1_BIT)
- #define MTK_NETSYS_V2		BIT(MTK_NETSYS_V2_BIT)
-+#define MTK_NETSYS_V3		BIT(MTK_NETSYS_V3_BIT)
- #define MTK_SOC_MT7628		BIT(MTK_SOC_MT7628_BIT)
- #define MTK_RSTCTRL_PPE1	BIT(MTK_RSTCTRL_PPE1_BIT)
- #define MTK_U3_COPHY_V2		BIT(MTK_U3_COPHY_V2_BIT)
+@@ -743,7 +767,8 @@ struct mtk_tx_buf {
+ 	enum mtk_tx_buf_type type;
+ 	void *data;
+ 
+-	u32 flags;
++	u16 mac_id;
++	u16 flags;
+ 	DEFINE_DMA_UNMAP_ADDR(dma_addr0);
+ 	DEFINE_DMA_UNMAP_LEN(dma_len0);
+ 	DEFINE_DMA_UNMAP_ADDR(dma_addr1);
+@@ -1192,6 +1217,11 @@ static inline bool mtk_is_netsys_v2_or_g
+ 	return eth->soc->version > 1;
+ }
+ 
++static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth)
++{
++	return eth->soc->version > 2;
++}
++
+ static inline struct mtk_foe_entry *
+ mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash)
+ {

lede/target/linux/generic/backport-6.1/750-v6.5-09-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch

@@ -1,17 +1,19 @@
-From 45b575fd9e6a455090820248bf1b98b1f2c7b6c8 Mon Sep 17 00:00:00 2001
+From db797ae0542220a98658229397da464c383c991c Mon Sep 17 00:00:00 2001
 From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Tue, 7 Mar 2023 15:56:00 +0000
-Subject: [PATCH 5/7] net: ethernet: mtk_eth_soc: convert caps in mtk_soc_data
- struct to u64
+Date: Tue, 25 Jul 2023 01:53:13 +0100
+Subject: [PATCH 103/250] net: ethernet: mtk_eth_soc: convert caps in
+ mtk_soc_data struct to u64
 
 This is a preliminary patch to introduce support for MT7988 SoC.
 
 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/9499ac3670b2fc5b444404b84e8a4a169beabbf2.1690246066.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 ---
- drivers/net/ethernet/mediatek/mtk_eth_path.c | 22 +++----
- drivers/net/ethernet/mediatek/mtk_eth_soc.h  | 62 ++++++++++----------
- 2 files changed, 42 insertions(+), 42 deletions(-)
+ drivers/net/ethernet/mediatek/mtk_eth_path.c | 22 ++++----
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h  | 56 ++++++++++----------
+ 2 files changed, 39 insertions(+), 39 deletions(-)
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
@@ -111,7 +113,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  				MTK_ETH_PATH_GMAC2_RGMII;
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -881,44 +881,44 @@ enum mkt_eth_capabilities {
+@@ -866,41 +866,41 @@ enum mkt_eth_capabilities {
  };
  
  /* Supported hardware group on SoCs */
@@ -127,9 +129,6 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 -#define MTK_SHARED_INT		BIT(MTK_SHARED_INT_BIT)
 -#define MTK_TRGMII_MT7621_CLK	BIT(MTK_TRGMII_MT7621_CLK_BIT)
 -#define MTK_QDMA		BIT(MTK_QDMA_BIT)
--#define MTK_NETSYS_V1		BIT(MTK_NETSYS_V1_BIT)
--#define MTK_NETSYS_V2		BIT(MTK_NETSYS_V2_BIT)
--#define MTK_NETSYS_V3		BIT(MTK_NETSYS_V3_BIT)
 -#define MTK_SOC_MT7628		BIT(MTK_SOC_MT7628_BIT)
 -#define MTK_RSTCTRL_PPE1	BIT(MTK_RSTCTRL_PPE1_BIT)
 -#define MTK_U3_COPHY_V2		BIT(MTK_U3_COPHY_V2_BIT)
@@ -145,9 +144,6 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +#define MTK_SHARED_INT		BIT_ULL(MTK_SHARED_INT_BIT)
 +#define MTK_TRGMII_MT7621_CLK	BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT)
 +#define MTK_QDMA		BIT_ULL(MTK_QDMA_BIT)
-+#define MTK_NETSYS_V1		BIT_ULL(MTK_NETSYS_V1_BIT)
-+#define MTK_NETSYS_V2		BIT_ULL(MTK_NETSYS_V2_BIT)
-+#define MTK_NETSYS_V3		BIT_ULL(MTK_NETSYS_V3_BIT)
 +#define MTK_SOC_MT7628		BIT_ULL(MTK_SOC_MT7628_BIT)
 +#define MTK_RSTCTRL_PPE1	BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
 +#define MTK_U3_COPHY_V2		BIT_ULL(MTK_U3_COPHY_V2_BIT)
@@ -186,7 +182,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  #define MTK_GMAC1_RGMII		(MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
  #define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
-@@ -1074,7 +1074,7 @@ struct mtk_reg_map {
+@@ -1045,7 +1045,7 @@ struct mtk_reg_map {
  struct mtk_soc_data {
  	const struct mtk_reg_map *reg_map;
  	u32             ana_rgc3;

lede/target/linux/generic/backport-6.1/750-v6.5-10-net-ethernet-mtk_eth_soc-convert-clock-bitmap-to-u64.patch

@@ -0,0 +1,132 @@
+From a1c9f7d1d24e90294f6a6755b137fcf306851e93 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 25 Jul 2023 01:53:28 +0100
+Subject: [PATCH 104/250] net: ethernet: mtk_eth_soc: convert clock bitmap to
+ u64
+
+The to-be-added MT7988 SoC adds many new clocks which need to be
+controlled by the Ethernet driver, which will result in their total
+number exceeding 32.
+Prepare by converting clock bitmaps into 64-bit types.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/6960a39bb0078cf84d7642a9558e6a91c6cc9df3.1690246066.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 96 +++++++++++----------
+ 1 file changed, 49 insertions(+), 47 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -666,54 +666,56 @@ enum mtk_clks_map {
+ 	MTK_CLK_MAX
+ };
+ 
+-#define MT7623_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \
+-				 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
+-				 BIT(MTK_CLK_TRGPLL))
+-#define MT7622_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \
+-				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
+-				 BIT(MTK_CLK_GP2) | \
+-				 BIT(MTK_CLK_SGMII_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII_CK) | \
+-				 BIT(MTK_CLK_ETH2PLL))
++#define MT7623_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \
++				 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
++				 BIT_ULL(MTK_CLK_TRGPLL))
++#define MT7622_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \
++				 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
++				 BIT_ULL(MTK_CLK_GP2) | \
++				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII_CK) | \
++				 BIT_ULL(MTK_CLK_ETH2PLL))
+ #define MT7621_CLKS_BITMAP	(0)
+ #define MT7628_CLKS_BITMAP	(0)
+-#define MT7629_CLKS_BITMAP	(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) |  \
+-				 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
+-				 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
+-				 BIT(MTK_CLK_SGMII_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII2_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII_CK) | \
+-				 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
+-#define MT7981_CLKS_BITMAP	(BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
+-				 BIT(MTK_CLK_WOCPU0) | \
+-				 BIT(MTK_CLK_SGMII_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII2_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII_CK))
+-#define MT7986_CLKS_BITMAP	(BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
+-				 BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
+-				 BIT(MTK_CLK_SGMII_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII_CDR_FB) | \
+-				 BIT(MTK_CLK_SGMII2_TX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_RX_250M) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_REF) | \
+-				 BIT(MTK_CLK_SGMII2_CDR_FB))
++#define MT7629_CLKS_BITMAP	(BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) |  \
++				 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
++				 BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \
++				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII_CK) | \
++				 BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP))
++#define MT7981_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
++				 BIT_ULL(MTK_CLK_GP1) | \
++				 BIT_ULL(MTK_CLK_WOCPU0) | \
++				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII_CK))
++#define MT7986_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
++				 BIT_ULL(MTK_CLK_GP1) | \
++				 BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \
++				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
++				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
++				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
+ 
+ enum mtk_dev_state {
+ 	MTK_HW_INIT,
+@@ -1046,7 +1048,7 @@ struct mtk_soc_data {
+ 	const struct mtk_reg_map *reg_map;
+ 	u32             ana_rgc3;
+ 	u64		caps;
+-	u32		required_clks;
++	u64		required_clks;
+ 	bool		required_pctl;
+ 	u8		offload_version;
+ 	u8		hash_offset;

lede/target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch

@@ -0,0 +1,477 @@
+From 94f825a7eadfc8b4c8828efdb7705d9703f9c73e Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 25 Jul 2023 01:57:42 +0100
+Subject: [PATCH 105/250] net: ethernet: mtk_eth_soc: add basic support for
+ MT7988 SoC
+
+Introduce support for ethernet chip available in MT7988 SoC to
+mtk_eth_soc driver. As a first step support only the first GMAC which
+is hard-wired to the internal DSA switch having 4 built-in gigabit
+Ethernet PHYs.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/25c8377095b95d186872eeda7aa055da83e8f0ca.1690246605.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_path.c |  14 +-
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c  | 201 +++++++++++++++++--
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h  |  86 +++++++-
+ 3 files changed, 273 insertions(+), 28 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
+@@ -43,7 +43,7 @@ static const char *mtk_eth_path_name(u64
+ static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path)
+ {
+ 	bool updated = true;
+-	u32 val, mask, set;
++	u32 mask, set, reg;
+ 
+ 	switch (path) {
+ 	case MTK_ETH_PATH_GMAC1_SGMII:
+@@ -59,11 +59,13 @@ static int set_mux_gdm1_to_gmac1_esw(str
+ 		break;
+ 	}
+ 
+-	if (updated) {
+-		val = mtk_r32(eth, MTK_MAC_MISC);
+-		val = (val & mask) | set;
+-		mtk_w32(eth, val, MTK_MAC_MISC);
+-	}
++	if (mtk_is_netsys_v3_or_greater(eth))
++		reg = MTK_MAC_MISC_V3;
++	else
++		reg = MTK_MAC_MISC;
++
++	if (updated)
++		mtk_m32(eth, mask, set, reg);
+ 
+ 	dev_dbg(eth->dev, "path %s in %s updated = %d\n",
+ 		mtk_eth_path_name(path), __func__, updated);
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -152,6 +152,54 @@ static const struct mtk_reg_map mt7986_r
+ 	.pse_oq_sta		= 0x01a0,
+ };
+ 
++static const struct mtk_reg_map mt7988_reg_map = {
++	.tx_irq_mask		= 0x461c,
++	.tx_irq_status		= 0x4618,
++	.pdma = {
++		.rx_ptr		= 0x6900,
++		.rx_cnt_cfg	= 0x6904,
++		.pcrx_ptr	= 0x6908,
++		.glo_cfg	= 0x6a04,
++		.rst_idx	= 0x6a08,
++		.delay_irq	= 0x6a0c,
++		.irq_status	= 0x6a20,
++		.irq_mask	= 0x6a28,
++		.adma_rx_dbg0	= 0x6a38,
++		.int_grp	= 0x6a50,
++	},
++	.qdma = {
++		.qtx_cfg	= 0x4400,
++		.qtx_sch	= 0x4404,
++		.rx_ptr		= 0x4500,
++		.rx_cnt_cfg	= 0x4504,
++		.qcrx_ptr	= 0x4508,
++		.glo_cfg	= 0x4604,
++		.rst_idx	= 0x4608,
++		.delay_irq	= 0x460c,
++		.fc_th		= 0x4610,
++		.int_grp	= 0x4620,
++		.hred		= 0x4644,
++		.ctx_ptr	= 0x4700,
++		.dtx_ptr	= 0x4704,
++		.crx_ptr	= 0x4710,
++		.drx_ptr	= 0x4714,
++		.fq_head	= 0x4720,
++		.fq_tail	= 0x4724,
++		.fq_count	= 0x4728,
++		.fq_blen	= 0x472c,
++		.tx_sch_rate	= 0x4798,
++	},
++	.gdm1_cnt		= 0x1c00,
++	.gdma_to_ppe		= 0x3333,
++	.ppe_base		= 0x2000,
++	.wdma_base = {
++		[0]		= 0x4800,
++		[1]		= 0x4c00,
++	},
++	.pse_iq_sta		= 0x0180,
++	.pse_oq_sta		= 0x01a0,
++};
++
+ /* strings used by ethtool */
+ static const struct mtk_ethtool_stats {
+ 	char str[ETH_GSTRING_LEN];
+@@ -179,10 +227,54 @@ static const struct mtk_ethtool_stats {
+ };
+ 
+ static const char * const mtk_clks_source_name[] = {
+-	"ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
+-	"sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
+-	"sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
+-	"sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1"
++	"ethif",
++	"sgmiitop",
++	"esw",
++	"gp0",
++	"gp1",
++	"gp2",
++	"gp3",
++	"xgp1",
++	"xgp2",
++	"xgp3",
++	"crypto",
++	"fe",
++	"trgpll",
++	"sgmii_tx250m",
++	"sgmii_rx250m",
++	"sgmii_cdr_ref",
++	"sgmii_cdr_fb",
++	"sgmii2_tx250m",
++	"sgmii2_rx250m",
++	"sgmii2_cdr_ref",
++	"sgmii2_cdr_fb",
++	"sgmii_ck",
++	"eth2pll",
++	"wocpu0",
++	"wocpu1",
++	"netsys0",
++	"netsys1",
++	"ethwarp_wocpu2",
++	"ethwarp_wocpu1",
++	"ethwarp_wocpu0",
++	"top_usxgmii0_sel",
++	"top_usxgmii1_sel",
++	"top_sgm0_sel",
++	"top_sgm1_sel",
++	"top_xfi_phy0_xtal_sel",
++	"top_xfi_phy1_xtal_sel",
++	"top_eth_gmii_sel",
++	"top_eth_refck_50m_sel",
++	"top_eth_sys_200m_sel",
++	"top_eth_sys_sel",
++	"top_eth_xgmii_sel",
++	"top_eth_mii_sel",
++	"top_netsys_sel",
++	"top_netsys_500m_sel",
++	"top_netsys_pao_2x_sel",
++	"top_netsys_sync_250m_sel",
++	"top_netsys_ppefb_250m_sel",
++	"top_netsys_warp_sel",
+ };
+ 
+ void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
+@@ -195,7 +287,7 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
+ 	return __raw_readl(eth->base + reg);
+ }
+ 
+-static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg)
++u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg)
+ {
+ 	u32 val;
+ 
+@@ -369,6 +461,19 @@ static void mtk_gmac0_rgmii_adjust(struc
+ 	dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n");
+ }
+ 
++static void mtk_setup_bridge_switch(struct mtk_eth *eth)
++{
++	/* Force Port1 XGMAC Link Up */
++	mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID),
++		MTK_XGMAC_STS(MTK_GMAC1_ID));
++
++	/* Adjust GSW bridge IPG to 11 */
++	mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK,
++		(GSW_IPG_11 << GSWTX_IPG_SHIFT) |
++		(GSW_IPG_11 << GSWRX_IPG_SHIFT),
++		MTK_GSW_CFG);
++}
++
+ static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
+ 					      phy_interface_t interface)
+ {
+@@ -438,6 +543,8 @@ static void mtk_mac_config(struct phylin
+ 					goto init_err;
+ 			}
+ 			break;
++		case PHY_INTERFACE_MODE_INTERNAL:
++			break;
+ 		default:
+ 			goto err_phy;
+ 		}
+@@ -515,6 +622,15 @@ static void mtk_mac_config(struct phylin
+ 		return;
+ 	}
+ 
++	/* Setup gmac */
++	if (mtk_is_netsys_v3_or_greater(eth) &&
++	    mac->interface == PHY_INTERFACE_MODE_INTERNAL) {
++		mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
++		mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
++
++		mtk_setup_bridge_switch(eth);
++	}
++
+ 	return;
+ 
+ err_phy:
+@@ -726,11 +842,15 @@ static int mtk_mdio_init(struct mtk_eth
+ 	}
+ 	divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
+ 
++	/* Configure MDC Turbo Mode */
++	if (mtk_is_netsys_v3_or_greater(eth))
++		mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3);
++
+ 	/* Configure MDC Divider */
+-	val = mtk_r32(eth, MTK_PPSC);
+-	val &= ~PPSC_MDC_CFG;
+-	val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO;
+-	mtk_w32(eth, val, MTK_PPSC);
++	val = FIELD_PREP(PPSC_MDC_CFG, divider);
++	if (!mtk_is_netsys_v3_or_greater(eth))
++		val |= PPSC_MDC_TURBO;
++	mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC);
+ 
+ 	dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
+ 
+@@ -1191,10 +1311,19 @@ static void mtk_tx_set_dma_desc_v2(struc
+ 		data |= TX_DMA_LS0;
+ 	WRITE_ONCE(desc->txd3, data);
+ 
+-	if (mac->id == MTK_GMAC3_ID)
+-		data = PSE_GDM3_PORT;
+-	else
+-		data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
++	 /* set forward port */
++	switch (mac->id) {
++	case MTK_GMAC1_ID:
++		data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2;
++		break;
++	case MTK_GMAC2_ID:
++		data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2;
++		break;
++	case MTK_GMAC3_ID:
++		data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2;
++		break;
++	}
++
+ 	data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
+ 	WRITE_ONCE(desc->txd4, data);
+ 
+@@ -4358,6 +4487,17 @@ static int mtk_add_mac(struct mtk_eth *e
+ 			  mac->phylink_config.supported_interfaces);
+ 	}
+ 
++	if (mtk_is_netsys_v3_or_greater(mac->hw) &&
++	    MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) &&
++	    id == MTK_GMAC1_ID) {
++		mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
++						       MAC_SYM_PAUSE |
++						       MAC_10000FD;
++		phy_interface_zero(mac->phylink_config.supported_interfaces);
++		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
++			  mac->phylink_config.supported_interfaces);
++	}
++
+ 	phylink = phylink_create(&mac->phylink_config,
+ 				 of_fwnode_handle(mac->of_node),
+ 				 phy_mode, &mtk_phylink_ops);
+@@ -4878,6 +5018,24 @@ static const struct mtk_soc_data mt7986_
+ 	},
+ };
+ 
++static const struct mtk_soc_data mt7988_data = {
++	.reg_map = &mt7988_reg_map,
++	.ana_rgc3 = 0x128,
++	.caps = MT7988_CAPS,
++	.hw_features = MTK_HW_FEATURES,
++	.required_clks = MT7988_CLKS_BITMAP,
++	.required_pctl = false,
++	.version = 3,
++	.txrx = {
++		.txd_size = sizeof(struct mtk_tx_dma_v2),
++		.rxd_size = sizeof(struct mtk_rx_dma_v2),
++		.rx_irq_done_mask = MTK_RX_DONE_INT_V2,
++		.rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
++		.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
++		.dma_len_offset = 8,
++	},
++};
++
+ static const struct mtk_soc_data rt5350_data = {
+ 	.reg_map = &mt7628_reg_map,
+ 	.caps = MT7628_CAPS,
+@@ -4896,14 +5054,15 @@ static const struct mtk_soc_data rt5350_
+ };
+ 
+ const struct of_device_id of_mtk_match[] = {
+-	{ .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
+-	{ .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
+-	{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
+-	{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
+-	{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
+-	{ .compatible = "mediatek,mt7981-eth", .data = &mt7981_data},
+-	{ .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
+-	{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
++	{ .compatible = "mediatek,mt2701-eth", .data = &mt2701_data },
++	{ .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
++	{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data },
++	{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data },
++	{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
++	{ .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
++	{ .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },
++	{ .compatible = "mediatek,mt7988-eth", .data = &mt7988_data },
++	{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, of_mtk_match);
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -117,7 +117,8 @@
+ #define MTK_CDMP_EG_CTRL	0x404
+ 
+ /* GDM Exgress Control Register */
+-#define MTK_GDMA_FWD_CFG(x)	(0x500 + (x * 0x1000))
++#define MTK_GDMA_FWD_CFG(x)	({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ?	\
++				   0x540 : 0x500 + (_x * 0x1000); })
+ #define MTK_GDMA_SPECIAL_TAG	BIT(24)
+ #define MTK_GDMA_ICS_EN		BIT(22)
+ #define MTK_GDMA_TCS_EN		BIT(21)
+@@ -126,6 +127,11 @@
+ #define MTK_GDMA_TO_PDMA	0x0
+ #define MTK_GDMA_DROP_ALL       0x7777
+ 
++/* GDM Egress Control Register */
++#define MTK_GDMA_EG_CTRL(x)	({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ?	\
++				   0x544 : 0x504 + (_x * 0x1000); })
++#define MTK_GDMA_XGDM_SEL	BIT(31)
++
+ /* Unicast Filter MAC Address Register - Low */
+ #define MTK_GDMA_MAC_ADRL(x)	(0x508 + (x * 0x1000))
+ 
+@@ -389,7 +395,26 @@
+ #define PHY_IAC_TIMEOUT		HZ
+ 
+ #define MTK_MAC_MISC		0x1000c
++#define MTK_MAC_MISC_V3		0x10010
+ #define MTK_MUX_TO_ESW		BIT(0)
++#define MISC_MDC_TURBO		BIT(4)
++
++/* XMAC status registers */
++#define MTK_XGMAC_STS(x)	(((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C)
++#define MTK_XGMAC_FORCE_LINK(x)	(((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15))
++#define MTK_USXGMII_PCS_LINK	BIT(8)
++#define MTK_XGMAC_RX_FC		BIT(5)
++#define MTK_XGMAC_TX_FC		BIT(4)
++#define MTK_USXGMII_PCS_MODE	GENMASK(3, 1)
++#define MTK_XGMAC_LINK_STS	BIT(0)
++
++/* GSW bridge registers */
++#define MTK_GSW_CFG		(0x10080)
++#define GSWTX_IPG_MASK		GENMASK(19, 16)
++#define GSWTX_IPG_SHIFT		16
++#define GSWRX_IPG_MASK		GENMASK(3, 0)
++#define GSWRX_IPG_SHIFT		0
++#define GSW_IPG_11		11
+ 
+ /* Mac control registers */
+ #define MTK_MAC_MCR(x)		(0x10100 + (x * 0x100))
+@@ -647,6 +672,11 @@ enum mtk_clks_map {
+ 	MTK_CLK_GP0,
+ 	MTK_CLK_GP1,
+ 	MTK_CLK_GP2,
++	MTK_CLK_GP3,
++	MTK_CLK_XGP1,
++	MTK_CLK_XGP2,
++	MTK_CLK_XGP3,
++	MTK_CLK_CRYPTO,
+ 	MTK_CLK_FE,
+ 	MTK_CLK_TRGPLL,
+ 	MTK_CLK_SGMII_TX_250M,
+@@ -663,6 +693,27 @@ enum mtk_clks_map {
+ 	MTK_CLK_WOCPU1,
+ 	MTK_CLK_NETSYS0,
+ 	MTK_CLK_NETSYS1,
++	MTK_CLK_ETHWARP_WOCPU2,
++	MTK_CLK_ETHWARP_WOCPU1,
++	MTK_CLK_ETHWARP_WOCPU0,
++	MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
++	MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
++	MTK_CLK_TOP_SGM_0_SEL,
++	MTK_CLK_TOP_SGM_1_SEL,
++	MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
++	MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
++	MTK_CLK_TOP_ETH_GMII_SEL,
++	MTK_CLK_TOP_ETH_REFCK_50M_SEL,
++	MTK_CLK_TOP_ETH_SYS_200M_SEL,
++	MTK_CLK_TOP_ETH_SYS_SEL,
++	MTK_CLK_TOP_ETH_XGMII_SEL,
++	MTK_CLK_TOP_ETH_MII_SEL,
++	MTK_CLK_TOP_NETSYS_SEL,
++	MTK_CLK_TOP_NETSYS_500M_SEL,
++	MTK_CLK_TOP_NETSYS_PAO_2X_SEL,
++	MTK_CLK_TOP_NETSYS_SYNC_250M_SEL,
++	MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL,
++	MTK_CLK_TOP_NETSYS_WARP_SEL,
+ 	MTK_CLK_MAX
+ };
+ 
+@@ -716,6 +767,36 @@ enum mtk_clks_map {
+ 				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
+ 				 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
+ 				 BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
++#define MT7988_CLKS_BITMAP	(BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \
++				 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
++				 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
++				 BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
++				 BIT_ULL(MTK_CLK_CRYPTO) | \
++				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
++				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
++				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
++				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
++				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
++				 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \
++				 BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL))
+ 
+ enum mtk_dev_state {
+ 	MTK_HW_INIT,
+@@ -964,6 +1045,8 @@ enum mkt_eth_capabilities {
+ 		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
+ 		      MTK_RSTCTRL_PPE1)
+ 
++#define MT7988_CAPS  (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1)
++
+ struct mtk_tx_dma_desc_info {
+ 	dma_addr_t	addr;
+ 	u32		size;
+@@ -1309,6 +1392,7 @@ void mtk_stats_update_mac(struct mtk_mac
+ 
+ void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
+ u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
++u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
+ 
+ int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
+ int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);

lede/target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch

@@ -0,0 +1,27 @@
+From 38a7eb76220731eff40602cf433f24880be0a6c2 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Thu, 27 Jul 2023 09:02:26 +0200
+Subject: [PATCH 106/250] net: ethernet: mtk_eth_soc: enable page_pool support
+ for MT7988 SoC
+
+In order to recycle pages, enable page_pool allocator for MT7988 SoC.
+
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://lore.kernel.org/r/fd4e8693980e47385a543e7b002eec0b88bd09df.1690440675.git.lorenzo@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -1659,7 +1659,7 @@ static void mtk_update_rx_cpu_idx(struct
+ 
+ static bool mtk_page_pool_enabled(struct mtk_eth *eth)
+ {
+-	return eth->soc->version == 2;
++	return mtk_is_netsys_v2_or_greater(eth);
+ }
+ 
+ static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,

lede/target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch

@@ -0,0 +1,135 @@
+From 199e7d5a7f03dd377f3a7a458360dbedd71d50ba Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Thu, 27 Jul 2023 09:07:28 +0200
+Subject: [PATCH 107/250] net: ethernet: mtk_eth_soc: enable nft hw
+ flowtable_offload for MT7988 SoC
+
+Enable hw Packet Process Engine (PPE) for MT7988 SoC.
+
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://lore.kernel.org/r/5e86341b0220a49620dadc02d77970de5ded9efc.1690441576.git.lorenzo@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |  3 +++
+ drivers/net/ethernet/mediatek/mtk_ppe.c     | 19 +++++++++++++++----
+ drivers/net/ethernet/mediatek/mtk_ppe.h     | 19 ++++++++++++++++++-
+ 3 files changed, 36 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -5026,6 +5026,9 @@ static const struct mtk_soc_data mt7988_
+ 	.required_clks = MT7988_CLKS_BITMAP,
+ 	.required_pctl = false,
+ 	.version = 3,
++	.offload_version = 2,
++	.hash_offset = 4,
++	.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma_v2),
+ 		.rxd_size = sizeof(struct mtk_rx_dma_v2),
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
+@@ -422,13 +422,22 @@ int mtk_foe_entry_set_wdma(struct mtk_et
+ 	struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry);
+ 	u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
+ 
+-	if (mtk_is_netsys_v2_or_greater(eth)) {
++	switch (eth->soc->version) {
++	case 3:
++		*ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
++		*ib2 |=  FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |
++			 MTK_FOE_IB2_WDMA_WINFO_V2;
++		l2->w3info = FIELD_PREP(MTK_FOE_WINFO_WCID_V3, wcid) |
++			     FIELD_PREP(MTK_FOE_WINFO_BSS_V3, bss);
++		break;
++	case 2:
+ 		*ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
+ 		*ib2 |=  FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |
+ 			 MTK_FOE_IB2_WDMA_WINFO_V2;
+ 		l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) |
+ 			    FIELD_PREP(MTK_FOE_WINFO_BSS, bss);
+-	} else {
++		break;
++	default:
+ 		*ib2 &= ~MTK_FOE_IB2_PORT_MG;
+ 		*ib2 |= MTK_FOE_IB2_WDMA_WINFO;
+ 		if (wdma_idx)
+@@ -436,6 +445,7 @@ int mtk_foe_entry_set_wdma(struct mtk_et
+ 		l2->vlan2 = FIELD_PREP(MTK_FOE_VLAN2_WINFO_BSS, bss) |
+ 			    FIELD_PREP(MTK_FOE_VLAN2_WINFO_WCID, wcid) |
+ 			    FIELD_PREP(MTK_FOE_VLAN2_WINFO_RING, txq);
++		break;
+ 	}
+ 
+ 	return 0;
+@@ -950,8 +960,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
+ 	mtk_ppe_init_foe_table(ppe);
+ 	ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys);
+ 
+-	val = MTK_PPE_TB_CFG_ENTRY_80B |
+-	      MTK_PPE_TB_CFG_AGE_NON_L4 |
++	val = MTK_PPE_TB_CFG_AGE_NON_L4 |
+ 	      MTK_PPE_TB_CFG_AGE_UNBIND |
+ 	      MTK_PPE_TB_CFG_AGE_TCP |
+ 	      MTK_PPE_TB_CFG_AGE_UDP |
+@@ -967,6 +976,8 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
+ 			 MTK_PPE_ENTRIES_SHIFT);
+ 	if (mtk_is_netsys_v2_or_greater(ppe->eth))
+ 		val |= MTK_PPE_TB_CFG_INFO_SEL;
++	if (!mtk_is_netsys_v3_or_greater(ppe->eth))
++		val |= MTK_PPE_TB_CFG_ENTRY_80B;
+ 	ppe_w32(ppe, MTK_PPE_TB_CFG, val);
+ 
+ 	ppe_w32(ppe, MTK_PPE_IP_PROTO_CHK,
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.h
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
+@@ -85,6 +85,17 @@ enum {
+ #define MTK_FOE_WINFO_BSS		GENMASK(5, 0)
+ #define MTK_FOE_WINFO_WCID		GENMASK(15, 6)
+ 
++#define MTK_FOE_WINFO_BSS_V3		GENMASK(23, 16)
++#define MTK_FOE_WINFO_WCID_V3		GENMASK(15, 0)
++
++#define MTK_FOE_WINFO_PAO_USR_INFO	GENMASK(15, 0)
++#define MTK_FOE_WINFO_PAO_TID		GENMASK(19, 16)
++#define MTK_FOE_WINFO_PAO_IS_FIXEDRATE	BIT(20)
++#define MTK_FOE_WINFO_PAO_IS_PRIOR	BIT(21)
++#define MTK_FOE_WINFO_PAO_IS_SP		BIT(22)
++#define MTK_FOE_WINFO_PAO_HF		BIT(23)
++#define MTK_FOE_WINFO_PAO_AMSDU_EN	BIT(24)
++
+ enum {
+ 	MTK_FOE_STATE_INVALID,
+ 	MTK_FOE_STATE_UNBIND,
+@@ -106,8 +117,13 @@ struct mtk_foe_mac_info {
+ 	u16 pppoe_id;
+ 	u16 src_mac_lo;
+ 
++	/* netsys_v2 */
+ 	u16 minfo;
+ 	u16 winfo;
++
++	/* netsys_v3 */
++	u32 w3info;
++	u32 wpao;
+ };
+ 
+ /* software-only entry type */
+@@ -218,6 +234,7 @@ struct mtk_foe_ipv6_6rd {
+ 
+ #define MTK_FOE_ENTRY_V1_SIZE	80
+ #define MTK_FOE_ENTRY_V2_SIZE	96
++#define MTK_FOE_ENTRY_V3_SIZE	128
+ 
+ struct mtk_foe_entry {
+ 	u32 ib1;
+@@ -228,7 +245,7 @@ struct mtk_foe_entry {
+ 		struct mtk_foe_ipv4_dslite dslite;
+ 		struct mtk_foe_ipv6 ipv6;
+ 		struct mtk_foe_ipv6_6rd ipv6_6rd;
+-		u32 data[23];
++		u32 data[31];
+ 	};
+ };
+ 

lede/target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch

@@ -0,0 +1,78 @@
+From 0c024632c1e7ff69914329bfd87bec749b9c0aed Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 2 Aug 2023 04:31:09 +0100
+Subject: [PATCH 108/250] net: ethernet: mtk_eth_soc: support per-flow
+ accounting on MT7988
+
+NETSYS_V3 uses 64 bits for each counters while older SoCs are using
+48/40 bits for each counter.
+Support reading per-flow byte and package counters on NETSYS_V3.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Link: https://lore.kernel.org/r/37a0928fa8c1253b197884c68ce1f54239421ac5.1690946442.git.daniel@makrotopia.org
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c  |  1 +
+ drivers/net/ethernet/mediatek/mtk_ppe.c      | 21 +++++++++++++-------
+ drivers/net/ethernet/mediatek/mtk_ppe_regs.h |  2 ++
+ 3 files changed, 17 insertions(+), 7 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -5028,6 +5028,7 @@ static const struct mtk_soc_data mt7988_
+ 	.version = 3,
+ 	.offload_version = 2,
+ 	.hash_offset = 4,
++	.has_accounting = true,
+ 	.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
+ 	.txrx = {
+ 		.txd_size = sizeof(struct mtk_tx_dma_v2),
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
+@@ -91,7 +91,6 @@ static int mtk_ppe_mib_wait_busy(struct
+ 
+ static int mtk_mib_entry_read(struct mtk_ppe *ppe, u16 index, u64 *bytes, u64 *packets)
+ {
+-	u32 byte_cnt_low, byte_cnt_high, pkt_cnt_low, pkt_cnt_high;
+ 	u32 val, cnt_r0, cnt_r1, cnt_r2;
+ 	int ret;
+ 
+@@ -106,12 +105,20 @@ static int mtk_mib_entry_read(struct mtk
+ 	cnt_r1 = readl(ppe->base + MTK_PPE_MIB_SER_R1);
+ 	cnt_r2 = readl(ppe->base + MTK_PPE_MIB_SER_R2);
+ 
+-	byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0);
+-	byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1);
+-	pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1);
+-	pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2);
+-	*bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low;
+-	*packets = (pkt_cnt_high << 16) | pkt_cnt_low;
++	if (mtk_is_netsys_v3_or_greater(ppe->eth)) {
++		/* 64 bit for each counter */
++		u32 cnt_r3 = readl(ppe->base + MTK_PPE_MIB_SER_R3);
++		*bytes = ((u64)cnt_r1 << 32) | cnt_r0;
++		*packets = ((u64)cnt_r3 << 32) | cnt_r2;
++	} else {
++		/* 48 bit byte counter, 40 bit packet counter */
++		u32 byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0);
++		u32 byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1);
++		u32 pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1);
++		u32 pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2);
++		*bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low;
++		*packets = (pkt_cnt_high << 16) | pkt_cnt_low;
++	}
+ 
+ 	return 0;
+ }
+--- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
++++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
+@@ -163,6 +163,8 @@ enum {
+ #define MTK_PPE_MIB_SER_R2			0x348
+ #define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH		GENMASK(23, 0)
+ 
++#define MTK_PPE_MIB_SER_R3			0x34c
++
+ #define MTK_PPE_MIB_CACHE_CTL			0x350
+ #define MTK_PPE_MIB_CACHE_CTL_EN		BIT(0)
+ #define MTK_PPE_MIB_CACHE_CTL_FLUSH		BIT(2)

lede/target/linux/generic/backport-6.1/750-v6.5-15-net-ethernet-mtk_eth_soc-fix-NULL-pointer-on-hw-rese.patch

@@ -0,0 +1,52 @@
+From 3b12f42772c26869d60398c1710aa27b27cd945c Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 21 Aug 2023 17:12:44 +0100
+Subject: [PATCH 109/250] net: ethernet: mtk_eth_soc: fix NULL pointer on hw
+ reset
+
+When a hardware reset is triggered on devices not initializing WED the
+calls to mtk_wed_fe_reset and mtk_wed_fe_reset_complete dereference a
+pointer on uninitialized stack memory.
+Break out of both functions in case a hw_list entry is 0.
+
+Fixes: 08a764a7c51b ("net: ethernet: mtk_wed: add reset/reset_complete callbacks")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://lore.kernel.org/r/5465c1609b464cc7407ae1530c40821dcdf9d3e6.1692634266.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_wed.c | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -214,9 +214,13 @@ void mtk_wed_fe_reset(void)
+ 
+ 	for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
+ 		struct mtk_wed_hw *hw = hw_list[i];
+-		struct mtk_wed_device *dev = hw->wed_dev;
++		struct mtk_wed_device *dev;
+ 		int err;
+ 
++		if (!hw)
++			break;
++
++		dev = hw->wed_dev;
+ 		if (!dev || !dev->wlan.reset)
+ 			continue;
+ 
+@@ -237,8 +241,12 @@ void mtk_wed_fe_reset_complete(void)
+ 
+ 	for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
+ 		struct mtk_wed_hw *hw = hw_list[i];
+-		struct mtk_wed_device *dev = hw->wed_dev;
++		struct mtk_wed_device *dev;
++
++		if (!hw)
++			break;
+ 
++		dev = hw->wed_dev;
+ 		if (!dev || !dev->wlan.reset_complete)
+ 			continue;
+ 

lede/target/linux/generic/backport-6.1/750-v6.5-16-net-ethernet-mtk_eth_soc-fix-register-definitions-fo.patch

@@ -0,0 +1,44 @@
+From 489aea123d74a846ce746bfdb3efe1e7ad512e0d Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 22 Aug 2023 17:31:24 +0100
+Subject: [PATCH 110/250] net: ethernet: mtk_eth_soc: fix register definitions
+ for MT7988
+
+More register macros need to be adjusted for the 3rd GMAC on MT7988.
+Account for added bit in SYSCFG0_SGMII_MASK.
+
+Fixes: 445eb6448ed3 ("net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Link: https://lore.kernel.org/r/1c8da012e2ca80939906d85f314138c552139f0f.1692721443.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -133,10 +133,12 @@
+ #define MTK_GDMA_XGDM_SEL	BIT(31)
+ 
+ /* Unicast Filter MAC Address Register - Low */
+-#define MTK_GDMA_MAC_ADRL(x)	(0x508 + (x * 0x1000))
++#define MTK_GDMA_MAC_ADRL(x)	({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ?	\
++				   0x548 : 0x508 + (_x * 0x1000); })
+ 
+ /* Unicast Filter MAC Address Register - High */
+-#define MTK_GDMA_MAC_ADRH(x)	(0x50C + (x * 0x1000))
++#define MTK_GDMA_MAC_ADRH(x)	({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ?	\
++				   0x54C : 0x50C + (_x * 0x1000); })
+ 
+ /* FE global misc reg*/
+ #define MTK_FE_GLO_MISC         0x124
+@@ -503,7 +505,7 @@
+ #define ETHSYS_SYSCFG0		0x14
+ #define SYSCFG0_GE_MASK		0x3
+ #define SYSCFG0_GE_MODE(x, y)	(x << (12 + (y * 2)))
+-#define SYSCFG0_SGMII_MASK     GENMASK(9, 8)
++#define SYSCFG0_SGMII_MASK     GENMASK(9, 7)
+ #define SYSCFG0_SGMII_GMAC1    ((2 << 8) & SYSCFG0_SGMII_MASK)
+ #define SYSCFG0_SGMII_GMAC2    ((3 << 8) & SYSCFG0_SGMII_MASK)
+ #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)

lede/target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch

@@ -0,0 +1,188 @@
+From 15a84d1c44ae8c1451c265ee60500588a24e8cd6 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 22 Aug 2023 17:32:03 +0100
+Subject: [PATCH 111/250] net: ethernet: mtk_eth_soc: add reset bits for MT7988
+
+Add bits needed to reset the frame engine on MT7988.
+
+Fixes: 445eb6448ed3 ("net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/89b6c38380e7a3800c1362aa7575600717bc7543.1692721443.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 76 +++++++++++++++------
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 16 +++--
+ 2 files changed, 68 insertions(+), 24 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -3592,19 +3592,34 @@ static void mtk_hw_reset(struct mtk_eth
+ {
+ 	u32 val;
+ 
+-	if (mtk_is_netsys_v2_or_greater(eth)) {
++	if (mtk_is_netsys_v2_or_greater(eth))
+ 		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
++
++	if (mtk_is_netsys_v3_or_greater(eth)) {
++		val = RSTCTRL_PPE0_V3;
++
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
++			val |= RSTCTRL_PPE1_V3;
++
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
++			val |= RSTCTRL_PPE2;
++
++		val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
++	} else if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		val = RSTCTRL_PPE0_V2;
++
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
++			val |= RSTCTRL_PPE1;
+ 	} else {
+ 		val = RSTCTRL_PPE0;
+ 	}
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
+-		val |= RSTCTRL_PPE1;
+-
+ 	ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
+ 
+-	if (mtk_is_netsys_v2_or_greater(eth))
++	if (mtk_is_netsys_v3_or_greater(eth))
++		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
++			     0x6f8ff);
++	else if (mtk_is_netsys_v2_or_greater(eth))
+ 		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
+ 			     0x3ffffff);
+ }
+@@ -3630,13 +3645,21 @@ static void mtk_hw_warm_reset(struct mtk
+ 		return;
+ 	}
+ 
+-	if (mtk_is_netsys_v2_or_greater(eth))
++	if (mtk_is_netsys_v3_or_greater(eth)) {
++		rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3;
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
++			rst_mask |= RSTCTRL_PPE1_V3;
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
++			rst_mask |= RSTCTRL_PPE2;
++
++		rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
++	} else if (mtk_is_netsys_v2_or_greater(eth)) {
+ 		rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
+-	else
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
++			rst_mask |= RSTCTRL_PPE1;
++	} else {
+ 		rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
+-
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
+-		rst_mask |= RSTCTRL_PPE1;
++	}
+ 
+ 	regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
+ 
+@@ -3988,11 +4011,17 @@ static void mtk_prepare_for_reset(struct
+ 	u32 val;
+ 	int i;
+ 
+-	/* disabe FE P3 and P4 */
+-	val = mtk_r32(eth, MTK_FE_GLO_CFG) | MTK_FE_LINK_DOWN_P3;
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
+-		val |= MTK_FE_LINK_DOWN_P4;
+-	mtk_w32(eth, val, MTK_FE_GLO_CFG);
++	/* set FE PPE ports link down */
++	for (i = MTK_GMAC1_ID;
++	     i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID);
++	     i += 2) {
++		val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
++			val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT);
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
++			val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT);
++		mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
++	}
+ 
+ 	/* adjust PPE configurations to prepare for reset */
+ 	for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
+@@ -4053,11 +4082,18 @@ static void mtk_pending_work(struct work
+ 		}
+ 	}
+ 
+-	/* enabe FE P3 and P4 */
+-	val = mtk_r32(eth, MTK_FE_GLO_CFG) & ~MTK_FE_LINK_DOWN_P3;
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
+-		val &= ~MTK_FE_LINK_DOWN_P4;
+-	mtk_w32(eth, val, MTK_FE_GLO_CFG);
++	/* set FE PPE ports link up */
++	for (i = MTK_GMAC1_ID;
++	     i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID);
++	     i += 2) {
++		val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
++			val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT);
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
++			val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT);
++
++		mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
++	}
+ 
+ 	clear_bit(MTK_RESETTING, &eth->state);
+ 
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -76,9 +76,8 @@
+ #define	MTK_HW_LRO_SDL_REMAIN_ROOM	1522
+ 
+ /* Frame Engine Global Configuration */
+-#define MTK_FE_GLO_CFG		0x00
+-#define MTK_FE_LINK_DOWN_P3	BIT(11)
+-#define MTK_FE_LINK_DOWN_P4	BIT(12)
++#define MTK_FE_GLO_CFG(x)	(((x) == MTK_GMAC3_ID) ? 0x24 : 0x00)
++#define MTK_FE_LINK_DOWN_P(x)	BIT(((x) + 8) % 16)
+ 
+ /* Frame Engine Global Reset Register */
+ #define MTK_RST_GL		0x04
+@@ -522,9 +521,15 @@
+ /* ethernet reset control register */
+ #define ETHSYS_RSTCTRL			0x34
+ #define RSTCTRL_FE			BIT(6)
++#define RSTCTRL_WDMA0			BIT(24)
++#define RSTCTRL_WDMA1			BIT(25)
++#define RSTCTRL_WDMA2			BIT(26)
+ #define RSTCTRL_PPE0			BIT(31)
+ #define RSTCTRL_PPE0_V2			BIT(30)
+ #define RSTCTRL_PPE1			BIT(31)
++#define RSTCTRL_PPE0_V3			BIT(29)
++#define RSTCTRL_PPE1_V3			BIT(30)
++#define RSTCTRL_PPE2			BIT(31)
+ #define RSTCTRL_ETH			BIT(23)
+ 
+ /* ethernet reset check idle register */
+@@ -931,6 +936,7 @@ enum mkt_eth_capabilities {
+ 	MTK_QDMA_BIT,
+ 	MTK_SOC_MT7628_BIT,
+ 	MTK_RSTCTRL_PPE1_BIT,
++	MTK_RSTCTRL_PPE2_BIT,
+ 	MTK_U3_COPHY_V2_BIT,
+ 
+ 	/* MUX BITS*/
+@@ -965,6 +971,7 @@ enum mkt_eth_capabilities {
+ #define MTK_QDMA		BIT_ULL(MTK_QDMA_BIT)
+ #define MTK_SOC_MT7628		BIT_ULL(MTK_SOC_MT7628_BIT)
+ #define MTK_RSTCTRL_PPE1	BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
++#define MTK_RSTCTRL_PPE2	BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
+ #define MTK_U3_COPHY_V2		BIT_ULL(MTK_U3_COPHY_V2_BIT)
+ 
+ #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW		\
+@@ -1047,7 +1054,8 @@ enum mkt_eth_capabilities {
+ 		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
+ 		      MTK_RSTCTRL_PPE1)
+ 
+-#define MT7988_CAPS  (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1)
++#define MT7988_CAPS  (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1 | \
++		      MTK_RSTCTRL_PPE2)
+ 
+ struct mtk_tx_dma_desc_info {
+ 	dma_addr_t	addr;

lede/target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch

@@ -0,0 +1,254 @@
+From 25ce45fe40b574e5d7ffa407f7f2db03e7d5a910 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 22 Aug 2023 17:32:54 +0100
+Subject: [PATCH 112/250] net: ethernet: mtk_eth_soc: add support for in-SoC
+ SRAM
+
+MT7981, MT7986 and MT7988 come with in-SoC SRAM dedicated for Ethernet
+DMA rings. Support using the SRAM without breaking existing device tree
+bindings, ie. only new SoC starting from MT7988 will have the SRAM
+declared as additional resource in device tree. For MT7981 and MT7986
+an offset on top of the main I/O base is used.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/e45e0f230c63ad58869e8fe35b95a2fb8925b625.1692721443.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 88 ++++++++++++++++-----
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 12 ++-
+ 2 files changed, 78 insertions(+), 22 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -1119,10 +1119,13 @@ static int mtk_init_fq_dma(struct mtk_et
+ 	dma_addr_t dma_addr;
+ 	int i;
+ 
+-	eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
+-					       cnt * soc->txrx.txd_size,
+-					       &eth->phy_scratch_ring,
+-					       GFP_KERNEL);
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM))
++		eth->scratch_ring = eth->sram_base;
++	else
++		eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
++						       cnt * soc->txrx.txd_size,
++						       &eth->phy_scratch_ring,
++						       GFP_KERNEL);
+ 	if (unlikely(!eth->scratch_ring))
+ 		return -ENOMEM;
+ 
+@@ -2430,8 +2433,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+ 	if (!ring->buf)
+ 		goto no_tx_mem;
+ 
+-	ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
+-				       &ring->phys, GFP_KERNEL);
++	if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) {
++		ring->dma = eth->sram_base + ring_size * sz;
++		ring->phys = eth->phy_scratch_ring + ring_size * (dma_addr_t)sz;
++	} else {
++		ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
++					       &ring->phys, GFP_KERNEL);
++	}
++
+ 	if (!ring->dma)
+ 		goto no_tx_mem;
+ 
+@@ -2530,8 +2539,7 @@ static void mtk_tx_clean(struct mtk_eth
+ 		kfree(ring->buf);
+ 		ring->buf = NULL;
+ 	}
+-
+-	if (ring->dma) {
++	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
+ 		dma_free_coherent(eth->dma_dev,
+ 				  ring->dma_size * soc->txrx.txd_size,
+ 				  ring->dma, ring->phys);
+@@ -2550,9 +2558,14 @@ static int mtk_rx_alloc(struct mtk_eth *
+ {
+ 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
+ 	struct mtk_rx_ring *ring;
+-	int rx_data_len, rx_dma_size;
++	int rx_data_len, rx_dma_size, tx_ring_size;
+ 	int i;
+ 
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
++		tx_ring_size = MTK_QDMA_RING_SIZE;
++	else
++		tx_ring_size = MTK_DMA_SIZE;
++
+ 	if (rx_flag == MTK_RX_FLAGS_QDMA) {
+ 		if (ring_no)
+ 			return -EINVAL;
+@@ -2587,9 +2600,20 @@ static int mtk_rx_alloc(struct mtk_eth *
+ 		ring->page_pool = pp;
+ 	}
+ 
+-	ring->dma = dma_alloc_coherent(eth->dma_dev,
+-				       rx_dma_size * eth->soc->txrx.rxd_size,
+-				       &ring->phys, GFP_KERNEL);
++	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
++	    rx_flag != MTK_RX_FLAGS_NORMAL) {
++		ring->dma = dma_alloc_coherent(eth->dma_dev,
++					       rx_dma_size * eth->soc->txrx.rxd_size,
++					       &ring->phys, GFP_KERNEL);
++	} else {
++		struct mtk_tx_ring *tx_ring = &eth->tx_ring;
++
++		ring->dma = tx_ring->dma + tx_ring_size *
++			    eth->soc->txrx.txd_size * (ring_no + 1);
++		ring->phys = tx_ring->phys + tx_ring_size *
++			     eth->soc->txrx.txd_size * (ring_no + 1);
++	}
++
+ 	if (!ring->dma)
+ 		return -ENOMEM;
+ 
+@@ -2674,7 +2698,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+ 	return 0;
+ }
+ 
+-static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
++static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram)
+ {
+ 	int i;
+ 
+@@ -2697,7 +2721,7 @@ static void mtk_rx_clean(struct mtk_eth
+ 		ring->data = NULL;
+ 	}
+ 
+-	if (ring->dma) {
++	if (!in_sram && ring->dma) {
+ 		dma_free_coherent(eth->dma_dev,
+ 				  ring->dma_size * eth->soc->txrx.rxd_size,
+ 				  ring->dma, ring->phys);
+@@ -3057,7 +3081,7 @@ static void mtk_dma_free(struct mtk_eth
+ 	for (i = 0; i < MTK_MAX_DEVS; i++)
+ 		if (eth->netdev[i])
+ 			netdev_reset_queue(eth->netdev[i]);
+-	if (eth->scratch_ring) {
++	if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
+ 		dma_free_coherent(eth->dma_dev,
+ 				  MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
+ 				  eth->scratch_ring, eth->phy_scratch_ring);
+@@ -3065,13 +3089,13 @@ static void mtk_dma_free(struct mtk_eth
+ 		eth->phy_scratch_ring = 0;
+ 	}
+ 	mtk_tx_clean(eth);
+-	mtk_rx_clean(eth, &eth->rx_ring[0]);
+-	mtk_rx_clean(eth, &eth->rx_ring_qdma);
++	mtk_rx_clean(eth, &eth->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM));
++	mtk_rx_clean(eth, &eth->rx_ring_qdma, false);
+ 
+ 	if (eth->hwlro) {
+ 		mtk_hwlro_rx_uninit(eth);
+ 		for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
+-			mtk_rx_clean(eth, &eth->rx_ring[i]);
++			mtk_rx_clean(eth, &eth->rx_ring[i], false);
+ 	}
+ 
+ 	kfree(eth->scratch_head);
+@@ -4639,7 +4663,7 @@ static int mtk_sgmii_init(struct mtk_eth
+ 
+ static int mtk_probe(struct platform_device *pdev)
+ {
+-	struct resource *res = NULL;
++	struct resource *res = NULL, *res_sram;
+ 	struct device_node *mac_np;
+ 	struct mtk_eth *eth;
+ 	int err, i;
+@@ -4659,6 +4683,20 @@ static int mtk_probe(struct platform_dev
+ 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
+ 		eth->ip_align = NET_IP_ALIGN;
+ 
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
++		/* SRAM is actual memory and supports transparent access just like DRAM.
++		 * Hence we don't require __iomem being set and don't need to use accessor
++		 * functions to read from or write to SRAM.
++		 */
++		if (mtk_is_netsys_v3_or_greater(eth)) {
++			eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1);
++			if (IS_ERR(eth->sram_base))
++				return PTR_ERR(eth->sram_base);
++		} else {
++			eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET;
++		}
++	}
++
+ 	spin_lock_init(&eth->page_lock);
+ 	spin_lock_init(&eth->tx_irq_lock);
+ 	spin_lock_init(&eth->rx_irq_lock);
+@@ -4722,6 +4760,18 @@ static int mtk_probe(struct platform_dev
+ 			err = -EINVAL;
+ 			goto err_destroy_sgmii;
+ 		}
++		if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
++			if (mtk_is_netsys_v3_or_greater(eth)) {
++				res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++				if (!res_sram) {
++					err = -EINVAL;
++					goto err_destroy_sgmii;
++				}
++				eth->phy_scratch_ring = res_sram->start;
++			} else {
++				eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET;
++			}
++		}
+ 	}
+ 
+ 	if (eth->soc->offload_version) {
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -139,6 +139,9 @@
+ #define MTK_GDMA_MAC_ADRH(x)	({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ?	\
+ 				   0x54C : 0x50C + (_x * 0x1000); })
+ 
++/* Internal SRAM offset */
++#define MTK_ETH_SRAM_OFFSET	0x40000
++
+ /* FE global misc reg*/
+ #define MTK_FE_GLO_MISC         0x124
+ 
+@@ -938,6 +941,7 @@ enum mkt_eth_capabilities {
+ 	MTK_RSTCTRL_PPE1_BIT,
+ 	MTK_RSTCTRL_PPE2_BIT,
+ 	MTK_U3_COPHY_V2_BIT,
++	MTK_SRAM_BIT,
+ 
+ 	/* MUX BITS*/
+ 	MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
+@@ -973,6 +977,7 @@ enum mkt_eth_capabilities {
+ #define MTK_RSTCTRL_PPE1	BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
+ #define MTK_RSTCTRL_PPE2	BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
+ #define MTK_U3_COPHY_V2		BIT_ULL(MTK_U3_COPHY_V2_BIT)
++#define MTK_SRAM		BIT_ULL(MTK_SRAM_BIT)
+ 
+ #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW		\
+ 	BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
+@@ -1048,14 +1053,14 @@ enum mkt_eth_capabilities {
+ #define MT7981_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
+ 		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
+ 		      MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
+-		      MTK_RSTCTRL_PPE1)
++		      MTK_RSTCTRL_PPE1 | MTK_SRAM)
+ 
+ #define MT7986_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
+ 		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
+-		      MTK_RSTCTRL_PPE1)
++		      MTK_RSTCTRL_PPE1 | MTK_SRAM)
+ 
+ #define MT7988_CAPS  (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1 | \
+-		      MTK_RSTCTRL_PPE2)
++		      MTK_RSTCTRL_PPE2 | MTK_SRAM)
+ 
+ struct mtk_tx_dma_desc_info {
+ 	dma_addr_t	addr;
+@@ -1215,6 +1220,7 @@ struct mtk_eth {
+ 	struct device			*dev;
+ 	struct device			*dma_dev;
+ 	void __iomem			*base;
++	void				*sram_base;
+ 	spinlock_t			page_lock;
+ 	spinlock_t			tx_irq_lock;
+ 	spinlock_t			rx_irq_lock;