Commit Graph

93 Commits

Author SHA1 Message Date
Yandong Lin
fc2a997a58 fix[mpp_enc_cfg]: Remove a redundant atr_str
Change-Id: I7553fcf8a7014ce3c2a13b1fd923ac91d78fb9d3
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
2025-01-16 06:19:31 +00:00
Yandong Lin
7939be1246 refactor[mpp_enc_cfg]: Adjust cu_qp_delta_depth
sync from mpp_interface

Change-Id: I2dfabef3acf01566df289396678a433ac84f3a15
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
2025-01-09 06:17:45 +00:00
Yandong Lin
2cb69a2860 fix[mpp_enc_cfg]: Add sao_bit_ratio from mpp_interface
Change-Id: Iba92fdd0052e661b74d747f921dfe25d5a408cd1
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
2025-01-09 03:32:10 +00:00
Yandong Lin
e447e0763e feat[mpp_enc_cfg]: Merge enc cfgs from mpp_interface
Change-Id: Ie08d9a26129096634b61fe60a10517efe0807180
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
2025-01-07 17:04:12 +08:00
Johnson Ding
b4efbdf9b7 feat[enc]: Add switch for disable IDR encoding when FPS changed.
1. No need to encode IDR when fps_in is changed. So remove it from
`check_resend_hdr`
2. If application do not want any IDR encoded when only fps is changed,
    call `mpp_enc_cfg_s32(cfg, "rc:fps_chg_no_idr", 0);` when
    initializing.
3. Keeping CPB when only SPS, PPS are updated without IDR encoded for
H.264 encoder.

Change-Id: I034dd789a3f24318004d942624eb10240f7db2e9
Signed-off-by: Johnson Ding <johnson.ding@rock-chips.com>
2024-12-25 09:41:11 +08:00
Tingjin Huang
179122cc99 fix[tune]: Replace qpmap_en with deblur_en
Deblur_en is more generic for upper application.

Change-Id: Ibe4e0f81851fdbbe8fb8b7d840a4a9380e0403b1
Signed-off-by: Tingjin Huang <timkingh.huang@rock-chips.com>
2024-09-29 09:46:19 +08:00
Tingjin Huang
01dee1b7d4 feat[vepu580]: Optimization to improve VMAF
Signed-off-by: Tingjin Huang <timkingh.huang@rock-chips.com>
Change-Id: Idaecf9a402aa9b87802d76911abb816e0dc557ec
2024-08-29 10:04:03 +08:00
Tingjin Huang
e03714e193 feat[vepu580]: Add qpmap and rc container interface
Signed-off-by: Tingjin Huang <timkingh.huang@rock-chips.com>
Change-Id: I9fb0683008880a2e025664052a64d290730e6b49
2024-08-29 10:04:03 +08:00
liming.lou
1bb6ff8993 feat[vepu510]: Sync code from enc_tune branch
1. Design 8 mode for smear
2. Adjust atf_e and atr_e switch
3. Adjust aq thd and aq qp delta
4. Modify appropriate parameters for smear
5. Add sao atr atl configure interface

Change-Id: I0afb7e3d920dddfd33ea8d81fcbda5dd0d6801d3
Signed-off-by: Tingjin Huang <timkingh.huang@rock-chips.com>
2024-08-27 10:23:33 +08:00
toby.zhang
03696728e1 feat[vepu510]: Sync code from enc_tune branch
1. Add anti-line tuning
2. Adjust AQ assignment
3. Add smart encoding
4. Add deblur/qpmap routine
5. Add atf & four level intensity control atf
6. Add atr anti_blur function
7. Add real time bitrate output
8. Add smear buffer for vepu510

Change-Id: Iae661686f6adacd0b5ec57c102c184e2537dfc7d
Signed-off-by: Tingjin Huang <timkingh.huang@rock-chips.com>
2024-08-27 10:23:23 +08:00
toby.zhang
02095f66d3 feat[vepu510]: Sync code from enc_tune branch
1. Add cu_qp_delta_depth cfg
2. Configure AQ regs for H.265
3. Configure regs according to scene mode
4. Support fixed frame level QP
5. Add RDO lambda table index
6. Update stat info for HEVC
7. Add tuning code for H.264 encoder

Change-Id: Id7dae4ed55e1b94622aee72cfce8f24c833d00e1
Signed-off-by: Tingjin Huang <timkingh.huang@rock-chips.com>
2024-08-27 10:08:49 +08:00
Yanjun Liao
fa97ca3dba feat[h265e]: Support force mark & use ltr
Change-Id: Ied10ca664f149a75ebc02733f884ffeb41449c4f
Signed-off-by: Yanjun Liao <yanjun.liao@rock-chips.com>
2024-07-16 09:55:38 +08:00
xueman.ruan
36e263402a fix[hal_h264e]: fix segment err when encode tsvc
update segment info after amend stream

Change-Id: I6dc1ace0bcd58746f3fd0755c980e22482219f3d
Signed-off-by: xueman.ruan <xueman.ruan@rock-chips.com>
2024-06-13 09:17:12 +08:00
Yanjun Liao
293f61a8f6 feat[enc_265]: Support get Largest Code Unit size
Case: mpp_enc_cfg_get_s32(p->cfg, "h265:lcu_size", &lcu_size);

Change-Id: I8f284b77b465377f600cb3449d0012edd5a64098
Signed-off-by: Yanjun Liao <yanjun.liao@rock-chips.com>
2024-05-24 15:19:56 +08:00
Yanjun Liao
25649d2fae fix[265e_api]: Support cons_intra_pred_flag cfg
Change-Id: I57d7df14086cab0a6019f77b7b4b6259f456455e
Signed-off-by: Yanjun Liao <yanjun.liao@rock-chips.com>
2024-03-29 10:18:14 +08:00
Johnson Ding
2b2f3669e4 feat[enc]: Add config entry for output chroma format
Change-Id: I29f4f764adc401a635e9fda2e2b41b2002078637
Signed-off-by: Johnson Ding <johnson.ding@rock-chips.com>
2024-03-08 11:07:36 +08:00
Herman Chen
02a35cb871 fix: Fix clerical error
fix denorminator to denominator

Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: I6e9deed4fe3bcdc1d2f7d56f3dccb87607d576bf
2024-03-05 11:31:47 +08:00
hdl
68177e2268 feat[vepu580]: Add frm min/max qp and scene_mode cmd param
Signed-off-by: hdl <hdl@rock-chips.com>
Change-Id: I27c3f3cfb599b8d05e58aceb1967bec4230d386e
2023-09-25 17:46:32 +08:00
hdl
9ff2961dcf feat[venc]: Add qbias for rkvenc encoder
Signed-off-by: hdl <hdl@rock-chips.com>
Change-Id: Ib463b777898a3c25bebbd2fcb95d872581f0b8f7
2023-09-25 16:34:03 +08:00
xueman.ruan
f91f152a1a [hal_h264e]: fix log2_max_frm_num config error.
Issue is introduced when user configs log2_max_frm_num.

1. use MppEncH264HwCfg instead of hw_poc_type.
2. slice_write can only use corresponding hardware config.

Signed-off-by: xueman.ruan <xueman.ruan@rock-chips.com>
Change-Id: Id5f3622512075eedc1e9dc99636c3f0dff43d6f1
2023-05-30 14:04:31 +08:00
xueman.ruan
0466c8aa6b [mpp_enc_cfg]: combine gop and ref cfg config.
Signed-off-by: xueman.ruan <xueman.ruan@rock-chips.com>
Change-Id: Ia15a0128d03b1a2624410b6f2a13effe3a03c47c
2023-03-21 09:29:37 +08:00
xueman.ruan
e6ef3d1d7a [h264e]: Fix profile compatibility error.
Issue introduced by encoding TSVC.

Signed-off-by: xueman.ruan <xueman.ruan@rock-chips.com>
Change-Id: I98c2c61634c7cc57180459e0427d5672fe407c47
2023-03-08 09:32:21 +08:00
Hongjin Li
0ee683acf3 [enc_gdr]: Platform supports intra refresh
Add parameters required for intra refresh
Add rate control corresponding to intra refresh

Change-Id: I6dbaf70e3c50cd0debf909ded9fb5c4f30df26ec
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
2023-01-11 11:04:44 +08:00
sayon.chen
cf5b3571e7 [h265e_cfg]: Add lpf across slice or tile cfg
Change-Id: Ib5afc2d9b95e85d523e545e580ccd0fcd7b8e416
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
2022-11-16 15:26:02 +08:00
sayon.chen
9405c48f97 [hal_h264e]: Support poc_type 2 & add tsvc prefix
Change-Id: Ibbb0ee179974fdade590b97c9b3b38bcf822dffc
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
2022-11-04 17:05:12 +08:00
xueman.ruan
09de35e9b5 [enc_cfg]: Update mirror transformation.
1. constraint the range of input argument.
2. add flip config, equal to vertical mirror transformation.
3. add mirroring_ext and rotation_ext to config set, for supporting
GET_CFG control.

Signed-off-by: xueman.ruan <xueman.ruan@rock-chips.com>
Change-Id: I01c0b9187a18851354e81b5f08afc6dcaaba8365
2022-09-21 15:21:40 +08:00
sayon.chen
273d2bdd92 [h265e_ps]: Add auto tile split cfg
Auto tile cfg will let encoder auto split picture into tiles
according to platform encoder core number.

When enabled on RK3588 all picture will be splited into two tiles.

Encoder cfg string: h265:auto_tile

Change-Id: I3bd91a7781fc2c7e0b43bf2e3be775a5b8098d78
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
2022-09-01 10:56:23 +08:00
xueman.ruan
82ae30f031 [h264e_sps]: Add parameters config for encoder
Encorder parameters: constraint_set0~5

Signed-off-by: xueman.ruan <xueman.ruan@rock-chips.com>
Change-Id: I7f90ff97881f875ffad77cf4125ee6623d179563
2022-08-16 12:16:57 +08:00
Herman Chen
61fbfb82cd [mpp_enc_cfg]: Add hw config for block mode
NOTE: Only for vepu580

Change-Id: Ic186ad014b734b5df01ae3218ed3d7219729c1ee
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
2022-07-05 11:45:03 +08:00
Herman Chen
8ce07dbfba [hal_vepu580]: Add slice segment info output
Change-Id: I79a036b6ed5c75b587564a91f392ac81f305e505
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
2022-07-01 15:14:35 +08:00
Herman Chen
6ddafd0bfa [mpp_enc]: Add split output flag
Split output flag is for low delay packet output mode.

Change-Id: I2f743f14b89864625406ebf94687f4f838f0df15
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
2022-05-10 11:19:23 +08:00
Herman Chen
f903701f44 [rk_mpi]: Add encoder query function
Change-Id: I869d30bf11b26feee02f5ba307d98f6bbdcf7058
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
2022-04-13 17:34:36 +08:00
Herman Chen
f0079f49d2 [h264e_vepu580]: Add dpb hal func and more buffer
Change-Id: I1e458732b821571d25079aebe19831948bd591ee
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
2022-03-26 16:04:22 +08:00
Herman Chen
2eb15d5918 [mpp_enc_cfg]: Add tuning scene mode check
Change-Id: I0d90589c6e57be6e348f6510a79d4a7ecc83ce9c
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
2022-03-08 10:48:25 +08:00
Herman Chen
ff40ff4325 [mpp_enc_cfg]: Add fine tuning paramter define
Change-Id: I832f6706c837aac9ef7885761a6ebbb830a08d4b
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
2022-03-07 18:07:28 +08:00
sayon.chen
8c04e0d562 [mpp_enc_roi]: Add roi generation function
vepu58x roi cfg generation is depended on vepu54x roi cfg.

1. Use roi_enable to enable roi test.
2. Use roi_type to test different roi config mode.

Old region mode is set to legacy now for future roi cfg will be more and
more complicated.

Change-Id: Ib9e8976b732f05625e7589b64752d38fbd83584b
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
2021-11-30 17:11:11 +08:00
sayon.chen
1fb20bb450 [mpp_enc]: Add new roi buffer config mode
The roi structure on vepu580 is too complex.

So we provide provide a buffer tunnel for externl user to config encoder
hardware directly.

External user should generate roi data structure according to datasheet.
Then config the base_addr, qp_addr, amv_addr, pmv_addr by metadata.

Change-Id: Iae50bf3ca36c1ff789140055d4d36a79afeb2e58
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
2021-11-20 18:34:30 +08:00
Yandong Lin
ac6f8b1384 [h264e_vepu]: add cfg to disable mb rc
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I71e72164756b23f181a67a8b8799b9867a0854fb
2021-11-09 18:26:25 +08:00
sayon.chen
09d2bca7e7 [h265e]: Add sao disable cfg
Change-Id: I446178d5d2aefa26750382f126fac582ae93e16c
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
2021-10-25 10:21:49 +08:00
sayon.chen
37397d6376 [rc_v2]: Rename stat_times to stats_time
Change-Id: I3cfd444b2d26d5bb2ce2a806efc1a74f4cce05b2
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
2021-06-28 16:17:50 +08:00
sayon.chen
f53dfac47c [rc_v2]: Support hierarchical QP cfg
Change-Id: I0827689ee27a7007cb157b2990089e3c34c6ad50
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
2021-06-02 15:24:24 +08:00
Yandong Lin
33784aca30 [rkv_enc_cmd]: Fix check info err when enc_cfg_set
Fix issue frome github:
https://github.com/rockchip-linux/mpp/issues/201
Err message:
mpp_cfg: cfg h264:max_tid expect RK_S32 input NOT RK_S32
mpp_cfg: cfg h264:max_ltr expect RK_S32 input NOT RK_S32
mpp_cfg: cfg h264:prefix_mode expect RK_S32 input NOT RK_S32
mpp_cfg: cfg h264:base_layer_pid expect RK_S32 input NOT RK_S32

Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I9dbd49a6ce04807455d1a7dc090cad96ae0f2c83
2021-05-21 15:41:11 +08:00
Yandong Lin
a0ec1ba235 [rkv_enc_cmd]: Fix check info err when mpp_enc_cfg_set
Err message:
mpp[16915]: mpp_cfg: cfg h264:poc_type expect RK_U32 input NOT RK_U32
mpp[16915]: mpp_cfg: cfg h264:log2_max_poc_lsb expect RK_U32 input NOT
RK_U32
mpp[16915]: mpp_cfg: cfg h264:log2_max_frm_num expect RK_U32 input NOT
RK_U32

Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: Ide77867beed2ee4e94df1179882713e600d3448b
2021-05-21 11:39:00 +08:00
Herman Chen
434f15ff26 [enc_cfg]: Fix max_reenc_times size check error
Change-Id: Ieb19f47d57ea54d450cf904475732d46a5b52928
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
2021-01-30 18:20:56 +08:00
Johnson Ding
e6d2ab3c60 [h264e]: Add gaps in frame_num config entry
Some of NVR product may do some thing special when decoding the first
GOP of bitstream encoded by MPP, and report "gaps in frame_num is not
allowed" although frame_num is bitstream is continuous. Setting
gaps_in_frame_num_allowed_flag to true will avoid this problem.

1. Set gaps_in_frame_num_allowed_flag true as default
2. call mpp_enc_cfg_set_u32(cfg, "h264:gaps_not_allowed", 1) if you
want gaps_in_frame_num_allowed_flag to be false.

Change-Id: I8242fb318e051a61772c02a2c8bb59e4b589ff6d
Signed-off-by: Johnson Ding <johnson.ding@rock-chips.com>
2021-01-15 16:40:48 +08:00
sayon.chen
816f1a4f7d [rc_v2]: Add debreath cfg interface
Change-Id: Id8a729dc35e1b4fd2c9d3eab95d902bd5d7d96f2
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
2021-01-15 14:55:14 +08:00
Herman Chen
f04fabc136 [mpp_enc_cfg]: Add global rc qp config
1. Add rc:qp config for user rate control config at frame level.
2. Add hw:qp config for hardware detail config.

NOTE: hardware config is only recommended for expert developer.

Change-Id: I8e28de97304577bcf77d67521f945355779ae102
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
2021-01-08 16:26:53 +08:00
Herman Chen
4aa5b4a046 [mpp_enc]: Restore max_qp_step
1. Restore max_qp_step which limit the qp change between two frames.
2. Set default H.265 ip_qp_delta to 5.

Change-Id: Iacd795da7f2df46e60ab3f5c45bc8b0f30aff5a5
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
2020-12-31 18:03:17 +08:00
Yandong Lin
2111a438c5 [mpp_enc]: Update osd data cfg
1. Add new structure: MppEncOSDData2
2. Different osd layer use separate buffer

Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I3be533eb602f23192086f56e06a1439dbb19c35c
2020-12-31 10:00:13 +08:00
Herman Chen
de8ace6622 [mpp_enc]: Separate qp change flag
Separate H.264 QP limit change flag into 3 flags

Change-Id: I658ab337569f8f715bde7633dce02b631a7d4239
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
2020-12-17 14:33:17 +08:00