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[mpeg4]: fix bug: add marco MPP_DIV for division

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tips: in mpeg4,the divisor named time_pp is likely to be 0.

Change-Id: If9c055cb03139e819fe901009024e3ad4bbe79a5
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
This commit is contained in:
Ding Wei
2018-08-30 08:58:33 +08:00
parent f7938a8746
commit fc1e2256b7
3 changed files with 8 additions and 6 deletions
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6
mpp/hal/vpu/mpg4d/hal_m4vd_vdpu1.c
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@@ -134,9 +134,9 @@ static void vdpu1_mpg4d_setup_regs_by_syntax(hal_mpg4_ctx *ctx, MppSyntax syntax
RK_U32 time_bp = pp->time_bp;
RK_U32 time_pp = pp->time_pp;
RK_U32 trb_per_trd_d0 = ((((RK_S64)(1 * time_bp + 0)) << 27) + 1 * (time_pp - 1)) / time_pp;
RK_U32 trb_per_trd_d1 = ((((RK_S64)(2 * time_bp + 1)) << 27) + 2 * (time_pp - 0)) / (2 * time_pp + 1);
RK_U32 trb_per_trd_dm1 = ((((RK_S64)(2 * time_bp - 1)) << 27) + 2 * (time_pp - 1)) / (2 * time_pp - 1);
RK_U32 trb_per_trd_d0 = MPP_DIV((((RK_S64)(1 * time_bp + 0)) << 27) + 1 * (time_pp - 1), time_pp);
RK_U32 trb_per_trd_d1 = MPP_DIV((((RK_S64)(2 * time_bp + 1)) << 27) + 2 * (time_pp - 0), 2 * time_pp + 1);
RK_U32 trb_per_trd_dm1 = MPP_DIV((((RK_S64)(2 * time_bp - 1)) << 27) + 2 * (time_pp - 1), 2 * time_pp - 1);
regs->SwReg03.sw_pic_b_e = 1;
regs->SwReg03.sw_pic_inter_e = 1;

6
mpp/hal/vpu/mpg4d/hal_m4vd_vdpu2.c
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@@ -132,9 +132,9 @@ static void vdpu2_mpg4d_setup_regs_by_syntax(hal_mpg4_ctx *ctx, MppSyntax syntax
RK_U32 time_bp = pp->time_bp;
RK_U32 time_pp = pp->time_pp;
RK_U32 trb_per_trd_d0 = ((((RK_S64)(1 * time_bp + 0)) << 27) + 1 * (time_pp - 1)) / time_pp;
RK_U32 trb_per_trd_d1 = ((((RK_S64)(2 * time_bp + 1)) << 27) + 2 * (time_pp - 0)) / (2 * time_pp + 1);
RK_U32 trb_per_trd_dm1 = ((((RK_S64)(2 * time_bp - 1)) << 27) + 2 * (time_pp - 1)) / (2 * time_pp - 1);
RK_U32 trb_per_trd_d0 = MPP_DIV((((RK_S64)(1 * time_bp + 0)) << 27) + 1 * (time_pp - 1), time_pp);
RK_U32 trb_per_trd_d1 = MPP_DIV((((RK_S64)(2 * time_bp + 1)) << 27) + 2 * (time_pp - 0), 2 * time_pp + 1);
RK_U32 trb_per_trd_dm1 = MPP_DIV((((RK_S64)(2 * time_bp - 1)) << 27) + 2 * (time_pp - 1), 2 * time_pp - 1);
regs->reg57_enable_ctrl.sw_pic_type_sel1 = 1;
regs->reg57_enable_ctrl.sw_pic_type_sel0 = 1;

2
osal/inc/mpp_common.h
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@@ -31,6 +31,8 @@
#define MPP_MIN3(a,b,c) MPP_MIN(MPP_MIN(a,b),c)
#define MPP_MIN4(a, b, c, d) MPP_MIN((a), MPP_MIN3((b), (c), (d)))
#define MPP_DIV(a, b) ((b) ? (a) / (b) : (a))
#define MPP_SWAP(type, a, b) do {type SWAP_tmp = b; b = a; a = SWAP_tmp;} while(0)
#define MPP_ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0]))
#define MPP_ALIGN(x, a) (((x)+(a)-1)&~((a)-1))