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fix[vp9d]: Fix AFBC to non-FBC mode switch issue

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When vp9 decoder switches from FBC mode to non-FBC mode it requires
resetting the alignment function in buf_slot.

Change-Id: I0c3e35e2c573d003192a2a82d9bdd9c30f42088c
Signed-off-by: Hery Xu <hery.xu@rock-chips.com>
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
This commit is contained in:
Hery Xu
2023-10-09 10:09:43 +08:00
committed by Herman Chen
parent 45fff92423
commit f377c2ae70
3 changed files with 19 additions and 9 deletions
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16
mpp/codec/dec/vp9/vp9d_parser.c
View File

@@ -382,11 +382,6 @@ MPP_RET vp9d_parser_deinit(Vp9CodecContext *vp9_ctx)
return MPP_OK; return MPP_OK;
} }
static RK_U32 hor_align_64(RK_U32 val)
{
return MPP_ALIGN(val, 64);
}
static RK_S32 vp9_alloc_frame(Vp9CodecContext *ctx, VP9Frame *frame) static RK_S32 vp9_alloc_frame(Vp9CodecContext *ctx, VP9Frame *frame)
{ {
VP9Context *s = ctx->priv_data; VP9Context *s = ctx->priv_data;
@@ -403,17 +398,20 @@ static RK_S32 vp9_alloc_frame(Vp9CodecContext *ctx, VP9Frame *frame)
mpp_frame_set_poc(frame->f, s->cur_poc); mpp_frame_set_poc(frame->f, s->cur_poc);
if (MPP_FRAME_FMT_IS_FBC(s->cfg->base.out_fmt)) { if (MPP_FRAME_FMT_IS_FBC(s->cfg->base.out_fmt)) {
RK_U32 fbc_hdr_stride = MPP_ALIGN(ctx->width, 64); RK_U32 fbc_hdr_stride = mpp_align_64(ctx->width);
mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, hor_align_64); mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, mpp_align_64);
mpp_frame_set_fmt(frame->f, ctx->pix_fmt | ((s->cfg->base.out_fmt & (MPP_FRAME_FBC_MASK)))); mpp_frame_set_fmt(frame->f, ctx->pix_fmt | ((s->cfg->base.out_fmt & (MPP_FRAME_FBC_MASK))));
if (*compat_ext_fbc_hdr_256_odd) if (*compat_ext_fbc_hdr_256_odd)
fbc_hdr_stride = MPP_ALIGN(ctx->width, 256) | 256; fbc_hdr_stride = mpp_align_256_odd(ctx->width);
mpp_frame_set_fbc_hdr_stride(frame->f, fbc_hdr_stride); mpp_frame_set_fbc_hdr_stride(frame->f, fbc_hdr_stride);
} else } else {
mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, mpp_align_256_odd);
mpp_slots_set_prop(s->slots, SLOTS_VER_ALIGN, mpp_align_64);
mpp_frame_set_fmt(frame->f, ctx->pix_fmt); mpp_frame_set_fmt(frame->f, ctx->pix_fmt);
}
if (s->cfg->base.enable_thumbnail && s->hw_info->cap_down_scale) if (s->cfg->base.enable_thumbnail && s->hw_info->cap_down_scale)
mpp_frame_set_thumbnail_en(frame->f, 1); mpp_frame_set_thumbnail_en(frame->f, 1);

2
osal/inc/mpp_common.h
View File

@@ -213,6 +213,8 @@ static __inline RK_U32 mpp_is_32bit()
RK_S32 axb_div_c(RK_S32 a, RK_S32 b, RK_S32 c); RK_S32 axb_div_c(RK_S32 a, RK_S32 b, RK_S32 c);
RK_U32 mpp_align_16(RK_U32 val); RK_U32 mpp_align_16(RK_U32 val);
RK_U32 mpp_align_64(RK_U32 val); RK_U32 mpp_align_64(RK_U32 val);
RK_U32 mpp_align_128(RK_U32 val);
RK_U32 mpp_align_256_odd(RK_U32 val);
#ifdef __cplusplus #ifdef __cplusplus
} }

10
osal/mpp_common.cpp
View File

@@ -116,3 +116,13 @@ RK_U32 mpp_align_64(RK_U32 val)
{ {
return MPP_ALIGN(val, 64); return MPP_ALIGN(val, 64);
} }
RK_U32 mpp_align_128(RK_U32 val)
{
return MPP_ALIGN(val, 128);
}
RK_U32 mpp_align_256_odd(RK_U32 val)
{
return MPP_ALIGN(val, 256) | 256;
}