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[hal_rkdec] add vdpu382 support

Browse Source 
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Change-Id: Ifcb1d35ceb41c3ca90bbfe482025c2147bff268e
This commit is contained in:
Chandler Chen
2022-11-15 14:03:04 +08:00
committed by Herman Chen
parent 4273d26af3
commit e96dc75dd1
24 changed files with 6492 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
mpp/hal/rkdec/CMakeLists.txt
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@@ -1,7 +1,7 @@
# vim: syntax=cmake
include_directories(inc)
add_library(vdpu34x_com STATIC vdpu34x_com.c)
add_library(vdpu34x_com STATIC vdpu34x_com.c vdpu382_com.c)
if( HAVE_AVSD )
add_subdirectory(avsd)

1
mpp/hal/rkdec/avs2d/CMakeLists.txt
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@@ -13,6 +13,7 @@ set(HAL_AVS2D_HDR
# hal avs2 decoder sourse
set(HAL_AVS2D_SRC
hal_avs2d_rkv.c
hal_avs2d_vdpu382.c
hal_avs2d_api.c
)

23
mpp/hal/rkdec/avs2d/hal_avs2d_api.c
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@@ -31,6 +31,7 @@
#include "hal_avs2d_api.h"
#include "hal_avs2d_rkv.h"
#include "hal_avs2d_vdpu382.h"
RK_U32 avs2d_hal_debug = 0;
@@ -81,12 +82,24 @@ MPP_RET hal_avs2d_init(void *hal, MppHalCfg *cfg)
p_hal = (Avs2dHalCtx_t *)hal;
memset(p_hal, 0, sizeof(Avs2dHalCtx_t));
RK_U32 hw_id = mpp_get_client_hw_id(VPU_CLIENT_RKVDEC);
p_api = &p_hal->hal_api;
p_api->init = hal_avs2d_rkv_init;
p_api->deinit = hal_avs2d_rkv_deinit;
p_api->reg_gen = hal_avs2d_rkv_gen_regs;
p_api->start = hal_avs2d_rkv_start;
p_api->wait = hal_avs2d_rkv_wait;
if (hw_id == HWID_VDPU382) {
p_api->init = hal_avs2d_vdpu382_init;
p_api->deinit = hal_avs2d_vdpu382_deinit;
p_api->reg_gen = hal_avs2d_vdpu382_gen_regs;
p_api->start = hal_avs2d_vdpu382_start;
p_api->wait = hal_avs2d_vdpu382_wait;
} else {
p_api->init = hal_avs2d_rkv_init;
p_api->deinit = hal_avs2d_rkv_deinit;
p_api->reg_gen = hal_avs2d_rkv_gen_regs;
p_api->start = hal_avs2d_rkv_start;
p_api->wait = hal_avs2d_rkv_wait;
}
p_api->reset = NULL;
p_api->flush = NULL;
p_api->control = NULL;

1109
mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c Normal file
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44
mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.h Normal file
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@@ -0,0 +1,44 @@
/*
* Copyright 2022 Rockchip Electronics Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __HAL_AVS2D_VDPU382_H__
#define __HAL_AVS2D_VDPU382_H__
#include "mpp_device.h"
#include "parser_api.h"
#include "hal_avs2d_api.h"
#include "hal_avs2d_global.h"
#include "avs2d_syntax.h"
#include "vdpu382.h"
#define AVS2D_REGISTERS (278)
#ifdef __cplusplus
extern "C" {
#endif
MPP_RET hal_avs2d_vdpu382_init (void *hal, MppHalCfg *cfg);
MPP_RET hal_avs2d_vdpu382_deinit (void *hal);
MPP_RET hal_avs2d_vdpu382_gen_regs(void *hal, HalTaskInfo *task);
MPP_RET hal_avs2d_vdpu382_start (void *hal, HalTaskInfo *task);
MPP_RET hal_avs2d_vdpu382_wait (void *hal, HalTaskInfo *task);
#ifdef __cplusplus
}
#endif
#endif /*__HAL_AVS2D_VDPU382_H__*/

1
mpp/hal/rkdec/h264d/CMakeLists.txt
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@@ -4,6 +4,7 @@
set(HAL_H264D_SRC
hal_h264d_api.c
hal_h264d_vdpu34x.c
hal_h264d_vdpu382.c
hal_h264d_rkv_reg.c
hal_h264d_vdpu2.c
hal_h264d_vdpu1.c

12
mpp/hal/rkdec/h264d/hal_h264d_api.c
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@@ -38,6 +38,7 @@
#include "hal_h264d_rkv_reg.h"
#include "hal_h264d_vdpu34x.h"
#include "hal_h264d_vdpu382.h"
#include "hal_h264d_vdpu2.h"
#include "hal_h264d_vdpu1.h"
@@ -133,7 +134,16 @@ MPP_RET hal_h264d_init(void *hal, MppHalCfg *cfg)
case VPU_CLIENT_RKVDEC : {
RK_U32 hw_id = mpp_get_client_hw_id(client_type);
if (hw_id == HWID_VDPU34X || hw_id == HWID_VDPU38X) {
if (hw_id == HWID_VDPU382) {
p_api->init = vdpu382_h264d_init;
p_api->deinit = vdpu382_h264d_deinit;
p_api->reg_gen = vdpu382_h264d_gen_regs;
p_api->start = vdpu382_h264d_start;
p_api->wait = vdpu382_h264d_wait;
p_api->reset = vdpu382_h264d_reset;
p_api->flush = vdpu382_h264d_flush;
p_api->control = vdpu382_h264d_control;
} else if (hw_id == HWID_VDPU34X || hw_id == HWID_VDPU38X) {
p_api->init = vdpu34x_h264d_init;
p_api->deinit = vdpu34x_h264d_deinit;
p_api->reg_gen = vdpu34x_h264d_gen_regs;

1230
mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c Normal file
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40
mpp/hal/rkdec/h264d/hal_h264d_vdpu382.h Normal file
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@@ -0,0 +1,40 @@
/*
* Copyright 2022 Rockchip Electronics Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __HAL_H264D_VDPU382_H__
#define __HAL_H264D_VDPU382_H__
#include "mpp_hal.h"
#include "vdpu382.h"
#ifdef __cplusplus
extern "C" {
#endif
MPP_RET vdpu382_h264d_init (void *hal, MppHalCfg *cfg);
MPP_RET vdpu382_h264d_deinit (void *hal);
MPP_RET vdpu382_h264d_gen_regs(void *hal, HalTaskInfo *task);
MPP_RET vdpu382_h264d_start (void *hal, HalTaskInfo *task);
MPP_RET vdpu382_h264d_wait (void *hal, HalTaskInfo *task);
MPP_RET vdpu382_h264d_reset (void *hal);
MPP_RET vdpu382_h264d_flush (void *hal);
MPP_RET vdpu382_h264d_control (void *hal, MpiCmd cmd_type, void *param);
#ifdef __cplusplus
}
#endif
#endif /* __HAL_H264D_VDPU382_H__ */

1
mpp/hal/rkdec/h265d/CMakeLists.txt
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@@ -6,6 +6,7 @@ set(HAL_H265D_SRC
hal_h265d_com.c
hal_h265d_rkv.c
hal_h265d_vdpu34x.c
hal_h265d_vdpu382.c
)
add_library(${HAL_H265D} STATIC ${HAL_H265D_SRC})

5
mpp/hal/rkdec/h265d/hal_h265d_api.c
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@@ -27,6 +27,7 @@
#include "hal_h265d_api.h"
#include "hal_h265d_rkv.h"
#include "hal_h265d_vdpu34x.h"
#include "hal_h265d_vdpu382.h"
RK_U32 hal_h265d_debug = 0;
@@ -58,7 +59,9 @@ MPP_RET hal_h265d_init(void *ctx, MppHalCfg *cfg)
p->is_v34x = (hw_id == HWID_VDPU34X || hw_id == HWID_VDPU38X);
p->client_type = client_type;
if (p->is_v34x)
if (hw_id == HWID_VDPU382)
p->api = &hal_h265d_vdpu382;
else if (p->is_v34x)
p->api = &hal_h265d_vdpu34x;
else
p->api = &hal_h265d_rkv;

1182
mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c Normal file
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33
mpp/hal/rkdec/h265d/hal_h265d_vdpu382.h Normal file
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@@ -0,0 +1,33 @@
/*
* Copyright 2022 Rockchip Electronics Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __HAL_H265D_VDPU382_H__
#define __HAL_H265D_VDPU382_H__
#include "mpp_hal.h"
#include "vdpu382.h"
#ifdef __cplusplus
extern "C" {
#endif
extern const MppHalApi hal_h265d_vdpu382;
#ifdef __cplusplus
}
#endif
#endif /* __HAL_H265D_VDPU382_H__ */

22
mpp/hal/rkdec/inc/vdpu382.h Normal file
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@@ -0,0 +1,22 @@
/*
* Copyright 2022 Rockchip Electronics Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __VDPU382_H__
#define __VDPU382_H__
#define HWID_VDPU382 (0x20220601)
#endif /* __VDPU382_H__ */

152
mpp/hal/rkdec/inc/vdpu382_avs2d.h Normal file
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@@ -0,0 +1,152 @@
/*
* Copyright 2022 Rockchip Electronics Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __VDPU382_AVS2D_H__
#define __VDPU382_AVS2D_H__
#include "vdpu382_com.h"
typedef struct Vdpu382RegAvs2dParam_t {
struct SWREG64_H26X_SET {
RK_U32 h26x_frame_orslice : 1;
RK_U32 h26x_rps_mode : 1;
RK_U32 h26x_stream_mode : 1;
RK_U32 h26x_stream_lastpacket : 1;
RK_U32 h264_firstslice_flag : 1;
RK_U32 reserve : 27;
} reg64;
RK_U32 reg65_cur_top_poc;
RK_U32 reg66_cur_bot_poc;
RK_U32 reg67_098_ref_poc[32];
struct SWREG99_AVS2_REF0_3_INFO {
RK_U32 ref0_field : 1;
RK_U32 : 1;
RK_U32 ref0_botfield_used : 1;
RK_U32 ref0_valid_flag : 1;
RK_U32 : 4;
RK_U32 ref1_field : 1;
RK_U32 : 1;
RK_U32 ref1_botfield_used : 1;
RK_U32 ref1_valid_flag : 1;
RK_U32 : 4;
RK_U32 ref2_field : 1;
RK_U32 : 1;
RK_U32 ref2_botfield_used : 1;
RK_U32 ref2_valid_flag : 1;
RK_U32 : 4;
RK_U32 ref3_field : 1;
RK_U32 : 1;
RK_U32 ref3_botfield_used : 1;
RK_U32 ref3_valid_flag : 1;
RK_U32 : 4;
} reg99;
struct SWREG100_AVS2_REF4_7_INFO {
RK_U32 ref4_field : 1;
RK_U32 : 1;
RK_U32 ref4_botfield_used : 1;
RK_U32 ref4_valid_flag : 1;
RK_U32 : 4;
RK_U32 ref5_field : 1;
RK_U32 : 1;
RK_U32 ref5_botfield_used : 1;
RK_U32 ref5_valid_flag : 1;
RK_U32 : 4;
RK_U32 ref6_field : 1;
RK_U32 : 1;
RK_U32 ref6_botfield_used : 1;
RK_U32 ref6_valid_flag : 1;
RK_U32 : 4;
RK_U32 ref7_field : 1;
RK_U32 : 1;
RK_U32 ref7_botfield_used : 1;
RK_U32 ref7_valid_flag : 1;
RK_U32 : 4;
} reg100;
RK_U32 reg101_102[2];
struct SW103_CTRL_EXTRA {
// 0 : use default 255, 1 : use fixed 256
RK_U32 slice_hor_pos_ctrl : 1;
RK_U32 : 31;
} reg103;
RK_U32 reg104;
struct SW105_HEAD_LEN {
RK_U32 head_len : 4;
RK_U32 count_update_en : 1;
RK_U32 : 27;
} reg105;
RK_U32 reg106_111[6];
struct SW112_ERROR_REF_INFO {
// 0 : Frame, 1 : field
RK_U32 ref_error_field : 1;
/**
* @brief Refer error is top field flag.
* 0 : Bottom field flag,
* 1 : Top field flag.
*/
RK_U32 ref_error_topfield : 1;
// For inter, 0 : top field is no used, 1 : top field is used.
RK_U32 ref_error_topfield_used : 1;
// For inter, 0 : bottom field is no used, 1 : bottom field is used.
RK_U32 ref_error_botfield_used : 1;
RK_U32 : 28;
} reg112;
} Vdpu382RegAvs2dParam;
typedef struct Vdpu382RegAvs2dAddr_t {
/* SWREG160 */
RK_U32 reg160_no_use;
/* SWREG161 */
RK_U32 head_base;
/* SWREG162 */
RK_U32 reg162_no_use;
/* SWREG163 */
RK_U32 rps_base;
/* SWREG164~179 */
RK_U32 ref_base[16];
/* SWREG180 */
RK_U32 scanlist_addr;
/* SWREG181~196 */
RK_U32 colmv_base[16];
/* SWREG197 */
RK_U32 cabactbl_base;
} Vdpu382RegAvs2dAddr;
typedef struct Vdpu382Avs2dRegSet_t {
Vdpu382RegCommon common;
Vdpu382RegAvs2dParam avs2d_param;
Vdpu382RegCommonAddr common_addr;
Vdpu382RegAvs2dAddr avs2d_addr;
Vdpu382RegIrqStatus irq_status;
Vdpu382RegStatistic statistic;
} Vdpu382Avs2dRegSet;
#endif /*__VDPU382_AVS2D_H__*/

544
mpp/hal/rkdec/inc/vdpu382_com.h Normal file
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@@ -0,0 +1,544 @@
/*
* Copyright 2022 Rockchip Electronics Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __VDPU382_COM_H__
#define __VDPU382_COM_H__
#include "mpp_device.h"
#include "mpp_buf_slot.h"
#include "vdpu382.h"
#define OFFSET_COMMON_REGS (8 * sizeof(RK_U32))
#define OFFSET_CODEC_PARAMS_REGS (64 * sizeof(RK_U32))
#define OFFSET_COMMON_ADDR_REGS (128 * sizeof(RK_U32))
#define OFFSET_CODEC_ADDR_REGS (160 * sizeof(RK_U32))
#define OFFSET_POC_HIGHBIT_REGS (200 * sizeof(RK_U32))
#define OFFSET_INTERRUPT_REGS (224 * sizeof(RK_U32))
#define OFFSET_STATISTIC_REGS (256 * sizeof(RK_U32))
#define RCB_ALLINE_SIZE (64)
#define MPP_RCB_BYTES(bits) MPP_ALIGN((bits + 7) / 8, RCB_ALLINE_SIZE)
typedef enum Vdpu382_RCB_TYPE_E {
RCB_DBLK_ROW,
RCB_INTRA_ROW,
RCB_TRANSD_ROW,
RCB_STRMD_ROW,
RCB_INTER_ROW,
RCB_SAO_ROW,
RCB_FBC_ROW,
RCB_TRANSD_COL,
RCB_INTER_COL,
RCB_FILT_COL,
RCB_BUF_COUNT,
} Vdpu382RcbType_e;
/* base: OFFSET_COMMON_REGS */
typedef struct Vdpu382RegCommon_t {
struct SWREG8_IN_OUT {
RK_U32 in_endian : 1;
RK_U32 in_swap32_e : 1;
RK_U32 in_swap64_e : 1;
RK_U32 str_endian : 1;
RK_U32 str_swap32_e : 1;
RK_U32 str_swap64_e : 1;
RK_U32 out_endian : 1;
RK_U32 out_swap32_e : 1;
RK_U32 out_cbcr_swap : 1;
RK_U32 out_swap64_e : 1;
RK_U32 reserve : 22;
} reg008;
struct SWREG9_DEC_MODE {
RK_U32 dec_mode : 10;
RK_U32 reserve : 22;
} reg009;
struct SWREG10_DEC_E {
RK_U32 dec_e : 1;
RK_U32 reserve : 31;
} reg010;
struct SWREG11_IMPORTANT_EN {
RK_U32 reserver : 1;
RK_U32 dec_clkgate_e : 1;
RK_U32 reserve1 : 2;
RK_U32 dec_irq_dis : 1;
RK_U32 dec_line_irq_dis : 1; //change to reg205[9]
RK_U32 buf_empty_en : 1;
RK_U32 reserve2 : 1;
RK_U32 dec_line_irq_en : 1;
RK_U32 reserve3 : 1;
RK_U32 dec_e_rewrite_valid : 1;
RK_U32 reserve4 : 9;
RK_U32 softrst_en_p : 1;
RK_U32 reserve5 : 1; //change to reg205[0]
RK_U32 err_head_fill_e : 1;
RK_U32 err_colmv_fill_e : 1;
RK_U32 pix_range_detection_e : 1;
RK_U32 reserve6 : 3;
RK_U32 wlast_match_fail : 1;
RK_U32 mmu_wlast_match_fail : 1;
RK_U32 reserve7 : 2;
} reg011;
struct SWREG12_SENCODARY_EN {
RK_U32 wr_ddr_align_en : 1;
RK_U32 colmv_compress_en : 1;
RK_U32 fbc_e : 1;
RK_U32 tile_e : 1;
RK_U32 reserve1 : 1;
RK_U32 error_info_en : 1;
RK_U32 info_collect_en : 1;
RK_U32 reserve2 : 1; //change to reg205[4]
RK_U32 scanlist_addr_valid_en : 1;
RK_U32 scale_down_en : 1;
RK_U32 reserve3 : 22;
} reg012;
struct SWREG13_EN_MODE_SET {
RK_U32 reserve0 : 1;
RK_U32 req_timeout_rst_sel : 1;
RK_U32 reserve1 : 1;
RK_U32 dec_commonirq_mode : 1;
RK_U32 reserve2 : 2;
RK_U32 stmerror_waitdecfifo_empty : 1;
RK_U32 reserve3 : 1;
RK_U32 strmd_zero_rm_en : 1;
RK_U32 reserve4 : 3;
RK_U32 allow_not_wr_unref_bframe : 1;
RK_U32 fbc_output_wr_disable : 1;
RK_U32 reserve5 : 4;
RK_U32 h26x_error_mode : 1;
RK_U32 reserve6 : 5;
RK_U32 cur_pic_is_idr : 1;
RK_U32 reserve8 : 6; //change to reg205[5]
RK_U32 filter_outbuf_mode : 1;
/* develop branch */
// RK_U32 reserve5 : 2;
// RK_U32 h26x_error_mode : 1;
// RK_U32 reserve6 : 2;
// RK_U32 ycacherd_prior : 1;
// RK_U32 reserve7 : 2;
// RK_U32 cur_pic_is_idr : 1;
// RK_U32 reserve8 : 1;
// RK_U32 right_auto_rst_disable : 1;
// RK_U32 frame_end_err_rst_flag : 1;
// RK_U32 rd_prior_mode : 1;
// RK_U32 rd_ctrl_prior_mode : 1;
// RK_U32 reserved9 : 1;
// RK_U32 filter_outbuf_mode : 1;
} reg013;
struct SWREG14_FBC_PARAM_SET {
RK_U32 fbc_force_uncompress : 1;
RK_U32 reserve0 : 2;
RK_U32 allow_16x8_cp_flag : 1;
RK_U32 reserve1 : 2;
RK_U32 fbc_h264_exten_4or8_flag: 1;
RK_U32 reserve2 : 25;
} reg014;
struct SWREG15_STREAM_PARAM_SET {
RK_U32 rlc_mode_direct_write : 1;
RK_U32 rlc_mode : 1;
RK_U32 strmd_ofifo_perf_opt_en : 1;
RK_U32 reserve0 : 2;
RK_U32 strm_start_bit : 7;
RK_U32 reserve1 : 20;
} reg015;
RK_U32 reg016_str_len;
struct SWREG17_SLICE_NUMBER {
RK_U32 slice_num : 25;
RK_U32 reserve : 7;
} reg017;
struct SWREG18_Y_HOR_STRIDE {
RK_U32 y_hor_virstride : 16;
RK_U32 reserve : 16;
} reg018;
struct SWREG19_UV_HOR_STRIDE {
RK_U32 uv_hor_virstride : 16;
RK_U32 reserve : 16;
} reg019;
union {
struct SWREG20_Y_STRIDE {
RK_U32 y_virstride : 28;
RK_U32 reserve : 4;
} reg020_y_virstride;
struct SWREG20_FBC_PAYLOAD_OFFSET {
RK_U32 reserve : 4;
RK_U32 payload_st_offset : 28;
} reg020_fbc_payload_off;
};
struct SWREG21_ERROR_CTRL_SET {
RK_U32 inter_error_prc_mode : 1;
RK_U32 error_intra_mode : 1;
RK_U32 error_deb_en : 1;
RK_U32 picidx_replace : 5;
RK_U32 error_spread_e : 1;
RK_U32 : 3;
RK_U32 error_inter_pred_cross_slice : 1;
RK_U32 reserve0 : 11;
RK_U32 roi_error_ctu_cal_en : 1;
RK_U32 reserve1 : 7;
} reg021;
struct SWREG22_ERR_ROI_CTU_OFFSET_START {
RK_U32 roi_x_ctu_offset_st : 12;
RK_U32 reserve0 : 4;
RK_U32 roi_y_ctu_offset_st : 12;
RK_U32 reserve1 : 4;
} reg022;
struct SWREG23_ERR_ROI_CTU_OFFSET_END {
RK_U32 roi_x_ctu_offset_end : 12;
RK_U32 reserve0 : 4;
RK_U32 roi_y_ctu_offset_end : 12;
RK_U32 reserve1 : 4;
} reg023;
struct SWREG24_CABAC_ERROR_EN_LOWBITS {
RK_U32 cabac_err_en_lowbits : 32;
} reg024;
struct SWREG25_CABAC_ERROR_EN_HIGHBITS {
RK_U32 cabac_err_en_highbits : 30;
RK_U32 reserve : 2;
} reg025;
struct SWREG26_BLOCK_GATING_EN {
RK_U32 swreg_block_gating_e : 20;
RK_U32 reserve : 11;
RK_U32 reg_cfg_gating_en : 1;
} reg026;
/* NOTE: reg027 ~ reg032 are added in vdpu38x at rk3588 */
struct SW027_CORE_SAFE_PIXELS {
// colmv and recon report coord x safe pixels
RK_U32 core_safe_x_pixels : 16;
// colmv and recon report coord y safe pixels
RK_U32 core_safe_y_pixels : 16;
} reg027;
struct SWREG28_MULTIPLY_CORE_CTRL {
RK_U32 swreg_vp9_wr_prob_idx : 3;
RK_U32 reserve0 : 1;
RK_U32 swreg_vp9_rd_prob_idx : 3;
RK_U32 reserve1 : 1;
RK_U32 swreg_ref_req_advance_flag : 1;
RK_U32 sw_colmv_req_advance_flag : 1;
RK_U32 sw_poc_only_highbit_flag : 1;
RK_U32 sw_poc_arb_flag : 1;
RK_U32 reserve2 : 4;
RK_U32 sw_film_idx : 10;
RK_U32 reserve3 : 2;
RK_U32 sw_pu_req_mismatch_dis : 1;
RK_U32 sw_colmv_req_mismatch_dis : 1;
RK_U32 reserve4 : 2;
} reg028;
struct SWREG29_SCALE_DOWN_CTRL {
RK_U32 scale_down_y_wratio : 5;
RK_U32 reserve0 : 3;
RK_U32 scale_down_y_hratio : 5;
RK_U32 reserve1 : 3;
RK_U32 scale_down_c_wratio : 5;
RK_U32 reserve2 : 3;
RK_U32 scale_down_c_hratio : 5;
RK_U32 reserve3 : 1;
RK_U32 scale_down_roi_mode : 1;
RK_U32 scale_down_tile_mode : 1;
} reg029;
struct SW032_Y_SCALE_DOWN_TILE8x8_HOR_STRIDE {
RK_U32 y_scale_down_hor_stride : 20;
RK_U32 : 12;
} reg030;
struct SW031_UV_SCALE_DOWN_TILE8x8_HOR_STRIDE {
RK_U32 uv_scale_down_hor_stride : 20;
RK_U32 : 12;
} reg031;
/* NOTE: reg027 ~ reg032 are added in vdpu38x at rk3588 */
/* NOTE: timeout must be config in vdpu38x */
RK_U32 reg032_timeout_threshold;
} Vdpu382RegCommon;
/* base: OFFSET_COMMON_ADDR_REGS */
typedef struct Vdpu382RegCommonAddr_t {
/* offset 128 */
RK_U32 reg128_rlc_base;
RK_U32 reg129_rlcwrite_base;
RK_U32 reg130_decout_base;
RK_U32 reg131_colmv_cur_base;
RK_U32 reg132_error_ref_base;
RK_U32 reg133_rcb_intra_base;
RK_U32 reg134_rcb_transd_row_base;
RK_U32 reg135_rcb_transd_col_base;
RK_U32 reg136_rcb_streamd_row_base;
RK_U32 reg137_rcb_inter_row_base;
RK_U32 reg138_rcb_inter_col_base;
RK_U32 reg139_rcb_dblk_base;
RK_U32 reg140_rcb_sao_base;
RK_U32 reg141_rcb_fbc_base;
RK_U32 reg142_rcb_filter_col_base;
} Vdpu382RegCommonAddr;
/* base: OFFSET_COMMON_ADDR_REGS */
typedef struct Vdpu382RegIrqStatus_t {
struct SWREG224_STA_INT {
RK_U32 dec_irq : 1;
RK_U32 dec_irq_raw : 1;
RK_U32 dec_rdy_sta : 1;
RK_U32 dec_bus_sta : 1;
RK_U32 dec_error_sta : 1;
RK_U32 dec_timeout_sta : 1;
RK_U32 buf_empty_sta : 1;
RK_U32 colmv_ref_error_sta : 1;
RK_U32 cabu_end_sta : 1;
RK_U32 softreset_rdy : 1;
RK_U32 dec_line_irq : 1;
RK_U32 dec_line_irq_raw : 1;
RK_U32 ltb_pause_sta : 1;
RK_U32 mmureset_rdy : 1;
RK_U32 ltb_end_sta : 1;
RK_U32 reserve : 17;
} reg224;
struct SWREG225_STA_ERR_INFO {
RK_U32 all_frame_error_flag : 1;
RK_U32 strmd_detect_error_flag : 1;
RK_U32 reserve : 30;
} reg225;
struct SWREG226_STA_CABAC_ERROR_STATUS {
RK_U32 strmd_error_status : 28;
RK_U32 reserve : 4;
} reg226;
struct SWREG227_STA_COLMV_ERROR_REF_PICIDX {
RK_U32 colmv_error_ref_picidx : 4;
RK_U32 reserve : 28;
} reg227;
struct SWREG228_STA_CABAC_ERROR_CTU_OFFSET {
RK_U32 cabac_error_ctu_offset_x : 12;
RK_U32 : 4;
RK_U32 cabac_error_ctu_offset_y : 12;
RK_U32 : 4;
} reg228;
struct SWREG229_STA_SAOWR_CTU_OFFSET {
RK_U32 saowr_xoffset : 16;
RK_U32 saowr_yoffset : 16;
} reg229;
struct SWREG230_STA_SLICE_DEC_NUM {
RK_U32 slicedec_num : 25;
RK_U32 reserve : 7;
} reg230;
struct SWREG231_STA_FRAME_ERROR_CTU_NUM {
RK_U32 frame_ctu_err_num : 32;
} reg231;
struct SWREG232_STA_ERROR_PACKET_NUM {
RK_U32 packet_err_num : 16;
RK_U32 reserve : 16;
} reg232;
struct SWREG233_STA_ERR_CTU_NUM_IN_RO {
RK_U32 error_ctu_num_in_roi : 24;
RK_U32 reserve : 8;
} reg233;
struct SWREG234_BUF_EMPTY_OFFSET {
RK_U32 coord_report_offset_x : 16;
RK_U32 coord_report_offset_y : 16;
} reg234;
struct SWREG235_COORD_REPORT_OUTBUF_HEIGHT {
RK_U32 coord_report_output_height : 16;
RK_U32 reserve : 16;
} reg235;
RK_U32 reserve_reg236_237[2];
} Vdpu382RegIrqStatus;
typedef struct Vdpu382RegStatistic_t {
struct SWREG256_DEBUG_PERF_LATENCY_CTRL0 {
RK_U32 axi_perf_work_e : 1;
RK_U32 axi_perf_clr_e : 1;
RK_U32 reserve0 : 1;
RK_U32 axi_cnt_type : 1;
RK_U32 rd_latency_id : 4;
RK_U32 rd_latency_thr : 12;
RK_U32 reserve1 : 12;
} reg256;
struct SWREG257_DEBUG_PERF_LATENCY_CTRL1 {
RK_U32 addr_align_type : 2;
RK_U32 ar_cnt_id_type : 1;
RK_U32 aw_cnt_id_type : 1;
RK_U32 ar_count_id : 4;
RK_U32 aw_count_id : 4;
RK_U32 rd_band_width_mode : 1;
RK_U32 reserve : 19;
} reg257;
struct SWREG258_DEBUG_PERF_RD_MAX_LATENCY_NUM {
RK_U32 rd_max_latency_num : 16;
RK_U32 reserve : 16;
} reg258;
RK_U32 reg259_rd_latency_thr_num_ch0;
RK_U32 reg260_rd_latency_acc_sum;
RK_U32 reg261_perf_rd_axi_total_byte;
RK_U32 reg262_perf_wr_axi_total_byte;
RK_U32 reg263_perf_working_cnt;
RK_U32 reserve_reg264;
struct SWREG265_DEBUG_PERF_SEL {
RK_U32 perf_cnt0_sel : 6;
RK_U32 reserve0 : 2;
RK_U32 perf_cnt1_sel : 6;
RK_U32 reserve1 : 2;
RK_U32 perf_cnt2_sel : 6;
RK_U32 reserve2 : 10;
} reg265;
RK_U32 reg266_perf_cnt0;
RK_U32 reg267_perf_cnt1;
RK_U32 reg268_perf_cnt2;
RK_U32 reserve_reg269;
struct SWREG270_DEBUG_QOS_CTRL {
RK_U32 bus2mc_buffer_qos_level : 8;
RK_U32 reserve0 : 8;
RK_U32 axi_rd_hurry_level : 2;
RK_U32 reserve1 : 2;
RK_U32 axi_wr_qos : 2;
RK_U32 reserve2 : 2;
RK_U32 axi_wr_hurry_level : 2;
RK_U32 reserve3 : 2;
RK_U32 axi_rd_qos : 2;
RK_U32 reserve4 : 2;
} reg270;
RK_U32 reg271_wr_wait_cycle_qos;
struct SWREG272_DEBUG_INT {
RK_U32 busidle_flag : 1;
RK_U32 reserved : 4;
RK_U32 mmu_busidle_flag : 1;
RK_U32 wr_tansfer_cnt : 8;
RK_U32 reserved1 : 2;
RK_U32 Sw_streamfifo_space2full : 7;
RK_U32 reserved2 : 1;
RK_U32 mmu_wr_transer_cnt : 8;
} reg272;
struct SWREG273 {
RK_U32 bus_status_flag : 19;
RK_U32 reserve0 : 12;
RK_U32 pps_no_ref_bframe_dec_r : 1;
} reg273;
RK_U16 reg274_y_min_value;
RK_U16 reg274_y_max_value;
RK_U16 reg275_u_min_value;
RK_U16 reg275_u_max_value;
RK_U16 reg276_v_min_value;
RK_U16 reg276_v_max_value;
struct SWREG277_ERROR_SPREAD_NUM {
RK_U32 err_spread_cnt_sum : 24;
RK_U32 : 8;
} reg277;
// RK_U32 reg277_err_spread_num;
// struct SWREG278_DEC_LINE_OFFSET_Y {
// RK_U32 dec_line_offset_y : 16;
// RK_U32 reserve : 16;
// } reg278;
} Vdpu382RegStatistic;
typedef struct vdpu382_rcb_info_t {
RK_S32 reg;
RK_S32 size;
RK_S32 offset;
} Vdpu382RcbInfo;
#ifdef __cplusplus
extern "C" {
#endif
RK_S32 vdpu382_get_rcb_buf_size(Vdpu382RcbInfo *info, RK_S32 width, RK_S32 height);
void vdpu382_setup_rcb(Vdpu382RegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu382RcbInfo *info);
RK_S32 vdpu382_compare_rcb_size(const void *a, const void *b);
void vdpu382_setup_statistic(Vdpu382RegCommon *com, Vdpu382RegStatistic *sta);
void vdpu382_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand);
#ifdef __cplusplus
}
#endif
#endif /* __VDPU382_COM_H__ */

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/*
* Copyright 2022 Rockchip Electronics Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __VDPU382_H264D_H__
#define __VDPU382_H264D_H__
#include "vdpu382_com.h"
/* base: OFFSET_CODEC_PARAMS_REGS */
typedef struct Vdpu382RegH264dParam_t {
struct SWREG64_H26X_SET {
RK_U32 h26x_frame_orslice : 1;
RK_U32 h26x_rps_mode : 1;
RK_U32 h26x_stream_mode : 1;
RK_U32 h26x_stream_lastpacket : 1;
RK_U32 h264_firstslice_flag : 1;
RK_U32 reserve : 27;
} reg64;
struct SWREG65_CUR_POC {
RK_U32 cur_top_poc : 32;
} reg65;
struct SWREG66_H264_CUR_POC1 {
RK_U32 cur_bot_poc : 32;
} reg66;
RK_U32 reg67_98_ref_poc[32];
struct SWREG99_H264_REG0_3_INFO {
RK_U32 ref0_field : 1;
RK_U32 ref0_topfield_used : 1;
RK_U32 ref0_botfield_used : 1;
RK_U32 ref0_colmv_use_flag : 1;
RK_U32 ref0_reserve : 4;
RK_U32 ref1_field : 1;
RK_U32 ref1_topfield_used : 1;
RK_U32 ref1_botfield_used : 1;
RK_U32 ref1_colmv_use_flag : 1;
RK_U32 ref1_reserve : 4;
RK_U32 ref2_field : 1;
RK_U32 ref2_topfield_used : 1;
RK_U32 ref2_botfield_used : 1;
RK_U32 ref2_colmv_use_flag : 1;
RK_U32 ref2_reserve : 4;
RK_U32 ref3_field : 1;
RK_U32 ref3_topfield_used : 1;
RK_U32 ref3_botfield_used : 1;
RK_U32 ref3_colmv_use_flag : 1;
RK_U32 ref3_reserve : 4;
} reg99;
struct SWREG100_H264_REG4_7_INFO {
RK_U32 ref4_field : 1;
RK_U32 ref4_topfield_used : 1;
RK_U32 ref4_botfield_used : 1;
RK_U32 ref4_colmv_use_flag : 1;
RK_U32 ref4_reserve : 4;
RK_U32 ref5_field : 1;
RK_U32 ref5_topfield_used : 1;
RK_U32 ref5_botfield_used : 1;
RK_U32 ref5_colmv_use_flag : 1;
RK_U32 ref5_reserve : 4;
RK_U32 ref6_field : 1;
RK_U32 ref6_topfield_used : 1;
RK_U32 ref6_botfield_used : 1;
RK_U32 ref6_colmv_use_flag : 1;
RK_U32 ref6_reserve : 4;
RK_U32 ref7_field : 1;
RK_U32 ref7_topfield_used : 1;
RK_U32 ref7_botfield_used : 1;
RK_U32 ref7_colmv_use_flag : 1;
RK_U32 ref7_reserve : 4;
} reg100;
struct SWREG101_H264_REG8_11_INFO {
RK_U32 ref8_field : 1;
RK_U32 ref8_topfield_used : 1;
RK_U32 ref8_botfield_used : 1;
RK_U32 ref8_colmv_use_flag : 1;
RK_U32 ref8_reserve : 4;
RK_U32 ref9_field : 1;
RK_U32 ref9_topfield_used : 1;
RK_U32 ref9_botfield_used : 1;
RK_U32 ref9_colmv_use_flag : 1;
RK_U32 ref9_reserve : 4;
RK_U32 ref10_field : 1;
RK_U32 ref10_topfield_used : 1;
RK_U32 ref10_botfield_used : 1;
RK_U32 ref10_colmv_use_flag : 1;
RK_U32 ref10_reserve : 4;
RK_U32 ref11_field : 1;
RK_U32 ref11_topfield_used : 1;
RK_U32 ref11_botfield_used : 1;
RK_U32 ref11_colmv_use_flag : 1;
RK_U32 ref11_reserve : 4;
} reg101;
struct SWREG102_H264_REG12_15_INFO {
RK_U32 ref12_field : 1;
RK_U32 ref12_topfield_used : 1;
RK_U32 ref12_botfield_used : 1;
RK_U32 ref12_colmv_use_flag : 1;
RK_U32 ref12_reserve : 4;
RK_U32 ref13_field : 1;
RK_U32 ref13_topfield_used : 1;
RK_U32 ref13_botfield_used : 1;
RK_U32 ref13_colmv_use_flag : 1;
RK_U32 ref13_reserve : 4;
RK_U32 ref14_field : 1;
RK_U32 ref14_topfield_used : 1;
RK_U32 ref14_botfield_used : 1;
RK_U32 ref14_colmv_use_flag : 1;
RK_U32 ref14_reserve : 4;
RK_U32 ref15_field : 1;
RK_U32 ref15_topfield_used : 1;
RK_U32 ref15_botfield_used : 1;
RK_U32 ref15_colmv_use_flag : 1;
RK_U32 ref15_reserve : 4;
} reg102;
struct SWREG103_111_NO_USE_REGS {
RK_U32 reserve;
} no_use_regs[9];
struct SWREG112_ERROR_REF_INFO {
RK_U32 avs2_ref_error_field : 1;
RK_U32 avs2_ref_error_topfield : 1;
RK_U32 ref_error_topfield_used : 1;
RK_U32 ref_error_botfield_used : 1;
RK_U32 reserve : 28;
} reg112;
} Vdpu382RegH264dParam;
/* base: OFFSET_CODEC_ADDR_REGS */
typedef struct Vdpu382RegH264dAddr_t {
/* SWREG160 */
RK_U32 reg160_no_use;
/* SWREG161 */
RK_U32 pps_base;
/* SWREG162 */
RK_U32 reg162_no_use;
/* SWREG163 */
RK_U32 rps_base;
/* SWREG164~179 */
RK_U32 ref_base[16];
/* SWREG180 */
RK_U32 scanlist_addr;
/* SWREG181~196 */
RK_U32 colmv_base[16];
/* SWREG197 */
RK_U32 cabactbl_base;
} Vdpu382RegH264dAddr;
typedef struct Vdpu382H264dHighPoc_t {
/* SWREG200 */
struct SWREG200_REF0_7_POC_HIGHBIT {
RK_U32 ref0_poc_highbit : 4;
RK_U32 ref1_poc_highbit : 4;
RK_U32 ref2_poc_highbit : 4;
RK_U32 ref3_poc_highbit : 4;
RK_U32 ref4_poc_highbit : 4;
RK_U32 ref5_poc_highbit : 4;
RK_U32 ref6_poc_highbit : 4;
RK_U32 ref7_poc_highbit : 4;
} reg200;
struct SWREG201_REF8_15_POC_HIGHBIT {
RK_U32 ref8_poc_highbit : 4;
RK_U32 ref9_poc_highbit : 4;
RK_U32 ref10_poc_highbit : 4;
RK_U32 ref11_poc_highbit : 4;
RK_U32 ref12_poc_highbit : 4;
RK_U32 ref13_poc_highbit : 4;
RK_U32 ref14_poc_highbit : 4;
RK_U32 ref15_poc_highbit : 4;
} reg201;
struct SWREG200_REF16_23_POC_HIGHBIT {
RK_U32 ref16_poc_highbit : 4;
RK_U32 ref17_poc_highbit : 4;
RK_U32 ref18_poc_highbit : 4;
RK_U32 ref19_poc_highbit : 4;
RK_U32 ref20_poc_highbit : 4;
RK_U32 ref21_poc_highbit : 4;
RK_U32 ref22_poc_highbit : 4;
RK_U32 ref23_poc_highbit : 4;
} reg202;
struct SWREG200_REF24_31_POC_HIGHBIT {
RK_U32 ref24_poc_highbit : 4;
RK_U32 ref25_poc_highbit : 4;
RK_U32 ref26_poc_highbit : 4;
RK_U32 ref27_poc_highbit : 4;
RK_U32 ref28_poc_highbit : 4;
RK_U32 ref29_poc_highbit : 4;
RK_U32 ref30_poc_highbit : 4;
RK_U32 ref31_poc_highbit : 4;
} reg203;
struct SWREG200_CUR_POC_HIGHBIT {
RK_U32 cur_poc_highbit : 4;
RK_U32 reserver : 28;
} reg204;
struct SWREG205_DEBUG_INFO {
RK_U32 force_softreset_valid : 1;
RK_U32 force_mmureset_valid : 1;
RK_U32 reserve0 : 2;
RK_U32 error_auto_rst_disable : 1;
RK_U32 right_auto_rst_disable : 1;
RK_U32 buf_empty_security_en : 1;
RK_U32 coord_realtime_report_en : 1;
RK_U32 fetchcmd_merge_dis : 1;
RK_U32 dec_timeout_dis : 1;
RK_U32 reg_cfg_wr_dis : 1;
RK_U32 reserve1 : 1;
RK_U32 force_busidle_req : 1;
RK_U32 mmu_force_busidle_req : 1;
RK_U32 mmu_sel : 1;
RK_U32 reserve2 : 17;
} reg205;
} Vdpu382H264dHighPoc_t;
typedef struct Vdpu382H264dRegSet_t {
Vdpu382RegCommon common;
Vdpu382RegH264dParam h264d_param;
Vdpu382RegCommonAddr common_addr;
Vdpu382RegH264dAddr h264d_addr;
Vdpu382H264dHighPoc_t h264d_highpoc;
Vdpu382RegIrqStatus irq_status;
Vdpu382RegStatistic statistic;
} Vdpu382H264dRegSet;
#endif /* __VDPU382_H264D_H__ */

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/*
* Copyright 2022 Rockchip Electronics Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __VDPU382_H265D_H__
#define __VDPU382_H265D_H__
#include "vdpu382_com.h"
typedef struct Vdpu382RegH265d_t {
struct SWREG64_H26X_SET {
RK_U32 h26x_frame_orslice : 1;
RK_U32 h26x_rps_mode : 1;
RK_U32 h26x_stream_mode : 1;
RK_U32 h26x_stream_lastpacket : 1;
RK_U32 h264_firstslice_flag : 1;
RK_U32 reserve : 27;
} reg64;
struct SWREG65_CUR_POC {
RK_U32 cur_top_poc : 32;
} reg65;
struct SWREG66_H264_CUR_POC1 {
RK_U32 cur_bot_poc : 32;
} reg66;
RK_U32 reg67_82_ref_poc[16];
struct SWREG83_98_H264_REF_POC {
RK_U32 ref_poc : 32;
} ref_poc_no_use[16];
/* struct SWREG99_HEVC_REF_VALID{
RK_U32 hevc_ref_valid : 15;
RK_U32 reserve : 17;
}hevc_ref_valid; */
struct SWREG99_HEVC_REF_VALID {
RK_U32 hevc_ref_valid_0 : 1;
RK_U32 hevc_ref_valid_1 : 1;
RK_U32 hevc_ref_valid_2 : 1;
RK_U32 hevc_ref_valid_3 : 1;
RK_U32 reserve0 : 4;
RK_U32 hevc_ref_valid_4 : 1;
RK_U32 hevc_ref_valid_5 : 1;
RK_U32 hevc_ref_valid_6 : 1;
RK_U32 hevc_ref_valid_7 : 1;
RK_U32 reserve1 : 4;
RK_U32 hevc_ref_valid_8 : 1;
RK_U32 hevc_ref_valid_9 : 1;
RK_U32 hevc_ref_valid_10 : 1;
RK_U32 hevc_ref_valid_11 : 1;
RK_U32 reserve2 : 4;
RK_U32 hevc_ref_valid_12 : 1;
RK_U32 hevc_ref_valid_13 : 1;
RK_U32 hevc_ref_valid_14 : 1;
RK_U32 reserve3 : 5;
} reg99;
RK_U32 reg100_102_no_use[3];
struct SWREG103_HEVC_MVC0 {
RK_U32 ref_pic_layer_same_with_cur : 16;
RK_U32 reserve : 16;
} reg103;
struct SWREG104_HEVC_MVC1 {
RK_U32 poc_lsb_not_present_flag : 1;
RK_U32 num_direct_ref_layers : 6;
RK_U32 reserve0 : 1;
RK_U32 num_reflayer_pics : 6;
RK_U32 default_ref_layers_active_flag : 1;
RK_U32 max_one_active_ref_layer_flag : 1;
RK_U32 poc_reset_info_present_flag : 1;
RK_U32 vps_poc_lsb_aligned_flag : 1;
RK_U32 mvc_poc15_valid_flag : 1;
RK_U32 reserve1 : 13;
} reg104;
struct SWREG105_111_NO_USE_REGS {
RK_U32 no_use_regs[7];
} no_use_regs;
struct SWREG112_ERROR_REF_INFO {
RK_U32 avs2_ref_error_field : 1;
RK_U32 avs2_ref_error_topfield : 1;
RK_U32 ref_error_topfield_used : 1;
RK_U32 ref_error_botfield_used : 1;
RK_U32 reserve : 28;
} reg112;
} Vdpu382RegH265d;
typedef struct Vdpu382RegH265dAddr_t {
struct SWREG160_VP9_DELTA_PROB_BASE {
RK_U32 vp9_delta_prob_base : 32;
} reg160_no_use;
RK_U32 reg161_pps_base;
RK_U32 reg162_no_use;
RK_U32 reg163_rps_base;
RK_U32 reg164_179_ref_base[16];
RK_U32 reg180_scanlist_addr;
RK_U32 reg181_196_colmv_base[16];
RK_U32 reg197_cabactbl_base;
} Vdpu382RegH265dAddr;
typedef struct Vdpu382H265dHighPoc_t {
/* SWREG200 */
struct SWREG200_REF0_7_POC_HIGHBIT {
RK_U32 ref0_poc_highbit : 4;
RK_U32 ref1_poc_highbit : 4;
RK_U32 ref2_poc_highbit : 4;
RK_U32 ref3_poc_highbit : 4;
RK_U32 ref4_poc_highbit : 4;
RK_U32 ref5_poc_highbit : 4;
RK_U32 ref6_poc_highbit : 4;
RK_U32 ref7_poc_highbit : 4;
} reg200;
struct SWREG201_REF8_15_POC_HIGHBIT {
RK_U32 ref8_poc_highbit : 4;
RK_U32 ref9_poc_highbit : 4;
RK_U32 ref10_poc_highbit : 4;
RK_U32 ref11_poc_highbit : 4;
RK_U32 ref12_poc_highbit : 4;
RK_U32 ref13_poc_highbit : 4;
RK_U32 ref14_poc_highbit : 4;
RK_U32 ref15_poc_highbit : 4;
} reg201;
struct SWREG200_REF16_23_POC_HIGHBIT {
RK_U32 ref16_poc_highbit : 4;
RK_U32 ref17_poc_highbit : 4;
RK_U32 ref18_poc_highbit : 4;
RK_U32 ref19_poc_highbit : 4;
RK_U32 ref20_poc_highbit : 4;
RK_U32 ref21_poc_highbit : 4;
RK_U32 ref22_poc_highbit : 4;
RK_U32 ref23_poc_highbit : 4;
} reg202;
struct SWREG200_REF24_31_POC_HIGHBIT {
RK_U32 ref24_poc_highbit : 4;
RK_U32 ref25_poc_highbit : 4;
RK_U32 ref26_poc_highbit : 4;
RK_U32 ref27_poc_highbit : 4;
RK_U32 ref28_poc_highbit : 4;
RK_U32 ref29_poc_highbit : 4;
RK_U32 ref30_poc_highbit : 4;
RK_U32 ref31_poc_highbit : 4;
} reg203;
struct SWREG200_CUR_POC_HIGHBIT {
RK_U32 cur_poc_highbit : 4;
RK_U32 reserver : 28;
} reg204;
struct SWREG205_DEBUG_INFO {
RK_U32 force_softreset_valid : 1;
RK_U32 force_mmureset_valid : 1;
RK_U32 reserve0 : 2;
RK_U32 error_auto_rst_disable : 1;
RK_U32 right_auto_rst_disable : 1;
RK_U32 buf_empty_security_en : 1;
RK_U32 coord_realtime_report_en : 1;
RK_U32 fetchcmd_merge_dis : 1;
RK_U32 dec_timeout_dis : 1;
RK_U32 reg_cfg_wr_dis : 1;
RK_U32 reserve1 : 1;
RK_U32 force_busidle_req : 1;
RK_U32 mmu_force_busidle_req : 1;
RK_U32 mmu_sel : 1;
RK_U32 reserve2 : 17;
} reg205;
} Vdpu382H2645HighPoc_t;
typedef struct Vdpu382H265dRegSet_t {
Vdpu382RegCommon common;
Vdpu382RegH265d h265d_param;
Vdpu382RegCommonAddr common_addr;
Vdpu382RegH265dAddr h265d_addr;
Vdpu382H2645HighPoc_t highpoc;
Vdpu382RegIrqStatus irq_status;
Vdpu382RegStatistic statistic;
} Vdpu382H265dRegSet;
#endif /* __VDPU382_H265D_H__ */

315
mpp/hal/rkdec/inc/vdpu382_vp9d.h Normal file
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@@ -0,0 +1,315 @@
/*
* Copyright 2022 Rockchip Electronics Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __HAL_VDPU382_VP9D_H__
#define __HAL_VDPU382_VP9D_H__
#include "rk_type.h"
#include "vdpu382_com.h"
typedef struct Vdpu382RegVp9dParam_t {
struct SWREG64_VP9_SET {
RK_U32 cprheader_offset : 16;
RK_U32 reserve : 16;
} reg64;
struct SWREG65_CUR_POC {
RK_U32 cur_poc : 32;
} reg65;
RK_U32 reg66;
struct SWREG67_74_VP9_SEGID_GRP {
RK_U32 segid_abs_delta : 1;
RK_U32 segid_frame_qp_delta_en : 1;
RK_U32 segid_frame_qp_delta : 9;
RK_U32 segid_frame_loopfitler_value_en : 1;
RK_U32 segid_frame_loopfilter_value : 7;
RK_U32 segid_referinfo_en : 1;
RK_U32 segid_referinfo : 2;
RK_U32 segid_frame_skip_en : 1;
RK_U32 reserve : 9;
} reg67_74[8];
struct SWREG75_VP9_INFO_LASTFRAME {
RK_U32 mode_deltas_lastframe : 14;
RK_U32 vp9_segment_id_clear : 1;
RK_U32 vp9_segment_id_update : 1;
RK_U32 segmentation_enable_lstframe : 1;
RK_U32 last_show_frame : 1;
RK_U32 last_intra_only : 1;
RK_U32 last_widthheight_eqcur : 1;
RK_U32 color_space_lastkeyframe : 3;
RK_U32 reserve1 : 9;
} reg75;
struct SWREG76_VP9_CPRHEADER_CONFIG {
RK_U32 tx_mode : 3;
RK_U32 frame_reference_mode : 2;
RK_U32 reserve : 27;
} reg76;
struct SWREG77_VP9_INTERCMD_NUM {
RK_U32 intercmd_num : 24;
RK_U32 reserve : 8;
} reg77;
struct SWREG78_VP9_LASTTILE_SIZE {
RK_U32 lasttile_size : 24;
RK_U32 reserve : 8;
} reg78;
struct SWREG79_VP9_LASTF_Y_HOR_VIRSTRIDE {
RK_U32 lastfy_hor_virstride : 16;
RK_U32 reserve : 16;
} reg79;
struct SWREG80_VP9_LASTF_UV_HOR_VIRSTRIDE {
RK_U32 lastfuv_hor_virstride : 16;
RK_U32 reserve : 16;
} reg80;
struct SWREG81_VP9_GOLDENF_Y_HOR_VIRSTRIDE {
RK_U32 goldenfy_hor_virstride : 16;
RK_U32 reserve : 16;
} reg81;
struct SWREG82_VP9_GOLDENF_UV_HOR_VIRSTRIDE {
RK_U32 goldenfuv_hor_virstride : 16;
RK_U32 reserve : 16;
} reg82;
struct SWREG83_VP9_ALTREFF_Y_HOR_VIRSTRIDE {
RK_U32 altreffy_hor_virstride : 16;
RK_U32 reserve : 16;
} reg83;
struct SWREG84_VP9_ALTREFF_UV_HOR_VIRSTRIDE {
RK_U32 altreffuv_hor_virstride : 16;
RK_U32 reserve : 16;
} reg84;
struct SWREG85_VP9_LASTF_Y_VIRSTRIDE {
RK_U32 lastfy_virstride : 28;
RK_U32 reserve : 4;
} reg85;
struct SWREG86_VP9_GOLDEN_Y_VIRSTRIDE {
RK_U32 goldeny_virstride : 28;
RK_U32 reserve : 4;
} reg86;
struct SWREG87_VP9_ALTREF_Y_VIRSTRIDE {
RK_U32 altrefy_virstride : 28;
RK_U32 reserve : 4;
} reg87;
struct SWREG88_VP9_LREF_HOR_SCALE {
RK_U32 lref_hor_scale : 16;
RK_U32 reserve : 16;
} reg88;
struct SWREG89_VP9_LREF_VER_SCALE {
RK_U32 lref_ver_scale : 16;
RK_U32 reserve : 16;
} reg89;
struct SWREG90_VP9_GREF_HOR_SCALE {
RK_U32 gref_hor_scale : 16;
RK_U32 reserve : 16;
} reg90;
struct SWREG91_VP9_GREF_VER_SCALE {
RK_U32 gref_ver_scale : 16;
RK_U32 reserve : 16;
} reg91;
struct SWREG92_VP9_AREF_HOR_SCALE {
RK_U32 aref_hor_scale : 16;
RK_U32 reserve : 16;
} reg92;
struct SWREG93_VP9_AREF_VER_SCALE {
RK_U32 aref_ver_scale : 16;
RK_U32 reserve : 16;
} reg93;
struct SWREG94_VP9_REF_DELTAS_LASTFRAME {
RK_U32 ref_deltas_lastframe : 28;
RK_U32 reserve : 4;
} reg94;
struct SWREG95_LAST_POC {
RK_U32 last_poc : 32;
} reg95;
struct SWREG96_GOLDEN_POC {
RK_U32 golden_poc : 32;
} reg96;
struct SWREG97_ALTREF_POC {
RK_U32 altref_poc : 32;
} reg97;
struct SWREG98_COF_REF_POC {
RK_U32 col_ref_poc : 32;
} reg98;
struct SWREG99_PROB_REF_POC {
RK_U32 prob_ref_poc : 32;
} reg99;
struct SWREG100_SEGID_REF_POC {
RK_U32 segid_ref_poc : 32;
} reg100;
RK_U32 reg101_102_no_use[2];
struct SWREG103_VP9_PROB_EN {
RK_U32 reserve : 20;
RK_U32 prob_update_en : 1;
RK_U32 refresh_en : 1;
RK_U32 prob_save_en : 1;
RK_U32 intra_only_flag : 1;
RK_U32 txfmmode_rfsh_en : 1;
RK_U32 ref_mode_rfsh_en : 1;
RK_U32 single_ref_rfsh_en : 1;
RK_U32 comp_ref_rfsh_en : 1;
RK_U32 interp_filter_switch_en : 1;
RK_U32 allow_high_precision_mv : 1;
RK_U32 last_key_frame_flag : 1;
RK_U32 inter_coef_rfsh_flag : 1;
} reg103;
RK_U32 reg104_no_use;
struct SWREG105_VP9CNT_UPD_EN_AVS2_HEADLEN {
RK_U32 avs2_head_len : 4;
RK_U32 count_update_en : 1;
RK_U32 reserve : 27;
} reg105;
struct SWREG106_VP9_FRAME_WIDTH_LAST {
RK_U32 framewidth_last : 16;
RK_U32 reserve : 16;
} reg106;
struct SWREG107_VP9_FRAME_HEIGHT_LAST {
RK_U32 frameheight_last : 16;
RK_U32 reserve : 16;
} reg107;
struct SWREG108_VP9_FRAME_WIDTH_GOLDEN {
RK_U32 framewidth_golden : 16;
RK_U32 reserve : 16;
} reg108;
struct SWREG109_VP9_FRAME_HEIGHT_GOLDEN {
RK_U32 frameheight_golden : 16;
RK_U32 reserve : 16;
} reg109;
struct SWREG110_VP9_FRAME_WIDTH_ALTREF {
RK_U32 framewidth_alfter : 16;
RK_U32 reserve : 16;
} reg110;
struct SWREG111_VP9_FRAME_HEIGHT_ALTREF {
RK_U32 frameheight_alfter : 16;
RK_U32 reserve : 16;
} reg111;
struct SWREG112_ERROR_REF_INFO {
RK_U32 ref_error_field : 1;
RK_U32 ref_error_topfield : 1;
RK_U32 ref_error_topfield_used : 1;
RK_U32 ref_error_botfield_used : 1;
RK_U32 reserve : 28;
} reg112;
} Vdpu382RegVp9dParam;
typedef struct Vdpu382RegVp9dAddr_t {
RK_U32 reg160_delta_prob_base;
RK_U32 reg161_pps_base;
RK_U32 reg162_last_prob_base;
RK_U32 reg163_rps_base;
RK_U32 reg164_ref_last_base;
RK_U32 reg165_ref_golden_base;
RK_U32 reg166_ref_alfter_base;
RK_U32 reg167_count_prob_base;
RK_U32 reg168_segidlast_base;
RK_U32 reg169_segidcur_base;
RK_U32 reg170_ref_colmv_base;
RK_U32 reg171_intercmd_base;
RK_U32 reg172_update_prob_wr_base;
RK_U32 reg173_179_no_use[7];
RK_U32 reg180_scanlist_base;
RK_U32 reg181_196_ref_colmv_base[16];
RK_U32 reg197_cabactbl_base;
RK_U32 reg198_204reserve[7];
struct SWREG205_DEBUG_INFO {
RK_U32 force_softreset_valid : 1;
RK_U32 force_mmureset_valid : 1;
RK_U32 reserve0 : 2;
RK_U32 error_auto_rst_disable : 1;
RK_U32 right_auto_rst_disable : 1;
RK_U32 buf_empty_security_en : 1;
RK_U32 coord_realtime_report_en : 1;
RK_U32 fetchcmd_merge_dis : 1;
RK_U32 dec_timeout_dis : 1;
RK_U32 reserve1 : 2;
RK_U32 force_busidle_req : 1;
RK_U32 mmu_force_busidle_req : 1;
RK_U32 mmu_sel : 1;
RK_U32 reserve2 : 17;
} reg205;
} Vdpu382RegVp9dAddr;
typedef struct Vdpu382Vp9dRegSet_t {
Vdpu382RegCommon common;
Vdpu382RegVp9dParam vp9d_param;
Vdpu382RegCommonAddr common_addr;
Vdpu382RegVp9dAddr vp9d_addr;
Vdpu382RegIrqStatus irq_status;
Vdpu382RegStatistic statistic;
} Vdpu382Vp9dRegSet;
#endif /* __HAL_VDPU382_VP9D_H__ */

194
mpp/hal/rkdec/vdpu382_com.c Normal file
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@@ -0,0 +1,194 @@
/*
* Copyright 2022 Rockchip Electronics Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#define MODULE_TAG "vdpu382_com"
#include <string.h>
#include "mpp_log.h"
#include "mpp_buffer.h"
#include "mpp_common.h"
#include "mpp_compat_impl.h"
#include "vdpu382_com.h"
static RK_U32 rcb_coeff[RCB_BUF_COUNT] = {
[RCB_INTRA_ROW] = 6, /* RCB_INTRA_ROW_COEF */
[RCB_TRANSD_ROW] = 1, /* RCB_TRANSD_ROW_COEF */
[RCB_TRANSD_COL] = 1, /* RCB_TRANSD_COL_COEF */
[RCB_STRMD_ROW] = 3, /* RCB_STRMD_ROW_COEF */
[RCB_INTER_ROW] = 6, /* RCB_INTER_ROW_COEF */
[RCB_INTER_COL] = 3, /* RCB_INTER_COL_COEF */
[RCB_DBLK_ROW] = 22, /* RCB_DBLK_ROW_COEF */
[RCB_SAO_ROW] = 6, /* RCB_SAO_ROW_COEF */
[RCB_FBC_ROW] = 11, /* RCB_FBC_ROW_COEF */
[RCB_FILT_COL] = 67, /* RCB_FILT_COL_COEF */
};
static RK_S32 update_size_offset(Vdpu382RcbInfo *info, RK_U32 reg,
RK_S32 offset, RK_S32 len, RK_S32 idx)
{
RK_S32 buf_size = 0;
buf_size = MPP_ALIGN(len * rcb_coeff[idx], RCB_ALLINE_SIZE);
info[idx].reg = reg;
info[idx].offset = offset;
info[idx].size = buf_size;
return buf_size;
}
RK_S32 vdpu382_get_rcb_buf_size(Vdpu382RcbInfo *info, RK_S32 width, RK_S32 height)
{
RK_S32 offset = 0;
offset += update_size_offset(info, 139, offset, width, RCB_DBLK_ROW);
offset += update_size_offset(info, 133, offset, width, RCB_INTRA_ROW);
offset += update_size_offset(info, 134, offset, width, RCB_TRANSD_ROW);
offset += update_size_offset(info, 136, offset, width, RCB_STRMD_ROW);
offset += update_size_offset(info, 137, offset, width, RCB_INTER_ROW);
offset += update_size_offset(info, 140, offset, width, RCB_SAO_ROW);
offset += update_size_offset(info, 141, offset, width, RCB_FBC_ROW);
/* col rcb */
offset += update_size_offset(info, 135, offset, height, RCB_TRANSD_COL);
offset += update_size_offset(info, 138, offset, height, RCB_INTER_COL);
offset += update_size_offset(info, 142, offset, height, RCB_FILT_COL);
return offset;
}
void vdpu382_setup_rcb(Vdpu382RegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu382RcbInfo *info)
{
MppDevRegOffsetCfg trans_cfg;
RK_S32 fd = mpp_buffer_get_fd(buf);
reg->reg139_rcb_dblk_base = fd;
reg->reg133_rcb_intra_base = fd;
reg->reg134_rcb_transd_row_base = fd;
reg->reg136_rcb_streamd_row_base = fd;
reg->reg137_rcb_inter_row_base = fd;
reg->reg140_rcb_sao_base = fd;
reg->reg141_rcb_fbc_base = fd;
reg->reg135_rcb_transd_col_base = fd;
reg->reg138_rcb_inter_col_base = fd;
reg->reg142_rcb_filter_col_base = fd;
if (info[RCB_DBLK_ROW].offset) {
trans_cfg.reg_idx = 139;
trans_cfg.offset = info[RCB_DBLK_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_INTRA_ROW].offset) {
trans_cfg.reg_idx = 133;
trans_cfg.offset = info[RCB_INTRA_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_TRANSD_ROW].offset) {
trans_cfg.reg_idx = 134;
trans_cfg.offset = info[RCB_TRANSD_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_STRMD_ROW].offset) {
trans_cfg.reg_idx = 136;
trans_cfg.offset = info[RCB_STRMD_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_INTER_ROW].offset) {
trans_cfg.reg_idx = 137;
trans_cfg.offset = info[RCB_INTER_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_SAO_ROW].offset) {
trans_cfg.reg_idx = 140;
trans_cfg.offset = info[RCB_SAO_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_FBC_ROW].offset) {
trans_cfg.reg_idx = 141;
trans_cfg.offset = info[RCB_FBC_ROW].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_TRANSD_COL].offset) {
trans_cfg.reg_idx = 135;
trans_cfg.offset = info[RCB_TRANSD_COL].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_INTER_COL].offset) {
trans_cfg.reg_idx = 138;
trans_cfg.offset = info[RCB_INTER_COL].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
if (info[RCB_FILT_COL].offset) {
trans_cfg.reg_idx = 142;
trans_cfg.offset = info[RCB_FILT_COL].offset;
mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
}
RK_S32 vdpu382_compare_rcb_size(const void *a, const void *b)
{
RK_S32 val = 0;
Vdpu382RcbInfo *p0 = (Vdpu382RcbInfo *)a;
Vdpu382RcbInfo *p1 = (Vdpu382RcbInfo *)b;
val = (p0->size > p1->size) ? -1 : 1;
return val;
}
void vdpu382_setup_statistic(Vdpu382RegCommon *com, Vdpu382RegStatistic *sta)
{
com->reg011.pix_range_detection_e = 1;
memset(sta, 0, sizeof(*sta));
sta->reg256.axi_perf_work_e = 1;
sta->reg256.axi_perf_clr_e = 1;
sta->reg256.axi_cnt_type = 1;
sta->reg257.addr_align_type = 1;
/* set hurry */
sta->reg270.axi_rd_hurry_level = 3;
sta->reg270.axi_wr_hurry_level = 1;
sta->reg270.axi_wr_qos = 1;
sta->reg270.axi_rd_qos = 3;
sta->reg270.bus2mc_buffer_qos_level = 255;
sta->reg271_wr_wait_cycle_qos = 0;
}
void vdpu382_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand)
{
RK_U32 ver_stride = 0;
RK_U32 img_height = mpp_frame_get_height(frame);
mpp_slots_set_prop(slots, SLOTS_HOR_ALIGN, mpp_align_64);
mpp_slots_set_prop(slots, SLOTS_VER_ALIGN, mpp_align_16);
ver_stride = mpp_align_16(img_height);
if (*compat_ext_fbc_buf_size) {
ver_stride += expand;
}
mpp_frame_set_ver_stride(frame, ver_stride);
}

1
mpp/hal/rkdec/vp9d/CMakeLists.txt
View File

@@ -6,6 +6,7 @@ set(HAL_VP9D_SRC
hal_vp9d_com.c
hal_vp9d_rkv.c
hal_vp9d_vdpu34x.c
hal_vp9d_vdpu382.c
)
add_library(hal_vp9d STATIC ${HAL_VP9D_SRC})

6
mpp/hal/rkdec/vp9d/hal_vp9d_api.c
View File

@@ -25,6 +25,7 @@
#include "hal_vp9d_ctx.h"
#include "hal_vp9d_rkv.h"
#include "hal_vp9d_vdpu34x.h"
#include "hal_vp9d_vdpu382.h"
RK_U32 hal_vp9d_debug = 0;
@@ -45,7 +46,10 @@ MPP_RET hal_vp9d_init(void *ctx, MppHalCfg *cfg)
p->dev = cfg->dev;
p->hw_id = hw_id;
p->client_type = client_type;
if (hw_id == HWID_VDPU34X || hw_id == HWID_VDPU38X) {
if (hw_id == HWID_VDPU382) {
p->api = &hal_vp9d_vdpu382;
cfg->support_fast_mode = 1;
} else if (hw_id == HWID_VDPU34X || hw_id == HWID_VDPU38X) {
p->api = &hal_vp9d_vdpu34x;
cfg->support_fast_mode = 1;
} else {

1075
mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.c Normal file
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File diff suppressed because it is too large Load Diff

32
mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.h Normal file
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@@ -0,0 +1,32 @@
/*
* Copyright 2022 Rockchip Electronics Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __HAL_VP9D_VDPU382_H__
#define __HAL_VP9D_VDPU382_H__
#include "mpp_hal.h"
#include "vdpu382.h"
#ifdef __cplusplus
extern "C" {
#endif
extern const MppHalApi hal_vp9d_vdpu382;
#ifdef __cplusplus
}
#endif
#endif /* __HAL_VP9D_VDPU382_H__ */