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[legacy]: Align input ver_stride to 8 not 16

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1. The input ver_stride can not be set by EncParameter. It is better to
align it to 8 not 16 to avoid green lines at bottom when the input frame
buffer is not aligned to 16.
2. But the allocated buffer size should be aligned to 16 to avoid
hardware error because hardware requires 16 aligned buffer to access.

Change-Id: I402ac167f29e22c9c363135e95bb4ad431d3c3ef
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
This commit is contained in:
Herman Chen
2020-08-06 14:11:50 +08:00
parent 408c54cd82
commit e48ece08be
1 changed files with 14 additions and 11 deletions
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25
mpp/legacy/vpu_api_legacy.cpp
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@@ -122,13 +122,13 @@ static MPP_RET vpu_api_set_enc_cfg(MppCtx mpp_ctx, MppApi *mpi, MppEncCfg enc_cf
mpp_enc_cfg_set_s32(enc_cfg, "prep:width", width);
mpp_enc_cfg_set_s32(enc_cfg, "prep:height", height);
mpp_enc_cfg_set_s32(enc_cfg, "prep:hor_stride", MPP_ALIGN(width, 16));
mpp_enc_cfg_set_s32(enc_cfg, "prep:ver_stride", MPP_ALIGN(height, 16));
mpp_enc_cfg_set_s32(enc_cfg, "prep:ver_stride", MPP_ALIGN(height, 8));
mpp_enc_cfg_set_s32(enc_cfg, "prep:format", fmt);
mpp_enc_cfg_set_s32(enc_cfg, "rc:mode", rc_mode ? MPP_ENC_RC_MODE_CBR : MPP_ENC_RC_MODE_FIXQP);
mpp_enc_cfg_set_s32(enc_cfg, "rc:mode", rc_mode ? MPP_ENC_RC_MODE_CBR : MPP_ENC_RC_MODE_VBR);
mpp_enc_cfg_set_s32(enc_cfg, "rc:bps_target", bps);
mpp_enc_cfg_set_s32(enc_cfg, "rc:bps_max", bps * 17 / 16);
mpp_enc_cfg_set_s32(enc_cfg, "rc:bps_min", bps * 15 / 16);
mpp_enc_cfg_set_s32(enc_cfg, "rc:bps_min", rc_mode ? bps * 15 / 16 : bps * 1 / 16);
mpp_enc_cfg_set_s32(enc_cfg, "rc:fps_in_flex", 0);
mpp_enc_cfg_set_s32(enc_cfg, "rc:fps_in_num", fps_in);
mpp_enc_cfg_set_s32(enc_cfg, "rc:fps_in_denorm", 1);
@@ -144,10 +144,13 @@ static MPP_RET vpu_api_set_enc_cfg(MppCtx mpp_ctx, MppApi *mpi, MppEncCfg enc_cf
mpp_enc_cfg_set_s32(enc_cfg, "h264:level", level);
mpp_enc_cfg_set_s32(enc_cfg, "h264:cabac_en", cabac_en);
mpp_enc_cfg_set_s32(enc_cfg, "h264:cabac_idc", 0);
mpp_enc_cfg_set_s32(enc_cfg, "h264:qp_init", rc_mode ? 0 : qp);
mpp_enc_cfg_set_s32(enc_cfg, "h264:qp_min", rc_mode ? 10 : qp);
mpp_enc_cfg_set_s32(enc_cfg, "h264:qp_max", rc_mode ? 51 : qp);
mpp_enc_cfg_set_s32(enc_cfg, "h264:qp_step", rc_mode ? 4 : 0);
mpp_enc_cfg_set_s32(enc_cfg, "h264:qp_init", -1);
mpp_enc_cfg_set_s32(enc_cfg, "h264:qp_min", 10);
mpp_enc_cfg_set_s32(enc_cfg, "h264:qp_max", 51);
mpp_enc_cfg_set_s32(enc_cfg, "h264:qp_min_i", 10);
mpp_enc_cfg_set_s32(enc_cfg, "h264:qp_max_i", 51);
mpp_enc_cfg_set_s32(enc_cfg, "h264:qp_step", 4);
mpp_enc_cfg_set_s32(enc_cfg, "h264:qp_delta_ip", 3);
} break;
case MPP_VIDEO_CodingMJPEG : {
mpp_enc_cfg_set_s32(enc_cfg, "jpeg:quant", qp);
@@ -1162,7 +1165,7 @@ RK_S32 VpuApiLegacy::encoder_sendframe(VpuCodecContext *ctx, EncInputStream_t *a
RK_U32 width = ctx->width;
RK_U32 height = ctx->height;
RK_U32 hor_stride = MPP_ALIGN(width, 16);
RK_U32 ver_stride = MPP_ALIGN(height, 16);
RK_U32 ver_stride = MPP_ALIGN(height, 8);
RK_S64 pts = aEncInStrm->timeUs;
RK_S32 fd = aEncInStrm->bufPhyAddr;
RK_U32 size = aEncInStrm->size;
@@ -1223,11 +1226,11 @@ RK_S32 VpuApiLegacy::encoder_sendframe(VpuCodecContext *ctx, EncInputStream_t *a
goto FUNC_RET;
}
if (format >= MPP_FMT_YUV420SP && format < MPP_FMT_YUV_BUTT) {
align_size = hor_stride * ver_stride * 3 / 2;
align_size = hor_stride * MPP_ALIGN(ver_stride, 16) * 3 / 2;
} else if (format >= MPP_FMT_RGB565 && format < MPP_FMT_BGR888) {
align_size = hor_stride * ver_stride * 3;
align_size = hor_stride * MPP_ALIGN(ver_stride, 16) * 3;
} else if (format >= MPP_FMT_RGB101010 && format < MPP_FMT_RGB_BUTT) {
align_size = hor_stride * ver_stride * 4;
align_size = hor_stride * MPP_ALIGN(ver_stride, 16) * 4;
} else {
mpp_err_f("unsupport input format:%d\n", format);
ret = MPP_NOK;