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[vepu541]: Fix reenc case no read roi again

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Change-Id: I857bd53ba173ae81fa1ab5065041c5d6ee9daca6
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
This commit is contained in:
sayon.chen
2020-04-30 16:06:08 +08:00
committed by Herman Chen
parent 02c7073f35
commit dfe13c041a
2 changed files with 42 additions and 41 deletions
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44
mpp/hal/rkenc/h264e/hal_h264e_vepu541.c
View File

@@ -226,7 +226,7 @@ static MPP_RET hal_h264e_vepu541_get_task(void *hal, HalEncTask *task)
HalH264eVepu541Ctx *ctx = (HalH264eVepu541Ctx *)hal;
RK_U32 updated = update_vepu541_syntax(ctx, &task->syntax);
MppEncPrepCfg *prep = &ctx->cfg->prep;
EncFrmStatus *frm_status = &task->rc_task->frm;
hal_h264e_dbg_func("enter %p\n", hal);
if (updated & SYN_TYPE_FLAG(H264E_SYN_CFG)) {
@@ -259,12 +259,12 @@ static MPP_RET hal_h264e_vepu541_get_task(void *hal, HalEncTask *task)
}
}
ctx->roi_data = NULL;
MppMeta meta = mpp_frame_get_meta(task->frame);
mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
mpp_meta_get_ptr(meta, KEY_OSD_DATA, (void **)&ctx->osd_cfg.osd_data);
if (!frm_status->reencode) {
MppMeta meta = mpp_frame_get_meta(task->frame);
mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
mpp_meta_get_ptr(meta, KEY_OSD_DATA, (void **)&ctx->osd_cfg.osd_data);
}
hal_h264e_dbg_func("leave %p\n", hal);
return MPP_OK;
@@ -606,25 +606,25 @@ static void setup_vepu541_rc_base(Vepu541H264eRegSet *regs, SynH264eSps *sps,
regs->reg055_063.rc_dthd[7] = positive_bits_thd;
regs->reg055_063.rc_dthd[8] = positive_bits_thd;
regs->reg064.qpmin_area0 = 1;
regs->reg064.qpmax_area0 = 51;
regs->reg064.qpmin_area1 = 1;
regs->reg064.qpmax_area1 = 51;
regs->reg064.qpmin_area2 = 1;
regs->reg064.qpmin_area0 = qp_min;
regs->reg064.qpmax_area0 = qp_max;
regs->reg064.qpmin_area1 = qp_min;
regs->reg064.qpmax_area1 = qp_max;
regs->reg064.qpmin_area2 = qp_min;
regs->reg065.qpmax_area2 = 51;
regs->reg065.qpmin_area3 = 1;
regs->reg065.qpmax_area3 = 51;
regs->reg065.qpmin_area4 = 1;
regs->reg065.qpmax_area4 = 51;
regs->reg065.qpmax_area2 = qp_max;
regs->reg065.qpmin_area3 = qp_min;
regs->reg065.qpmax_area3 = qp_max;
regs->reg065.qpmin_area4 = qp_min;
regs->reg065.qpmax_area4 = qp_max;
regs->reg066.qpmin_area5 = 1;
regs->reg066.qpmax_area5 = 51;
regs->reg066.qpmin_area6 = 1;
regs->reg066.qpmax_area6 = 51;
regs->reg066.qpmin_area7 = 1;
regs->reg066.qpmin_area5 = qp_min;
regs->reg066.qpmax_area5 = qp_max;
regs->reg066.qpmin_area6 = qp_min;
regs->reg066.qpmax_area6 = qp_max;
regs->reg066.qpmin_area7 = qp_min;
regs->reg067.qpmax_area7 = 51;
regs->reg067.qpmax_area7 = qp_max;
regs->reg067.qpmap_mode = qpmap_mode;
hal_h264e_dbg_func("leave\n");

39
mpp/hal/rkenc/h265e/hal_h265e_vepu541.c
View File

@@ -595,22 +595,22 @@ static MPP_RET vepu541_h265_set_rc_regs(H265eV541HalContext *ctx, H265eV541RegSe
regs->rc_adj1.qp_adjust7 = 0;
regs->rc_adj1.qp_adjust8 = 1;
regs->qpmap0.qpmin_area0 = 1;
regs->qpmap0.qpmax_area0 = 51;
regs->qpmap0.qpmin_area1 = 1;
regs->qpmap0.qpmax_area1 = 51;
regs->qpmap0.qpmin_area2 = 1;
regs->qpmap1.qpmax_area2 = 51;
regs->qpmap1.qpmin_area3 = 1;
regs->qpmap1.qpmax_area3 = 51;
regs->qpmap1.qpmin_area4 = 1;
regs->qpmap1.qpmax_area4 = 51;
regs->qpmap2.qpmin_area5 = 1;
regs->qpmap2.qpmax_area5 = 51;
regs->qpmap2.qpmin_area6 = 1;
regs->qpmap2.qpmax_area6 = 51;
regs->qpmap2.qpmin_area7 = 1;
regs->qpmap3.qpmax_area7 = 51;
regs->qpmap0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min;
regs->qpmap0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max;
regs->qpmap0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min;
regs->qpmap0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max;
regs->qpmap0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;;
regs->qpmap1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max;
regs->qpmap1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;;
regs->qpmap1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max;
regs->qpmap1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;;
regs->qpmap1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max;
regs->qpmap2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;;
regs->qpmap2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max;
regs->qpmap2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;;
regs->qpmap2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max;
regs->qpmap2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;;
regs->qpmap3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max;
regs->qpmap3.qpmap_mode = h265->qpmap_mode;
}
if (ctx->frame_type == INTRA_FRAME) {
@@ -1355,9 +1355,10 @@ MPP_RET hal_h265e_v541_get_task(void *hal, HalEncTask *task)
} else {
ctx->frame_type = INTER_P_FRAME;
}
mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
mpp_meta_get_ptr(meta, KEY_OSD_DATA, (void **)&ctx->osd_cfg.osd_data);
if (!frm_status->reencode) {
mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
mpp_meta_get_ptr(meta, KEY_OSD_DATA, (void **)&ctx->osd_cfg.osd_data);
}
h265e_hal_leave();
return MPP_OK;