package/mpp
1
0
Fork 0
mirror of https://github.com/nyanmisaka/mpp.git synced 2025-10-04 16:52:40 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

[vepu541]: Fix roi error

Browse Source 
1. Fix h.264 encoder roi buffer leak error.
2. Set all qparea to [1, 51] range.

Change-Id: I8434fc5fc60071ec533aba68fc2fe3be5a087bcd
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
This commit is contained in:
Herman Chen
2020-04-29 18:40:14 +08:00
parent 4709cb2a95
commit 02c7073f35
3 changed files with 76 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
mpp/hal/rkenc/h264e/hal_h264e_vepu541.c
View File

@@ -113,6 +113,16 @@ static MPP_RET hal_h264e_vepu541_deinit(void *hal)
p->dev_ctx = NULL;
}
if (p->roi_buf) {
mpp_buffer_put(p->roi_buf);
p->roi_buf = NULL;
}
if (p->roi_grp) {
mpp_buffer_group_put(p->roi_grp);
p->roi_grp = NULL;
}
if (p->hw_recn) {
hal_bufs_deinit(p->hw_recn);
p->hw_recn = NULL;
@@ -596,25 +606,25 @@ static void setup_vepu541_rc_base(Vepu541H264eRegSet *regs, SynH264eSps *sps,
regs->reg055_063.rc_dthd[7] = positive_bits_thd;
regs->reg055_063.rc_dthd[8] = positive_bits_thd;
regs->reg064.qpmin_area0 = 21;
regs->reg064.qpmax_area0 = 50;
regs->reg064.qpmin_area1 = 20;
regs->reg064.qpmax_area1 = 50;
regs->reg064.qpmin_area2 = 20;
regs->reg064.qpmin_area0 = 1;
regs->reg064.qpmax_area0 = 51;
regs->reg064.qpmin_area1 = 1;
regs->reg064.qpmax_area1 = 51;
regs->reg064.qpmin_area2 = 1;
regs->reg065.qpmax_area2 = 50;
regs->reg065.qpmin_area3 = 20;
regs->reg065.qpmax_area3 = 50;
regs->reg065.qpmin_area4 = 20;
regs->reg065.qpmax_area4 = 50;
regs->reg065.qpmax_area2 = 51;
regs->reg065.qpmin_area3 = 1;
regs->reg065.qpmax_area3 = 51;
regs->reg065.qpmin_area4 = 1;
regs->reg065.qpmax_area4 = 51;
regs->reg066.qpmin_area5 = 20;
regs->reg066.qpmax_area5 = 50;
regs->reg066.qpmin_area6 = 20;
regs->reg066.qpmax_area6 = 50;
regs->reg066.qpmin_area7 = 20;
regs->reg066.qpmin_area5 = 1;
regs->reg066.qpmax_area5 = 51;
regs->reg066.qpmin_area6 = 1;
regs->reg066.qpmax_area6 = 51;
regs->reg066.qpmin_area7 = 1;
regs->reg067.qpmax_area7 = 49;
regs->reg067.qpmax_area7 = 51;
regs->reg067.qpmap_mode = qpmap_mode;
hal_h264e_dbg_func("leave\n");

32
mpp/hal/rkenc/h265e/hal_h265e_vepu541.c
View File

@@ -595,22 +595,22 @@ static MPP_RET vepu541_h265_set_rc_regs(H265eV541HalContext *ctx, H265eV541RegSe
regs->rc_adj1.qp_adjust7 = 0;
regs->rc_adj1.qp_adjust8 = 1;
regs->qpmap0.qpmin_area0 = h265->qpmin_map[0];
regs->qpmap0.qpmax_area0 = h265->qpmax_map[0];
regs->qpmap0.qpmin_area1 = h265->qpmin_map[1];
regs->qpmap0.qpmax_area1 = h265->qpmax_map[1];
regs->qpmap0.qpmin_area2 = h265->qpmin_map[2];
regs->qpmap1.qpmax_area2 = h265->qpmax_map[2];
regs->qpmap1.qpmin_area3 = h265->qpmin_map[3];
regs->qpmap1.qpmax_area3 = h265->qpmax_map[3];
regs->qpmap1.qpmin_area4 = h265->qpmin_map[4];
regs->qpmap1.qpmax_area4 = h265->qpmax_map[4];
regs->qpmap2.qpmin_area5 = h265->qpmin_map[5];
regs->qpmap2.qpmax_area5 = h265->qpmax_map[5];
regs->qpmap2.qpmin_area6 = h265->qpmin_map[6];
regs->qpmap2.qpmax_area6 = h265->qpmax_map[6];
regs->qpmap2.qpmin_area7 = h265->qpmin_map[7];
regs->qpmap3.qpmax_area7 = h265->qpmax_map[7];
regs->qpmap0.qpmin_area0 = 1;
regs->qpmap0.qpmax_area0 = 51;
regs->qpmap0.qpmin_area1 = 1;
regs->qpmap0.qpmax_area1 = 51;
regs->qpmap0.qpmin_area2 = 1;
regs->qpmap1.qpmax_area2 = 51;
regs->qpmap1.qpmin_area3 = 1;
regs->qpmap1.qpmax_area3 = 51;
regs->qpmap1.qpmin_area4 = 1;
regs->qpmap1.qpmax_area4 = 51;
regs->qpmap2.qpmin_area5 = 1;
regs->qpmap2.qpmax_area5 = 51;
regs->qpmap2.qpmin_area6 = 1;
regs->qpmap2.qpmax_area6 = 51;
regs->qpmap2.qpmin_area7 = 1;
regs->qpmap3.qpmax_area7 = 51;
regs->qpmap3.qpmap_mode = h265->qpmap_mode;
}
if (ctx->frame_type == INTRA_FRAME) {

35
test/mpi_enc_test.c
View File

@@ -53,6 +53,8 @@ typedef struct {
MppEncOSDPltCfg osd_plt_cfg;
MppEncOSDPlt osd_plt;
MppEncOSDData osd_data;
MppEncROIRegion roi_region[3];
MppEncROICfg roi_cfg;
// input / output
MppBuffer frm_buf;
@@ -87,6 +89,7 @@ typedef struct {
RK_U32 split_arg;
RK_U32 user_data_enable;
RK_U32 roi_enable;
// rate control runtime parameter
RK_S32 gop;
@@ -446,6 +449,7 @@ MPP_RET test_mpp_setup(MpiEncTestData *p)
}
mpp_env_get_u32("osd_enable", &p->user_data_enable, 0);
mpp_env_get_u32("roi_enable", &p->roi_enable, 0);
RET:
return ret;
@@ -537,7 +541,7 @@ MPP_RET test_mpp_run(MpiEncTestData *p)
else
mpp_frame_set_buffer(frame, p->frm_buf);
if (p->osd_enable || p->user_data_enable) {
if (p->osd_enable || p->user_data_enable || p->roi_enable) {
MppMeta meta = mpp_frame_get_meta(frame);
if (p->user_data_enable) {
@@ -556,6 +560,35 @@ MPP_RET test_mpp_run(MpiEncTestData *p)
mpi_enc_gen_osd_data(&p->osd_data, p->osd_idx_buf, p->frame_count);
mpp_meta_set_ptr(meta, KEY_OSD_DATA, (void*)&p->osd_data);
}
if (p->roi_enable) {
MppEncROIRegion *region = p->roi_region;
/* calculated in pixels */
region->x = 304;
region->y = 480;
region->w = 1344;
region->h = 600;
region->intra = 0; /* flag of forced intra macroblock */
region->quality = 24; /* qp of macroblock */
region->abs_qp_en = 1;
region->area_map_en = 1;
region->qp_area_idx = 0;
region++;
region->x = region->y = 16;
region->w = region->h = 64; /* 16-pixel aligned is better */
region->intra = 1; /* flag of forced intra macroblock */
region->quality = 10; /* qp of macroblock */
region->abs_qp_en = 1;
region->area_map_en = 1;
region->qp_area_idx = 1;
p->roi_cfg.number = 2;
p->roi_cfg.regions = p->roi_region;
mpp_meta_set_ptr(meta, KEY_ROI_DATA, (void*)&p->roi_cfg); // new way for roi
}
}
/*