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[vepu5xx]: Fix encoder hw stuck

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Set rfp_load_thd to zero to avoid reference window timeout stuck.

Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: I0d24ef109304cb3262167538e2872447bad707f7
This commit is contained in:
Herman Chen
2022-12-23 18:17:47 +08:00
parent f07778c8c1
commit dde7c5ae48
4 changed files with 4 additions and 4 deletions
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2
mpp/hal/rkenc/h264e/hal_h264e_vepu580.c
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@@ -567,7 +567,7 @@ static void setup_vepu580_normal(HalVepu580RegSet *regs)
/* reg007 INT_STA is read only */ /* reg007 INT_STA is read only */
/* reg008 ~ reg0011 gap */ /* reg008 ~ reg0011 gap */
regs->reg_ctl.enc_wdg.vs_load_thd = 0x1fffff; regs->reg_ctl.enc_wdg.vs_load_thd = 0x1fffff;
regs->reg_ctl.enc_wdg.rfp_load_thd = 0xff; regs->reg_ctl.enc_wdg.rfp_load_thd = 0;
/* reg015 DTRNS_MAP */ /* reg015 DTRNS_MAP */
regs->reg_ctl.dtrns_map.cmvw_bus_ordr = 0; regs->reg_ctl.dtrns_map.cmvw_bus_ordr = 0;

2
mpp/hal/rkenc/h265e/hal_h265e_vepu540c.c
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@@ -1200,7 +1200,7 @@ MPP_RET hal_h265e_v540c_gen_regs(void *hal, HalEncTask *task)
// reg_ctl->reg0013_dtrns_cfg.dspr_otsd = (ctx->frame_type == INTER_P_FRAME); // reg_ctl->reg0013_dtrns_cfg.dspr_otsd = (ctx->frame_type == INTER_P_FRAME);
reg_ctl->reg0013_dtrns_cfg.axi_brsp_cke = 0x0; reg_ctl->reg0013_dtrns_cfg.axi_brsp_cke = 0x0;
reg_ctl->reg0014_enc_wdg.vs_load_thd = 0x1fffff; reg_ctl->reg0014_enc_wdg.vs_load_thd = 0x1fffff;
reg_ctl->reg0014_enc_wdg.rfp_load_thd = 0xff; reg_ctl->reg0014_enc_wdg.rfp_load_thd = 0;
reg_ctl->reg0021_func_en.cke = 1; reg_ctl->reg0021_func_en.cke = 1;
reg_ctl->reg0021_func_en.resetn_hw_en = 1; reg_ctl->reg0021_func_en.resetn_hw_en = 1;

2
mpp/hal/rkenc/h265e/hal_h265e_vepu580.c
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@@ -2402,7 +2402,7 @@ MPP_RET hal_h265e_v580_gen_regs(void *hal, HalEncTask *task)
reg_ctl->reg0013_dtrns_cfg.dspr_otsd = (ctx->frame_type == INTER_P_FRAME); reg_ctl->reg0013_dtrns_cfg.dspr_otsd = (ctx->frame_type == INTER_P_FRAME);
reg_ctl->reg0013_dtrns_cfg.axi_brsp_cke = 0x0; reg_ctl->reg0013_dtrns_cfg.axi_brsp_cke = 0x0;
reg_ctl->reg0014_enc_wdg.vs_load_thd = 0x1fffff; reg_ctl->reg0014_enc_wdg.vs_load_thd = 0x1fffff;
reg_ctl->reg0014_enc_wdg.rfp_load_thd = 0xff; reg_ctl->reg0014_enc_wdg.rfp_load_thd = 0;
reg_ctl->reg0021_func_en.cke = 1; reg_ctl->reg0021_func_en.cke = 1;
reg_ctl->reg0021_func_en.resetn_hw_en = 1; reg_ctl->reg0021_func_en.resetn_hw_en = 1;

2
mpp/hal/rkenc/jpege/hal_jpege_vepu540c.c
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@@ -195,7 +195,7 @@ MPP_RET hal_jpege_v540c_gen_regs(void *hal, HalEncTask *task)
reg_ctl->reg0013_dtrns_cfg.axi_brsp_cke = 0x0; reg_ctl->reg0013_dtrns_cfg.axi_brsp_cke = 0x0;
reg_ctl->reg0014_enc_wdg.vs_load_thd = 0x1fffff; reg_ctl->reg0014_enc_wdg.vs_load_thd = 0x1fffff;
reg_ctl->reg0014_enc_wdg.rfp_load_thd = 0xff; reg_ctl->reg0014_enc_wdg.rfp_load_thd = 0;
vepu540c_set_jpeg_reg(&cfg); vepu540c_set_jpeg_reg(&cfg);
{ {