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[hal_h264e]: move syntax from hw_cfg to sps or pps

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including syntax below:
transform_8x8_mode, constrained_intra_pred,
chroma_qp_index_offset, second_chroma_qp_index_offset,
cabac_init_idc, enable_cabac, pps_id, profile_idc,
level_idc

Change-Id: I708f4126eba731758473f64197cf52cdc0592ca3
Signed-off-by: Lin Kesheng <lks@rock-chips.com>
This commit is contained in:
Lin Kesheng
2017-01-23 10:04:00 +08:00
parent d92760e77a
commit d1857e4390
5 changed files with 14 additions and 100 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
mpp/common/h264e_syntax.h
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@@ -62,21 +62,13 @@ typedef struct H264eHwCfg_t {
*/
RK_S32 frame_type;
/* Parameter in sps/pps/slice */
RK_S32 enable_cabac;
RK_S32 cabac_init_idc;
RK_S32 constrained_intra_prediction;
RK_S32 transform8x8_mode;
RK_S32 pps_id;
RK_S32 frame_num;
RK_S32 pic_order_cnt_lsb;
RK_S32 filter_disable;
RK_S32 idr_pic_id;
RK_S32 slice_alpha_offset;
RK_S32 slice_beta_offset;
RK_S32 chroma_qp_index_offset;
RK_S32 second_chroma_qp_index_offset;
RK_S32 inter4x4_disabled;
/* rate control relevant */
@@ -100,8 +92,6 @@ typedef struct H264eHwCfg_t {
RK_S32 delta_qp[9];
/* RKVENC extra syntax below */
RK_S32 profile_idc;
RK_S32 level_idc;
RK_S32 link_table_en;
RK_S32 keyframe_max_interval;

2
mpp/hal/common/h264/hal_h264e_com.c
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@@ -723,7 +723,7 @@ MPP_RET hal_h264e_set_pps(h264e_hal_context *ctx, h264e_hal_pps *pps, h264e_hal_
h264e_hal_log_err("CQM_CUSTOM mode is not supported now");
return MPP_NOK;
default:
h264e_hal_log_err("invalid cqm_preset mode");
h264e_hal_log_err("invalid cqm_preset mode %d", b_cqm_preset);
return MPP_NOK;
}

41
mpp/hal/common/h264/test/h264e_hal_test.c
View File

@@ -432,10 +432,6 @@ static MPP_RET get_vpu_syntax_in(H264eHwCfg *syn, MppBuffer hw_in_buf, MppBuffer
fgets(temp, 512, fp_golden_syntax_in);
syn->slice_beta_offset = data;
fscanf(fp_golden_syntax_in, "%d", &data);
fgets(temp, 512, fp_golden_syntax_in);
syn->chroma_qp_index_offset = data;
fscanf(fp_golden_syntax_in, "%d", &data);
fgets(temp, 512, fp_golden_syntax_in);
syn->filter_disable = data;
@@ -444,10 +440,6 @@ static MPP_RET get_vpu_syntax_in(H264eHwCfg *syn, MppBuffer hw_in_buf, MppBuffer
fgets(temp, 512, fp_golden_syntax_in);
syn->idr_pic_id = data;
fscanf(fp_golden_syntax_in, "%d", &data);
fgets(temp, 512, fp_golden_syntax_in);
syn->pps_id = data;
fscanf(fp_golden_syntax_in, "%d", &data);
fgets(temp, 512, fp_golden_syntax_in);
syn->frame_num = data;
@@ -460,18 +452,6 @@ static MPP_RET get_vpu_syntax_in(H264eHwCfg *syn, MppBuffer hw_in_buf, MppBuffer
fgets(temp, 512, fp_golden_syntax_in);
syn->inter4x4_disabled = data;
fscanf(fp_golden_syntax_in, "%d", &data);
fgets(temp, 512, fp_golden_syntax_in);
syn->enable_cabac = data;
fscanf(fp_golden_syntax_in, "%d", &data);
fgets(temp, 512, fp_golden_syntax_in);
syn->transform8x8_mode = data;
fscanf(fp_golden_syntax_in, "%d", &data);
fgets(temp, 512, fp_golden_syntax_in);
syn->cabac_init_idc = data;
fscanf(fp_golden_syntax_in, "%d", &data);
fgets(temp, 512, fp_golden_syntax_in);
syn->qp = data;
@@ -596,10 +576,6 @@ static MPP_RET get_rkv_syntax_in( H264eHwCfg *syn, MppBuffer *hw_in_buf, MppBuff
mpp_log("make syntax begin");
syn->width = cfg->pic_width;
syn->height = cfg->pic_height;
syn->level_idc = H264_LEVEL_4_1;
syn->profile_idc = H264_PROFILE_HIGH;
mpp_log("syn->level_idc %d", syn->level_idc);
mpp_log("syn->profile_idc %d", syn->profile_idc);
syn->keyframe_max_interval = 30;
if (g_frame_cnt == 0 || g_frame_cnt % syn->keyframe_max_interval == 0) {
syn->frame_type = 1; //intra
@@ -612,15 +588,7 @@ static MPP_RET get_rkv_syntax_in( H264eHwCfg *syn, MppBuffer *hw_in_buf, MppBuff
csp_info.aswap = 0; //TODO:
syn->input_format = h264e_rkv_revert_csp(csp_info);
syn->enable_cabac = 1;
syn->chroma_qp_index_offset = 0;
syn->second_chroma_qp_index_offset = 0;
syn->pps_id = 0 ;
syn->frame_num = 0;
syn->cabac_init_idc = 0;
syn->idr_pic_id = 0;
syn->pic_order_cnt_lsb = 0;
@@ -637,8 +605,6 @@ static MPP_RET get_rkv_syntax_in( H264eHwCfg *syn, MppBuffer *hw_in_buf, MppBuff
H264E_HAL_FSCAN(fp, "%d\n", syn->width);
H264E_HAL_FSCAN(fp, "%d\n", syn->height);
H264E_HAL_FSCAN(fp, "%d\n", syn->level_idc);
H264E_HAL_FSCAN(fp, "%d\n", syn->profile_idc);
H264E_HAL_FSCAN(fp, "%d\n", syn->frame_type);
H264E_HAL_FSCAN(fp, "%d\n", syn->qp);
H264E_HAL_FSCAN(fp, "%d\n", syn->input_format);
@@ -802,18 +768,11 @@ MPP_RET h264_hal_test_call_back(void *control, void *feedback)
static void h264e_hal_set_extra_info_cfg(h264e_control_extra_info_cfg *info, H264eHwCfg *syn)
{
info->chroma_qp_index_offset = syn->chroma_qp_index_offset;
info->enable_cabac = syn->enable_cabac;
info->pic_luma_height = syn->height;
info->pic_luma_width = syn->width;
info->transform8x8_mode = syn->transform8x8_mode;
info->input_image_format = syn->input_format;
info->profile_idc = syn->profile_idc;
info->level_idc = syn->level_idc;
info->keyframe_max_interval = syn->keyframe_max_interval;
info->second_chroma_qp_index_offset = syn->second_chroma_qp_index_offset;
info->pps_id = syn->pps_id;
info->frame_rate = 30;
}

32
mpp/hal/rkenc/h264e/hal_h264e_rkv.c
View File

@@ -301,20 +301,12 @@ static void hal_h264e_rkv_dump_mpp_syntax_in(H264eHwCfg *syn, h264e_hal_context
fprintf(fp, "%-16d %s\n", syn->width, "pic_luma_width");
fprintf(fp, "%-16d %s\n", syn->height, "pic_luma_height");
fprintf(fp, "%-16d %s\n", syn->level_idc, "level_idc");
fprintf(fp, "%-16d %s\n", syn->profile_idc, "profile_idc");
fprintf(fp, "%-16d %s\n", syn->coding_type, "frame_coding_type");
fprintf(fp, "%-16d %s\n", syn->qp, "swreg10.pic_qp");
fprintf(fp, "%-16d %s\n", syn->input_format, "swreg14.src_cfmt");
fprintf(fp, "%-16d %s\n", syn->enable_cabac, "swreg59.etpy_mode");
fprintf(fp, "%-16d %s\n", syn->chroma_qp_index_offset, "swreg59.cb_ofst");
fprintf(fp, "%-16d %s\n", syn->second_chroma_qp_index_offset, "swreg59.cr_ofst");
fprintf(fp, "%-16d %s\n", syn->frame_type, "swreg60.sli_type");
fprintf(fp, "%-16d %s\n", syn->pps_id, "swreg60.pps_id");
fprintf(fp, "%-16d %s\n", syn->frame_num, "swreg60.frm_num");
fprintf(fp, "%-16d %s\n", syn->cabac_init_idc, "swreg60.cbc_init_idc");
fprintf(fp, "%-16d %s\n", syn->idr_pic_id, "swreg61.idr_pid");
fprintf(fp, "%-16d %s\n", syn->pic_order_cnt_lsb, "swreg61.poc_lsb");
@@ -2719,19 +2711,12 @@ static MPP_RET hal_h264e_rkv_update_hw_cfg(h264e_hal_context *ctx, HalEncTask *t
if (codec->change) {
// TODO: setup sps / pps here
hw_cfg->pps_id = 0;
hw_cfg->idr_pic_id = !ctx->idr_pic_id;
hw_cfg->enable_cabac = codec->entropy_coding_mode;
hw_cfg->cabac_init_idc = codec->cabac_init_idc;
hw_cfg->transform8x8_mode = codec->transform8x8_mode;
hw_cfg->chroma_qp_index_offset = codec->chroma_cb_qp_offset;
hw_cfg->second_chroma_qp_index_offset = codec->chroma_cr_qp_offset;
hw_cfg->filter_disable = codec->deblock_disable;
hw_cfg->slice_alpha_offset = codec->deblock_offset_alpha;
hw_cfg->slice_beta_offset = codec->deblock_offset_beta;
hw_cfg->inter4x4_disabled = (codec->profile >= 31) ? (1) : (0);
hw_cfg->constrained_intra_prediction = codec->constrained_intra_pred_mode;
hw_cfg->cabac_init_idc = codec->cabac_init_idc;
hw_cfg->qp = codec->qp_init;
hw_cfg->qp_prev = hw_cfg->qp;
@@ -2872,7 +2857,6 @@ static MPP_RET hal_h264e_rkv_update_hw_cfg(h264e_hal_context *ctx, HalEncTask *t
MPP_RET hal_h264e_rkv_gen_regs(void *hal, HalTaskInfo *task)
{
h264e_hal_context *ctx = (h264e_hal_context *)hal;
h264e_hal_param *par = &ctx->param;
h264e_rkv_reg_set *regs = NULL;
h264e_rkv_ioctl_reg_info *ioctl_reg_info = NULL;
H264eHwCfg *syn = &ctx->hw_cfg;
@@ -3139,14 +3123,8 @@ MPP_RET hal_h264e_rkv_gen_regs(void *hal, HalTaskInfo *task)
regs->swreg56.rect_size = (sps->i_profile_idc == H264_PROFILE_BASELINE && sps->i_level_idc <= 30);
regs->swreg56.inter_4x4 = 1;
regs->swreg56.arb_sel = 0; //syn->swreg56.arb_sel;
regs->swreg56.vlc_lmt = (sps->i_profile_idc < H264_PROFILE_HIGH && !syn->enable_cabac);
regs->swreg56.vlc_lmt = (sps->i_profile_idc < H264_PROFILE_HIGH && !pps->b_cabac);
regs->swreg56.rdo_mark = 0; //syn->swreg56.rdo_mark;
/*if (syn->transform8x8_mode == 0 && (syn->swreg56.rdo_mark & 0xb5) == 0xb5) //NOTE: bug may exist here
{
h264e_hal_log_err("RdoMark and trans8x8 conflict!");
mpp_assert(0);
return MPP_NOK;
}*/
{
RK_U32 i_nal_type = 0, i_nal_ref_idc = 0;
@@ -3179,9 +3157,9 @@ MPP_RET hal_h264e_rkv_gen_regs(void *hal, HalTaskInfo *task)
regs->swreg58.drct_8x8 = 1; //syn->swreg58.drct_8x8;
regs->swreg58.mpoc_lm4 = sps->i_log2_max_poc_lsb - 4; //syn->swreg58.mpoc_lm4;
regs->swreg59.etpy_mode = syn->enable_cabac;
regs->swreg59.etpy_mode = pps->b_cabac;
regs->swreg59.trns_8x8 = pps->b_transform_8x8_mode; //syn->swreg59.trns_8x8;
regs->swreg59.csip_flg = par->constrained_intra; //syn->swreg59.csip_flg;
regs->swreg59.csip_flg = pps->b_constrained_intra_pred;
regs->swreg59.num_ref0_idx = pps->i_num_ref_idx_l0_default_active - 1; //syn->swreg59.num_ref0_idx;
regs->swreg59.num_ref1_idx = pps->i_num_ref_idx_l1_default_active - 1; //syn->swreg59.num_ref1_idx;
regs->swreg59.pic_init_qp = pps->i_pic_init_qp - H264_QP_BD_OFFSET;
@@ -3191,7 +3169,7 @@ MPP_RET hal_h264e_rkv_gen_regs(void *hal, HalTaskInfo *task)
regs->swreg59.dbf_cp_flg = 1; //syn->deblocking_filter_control;
regs->swreg60.sli_type = syn->frame_type; //syn->swreg60.sli_type;
regs->swreg60.pps_id = syn->pps_id;
regs->swreg60.pps_id = pps->i_id;
regs->swreg60.drct_smvp = 0x0;
regs->swreg60.num_ref_ovrd = 0;
regs->swreg60.cbc_init_idc = syn->cabac_init_idc;

29
mpp/hal/vpu/h264e/hal_h264e_vpu.c
View File

@@ -123,16 +123,11 @@ static void hal_h264e_vpu_dump_mpp_syntax_in(H264eHwCfg *syn, h264e_hal_context
fprintf(fp, "%-16d %s\n", syn->frame_type, "frame_coding_type");
fprintf(fp, "%-16d %s\n", syn->slice_alpha_offset, "slice_alpha_offset");
fprintf(fp, "%-16d %s\n", syn->slice_beta_offset, "slice_beta_offset");
fprintf(fp, "%-16d %s\n", syn->chroma_qp_index_offset, "chroma_qp_index_offset");
fprintf(fp, "%-16d %s\n", syn->filter_disable, "filter_disable");
fprintf(fp, "%-16d %s\n", syn->idr_pic_id, "idr_pic_id");
fprintf(fp, "%-16d %s\n", syn->pps_id, "pps_id");
fprintf(fp, "%-16d %s\n", syn->frame_num, "frame_num");
fprintf(fp, "%-16d %s\n", syn->slice_size_mb_rows, "slice_size_mb_rows");
fprintf(fp, "%-16d %s\n", syn->inter4x4_disabled, "h264_inter4x4_disabled");
fprintf(fp, "%-16d %s\n", syn->enable_cabac, "enable_cabac");
fprintf(fp, "%-16d %s\n", syn->transform8x8_mode, "transform8x8_mode");
fprintf(fp, "%-16d %s\n", syn->cabac_init_idc, "cabac_init_idc");
fprintf(fp, "%-16d %s\n", syn->qp, "qp");
fprintf(fp, "%-16d %s\n", syn->mad_qp_delta, "mad_qp_delta");
fprintf(fp, "%-16d %s\n", syn->mad_threshold, "mad_threshold");
@@ -343,7 +338,7 @@ static void hal_h264e_vpu_swap_endian(RK_U32 *buf, RK_S32 size_bytes)
}
}
static void hal_h264e_vpu_write_cabac_table(MppBuffer hw_cabac_tab_buf, RK_U32 cabac_init_idc)
static void hal_h264e_vpu_write_cabac_table(MppBuffer hw_cabac_tab_buf, RK_S32 cabac_init_idc)
{
const RK_S32(*context)[460][2];
RK_S32 i, j, qp;
@@ -1030,19 +1025,12 @@ static MPP_RET hal_h264e_vpu_update_hw_cfg(h264e_hal_context *ctx, HalEncTask *t
if (codec->change) {
// TODO: setup sps / pps here
hw_cfg->pps_id = 0;
hw_cfg->idr_pic_id = !ctx->idr_pic_id;
hw_cfg->enable_cabac = codec->entropy_coding_mode;
hw_cfg->cabac_init_idc = codec->cabac_init_idc;
hw_cfg->transform8x8_mode = codec->transform8x8_mode;
hw_cfg->chroma_qp_index_offset = codec->chroma_cb_qp_offset;
hw_cfg->second_chroma_qp_index_offset = codec->chroma_cr_qp_offset;
hw_cfg->filter_disable = codec->deblock_disable;
hw_cfg->slice_alpha_offset = codec->deblock_offset_alpha;
hw_cfg->slice_beta_offset = codec->deblock_offset_beta;
hw_cfg->inter4x4_disabled = (codec->profile >= 31) ? (1) : (0);
hw_cfg->constrained_intra_prediction = codec->constrained_intra_pred_mode;
hw_cfg->cabac_init_idc = codec->cabac_init_idc;
hw_cfg->qp = codec->qp_init;
hw_cfg->qp_prev = hw_cfg->qp;
@@ -1141,7 +1129,6 @@ MPP_RET hal_h264e_vpu_gen_regs(void *hal, HalTaskInfo *task)
h264e_hal_vpu_extra_info *extra_info = (h264e_hal_vpu_extra_info *)ctx->extra_info;
h264e_hal_pps *pps = &extra_info->pps;
h264e_hal_vpu_buffers *bufs = (h264e_hal_vpu_buffers *)ctx->buffers;
MppEncH264Cfg *codec = &ctx->cfg->codec.h264;
MppEncPrepCfg *prep = &ctx->cfg->prep;
H264eHwCfg *hw_cfg = &ctx->hw_cfg;
RK_U32 *reg = (RK_U32 *)ctx->regs;
@@ -1212,10 +1199,10 @@ MPP_RET hal_h264e_vpu_gen_regs(void *hal, HalTaskInfo *task)
val = 0;
if (mb_w * mb_h > 3600)
val = VEPU_REG_DISABLE_QUARTER_PIXEL_MV;
val |= VEPU_REG_CABAC_INIT_IDC(codec->cabac_init_idc);
if (codec->entropy_coding_mode)
val |= VEPU_REG_CABAC_INIT_IDC(hw_cfg->cabac_init_idc);
if (pps->b_cabac)
val |= VEPU_REG_ENTROPY_CODING_MODE;
if (codec->transform8x8_mode)
if (pps->b_transform_8x8_mode)
val |= VEPU_REG_H264_TRANS8X8_MODE;
if (hw_cfg->inter4x4_disabled)
val |= VEPU_REG_H264_INTER4X4_MODE;
@@ -1296,13 +1283,13 @@ MPP_RET hal_h264e_vpu_gen_regs(void *hal, HalTaskInfo *task)
val = VEPU_REG_PPS_INIT_QP(pps->i_pic_init_qp)
| VEPU_REG_SLICE_FILTER_ALPHA(hw_cfg->slice_alpha_offset)
| VEPU_REG_SLICE_FILTER_BETA(hw_cfg->slice_beta_offset)
| VEPU_REG_CHROMA_QP_OFFSET(hw_cfg->chroma_qp_index_offset)
| VEPU_REG_CHROMA_QP_OFFSET(pps->i_chroma_qp_index_offset)
| VEPU_REG_IDR_PIC_ID(hw_cfg->idr_pic_id);
if (hw_cfg->filter_disable)
val |= VEPU_REG_FILTER_DISABLE;
if (hw_cfg->constrained_intra_prediction)
if (pps->b_constrained_intra_pred)
val |= VEPU_REG_CONSTRAINED_INTRA_PREDICTION;
H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL2, val);
@@ -1370,7 +1357,7 @@ MPP_RET hal_h264e_vpu_gen_regs(void *hal, HalTaskInfo *task)
| VEPU_REG_INPUT_SWAP32;
H264E_HAL_SET_REG(reg, VEPU_REG_DATA_ENDIAN, val);
val = VEPU_REG_PPS_ID(hw_cfg->pps_id)
val = VEPU_REG_PPS_ID(pps->i_id)
| VEPU_REG_INTRA_PRED_MODE(h264_prev_mode_favor[hw_cfg->qp])
| VEPU_REG_FRAME_NUM(hw_cfg->frame_num);
H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL3, val);