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fix[hal_h265e_vepu510]: Add cudecis reg cfg
Change-Id: I392c58ca6d11f9a3a7f5578170c345aada32260b Signed-off-by: Yanjun Liao <yanjun.liao@rock-chips.com>
This commit is contained in:
Yanjun Liao
@@ -430,6 +430,142 @@ typedef struct Vepu510SqiCfg_t {
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RK_U32 i_cu16_madi_cost_multi : 8;
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RK_U32 reserved : 8;
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} rdo_atr_i_cu16_madi_cfg0;
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/* 0x00002100 reg2112 */
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struct {
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RK_U32 base_thre_rough_mad32_intra : 4;
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RK_U32 delta0_thre_rough_mad32_intra : 4;
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RK_U32 delta1_thre_rough_mad32_intra : 6;
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RK_U32 delta2_thre_rough_mad32_intra : 6;
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RK_U32 delta3_thre_rough_mad32_intra : 7;
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RK_U32 delta4_thre_rough_mad32_intra_low5 : 5;
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} cudecis_thd0;
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/* 0x00002104 reg2113 */
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struct {
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RK_U32 delta4_thre_rough_mad32_intra_high2 : 2;
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RK_U32 delta5_thre_rough_mad32_intra : 7;
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RK_U32 delta6_thre_rough_mad32_intra : 7;
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RK_U32 base_thre_fine_mad32_intra : 4;
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RK_U32 delta0_thre_fine_mad32_intra : 4;
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RK_U32 delta1_thre_fine_mad32_intra : 5;
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RK_U32 delta2_thre_fine_mad32_intra_low3 : 3;
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} cudecis_thd1;
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/* 0x00002108 reg2114 */
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struct {
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RK_U32 delta2_thre_fine_mad32_intra_high2 : 2;
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RK_U32 delta3_thre_fine_mad32_intra : 5;
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RK_U32 delta4_thre_fine_mad32_intra : 5;
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RK_U32 delta5_thre_fine_mad32_intra : 6;
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RK_U32 delta6_thre_fine_mad32_intra : 6;
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RK_U32 base_thre_str_edge_mad32_intra : 3;
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RK_U32 delta0_thre_str_edge_mad32_intra : 2;
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RK_U32 delta1_thre_str_edge_mad32_intra : 3;
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} cudecis_thd2;
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/* 0x0000210c reg2115 */
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struct {
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RK_U32 delta2_thre_str_edge_mad32_intra : 3;
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RK_U32 delta3_thre_str_edge_mad32_intra : 4;
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RK_U32 base_thre_str_edge_bgrad32_intra : 5;
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RK_U32 delta0_thre_str_edge_bgrad32_intra : 2;
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RK_U32 delta1_thre_str_edge_bgrad32_intra : 3;
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RK_U32 delta2_thre_str_edge_bgrad32_intra : 4;
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RK_U32 delta3_thre_str_edge_bgrad32_intra : 5;
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RK_U32 base_thre_mad16_intra : 3;
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RK_U32 delta0_thre_mad16_intra : 3;
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} cudecis_thd3;
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/* 0x00002110 reg2116 */
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struct {
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RK_U32 delta1_thre_mad16_intra : 3;
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RK_U32 delta2_thre_mad16_intra : 4;
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RK_U32 delta3_thre_mad16_intra : 5;
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RK_U32 delta4_thre_mad16_intra : 5;
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RK_U32 delta5_thre_mad16_intra : 6;
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RK_U32 delta6_thre_mad16_intra : 6;
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RK_U32 delta0_thre_mad16_ratio_intra : 3;
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} cudecis_thd4;
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/* 0x00002114 reg2117 */
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struct {
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RK_U32 delta1_thre_mad16_ratio_intra : 3;
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RK_U32 delta2_thre_mad16_ratio_intra : 3;
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RK_U32 delta3_thre_mad16_ratio_intra : 3;
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RK_U32 delta4_thre_mad16_ratio_intra : 3;
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RK_U32 delta5_thre_mad16_ratio_intra : 3;
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RK_U32 delta6_thre_mad16_ratio_intra : 3;
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RK_U32 delta7_thre_mad16_ratio_intra : 3;
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RK_U32 delta0_thre_rough_bgrad32_intra : 3;
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RK_U32 delta1_thre_rough_bgrad32_intra : 4;
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RK_U32 delta2_thre_rough_bgrad32_intra_low4 : 4;
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} cudecis_thd5;
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/* 0x00002118 reg2118 */
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struct {
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RK_U32 delta2_thre_rough_bgrad32_intra_high2 : 2;
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RK_U32 delta3_thre_rough_bgrad32_intra : 10;
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RK_U32 delta4_thre_rough_bgrad32_intra : 10;
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RK_U32 delta5_thre_rough_bgrad32_intra_low10 : 10;
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} cudecis_thd6;
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/* 0x0000211c reg2119 */
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struct {
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RK_U32 delta5_thre_rough_bgrad32_intra_high1 : 1;
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RK_U32 delta6_thre_rough_bgrad32_intra : 12;
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RK_U32 delta7_thre_rough_bgrad32_intra : 13;
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RK_U32 delta0_thre_bgrad16_ratio_intra : 4;
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RK_U32 delta1_thre_bgrad16_ratio_intra_low2 : 2;
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} cudecis_thd7;
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/* 0x00002120 reg2120 */
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struct {
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RK_U32 delta1_thre_bgrad16_ratio_intra_high2 : 2;
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RK_U32 delta2_thre_bgrad16_ratio_intra : 4;
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RK_U32 delta3_thre_bgrad16_ratio_intra : 4;
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RK_U32 delta4_thre_bgrad16_ratio_intra : 4;
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RK_U32 delta5_thre_bgrad16_ratio_intra : 4;
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RK_U32 delta6_thre_bgrad16_ratio_intra : 4;
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RK_U32 delta7_thre_bgrad16_ratio_intra : 4;
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RK_U32 delta0_thre_fme_ratio_inter : 3;
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RK_U32 delta1_thre_fme_ratio_inter : 3;
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} cudecis_thdt8;
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/* 0x00002124 reg2121 */
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struct {
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RK_U32 delta2_thre_fme_ratio_inter : 3;
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RK_U32 delta3_thre_fme_ratio_inter : 3;
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RK_U32 delta4_thre_fme_ratio_inter : 3;
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RK_U32 delta5_thre_fme_ratio_inter : 3;
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RK_U32 delta6_thre_fme_ratio_inter : 3;
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RK_U32 delta7_thre_fme_ratio_inter : 3;
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RK_U32 base_thre_fme32_inter : 3;
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RK_U32 delta0_thre_fme32_inter : 3;
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RK_U32 delta1_thre_fme32_inter : 4;
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RK_U32 delta2_thre_fme32_inter : 4;
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} cudecis_thd9;
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/* 0x00002128 reg2122 */
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struct {
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RK_U32 delta3_thre_fme32_inter : 5;
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RK_U32 delta4_thre_fme32_inter : 6;
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RK_U32 delta5_thre_fme32_inter : 7;
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RK_U32 delta6_thre_fme32_inter : 8;
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RK_U32 thre_cme32_inter : 6;
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} cudecis_thd10;
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/* 0x0000212c reg2123 */
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struct {
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RK_U32 delta0_thre_mad_fme_ratio_inter : 4;
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RK_U32 delta1_thre_mad_fme_ratio_inter : 4;
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RK_U32 delta2_thre_mad_fme_ratio_inter : 4;
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RK_U32 delta3_thre_mad_fme_ratio_inter : 4;
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RK_U32 delta4_thre_mad_fme_ratio_inter : 4;
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RK_U32 delta5_thre_mad_fme_ratio_inter : 4;
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RK_U32 delta6_thre_mad_fme_ratio_inter : 4;
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RK_U32 delta7_thre_mad_fme_ratio_inter : 4;
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} cudecis_thd11;
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} Vepu510Sqi;
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typedef struct Vepu510RoiRegion_t {
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@@ -481,6 +481,118 @@ static void vepu510_h265_rdo_cfg (Vepu510Sqi *reg)
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reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_thd0 = 4;
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reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_thd1 = 6;
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reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_cost_multi = 24;
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/* 0x00002100 reg2112 */
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reg->cudecis_thd0.base_thre_rough_mad32_intra = 9;
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reg->cudecis_thd0.delta0_thre_rough_mad32_intra = 10;
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reg->cudecis_thd0.delta1_thre_rough_mad32_intra = 55;
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reg->cudecis_thd0.delta2_thre_rough_mad32_intra = 55;
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reg->cudecis_thd0.delta3_thre_rough_mad32_intra = 66;
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reg->cudecis_thd0.delta4_thre_rough_mad32_intra_low5 = 2;
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/* 0x00002104 reg2113 */
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reg->cudecis_thd1.delta4_thre_rough_mad32_intra_high2 = 2;
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reg->cudecis_thd1.delta5_thre_rough_mad32_intra = 74;
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reg->cudecis_thd1.delta6_thre_rough_mad32_intra = 106;
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reg->cudecis_thd1.base_thre_fine_mad32_intra = 8;
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reg->cudecis_thd1.delta0_thre_fine_mad32_intra = 0;
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reg->cudecis_thd1.delta1_thre_fine_mad32_intra = 13;
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reg->cudecis_thd1.delta2_thre_fine_mad32_intra_low3 = 6;
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/* 0x00002108 reg2114 */
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reg->cudecis_thd2.delta2_thre_fine_mad32_intra_high2 = 1;
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reg->cudecis_thd2.delta3_thre_fine_mad32_intra = 17;
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reg->cudecis_thd2.delta4_thre_fine_mad32_intra = 23;
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reg->cudecis_thd2.delta5_thre_fine_mad32_intra = 50;
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reg->cudecis_thd2.delta6_thre_fine_mad32_intra = 54;
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reg->cudecis_thd2.base_thre_str_edge_mad32_intra = 6;
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reg->cudecis_thd2.delta0_thre_str_edge_mad32_intra = 0;
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reg->cudecis_thd2.delta1_thre_str_edge_mad32_intra = 0;
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/* 0x0000210c reg2115 */
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reg->cudecis_thd3.delta2_thre_str_edge_mad32_intra = 3;
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reg->cudecis_thd3.delta3_thre_str_edge_mad32_intra = 8;
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reg->cudecis_thd3.base_thre_str_edge_bgrad32_intra = 25;
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reg->cudecis_thd3.delta0_thre_str_edge_bgrad32_intra = 0;
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reg->cudecis_thd3.delta1_thre_str_edge_bgrad32_intra = 0;
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reg->cudecis_thd3.delta2_thre_str_edge_bgrad32_intra = 7;
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reg->cudecis_thd3.delta3_thre_str_edge_bgrad32_intra = 0;
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reg->cudecis_thd3.base_thre_mad16_intra = 6;
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reg->cudecis_thd3.delta0_thre_mad16_intra = 0;
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/* 0x00002110 reg2116 */
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reg->cudecis_thd4.delta1_thre_mad16_intra = 3;
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reg->cudecis_thd4.delta2_thre_mad16_intra = 3;
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reg->cudecis_thd4.delta3_thre_mad16_intra = 24;
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reg->cudecis_thd4.delta4_thre_mad16_intra = 28;
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reg->cudecis_thd4.delta5_thre_mad16_intra = 40;
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reg->cudecis_thd4.delta6_thre_mad16_intra = 52;
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reg->cudecis_thd4.delta0_thre_mad16_ratio_intra = 7;
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/* 0x00002114 reg2117 */
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reg->cudecis_thd5.delta1_thre_mad16_ratio_intra = 7;
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reg->cudecis_thd5.delta2_thre_mad16_ratio_intra = 2;
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reg->cudecis_thd5.delta3_thre_mad16_ratio_intra = 2;
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reg->cudecis_thd5.delta4_thre_mad16_ratio_intra = 0;
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reg->cudecis_thd5.delta5_thre_mad16_ratio_intra = 0;
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reg->cudecis_thd5.delta6_thre_mad16_ratio_intra = 0;
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reg->cudecis_thd5.delta7_thre_mad16_ratio_intra = 4;
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reg->cudecis_thd5.delta0_thre_rough_bgrad32_intra = 1;
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reg->cudecis_thd5.delta1_thre_rough_bgrad32_intra = 5;
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reg->cudecis_thd5.delta2_thre_rough_bgrad32_intra_low4 = 8;
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/* 0x00002118 reg2118 */
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reg->cudecis_thd6.delta2_thre_rough_bgrad32_intra_high2 = 2;
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reg->cudecis_thd6.delta3_thre_rough_bgrad32_intra = 540;
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reg->cudecis_thd6.delta4_thre_rough_bgrad32_intra = 692;
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reg->cudecis_thd6.delta5_thre_rough_bgrad32_intra_low10 = 866;
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/* 0x0000211c reg2119 */
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reg->cudecis_thd7.delta5_thre_rough_bgrad32_intra_high1 = 1;
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reg->cudecis_thd7.delta6_thre_rough_bgrad32_intra = 3286;
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reg->cudecis_thd7.delta7_thre_rough_bgrad32_intra = 6620;
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reg->cudecis_thd7.delta0_thre_bgrad16_ratio_intra = 8;
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reg->cudecis_thd7.delta1_thre_bgrad16_ratio_intra_low2 = 3;
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/* 0x00002120 reg2120 */
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reg->cudecis_thdt8.delta1_thre_bgrad16_ratio_intra_high2 = 2;
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reg->cudecis_thdt8.delta2_thre_bgrad16_ratio_intra = 15;
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reg->cudecis_thdt8.delta3_thre_bgrad16_ratio_intra = 15;
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reg->cudecis_thdt8.delta4_thre_bgrad16_ratio_intra = 13;
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reg->cudecis_thdt8.delta5_thre_bgrad16_ratio_intra = 13;
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reg->cudecis_thdt8.delta6_thre_bgrad16_ratio_intra = 7;
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reg->cudecis_thdt8.delta7_thre_bgrad16_ratio_intra = 15;
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reg->cudecis_thdt8.delta0_thre_fme_ratio_inter = 4;
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reg->cudecis_thdt8.delta1_thre_fme_ratio_inter = 4;
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/* 0x00002124 reg2121 */
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reg->cudecis_thd9.delta2_thre_fme_ratio_inter = 3;
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reg->cudecis_thd9.delta3_thre_fme_ratio_inter = 2;
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reg->cudecis_thd9.delta4_thre_fme_ratio_inter = 0;
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reg->cudecis_thd9.delta5_thre_fme_ratio_inter = 0;
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reg->cudecis_thd9.delta6_thre_fme_ratio_inter = 0;
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reg->cudecis_thd9.delta7_thre_fme_ratio_inter = 0;
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reg->cudecis_thd9.base_thre_fme32_inter = 4;
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reg->cudecis_thd9.delta0_thre_fme32_inter = 2;
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reg->cudecis_thd9.delta1_thre_fme32_inter = 7;
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reg->cudecis_thd9.delta2_thre_fme32_inter = 12;
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/* 0x00002128 reg2122 */
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reg->cudecis_thd10.delta3_thre_fme32_inter = 23;
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reg->cudecis_thd10.delta4_thre_fme32_inter = 41;
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reg->cudecis_thd10.delta5_thre_fme32_inter = 71;
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reg->cudecis_thd10.delta6_thre_fme32_inter = 123;
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reg->cudecis_thd10.thre_cme32_inter = 48;
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/* 0x0000212c reg2123 */
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reg->cudecis_thd11.delta0_thre_mad_fme_ratio_inter = 0;
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reg->cudecis_thd11.delta1_thre_mad_fme_ratio_inter = 7;
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reg->cudecis_thd11.delta2_thre_mad_fme_ratio_inter = 7;
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reg->cudecis_thd11.delta3_thre_mad_fme_ratio_inter = 6;
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reg->cudecis_thd11.delta4_thre_mad_fme_ratio_inter = 5;
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reg->cudecis_thd11.delta5_thre_mad_fme_ratio_inter = 4;
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reg->cudecis_thd11.delta6_thre_mad_fme_ratio_inter = 4;
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reg->cudecis_thd11.delta7_thre_mad_fme_ratio_inter = 4;
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}
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static void vepu510_h265_global_cfg_set(H265eV510HalContext *ctx, H265eV510RegSet *regs)
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