From be2dfdbd0a9bbf7e476bfdb83e74c6078885dff5 Mon Sep 17 00:00:00 2001 From: Yanjun Liao Date: Fri, 8 Mar 2024 17:00:53 +0800 Subject: [PATCH] fix[hal_h265e_vepu510]: Add cudecis reg cfg Change-Id: I392c58ca6d11f9a3a7f5578170c345aada32260b Signed-off-by: Yanjun Liao --- mpp/hal/rkenc/common/vepu510_common.h | 136 ++++++++++++++++++++++++ mpp/hal/rkenc/h265e/hal_h265e_vepu510.c | 112 +++++++++++++++++++ 2 files changed, 248 insertions(+) diff --git a/mpp/hal/rkenc/common/vepu510_common.h b/mpp/hal/rkenc/common/vepu510_common.h index d2e4a406..6173f820 100644 --- a/mpp/hal/rkenc/common/vepu510_common.h +++ b/mpp/hal/rkenc/common/vepu510_common.h @@ -430,6 +430,142 @@ typedef struct Vepu510SqiCfg_t { RK_U32 i_cu16_madi_cost_multi : 8; RK_U32 reserved : 8; } rdo_atr_i_cu16_madi_cfg0; + + /* 0x00002100 reg2112 */ + struct { + RK_U32 base_thre_rough_mad32_intra : 4; + RK_U32 delta0_thre_rough_mad32_intra : 4; + RK_U32 delta1_thre_rough_mad32_intra : 6; + RK_U32 delta2_thre_rough_mad32_intra : 6; + RK_U32 delta3_thre_rough_mad32_intra : 7; + RK_U32 delta4_thre_rough_mad32_intra_low5 : 5; + } cudecis_thd0; + + /* 0x00002104 reg2113 */ + struct { + RK_U32 delta4_thre_rough_mad32_intra_high2 : 2; + RK_U32 delta5_thre_rough_mad32_intra : 7; + RK_U32 delta6_thre_rough_mad32_intra : 7; + RK_U32 base_thre_fine_mad32_intra : 4; + RK_U32 delta0_thre_fine_mad32_intra : 4; + RK_U32 delta1_thre_fine_mad32_intra : 5; + RK_U32 delta2_thre_fine_mad32_intra_low3 : 3; + } cudecis_thd1; + + /* 0x00002108 reg2114 */ + struct { + RK_U32 delta2_thre_fine_mad32_intra_high2 : 2; + RK_U32 delta3_thre_fine_mad32_intra : 5; + RK_U32 delta4_thre_fine_mad32_intra : 5; + RK_U32 delta5_thre_fine_mad32_intra : 6; + RK_U32 delta6_thre_fine_mad32_intra : 6; + RK_U32 base_thre_str_edge_mad32_intra : 3; + RK_U32 delta0_thre_str_edge_mad32_intra : 2; + RK_U32 delta1_thre_str_edge_mad32_intra : 3; + } cudecis_thd2; + + /* 0x0000210c reg2115 */ + struct { + RK_U32 delta2_thre_str_edge_mad32_intra : 3; + RK_U32 delta3_thre_str_edge_mad32_intra : 4; + RK_U32 base_thre_str_edge_bgrad32_intra : 5; + RK_U32 delta0_thre_str_edge_bgrad32_intra : 2; + RK_U32 delta1_thre_str_edge_bgrad32_intra : 3; + RK_U32 delta2_thre_str_edge_bgrad32_intra : 4; + RK_U32 delta3_thre_str_edge_bgrad32_intra : 5; + RK_U32 base_thre_mad16_intra : 3; + RK_U32 delta0_thre_mad16_intra : 3; + } cudecis_thd3; + + /* 0x00002110 reg2116 */ + struct { + RK_U32 delta1_thre_mad16_intra : 3; + RK_U32 delta2_thre_mad16_intra : 4; + RK_U32 delta3_thre_mad16_intra : 5; + RK_U32 delta4_thre_mad16_intra : 5; + RK_U32 delta5_thre_mad16_intra : 6; + RK_U32 delta6_thre_mad16_intra : 6; + RK_U32 delta0_thre_mad16_ratio_intra : 3; + } cudecis_thd4; + + /* 0x00002114 reg2117 */ + struct { + RK_U32 delta1_thre_mad16_ratio_intra : 3; + RK_U32 delta2_thre_mad16_ratio_intra : 3; + RK_U32 delta3_thre_mad16_ratio_intra : 3; + RK_U32 delta4_thre_mad16_ratio_intra : 3; + RK_U32 delta5_thre_mad16_ratio_intra : 3; + RK_U32 delta6_thre_mad16_ratio_intra : 3; + RK_U32 delta7_thre_mad16_ratio_intra : 3; + RK_U32 delta0_thre_rough_bgrad32_intra : 3; + RK_U32 delta1_thre_rough_bgrad32_intra : 4; + RK_U32 delta2_thre_rough_bgrad32_intra_low4 : 4; + } cudecis_thd5; + + /* 0x00002118 reg2118 */ + struct { + RK_U32 delta2_thre_rough_bgrad32_intra_high2 : 2; + RK_U32 delta3_thre_rough_bgrad32_intra : 10; + RK_U32 delta4_thre_rough_bgrad32_intra : 10; + RK_U32 delta5_thre_rough_bgrad32_intra_low10 : 10; + } cudecis_thd6; + + /* 0x0000211c reg2119 */ + struct { + RK_U32 delta5_thre_rough_bgrad32_intra_high1 : 1; + RK_U32 delta6_thre_rough_bgrad32_intra : 12; + RK_U32 delta7_thre_rough_bgrad32_intra : 13; + RK_U32 delta0_thre_bgrad16_ratio_intra : 4; + RK_U32 delta1_thre_bgrad16_ratio_intra_low2 : 2; + } cudecis_thd7; + + /* 0x00002120 reg2120 */ + struct { + RK_U32 delta1_thre_bgrad16_ratio_intra_high2 : 2; + RK_U32 delta2_thre_bgrad16_ratio_intra : 4; + RK_U32 delta3_thre_bgrad16_ratio_intra : 4; + RK_U32 delta4_thre_bgrad16_ratio_intra : 4; + RK_U32 delta5_thre_bgrad16_ratio_intra : 4; + RK_U32 delta6_thre_bgrad16_ratio_intra : 4; + RK_U32 delta7_thre_bgrad16_ratio_intra : 4; + RK_U32 delta0_thre_fme_ratio_inter : 3; + RK_U32 delta1_thre_fme_ratio_inter : 3; + } cudecis_thdt8; + + /* 0x00002124 reg2121 */ + struct { + RK_U32 delta2_thre_fme_ratio_inter : 3; + RK_U32 delta3_thre_fme_ratio_inter : 3; + RK_U32 delta4_thre_fme_ratio_inter : 3; + RK_U32 delta5_thre_fme_ratio_inter : 3; + RK_U32 delta6_thre_fme_ratio_inter : 3; + RK_U32 delta7_thre_fme_ratio_inter : 3; + RK_U32 base_thre_fme32_inter : 3; + RK_U32 delta0_thre_fme32_inter : 3; + RK_U32 delta1_thre_fme32_inter : 4; + RK_U32 delta2_thre_fme32_inter : 4; + } cudecis_thd9; + + /* 0x00002128 reg2122 */ + struct { + RK_U32 delta3_thre_fme32_inter : 5; + RK_U32 delta4_thre_fme32_inter : 6; + RK_U32 delta5_thre_fme32_inter : 7; + RK_U32 delta6_thre_fme32_inter : 8; + RK_U32 thre_cme32_inter : 6; + } cudecis_thd10; + + /* 0x0000212c reg2123 */ + struct { + RK_U32 delta0_thre_mad_fme_ratio_inter : 4; + RK_U32 delta1_thre_mad_fme_ratio_inter : 4; + RK_U32 delta2_thre_mad_fme_ratio_inter : 4; + RK_U32 delta3_thre_mad_fme_ratio_inter : 4; + RK_U32 delta4_thre_mad_fme_ratio_inter : 4; + RK_U32 delta5_thre_mad_fme_ratio_inter : 4; + RK_U32 delta6_thre_mad_fme_ratio_inter : 4; + RK_U32 delta7_thre_mad_fme_ratio_inter : 4; + } cudecis_thd11; } Vepu510Sqi; typedef struct Vepu510RoiRegion_t { diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu510.c b/mpp/hal/rkenc/h265e/hal_h265e_vepu510.c index cb3cb9cc..2b6454b6 100644 --- a/mpp/hal/rkenc/h265e/hal_h265e_vepu510.c +++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu510.c @@ -481,6 +481,118 @@ static void vepu510_h265_rdo_cfg (Vepu510Sqi *reg) reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_thd0 = 4; reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_thd1 = 6; reg->rdo_atr_i_cu16_madi_cfg0.i_cu16_madi_cost_multi = 24; + + /* 0x00002100 reg2112 */ + reg->cudecis_thd0.base_thre_rough_mad32_intra = 9; + reg->cudecis_thd0.delta0_thre_rough_mad32_intra = 10; + reg->cudecis_thd0.delta1_thre_rough_mad32_intra = 55; + reg->cudecis_thd0.delta2_thre_rough_mad32_intra = 55; + reg->cudecis_thd0.delta3_thre_rough_mad32_intra = 66; + reg->cudecis_thd0.delta4_thre_rough_mad32_intra_low5 = 2; + + /* 0x00002104 reg2113 */ + reg->cudecis_thd1.delta4_thre_rough_mad32_intra_high2 = 2; + reg->cudecis_thd1.delta5_thre_rough_mad32_intra = 74; + reg->cudecis_thd1.delta6_thre_rough_mad32_intra = 106; + reg->cudecis_thd1.base_thre_fine_mad32_intra = 8; + reg->cudecis_thd1.delta0_thre_fine_mad32_intra = 0; + reg->cudecis_thd1.delta1_thre_fine_mad32_intra = 13; + reg->cudecis_thd1.delta2_thre_fine_mad32_intra_low3 = 6; + + /* 0x00002108 reg2114 */ + reg->cudecis_thd2.delta2_thre_fine_mad32_intra_high2 = 1; + reg->cudecis_thd2.delta3_thre_fine_mad32_intra = 17; + reg->cudecis_thd2.delta4_thre_fine_mad32_intra = 23; + reg->cudecis_thd2.delta5_thre_fine_mad32_intra = 50; + reg->cudecis_thd2.delta6_thre_fine_mad32_intra = 54; + reg->cudecis_thd2.base_thre_str_edge_mad32_intra = 6; + reg->cudecis_thd2.delta0_thre_str_edge_mad32_intra = 0; + reg->cudecis_thd2.delta1_thre_str_edge_mad32_intra = 0; + + /* 0x0000210c reg2115 */ + reg->cudecis_thd3.delta2_thre_str_edge_mad32_intra = 3; + reg->cudecis_thd3.delta3_thre_str_edge_mad32_intra = 8; + reg->cudecis_thd3.base_thre_str_edge_bgrad32_intra = 25; + reg->cudecis_thd3.delta0_thre_str_edge_bgrad32_intra = 0; + reg->cudecis_thd3.delta1_thre_str_edge_bgrad32_intra = 0; + reg->cudecis_thd3.delta2_thre_str_edge_bgrad32_intra = 7; + reg->cudecis_thd3.delta3_thre_str_edge_bgrad32_intra = 0; + reg->cudecis_thd3.base_thre_mad16_intra = 6; + reg->cudecis_thd3.delta0_thre_mad16_intra = 0; + + /* 0x00002110 reg2116 */ + reg->cudecis_thd4.delta1_thre_mad16_intra = 3; + reg->cudecis_thd4.delta2_thre_mad16_intra = 3; + reg->cudecis_thd4.delta3_thre_mad16_intra = 24; + reg->cudecis_thd4.delta4_thre_mad16_intra = 28; + reg->cudecis_thd4.delta5_thre_mad16_intra = 40; + reg->cudecis_thd4.delta6_thre_mad16_intra = 52; + reg->cudecis_thd4.delta0_thre_mad16_ratio_intra = 7; + + /* 0x00002114 reg2117 */ + reg->cudecis_thd5.delta1_thre_mad16_ratio_intra = 7; + reg->cudecis_thd5.delta2_thre_mad16_ratio_intra = 2; + reg->cudecis_thd5.delta3_thre_mad16_ratio_intra = 2; + reg->cudecis_thd5.delta4_thre_mad16_ratio_intra = 0; + reg->cudecis_thd5.delta5_thre_mad16_ratio_intra = 0; + reg->cudecis_thd5.delta6_thre_mad16_ratio_intra = 0; + reg->cudecis_thd5.delta7_thre_mad16_ratio_intra = 4; + reg->cudecis_thd5.delta0_thre_rough_bgrad32_intra = 1; + reg->cudecis_thd5.delta1_thre_rough_bgrad32_intra = 5; + reg->cudecis_thd5.delta2_thre_rough_bgrad32_intra_low4 = 8; + + /* 0x00002118 reg2118 */ + reg->cudecis_thd6.delta2_thre_rough_bgrad32_intra_high2 = 2; + reg->cudecis_thd6.delta3_thre_rough_bgrad32_intra = 540; + reg->cudecis_thd6.delta4_thre_rough_bgrad32_intra = 692; + reg->cudecis_thd6.delta5_thre_rough_bgrad32_intra_low10 = 866; + + /* 0x0000211c reg2119 */ + reg->cudecis_thd7.delta5_thre_rough_bgrad32_intra_high1 = 1; + reg->cudecis_thd7.delta6_thre_rough_bgrad32_intra = 3286; + reg->cudecis_thd7.delta7_thre_rough_bgrad32_intra = 6620; + reg->cudecis_thd7.delta0_thre_bgrad16_ratio_intra = 8; + reg->cudecis_thd7.delta1_thre_bgrad16_ratio_intra_low2 = 3; + + /* 0x00002120 reg2120 */ + reg->cudecis_thdt8.delta1_thre_bgrad16_ratio_intra_high2 = 2; + reg->cudecis_thdt8.delta2_thre_bgrad16_ratio_intra = 15; + reg->cudecis_thdt8.delta3_thre_bgrad16_ratio_intra = 15; + reg->cudecis_thdt8.delta4_thre_bgrad16_ratio_intra = 13; + reg->cudecis_thdt8.delta5_thre_bgrad16_ratio_intra = 13; + reg->cudecis_thdt8.delta6_thre_bgrad16_ratio_intra = 7; + reg->cudecis_thdt8.delta7_thre_bgrad16_ratio_intra = 15; + reg->cudecis_thdt8.delta0_thre_fme_ratio_inter = 4; + reg->cudecis_thdt8.delta1_thre_fme_ratio_inter = 4; + + /* 0x00002124 reg2121 */ + reg->cudecis_thd9.delta2_thre_fme_ratio_inter = 3; + reg->cudecis_thd9.delta3_thre_fme_ratio_inter = 2; + reg->cudecis_thd9.delta4_thre_fme_ratio_inter = 0; + reg->cudecis_thd9.delta5_thre_fme_ratio_inter = 0; + reg->cudecis_thd9.delta6_thre_fme_ratio_inter = 0; + reg->cudecis_thd9.delta7_thre_fme_ratio_inter = 0; + reg->cudecis_thd9.base_thre_fme32_inter = 4; + reg->cudecis_thd9.delta0_thre_fme32_inter = 2; + reg->cudecis_thd9.delta1_thre_fme32_inter = 7; + reg->cudecis_thd9.delta2_thre_fme32_inter = 12; + + /* 0x00002128 reg2122 */ + reg->cudecis_thd10.delta3_thre_fme32_inter = 23; + reg->cudecis_thd10.delta4_thre_fme32_inter = 41; + reg->cudecis_thd10.delta5_thre_fme32_inter = 71; + reg->cudecis_thd10.delta6_thre_fme32_inter = 123; + reg->cudecis_thd10.thre_cme32_inter = 48; + + /* 0x0000212c reg2123 */ + reg->cudecis_thd11.delta0_thre_mad_fme_ratio_inter = 0; + reg->cudecis_thd11.delta1_thre_mad_fme_ratio_inter = 7; + reg->cudecis_thd11.delta2_thre_mad_fme_ratio_inter = 7; + reg->cudecis_thd11.delta3_thre_mad_fme_ratio_inter = 6; + reg->cudecis_thd11.delta4_thre_mad_fme_ratio_inter = 5; + reg->cudecis_thd11.delta5_thre_mad_fme_ratio_inter = 4; + reg->cudecis_thd11.delta6_thre_mad_fme_ratio_inter = 4; + reg->cudecis_thd11.delta7_thre_mad_fme_ratio_inter = 4; } static void vepu510_h265_global_cfg_set(H265eV510HalContext *ctx, H265eV510RegSet *regs)