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[mpp_enc_ref]: Add vepu541 H.264 reference process
Add vepu541 H.264 reorder / mmco process. Change-Id: I434a539a111ec749f89d1485d6cab7b4106d4d89 Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
This commit is contained in:
Herman Chen
@@ -225,8 +225,10 @@ static MPP_RET hal_h264e_vepu541_get_task(void *hal, HalEncTask *task)
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{
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HalH264eVepu541Ctx *ctx = (HalH264eVepu541Ctx *)hal;
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RK_U32 updated = update_vepu541_syntax(ctx, &task->syntax);
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MppEncPrepCfg *prep = &ctx->cfg->prep;
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MppEncCfgSet *cfg = ctx->cfg;
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MppEncPrepCfg *prep = &cfg->prep;
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EncFrmStatus *frm_status = &task->rc_task->frm;
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hal_h264e_dbg_func("enter %p\n", hal);
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if (updated & SYN_TYPE_FLAG(H264E_SYN_CFG)) {
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@@ -242,8 +244,14 @@ static MPP_RET hal_h264e_vepu541_get_task(void *hal, HalEncTask *task)
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(ctx->pixel_buf_fbc_bdy_size != pixel_buf_fbc_bdy_size) ||
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(ctx->pixel_buf_size != pixel_buf_size) ||
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(ctx->thumb_buf_size != thumb_buf_size)) {
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MppEncRefCfg ref_cfg = cfg->ref_cfg;
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size_t sizes[2];
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RK_S32 max_cnt = ctx->sps->num_ref_frames + 1;
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RK_S32 max_cnt = 2;
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if (ref_cfg) {
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MppEncCpbInfo *info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
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max_cnt = MPP_MAX(max_cnt, info->dpb_size + 1);
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}
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/* pixel buffer */
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sizes[0] = pixel_buf_size;
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@@ -471,43 +479,175 @@ static void setup_vepu541_codec(Vepu541H264eRegSet *regs, SynH264eSps *sps,
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regs->reg107.idr_pic_id = (slice->slice_type == H264_I_SLICE) ? slice->idr_pic_id : (RK_U32)(-1);
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regs->reg107.poc_lsb = slice->pic_order_cnt_lsb;
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// TODO: reorder implement
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regs->reg108.ref_list0_rodr = 0; //slice->ref_pic_list_modification_flag;
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regs->reg108.rodr_pic_idx = 0;
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regs->reg108.dis_dblk_idc = slice->disable_deblocking_filter_idc;
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regs->reg108.sli_alph_ofst = slice->slice_alpha_c0_offset_div2;
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regs->reg108.rodr_pic_num = 0;
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if (slice->slice_type == H264_I_SLICE) {
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regs->reg109.nopp_flg = slice->no_output_of_prior_pics;
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regs->reg109.ltrf_flg = slice->long_term_reference_flag;
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regs->reg109.arpm_flg = 0;
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regs->reg109.mmco4_pre = 0;
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regs->reg109.mmco_type0 = 0;
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regs->reg109.mmco_parm0 = 0;
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regs->reg109.mmco_type1 = 0;
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regs->reg110.mmco_parm1 = 0;
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regs->reg109.mmco_type2 = 0;
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regs->reg110.mmco_parm2 = 0;
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} else {
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regs->reg109.nopp_flg = 0;
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regs->reg109.ltrf_flg = 0;
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regs->reg109.arpm_flg = 0;
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regs->reg109.mmco4_pre = 0;
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regs->reg109.mmco_type0 = 0;
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regs->reg109.mmco_parm0 = 0;
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regs->reg109.mmco_type1 = 0;
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regs->reg110.mmco_parm1 = 0;
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regs->reg109.mmco_type2 = 0;
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regs->reg110.mmco_parm2 = 0;
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{ /* reorder process */
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H264eRplmo rplmo;
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MPP_RET ret = h264e_reorder_rd_op(slice->reorder, &rplmo);
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if (MPP_OK == ret) {
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regs->reg108.ref_list0_rodr = 1;
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regs->reg108.rodr_pic_idx = rplmo.modification_of_pic_nums_idc;
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switch (rplmo.modification_of_pic_nums_idc) {
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case 0 :
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case 1 : {
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regs->reg108.rodr_pic_num = rplmo.abs_diff_pic_num_minus1;
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} break;
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case 2 : {
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regs->reg108.rodr_pic_num = rplmo.long_term_pic_idx;
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} break;
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default : {
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mpp_err_f("invalid modification_of_pic_nums_idc %d\n",
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rplmo.modification_of_pic_nums_idc);
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} break;
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}
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} else {
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// slice->ref_pic_list_modification_flag;
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regs->reg108.ref_list0_rodr = 0;
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regs->reg108.rodr_pic_idx = 0;
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regs->reg108.rodr_pic_num = 0;
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}
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}
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/* clear all mmco arg first */
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regs->reg109.nopp_flg = 0;
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regs->reg109.ltrf_flg = 0;
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regs->reg109.arpm_flg = 0;
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regs->reg109.mmco4_pre = 0;
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regs->reg109.mmco_type0 = 0;
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regs->reg109.mmco_parm0 = 0;
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regs->reg109.mmco_type1 = 0;
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regs->reg110.mmco_parm1 = 0;
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regs->reg109.mmco_type2 = 0;
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regs->reg110.mmco_parm2 = 0;
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regs->reg114.long_term_frame_idx0 = 0;
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regs->reg114.long_term_frame_idx1 = 0;
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regs->reg114.long_term_frame_idx2 = 0;
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regs->reg115.dlt_poc_s0_m12 = 0;
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regs->reg115.dlt_poc_s0_m13 = 0;
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/* only update used parameter */
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if (slice->slice_type == H264_I_SLICE) {
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regs->reg109.nopp_flg = slice->no_output_of_prior_pics;
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regs->reg109.ltrf_flg = slice->long_term_reference_flag;
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} else {
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if (!h264e_marking_is_empty(slice->marking)) {
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H264eMmco mmco;
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regs->reg109.arpm_flg = 1;
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/* max 3 mmco */
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do {
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RK_S32 type = 0;
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RK_S32 param_0 = 0;
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RK_S32 param_1 = 0;
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h264e_marking_rd_op(slice->marking, &mmco);
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type = mmco.mmco;
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switch (type) {
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case 1 : {
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param_0 = mmco.difference_of_pic_nums_minus1;
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} break;
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case 2 : {
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param_0 = mmco.long_term_pic_num;
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} break;
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case 3 : {
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param_0 = mmco.difference_of_pic_nums_minus1;
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param_1 = mmco.long_term_frame_idx;
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} break;
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case 4 : {
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param_0 = mmco.max_long_term_frame_idx_plus1;
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} break;
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case 5 : {
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} break;
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case 6 : {
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param_0 = mmco.long_term_frame_idx;
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} break;
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default : {
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mpp_err_f("unsupported mmco 0 %d\n", type);
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type = 0;
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} break;
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}
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regs->reg109.mmco_type0 = type;
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regs->reg109.mmco_parm0 = param_0;
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regs->reg114.long_term_frame_idx0 = param_1;
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if (h264e_marking_is_empty(slice->marking))
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break;
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h264e_marking_rd_op(slice->marking, &mmco);
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type = mmco.mmco;
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param_0 = 0;
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param_1 = 0;
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switch (type) {
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case 1 : {
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param_0 = mmco.difference_of_pic_nums_minus1;
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} break;
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case 2 : {
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param_0 = mmco.long_term_pic_num;
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} break;
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case 3 : {
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param_0 = mmco.difference_of_pic_nums_minus1;
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param_1 = mmco.long_term_frame_idx;
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} break;
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case 4 : {
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param_0 = mmco.max_long_term_frame_idx_plus1;
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} break;
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case 5 : {
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} break;
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case 6 : {
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param_0 = mmco.long_term_frame_idx;
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} break;
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default : {
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mpp_err_f("unsupported mmco 0 %d\n", type);
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type = 0;
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} break;
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}
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regs->reg109.mmco_type1 = type;
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regs->reg110.mmco_parm1 = param_0;
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regs->reg114.long_term_frame_idx1 = param_1;
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if (h264e_marking_is_empty(slice->marking))
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break;
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h264e_marking_rd_op(slice->marking, &mmco);
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type = mmco.mmco;
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param_0 = 0;
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param_1 = 0;
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switch (type) {
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case 1 : {
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param_0 = mmco.difference_of_pic_nums_minus1;
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} break;
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case 2 : {
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param_0 = mmco.long_term_pic_num;
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} break;
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case 3 : {
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param_0 = mmco.difference_of_pic_nums_minus1;
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param_1 = mmco.long_term_frame_idx;
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} break;
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case 4 : {
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param_0 = mmco.max_long_term_frame_idx_plus1;
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} break;
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case 5 : {
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} break;
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case 6 : {
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param_0 = mmco.long_term_frame_idx;
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} break;
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default : {
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mpp_err_f("unsupported mmco 0 %d\n", type);
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type = 0;
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} break;
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}
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regs->reg109.mmco_type2 = type;
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regs->reg110.mmco_parm2 = param_0;
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regs->reg114.long_term_frame_idx2 = param_1;
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} while (0);
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}
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}
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hal_h264e_dbg_func("leave\n");
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}
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@@ -1724,14 +1724,9 @@ typedef struct Vepu541H264eRegSet_t {
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/*
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* SYNT_REFM3
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* Address offset: 0x01CC Access type: read and write
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* Reference frame mark3 for H.264
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* Reference frame mark3 for HEVC
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*/
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struct {
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/* delta_poc_s0_minus1[2] */
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RK_U32 dlt_poc_s0_m12 : 16;
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/* delta_poc_s0_minus1[3] */
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RK_U32 dlt_poc_s0_m13 : 16;
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} reg115;
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RK_U32 reg115;
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/*
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* OSD_POS
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