[hal_av1d]: Implement av1 decoder hal module

Change-Id: I9dc410b55cc614e7a4a6353d52a70c806e467b2e
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>

mpp/hal/CMakeLists.txt

@@ -32,6 +32,7 @@ target_link_libraries(mpp_hal
                       ${HAL_VP8D}
                       ${HAL_VP9D}
                       ${HAL_JPEGD}
+                      ${HAL_AV1D}
                       ${HAL_H264E}
                       ${HAL_JPEGE}
                       ${HAL_H265E}

mpp/hal/inc/hal_av1d_api.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright 2021 Rockchip Electronics Co. LTD
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __HAL_AV1D_API_H__
+#define __HAL_AV1D_API_H__
+
+#include "mpp_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const MppHalApi hal_api_av1d;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__HAL_H265D_API_H__*/

mpp/hal/mpp_hal.cpp

@@ -33,6 +33,7 @@
 #include "hal_m2vd_api.h"
 #include "hal_mpg4d_api.h"
 #include "hal_jpegd_api.h"
+#include "hal_av1d_api.h"
 
 // for test and demo
 #include "hal_dummy_dec_api.h"
@@ -68,6 +69,9 @@ static const MppHalApi *hw_apis[] = {
 #endif
 #if HAVE_JPEGD
     &hal_api_jpegd,
+#endif
+#if HAVE_AV1D
+    &hal_api_av1d,
 #endif
     &hal_api_dummy_dec,
     &hal_api_dummy_enc,

mpp/hal/vpu/CMakeLists.txt

@@ -22,6 +22,10 @@ if( HAVE_JPEGD )
     add_subdirectory(jpegd)
 endif()
 
+if( HAVE_AV1D )
+    add_subdirectory(av1d)
+endif()
+
 if( HAVE_JPEGE )
     add_subdirectory(jpege)
 endif()

mpp/hal/vpu/av1d/CMakeLists.txt

@@ -0,0 +1,22 @@
+# vim: syntax=cmake
+# hal jpeg reg
+
+set(HAL_AV1D_HDR
+    hal_av1d_common.h
+    )
+
+set(HAL_AV1D_SRC
+    hal_av1d_api.c
+    hal_av1d_vdpu.c
+    film_grain_noise_table.c
+    )
+
+add_library(${HAL_AV1D} STATIC
+            ${HAL_AV1D_SRC}
+            ${HAL_AV1D_HDR}
+            )
+
+set_target_properties(${HAL_AV1D} PROPERTIES FOLDER "mpp/hal")
+target_link_libraries(${HAL_AV1D} mpp_base)
+
+#add_subdirectory(test)

mpp/hal/vpu/av1d/av1d_common.h

@@ -0,0 +1,840 @@
+/*
+ * Copyright 2021 Rockchip Electronics Co. LTD
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AV1D_COMMON_H__
+#define __AV1D_COMMON_H__
+
+#include "mpp_common.h"
+#include "hal_av1d_common.h"
+#define AV1_REF_SCALE_SHIFT 14
+
+#define NUM_REF_FRAMES 8
+#define NUM_REF_FRAMES_LG2 3
+
+// Max tiles for AV1 (custom size) for Level <= 6.x
+#define AV1_MAX_TILES 128
+#define AV1_MAX_TILE_COL 64
+#define AV1_MAX_TILE_ROW 64
+
+#define AV1_MIN_COMP_BASIS 8
+#define AV1_MAX_CODED_FRAME_SIZE \
+  (8192 * 4352 * 10 * 6 / 32 / AV1_MIN_COMP_BASIS) /* approx 8 MB */
+
+#define ALLOWED_REFS_PER_FRAME_EX 7
+
+#define NUM_FRAME_CONTEXTS_LG2_EX 3
+#define NUM_FRAME_CONTEXTS_EX (1 << NUM_FRAME_CONTEXTS_LG2_EX)
+
+#define MIN_TILE_WIDTH 256
+#define MAX_TILE_WIDTH 4096
+#define MIN_TILE_WIDTH_SBS (MIN_TILE_WIDTH >> 6)
+#define MAX_TILE_WIDTH_SBS (MAX_TILE_WIDTH >> 6)
+#define FRAME_OFFSET_BITS 5
+#define MAX_TILE_AREA (4096 * 2304)
+#define AV1_MAX_TILE_COLS 64
+#define AV1_MAX_TILE_ROWS 64
+
+#define ALLOWED_REFS_PER_FRAME 3
+
+#define NUM_FRAME_CONTEXTS_LG2 2
+#define NUM_FRAME_CONTEXTS (1 << NUM_FRAME_CONTEXTS_LG2)
+
+#define DCPREDSIMTHRESH 0
+#define DCPREDCNTTHRESH 3
+
+#define PREDICTION_PROBS 3
+
+#define DEFAULT_PRED_PROB_0 120
+#define DEFAULT_PRED_PROB_1 80
+#define DEFAULT_PRED_PROB_2 40
+
+#define AV1_DEF_UPDATE_PROB 252
+
+#define MBSKIP_CONTEXTS 3
+
+#define MAX_MB_SEGMENTS 8
+#define MB_SEG_TREE_PROBS (MAX_MB_SEGMENTS - 1)
+
+#define MAX_REF_LF_DELTAS_EX 8
+
+#define MAX_REF_LF_DELTAS 4
+#define MAX_MODE_LF_DELTAS 2
+
+/* Segment Feature Masks */
+#define SEGMENT_DELTADATA 0
+#define SEGMENT_ABSDATA 1
+#define MAX_MV_REFS 9
+
+#define AV1_SWITCHABLE_FILTERS 3 /* number of switchable filters */
+#define SWITCHABLE_FILTER_CONTEXTS ((AV1_SWITCHABLE_FILTERS + 1) * 4)
+#ifdef DUAL_FILTER
+#define AV1_SWITCHABLE_EXT_FILTERS 4 /* number of switchable filters */
+#endif
+
+#define COMP_PRED_CONTEXTS 2
+
+#define COEF_UPDATE_PROB 252
+#define AV1_PROB_HALF 128
+#define AV1_NMV_UPDATE_PROB 252
+#define AV1_MV_UPDATE_PRECISION 7
+#define MV_JOINTS 4
+#define MV_FP_SIZE 4
+#define MV_CLASSES 11
+#define CLASS0_BITS 1
+#define CLASS0_SIZE (1 << CLASS0_BITS)
+#define MV_OFFSET_BITS (MV_CLASSES + CLASS0_BITS - 2)
+
+#define MV_MAX_BITS (MV_CLASSES + CLASS0_BITS + 2)
+#define MV_MAX ((1 << MV_MAX_BITS) - 1)
+#define MV_VALS ((MV_MAX << 1) + 1)
+
+#define MAX_ENTROPY_TOKENS 12
+#define ENTROPY_NODES 11
+
+/* The first nodes of the entropy probs are unconstrained, the rest are
+ * modeled with statistic distribution. */
+#define UNCONSTRAINED_NODES 3
+#define MODEL_NODES (ENTROPY_NODES - UNCONSTRAINED_NODES)
+#define PIVOT_NODE 2  // which node is pivot
+#define COEFPROB_MODELS 128
+
+/* Entropy nodes above is divided in two parts, first three probs in part1
+ * and the modeled probs in part2. Part1 is padded so that tables align with
+ *  32 byte addresses, so there is four bytes for each table. */
+#define ENTROPY_NODES_PART1 4
+#define ENTROPY_NODES_PART2 8
+#define INTER_MODE_CONTEXTS 7
+#define AV1_INTER_MODE_CONTEXTS 15
+
+#define CFL_JOINT_SIGNS 8
+#define CFL_ALPHA_CONTEXTS 6
+#define CFL_ALPHABET_SIZE 16
+
+#define NEWMV_MODE_CONTEXTS 6
+#define ZEROMV_MODE_CONTEXTS 2
+#define GLOBALMV_MODE_CONTEXTS 2
+#define REFMV_MODE_CONTEXTS 9
+#define DRL_MODE_CONTEXTS 3
+#define NMV_CONTEXTS 3
+
+#define INTRA_INTER_CONTEXTS 4
+#define COMP_INTER_CONTEXTS 5
+#define REF_CONTEXTS 5
+#define AV1_REF_CONTEXTS 3
+#define FWD_REFS 4
+#define BWD_REFS 3
+#define SINGLE_REFS 7
+
+#define BLOCK_TYPES 2
+#define REF_TYPES 2  // intra=0, inter=1
+#define COEF_BANDS 6
+#define PREV_COEF_CONTEXTS 6
+
+#define MODULUS_PARAM 13 /* Modulus parameter */
+
+#define ACTIVE_HT 110  // quantization stepsize threshold
+
+#define MAX_MV_REF_CANDIDATES 2
+
+/* Coefficient token alphabet */
+
+#define ZERO_TOKEN 0         /* 0         Extra Bits 0+0 */
+#define ONE_TOKEN 1          /* 1         Extra Bits 0+1 */
+#define TWO_TOKEN 2          /* 2         Extra Bits 0+1 */
+#define THREE_TOKEN 3        /* 3         Extra Bits 0+1 */
+#define FOUR_TOKEN 4         /* 4         Extra Bits 0+1 */
+#define DCT_VAL_CATEGORY1 5  /* 5-6       Extra Bits 1+1 */
+#define DCT_VAL_CATEGORY2 6  /* 7-10      Extra Bits 2+1 */
+#define DCT_VAL_CATEGORY3 7  /* 11-18     Extra Bits 3+1 */
+#define DCT_VAL_CATEGORY4 8  /* 19-34     Extra Bits 4+1 */
+#define DCT_VAL_CATEGORY5 9  /* 35-66     Extra Bits 5+1 */
+#define DCT_VAL_CATEGORY6 10 /* 67+       Extra Bits 13+1 */
+#define DCT_EOB_TOKEN 11     /* EOB       Extra Bits 0+0 */
+#define MAX_ENTROPY_TOKENS 12
+
+#define INTERINTRA_MODES 4
+#define INTER_COMPOUND_MODES 8
+#define COMPOUND_TYPES 3
+#define HEAD_TOKENS 5
+#define TAIL_TOKENS 9
+#define ONE_TOKEN_EOB 1
+#define ONE_TOKEN_NEOB 2
+
+#define MULTICORE_LEFT_TILE 1
+#define MULTICORE_INNER_TILE 2
+#define MULTICORE_RIGHT_TILE 3
+
+#define DCT_EOB_MODEL_TOKEN 3 /* EOB       Extra Bits 0+0 */
+
+typedef RK_U32 av1_coeff_count[REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS]
+[UNCONSTRAINED_NODES + 1];
+typedef RK_U8 av1_coeff_probs[REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS]
+[UNCONSTRAINED_NODES];
+
+#define BLOCK_SIZE_GROUPS 4
+
+// AV1 extended transforms (ext_tx)
+#define EXT_TX_SETS_INTER 4  // Sets of transform selections for INTER
+#define EXT_TX_SETS_INTRA 3  // Sets of transform selections for INTRA
+#define EXTTX_SIZES 4        // ext_tx experiment tx sizes
+#define EXT_TX_TYPES 16
+
+#define EXT_TX_SIZES 3
+
+#define TX_TYPES 4
+
+#define ROUND_POWER_OF_TWO(value, n) (((value) + (1 << ((n)-1))) >> (n))
+
+/* Shift down with rounding for use when n >= 0, value >= 0 for (64 bit) */
+#define ROUND_POWER_OF_TWO_64(value, n) \
+    (((value) + ((((int64)1 << (n)) >> 1))) >> (n))
+
+/* Shift down with rounding for signed integers, for use when n >= 0 (64 bit) */
+#define ROUND_POWER_OF_TWO_SIGNED_64(value, n) \
+    (((value) < 0) ? -ROUND_POWER_OF_TWO_64(-(value), (n)) \
+                   : ROUND_POWER_OF_TWO_64((value), (n)))
+
+/* Shift down with rounding for signed integers, for use when n >= 0 */
+#define ROUND_POWER_OF_TWO_SIGNED(value, n) \
+    (((value) < 0) ? -ROUND_POWER_OF_TWO(-(value), (n)) \
+                   : ROUND_POWER_OF_TWO((value), (n)))
+
+typedef RK_U16 av1_cdf;
+
+enum BlockSizeType {
+    BLOCK_SIZE_AB4X4,
+    BLOCK_SIZE_SB4X8,
+    BLOCK_SIZE_SB8X4,
+    BLOCK_SIZE_SB8X8,
+    BLOCK_SIZE_SB8X16,
+    BLOCK_SIZE_SB16X8,
+    BLOCK_SIZE_MB16X16,
+    BLOCK_SIZE_SB16X32,
+    BLOCK_SIZE_SB32X16,
+    BLOCK_SIZE_SB32X32,
+    BLOCK_SIZE_SB32X64,
+    BLOCK_SIZE_SB64X32,
+    BLOCK_SIZE_SB64X64,
+    BLOCK_SIZE_SB64X128,
+    BLOCK_SIZE_SB128X64,
+    BLOCK_SIZE_SB128X128,
+    BLOCK_SIZE_SB4X16,
+    BLOCK_SIZE_SB16X4,
+    BLOCK_SIZE_SB8X32,
+    BLOCK_SIZE_SB32X8,
+    BLOCK_SIZE_SB16X64,
+    BLOCK_SIZE_SB64X16,
+    BLOCK_SIZE_TYPES,
+    BLOCK_SIZES_ALL = BLOCK_SIZE_TYPES
+};
+
+enum PartitionType {
+    PARTITION_NONE,
+    PARTITION_HORZ,
+    PARTITION_VERT,
+    PARTITION_SPLIT,
+    /*
+    PARTITION_HORZ_A,
+    PARTITION_HORZ_B,
+    PARTITION_VERT_A,
+    PARTITION_VERT_B,
+    PARTITION_HORZ_4,
+    PARTITION_VERT_4,
+    */
+    PARTITION_TYPES
+};
+
+#define PARTITION_PLOFFSET 4  // number of probability models per block size
+#define NUM_PARTITION_CONTEXTS (4 * PARTITION_PLOFFSET)
+
+enum FrameType {
+    KEY_FRAME = 0,
+    INTER_FRAME = 1,
+    NUM_FRAME_TYPES,
+};
+
+enum MbPredictionMode {
+    DC_PRED,  /* average of above and left pixels */
+    V_PRED,   /* vertical prediction */
+    H_PRED,   /* horizontal prediction */
+    D45_PRED, /* Directional 45 deg prediction  [anti-clockwise from 0 deg hor] */
+    D135_PRED, /* Directional 135 deg prediction [anti-clockwise from 0 deg hor]
+              */
+    D117_PRED, /* Directional 112 deg prediction [anti-clockwise from 0 deg hor]
+              */
+    D153_PRED, /* Directional 157 deg prediction [anti-clockwise from 0 deg hor]
+              */
+    D27_PRED, /* Directional 22 deg prediction  [anti-clockwise from 0 deg hor] */
+    D63_PRED, /* Directional 67 deg prediction  [anti-clockwise from 0 deg hor] */
+    SMOOTH_PRED,
+    TM_PRED_AV1 = SMOOTH_PRED,
+    SMOOTH_V_PRED,  // Vertical interpolation
+    SMOOTH_H_PRED,  // Horizontal interpolation
+    TM_PRED,        /* Truemotion prediction */
+    PAETH_PRED = TM_PRED,
+    NEARESTMV,
+    NEARMV,
+    ZEROMV,
+    NEWMV,
+    NEAREST_NEARESTMV,
+    NEAR_NEARMV,
+    NEAREST_NEWMV,
+    NEW_NEARESTMV,
+    NEAR_NEWMV,
+    NEW_NEARMV,
+    ZERO_ZEROMV,
+    NEW_NEWMV,
+    SPLITMV,
+    MB_MODE_COUNT
+};
+
+// Must match hardware/src/include/common_defs.h
+#define AV1_INTRA_MODES 13
+
+#define MAX_INTRA_MODES AV1_INTRA_MODES
+
+#define MAX_INTRA_MODES_DRAM_ALIGNED ((MAX_INTRA_MODES + 15) & (~15))
+
+#define AV1_INTER_MODES (1 + NEWMV - NEARESTMV)
+
+#define MOTION_MODE_CONTEXTS 10
+
+#define DIRECTIONAL_MODES 8
+#define MAX_ANGLE_DELTA 3
+
+enum FilterIntraModeType {
+    FILTER_DC_PRED,
+    FILTER_V_PRED,
+    FILTER_H_PRED,
+    FILTER_D153_PRED,
+    FILTER_PAETH_PRED,
+    FILTER_INTRA_MODES,
+    FILTER_INTRA_UNUSED = 7
+};
+
+#define FILTER_INTRA_SIZES 19
+
+enum { SIMPLE_TRANSLATION, OBMC_CAUSAL, MOTION_MODE_COUNT };
+
+#define SUBMVREF_COUNT 5
+
+/* Integer pel reference mv threshold for use of high-precision 1/8 mv */
+#define COMPANDED_MVREF_THRESH 8
+
+#define TX_SIZE_CONTEXTS 2
+#define AV1_TX_SIZE_CONTEXTS 3
+#define VARTX_PART_CONTEXTS 22
+#define TXFM_PARTITION_CONTEXTS 22
+
+enum InterpolationFilterType {
+    EIGHTTAP_SMOOTH,
+    EIGHTTAP,
+    EIGHTTAP_SHARP,
+#ifdef DUAL_FILTER
+    EIGHTTAP_SMOOTH2,
+    BILINEAR,
+    SWITCHABLE, /* should be the last one */
+#else
+    BILINEAR,
+    SWITCHABLE, /* should be the last one */
+#endif
+    MULTITAP_SHARP = EIGHTTAP_SHARP
+};
+
+static const int av1_literal_to_filter[4] = {
+    EIGHTTAP_SMOOTH, EIGHTTAP,
+    EIGHTTAP_SHARP, BILINEAR
+};
+
+extern const enum InterpolationFilterType
+av1hwd_switchable_interp[AV1_SWITCHABLE_FILTERS];
+
+enum CompPredModeType {
+    SINGLE_PREDICTION_ONLY = 0,
+    COMP_PREDICTION_ONLY = 1,
+    HYBRID_PREDICTION = 2,
+    NB_PREDICTION_TYPES = 3,
+};
+
+enum TxfmMode {
+    ONLY_4X4 = 0,
+    ALLOW_8X8 = 1,
+    ALLOW_16X16 = 2,
+    ALLOW_32X32 = 3,
+    TX_MODE_LARGEST = ALLOW_32X32,  // AV1
+    TX_MODE_SELECT = 4,
+    NB_TXFM_MODES = 5,
+};
+
+enum SegLevelFeatures {
+    SEG_LVL_ALT_Q = 0,
+    SEG_LVL_ALT_LF = 1,
+    SEG_LVL_REF_FRAME = 2,
+    SEG_LVL_SKIP = 3,
+    SEG_LVL_MAX = 4
+};
+
+enum { AV1_SEG_FEATURE_DELTA, AV1_SEG_FEATURE_ABS };
+
+static const int av1_seg_feature_data_signed[SEG_AV1_LVL_MAX] = {
+    1, 1, 1, 1,
+    1, 0, 0
+};
+
+static const int av1_seg_feature_data_max[SEG_AV1_LVL_MAX] = {
+    255, 63, 63, 63,
+    63,  7,  0
+};
+
+static const int av1_seg_feature_data_bits[SEG_AV1_LVL_MAX] = {
+    8, 6, 6, 6,
+    6, 3, 0
+};
+
+enum TxSize {
+    TX_4X4 = 0,
+    TX_8X8 = 1,
+    TX_16X16 = 2,
+    TX_32X32 = 3,
+    TX_SIZE_MAX_SB,
+};
+#define MAX_TX_DEPTH 2
+
+enum TxType { DCT_DCT = 0, ADST_DCT = 1, DCT_ADST = 2, ADST_ADST = 3 };
+
+enum SplitMvPartitioningType {
+    PARTITIONING_16X8 = 0,
+    PARTITIONING_8X16,
+    PARTITIONING_8X8,
+    PARTITIONING_4X4,
+    NB_PARTITIONINGS,
+};
+
+enum PredId {
+    PRED_SEG_ID = 0,
+    PRED_MBSKIP = 1,
+    PRED_SWITCHABLE_INTERP = 2,
+    PRED_INTRA_INTER = 3,
+    PRED_COMP_INTER_INTER = 4,
+    PRED_SINGLE_REF_P1 = 5,
+    PRED_SINGLE_REF_P2 = 6,
+    PRED_COMP_REF_P = 7,
+    PRED_TX_SIZE = 8
+};
+
+/* Symbols for coding which components are zero jointly */
+enum MvJointType {
+    MV_JOINT_ZERO = 0,   /* Zero vector */
+    MV_JOINT_HNZVZ = 1,  /* Vert zero, hor nonzero */
+    MV_JOINT_HZVNZ = 2,  /* Hor zero, vert nonzero */
+    MV_JOINT_HNZVNZ = 3, /* Both components nonzero */
+};
+
+/* Symbols for coding magnitude class of nonzero components */
+enum MvClassType {
+    MV_CLASS_0 = 0,   /* (0, 2]     integer pel */
+    MV_CLASS_1 = 1,   /* (2, 4]     integer pel */
+    MV_CLASS_2 = 2,   /* (4, 8]     integer pel */
+    MV_CLASS_3 = 3,   /* (8, 16]    integer pel */
+    MV_CLASS_4 = 4,   /* (16, 32]   integer pel */
+    MV_CLASS_5 = 5,   /* (32, 64]   integer pel */
+    MV_CLASS_6 = 6,   /* (64, 128]  integer pel */
+    MV_CLASS_7 = 7,   /* (128, 256] integer pel */
+    MV_CLASS_8 = 8,   /* (256, 512] integer pel */
+    MV_CLASS_9 = 9,   /* (512, 1024] integer pel */
+    MV_CLASS_10 = 10, /* (1024,2048] integer pel */
+};
+
+enum RefreshFrameContextModeAv1 {
+    /**
+     * AV1 Only, no refresh
+     */
+    AV1_REFRESH_FRAME_CONTEXT_NONE,
+    /**
+     * Update frame context to values resulting from backward probability
+     * updates based on entropy/counts in the decoded frame
+     */
+    AV1_REFRESH_FRAME_CONTEXT_BACKWARD
+};
+
+// 75B
+struct NmvContext {
+    // Start at +27B offset
+    RK_U8 joints[MV_JOINTS - 1];  // 3B
+    RK_U8 sign[2];                // 2B
+
+    // A+1
+    RK_U8 class0[2][CLASS0_SIZE - 1];  // 2B
+    RK_U8 fp[2][MV_FP_SIZE - 1];       // 6B
+    RK_U8 class0_hp[2];                // 2B
+    RK_U8 hp[2];                       // 2B
+    RK_U8 classes[2][MV_CLASSES - 1];  // 20B
+
+    // A+2
+    RK_U8 class0_fp[2][CLASS0_SIZE][MV_FP_SIZE - 1];  // 12B
+    RK_U8 bits[2][MV_OFFSET_BITS];                    // 20B
+};
+
+struct NmvContextCounts {
+    // 8dw (u32) / DRAM word (u256)
+    RK_U32 joints[MV_JOINTS];
+    RK_U32 sign[2][2];
+    RK_U32 classes[2][MV_CLASSES];
+    RK_U32 class0[2][CLASS0_SIZE];
+    RK_U32 bits[2][MV_OFFSET_BITS][2];
+    RK_U32 class0_fp[2][CLASS0_SIZE][4];
+    RK_U32 fp[2][4];
+    RK_U32 class0_hp[2][2];
+    RK_U32 hp[2][2];
+};
+
+typedef RK_U8 av1_prob;
+
+#define ICDF(x) (32768U - (x))
+#define CDF_SIZE(x) ((x)-1)
+
+#define AV1HWPAD(x, y) RK_U8 x[y]
+
+struct NmvJointSign {
+    RK_U8 joints[MV_JOINTS - 1];  // 3B
+    RK_U8 sign[2];                // 2B
+};
+
+struct NmvMagnitude {
+    RK_U8 class0[2][CLASS0_SIZE - 1];
+    RK_U8 fp[2][MV_FP_SIZE - 1];
+    RK_U8 class0_hp[2];
+    RK_U8 hp[2];
+    RK_U8 classes[2][MV_CLASSES - 1];
+    RK_U8 class0_fp[2][CLASS0_SIZE][MV_FP_SIZE - 1];
+    RK_U8 bits[2][MV_OFFSET_BITS];
+};
+
+struct RefMvNmvContext {
+    // Starts at +4B offset (for mbskip)
+    struct NmvJointSign joints_sign[NMV_CONTEXTS];  // 15B
+    AV1HWPAD(pad1, 13);
+
+    // A+1
+    struct NmvMagnitude magnitude[NMV_CONTEXTS];
+};
+
+/* Adaptive entropy contexts, padding elements are added to have
+ * 256 bit aligned tables for HW access.
+ * Compile with TRACE_PROB_TABLES to print bases for each table. */
+struct Av1AdaptiveEntropyProbs {
+    // address A (56)
+
+    // Address A+0
+    RK_U8 inter_mode_prob[INTER_MODE_CONTEXTS][4];  // 7*4 = 28B
+    RK_U8 intra_inter_prob[INTRA_INTER_CONTEXTS];   // 4B
+
+    // Address A+1
+    RK_U8 uv_mode_prob[MAX_INTRA_MODES]
+    [MAX_INTRA_MODES_DRAM_ALIGNED];  // 10*16/32 = 5 addrs
+
+#if ((MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32)
+    AV1HWPAD(pad1,
+             ((MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32 == 0)
+             ? 0
+             : 32 - (MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32);
+#endif
+
+    // Address A+6
+    RK_U8 tx8x8_prob[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB - 3];    // 2*(4-3) = 2B
+    RK_U8 tx16x16_prob[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB - 2];  // 2*(4-2) = 4B
+    RK_U8 tx32x32_prob[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB - 1];  // 2*(4-1) = 6B
+
+    RK_U8 switchable_interp_prob[AV1_SWITCHABLE_FILTERS + 1]
+    [AV1_SWITCHABLE_FILTERS - 1];  // 8B
+    RK_U8 comp_inter_prob[COMP_INTER_CONTEXTS];                // 5B
+
+    AV1HWPAD(pad6, 7);
+
+    // Address A+7
+    RK_U8 sb_ymode_prob[BLOCK_SIZE_GROUPS]
+    [MAX_INTRA_MODES_DRAM_ALIGNED];  // 4*16/32 = 2 addrs
+
+    // Address A+9
+    RK_U8 partition_prob[NUM_FRAME_TYPES][NUM_PARTITION_CONTEXTS]
+    [PARTITION_TYPES];  // 2*16*4 = 4 addrs
+
+    // Address A+13
+    AV1HWPAD(pad13, 24);
+    RK_U8 mbskip_probs[MBSKIP_CONTEXTS];  // 3B
+    struct NmvContext nmvc;
+
+    // Address A+16
+    RK_U8 single_ref_prob[REF_CONTEXTS][2];          // 10B
+    RK_U8 comp_ref_prob[REF_CONTEXTS];               // 5B
+    RK_U8 mb_segment_tree_probs[MB_SEG_TREE_PROBS];  // 7B
+    RK_U8 segment_pred_probs[PREDICTION_PROBS];      // 3B
+    AV1HWPAD(pad16, 7);
+
+    // Address A+17
+    RK_U8 prob_coeffs[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS]
+    [ENTROPY_NODES_PART1];  // 18 addrs
+    RK_U8 prob_coeffs8x8[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS]
+    [ENTROPY_NODES_PART1];
+    RK_U8 prob_coeffs16x16[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS]
+    [ENTROPY_NODES_PART1];
+    RK_U8 prob_coeffs32x32[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS]
+    [ENTROPY_NODES_PART1];
+};
+
+/* Entropy contexts */
+struct Av1EntropyProbs {
+    /* Default keyframe probs */
+    /* Table formatted for 256b memory, probs 0to7 for all tables followed by
+     * probs 8toN for all tables.
+     * Compile with TRACE_PROB_TABLES to print bases for each table. */
+
+    // In AOM code, this table is [M][M][M-1]; we pad to 16B so each entry is 1/2
+    // DRAM word.
+    RK_U8 kf_bmode_prob[MAX_INTRA_MODES][MAX_INTRA_MODES]
+    [MAX_INTRA_MODES_DRAM_ALIGNED];
+
+#if ((MAX_INTRA_MODES * MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32)
+    AV1HWPAD(pad0, (((MAX_INTRA_MODES * MAX_INTRA_MODES *
+                      MAX_INTRA_MODES_DRAM_ALIGNED) %
+                     32) == 0)
+             ? 0
+             : 32 - ((MAX_INTRA_MODES * MAX_INTRA_MODES *
+                      MAX_INTRA_MODES_DRAM_ALIGNED) %
+                     32));
+#endif
+
+    // Address 50
+    AV1HWPAD(unused_bytes, 4);  // 4B of padding to maintain the old alignments.
+    RK_U8 ref_pred_probs[PREDICTION_PROBS];   // 3B
+    RK_U8 ref_scores[MAX_REF_FRAMES];         // 4B
+    RK_U8 prob_comppred[COMP_PRED_CONTEXTS];  // 2B
+
+    AV1HWPAD(pad1, 19);
+
+    // Address 51
+    RK_U8 kf_uv_mode_prob[MAX_INTRA_MODES][MAX_INTRA_MODES_DRAM_ALIGNED];
+
+#if ((MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32)
+    AV1HWPAD(pad51,
+             ((MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32 == 0)
+             ? 0
+             : 32 - (MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32);
+#endif
+
+    // Address 56
+    struct Av1AdaptiveEntropyProbs a;  // Probs with backward adaptation
+};
+
+/* Counters for adaptive entropy contexts */
+struct Av1EntropyCounts {
+    RK_U32 inter_mode_counts[INTER_MODE_CONTEXTS][AV1_INTER_MODES - 1][2];
+    RK_U32 sb_ymode_counts[BLOCK_SIZE_GROUPS][MAX_INTRA_MODES];
+    RK_U32 uv_mode_counts[MAX_INTRA_MODES][MAX_INTRA_MODES];
+    RK_U32 partition_counts[NUM_PARTITION_CONTEXTS][PARTITION_TYPES];
+    RK_U32 switchable_interp_counts[AV1_SWITCHABLE_FILTERS + 1]
+    [AV1_SWITCHABLE_FILTERS];
+    RK_U32 intra_inter_count[INTRA_INTER_CONTEXTS][2];
+    RK_U32 comp_inter_count[COMP_INTER_CONTEXTS][2];
+    RK_U32 single_ref_count[REF_CONTEXTS][2][2];
+    RK_U32 comp_ref_count[REF_CONTEXTS][2];
+    RK_U32 tx32x32_count[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB];
+    RK_U32 tx16x16_count[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB - 1];
+    RK_U32 tx8x8_count[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB - 2];
+    RK_U32 mbskip_count[MBSKIP_CONTEXTS][2];
+
+    struct NmvContextCounts nmvcount;
+
+    RK_U32 count_coeffs[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS][UNCONSTRAINED_NODES + 1];
+    RK_U32 count_coeffs8x8[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS][UNCONSTRAINED_NODES + 1];
+    RK_U32 count_coeffs16x16[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS][UNCONSTRAINED_NODES + 1];
+    RK_U32 count_coeffs32x32[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS][UNCONSTRAINED_NODES + 1];
+
+    RK_U32 count_eobs[TX_SIZE_MAX_SB][BLOCK_TYPES][REF_TYPES][COEF_BANDS]
+    [PREV_COEF_CONTEXTS];
+};
+
+struct CoeffHeadCDFModel {
+    RK_U16 band0[3][5];
+    RK_U16 bands[5][6][4];
+};
+
+struct CoeffTailCDFModel {
+    RK_U16 band0[3][9];
+    RK_U16 bands[5][6][9];
+};
+
+// 135
+typedef struct CoeffHeadCDFModel coeff_head_cdf_model[BLOCK_TYPES][REF_TYPES];
+// 297
+typedef struct CoeffTailCDFModel coeff_tail_cdf_model[BLOCK_TYPES][REF_TYPES];
+
+//#define PALETTE_BLOCK_SIZES (BLOCK_SIZE_SB64X64 - BLOCK_SIZE_SB8X8 + 1)
+#define PALETTE_BLOCK_SIZES 7
+#define PALETTE_SIZES 7
+#define PALETTE_Y_MODE_CONTEXTS 3
+#define PALETTE_UV_MODE_CONTEXTS 2
+#define PALETTE_COLOR_INDEX_CONTEXTS 5
+#define PALETTE_IDX_CONTEXTS 18
+#define PALETTE_COLORS 8
+#define KF_MODE_CONTEXTS 5
+
+#define PLANE_TYPES 2
+#define TX_SIZES 5
+#define TXB_SKIP_CONTEXTS 13
+#define DC_SIGN_CONTEXTS 3
+#define SIG_COEF_CONTEXTS_EOB 4
+#define SIG_COEF_CONTEXTS 42
+#define COEFF_BASE_CONTEXTS 42
+#define EOB_COEF_CONTEXTS 9
+#define LEVEL_CONTEXTS 21
+#define NUM_BASE_LEVELS 2
+#define BR_CDF_SIZE 4
+#define MOTION_MODES 3
+#define DELTA_Q_PROBS 3
+#define COMP_REF_TYPE_CONTEXTS 5
+#define UNI_COMP_REF_CONTEXTS 3
+#define UNIDIR_COMP_REFS 4
+//#define FILTER_INTRA_MODES 5
+#define SKIP_MODE_CONTEXTS 3
+#define SKIP_CONTEXTS 3
+#define COMP_INDEX_CONTEXTS 6
+#define COMP_GROUP_IDX_CONTEXTS 7
+#define MAX_TX_CATS 4
+#define CFL_ALLOWED_TYPES 2
+#define UV_INTRA_MODES 14
+#define EXT_PARTITION_TYPES 10
+#define AV1_PARTITION_CONTEXTS (5 * PARTITION_PLOFFSET)
+
+#define RESTORE_SWITCHABLE_TYPES 3
+#define DELTA_LF_PROBS 3
+#define FRAME_LF_COUNT 4
+#define MAX_SEGMENTS 8
+#define TOKEN_CDF_Q_CTXS 4
+#define SEG_TEMPORAL_PRED_CTXS 3
+#define SPATIAL_PREDICTION_PROBS 3
+
+typedef RK_U16 aom_cdf_prob;
+
+typedef struct {
+    RK_U16 joint_cdf[3];
+    RK_U16 sign_cdf[2];
+    RK_U16 clsss_cdf[2][10];
+    RK_U16 clsss0_fp_cdf[2][2][3];
+    RK_U16 fp_cdf[2][3];
+    RK_U16 class0_hp_cdf[2];
+    RK_U16 hp_cdf[2];
+    RK_U16 class0_cdf[2];
+    RK_U16 bits_cdf[2][10];
+} MvCDFs;
+
+typedef struct {
+    RK_U16 partition_cdf[13][16];
+    // 64
+    RK_U16 kf_ymode_cdf[KF_MODE_CONTEXTS][KF_MODE_CONTEXTS][AV1_INTRA_MODES - 1];
+    RK_U16 segment_pred_cdf[PREDICTION_PROBS];
+    RK_U16 spatial_pred_seg_tree_cdf[SPATIAL_PREDICTION_PROBS][MAX_MB_SEGMENTS - 1];
+    RK_U16 mbskip_cdf[MBSKIP_CONTEXTS];
+    RK_U16 delta_q_cdf[DELTA_Q_PROBS];
+    RK_U16 delta_lf_multi_cdf[FRAME_LF_COUNT][DELTA_LF_PROBS];
+    RK_U16 delta_lf_cdf[DELTA_LF_PROBS];
+    RK_U16 skip_mode_cdf[SKIP_MODE_CONTEXTS];
+    RK_U16 vartx_part_cdf[VARTX_PART_CONTEXTS][1];
+    RK_U16 tx_size_cdf[MAX_TX_CATS][AV1_TX_SIZE_CONTEXTS][MAX_TX_DEPTH];
+    RK_U16 if_ymode_cdf[BLOCK_SIZE_GROUPS][AV1_INTRA_MODES - 1];
+    RK_U16 uv_mode_cdf[2][AV1_INTRA_MODES][AV1_INTRA_MODES - 1 + 1];
+    RK_U16 intra_inter_cdf[INTRA_INTER_CONTEXTS];
+    RK_U16 comp_inter_cdf[COMP_INTER_CONTEXTS];
+    RK_U16 single_ref_cdf[AV1_REF_CONTEXTS][SINGLE_REFS - 1];
+    RK_U16 comp_ref_type_cdf[COMP_REF_TYPE_CONTEXTS][1];
+    RK_U16 uni_comp_ref_cdf[UNI_COMP_REF_CONTEXTS][UNIDIR_COMP_REFS - 1][1];
+    RK_U16 comp_ref_cdf[AV1_REF_CONTEXTS][FWD_REFS - 1];
+    RK_U16 comp_bwdref_cdf[AV1_REF_CONTEXTS][BWD_REFS - 1];
+    RK_U16 newmv_cdf[NEWMV_MODE_CONTEXTS];
+    RK_U16 zeromv_cdf[ZEROMV_MODE_CONTEXTS];
+    RK_U16 refmv_cdf[REFMV_MODE_CONTEXTS];
+    RK_U16 drl_cdf[DRL_MODE_CONTEXTS];
+    RK_U16 interp_filter_cdf[SWITCHABLE_FILTER_CONTEXTS][AV1_SWITCHABLE_FILTERS - 1];
+
+    MvCDFs mv_cdf;
+
+    RK_U16 obmc_cdf[BLOCK_SIZE_TYPES];
+    RK_U16 motion_mode_cdf[BLOCK_SIZE_TYPES][2];
+
+    RK_U16 inter_compound_mode_cdf[AV1_INTER_MODE_CONTEXTS][INTER_COMPOUND_MODES - 1];
+    RK_U16 compound_type_cdf[BLOCK_SIZE_TYPES][CDF_SIZE(COMPOUND_TYPES - 1)];
+    RK_U16 interintra_cdf[BLOCK_SIZE_GROUPS];
+    RK_U16 interintra_mode_cdf[BLOCK_SIZE_GROUPS][INTERINTRA_MODES - 1];
+    RK_U16 wedge_interintra_cdf[BLOCK_SIZE_TYPES];
+    RK_U16 wedge_idx_cdf[BLOCK_SIZE_TYPES][CDF_SIZE(16)];
+
+    RK_U16 palette_y_mode_cdf[PALETTE_BLOCK_SIZES][PALETTE_Y_MODE_CONTEXTS][1];
+    RK_U16 palette_uv_mode_cdf[PALETTE_UV_MODE_CONTEXTS][1];
+    RK_U16 palette_y_size_cdf[PALETTE_BLOCK_SIZES][PALETTE_SIZES - 1];
+    RK_U16 palette_uv_size_cdf[PALETTE_BLOCK_SIZES][PALETTE_SIZES - 1];
+
+    RK_U16 cfl_sign_cdf[CFL_JOINT_SIGNS - 1];
+    RK_U16 cfl_alpha_cdf[CFL_ALPHA_CONTEXTS][CFL_ALPHABET_SIZE - 1];
+
+    RK_U16 intrabc_cdf[1];
+    RK_U16 angle_delta_cdf[DIRECTIONAL_MODES][6];
+
+    RK_U16 filter_intra_mode_cdf[FILTER_INTRA_MODES - 1];
+    RK_U16 filter_intra_cdf[BLOCK_SIZES_ALL];
+    RK_U16 comp_group_idx_cdf[COMP_GROUP_IDX_CONTEXTS][CDF_SIZE(2)];
+    RK_U16 compound_idx_cdf[COMP_INDEX_CONTEXTS][CDF_SIZE(2)];
+
+    RK_U16 dummy0[14];
+
+    // Palette index contexts; sizes 1/7, 2/6, 3/5 packed together
+    RK_U16 palette_y_color_index_cdf[PALETTE_IDX_CONTEXTS][8];
+    RK_U16 palette_uv_color_index_cdf[PALETTE_IDX_CONTEXTS][8];
+    // RK_U16 dummy1[0];
+
+    // Note: cdf space can be optimized (most sets have fewer than EXT_TX_TYPES
+    // symbols)
+    RK_U16 tx_type_intra0_cdf[EXTTX_SIZES][AV1_INTRA_MODES][8];
+    RK_U16 tx_type_intra1_cdf[EXTTX_SIZES][AV1_INTRA_MODES][4];
+    RK_U16 tx_type_inter_cdf[2][EXTTX_SIZES][EXT_TX_TYPES];
+
+    aom_cdf_prob txb_skip_cdf[TX_SIZES][TXB_SKIP_CONTEXTS][CDF_SIZE(2)];
+    aom_cdf_prob eob_extra_cdf[TX_SIZES][PLANE_TYPES][EOB_COEF_CONTEXTS][CDF_SIZE(2)];
+    RK_U16 dummy_[5];
+
+    aom_cdf_prob eob_flag_cdf16[PLANE_TYPES][2][4];
+    aom_cdf_prob eob_flag_cdf32[PLANE_TYPES][2][8];
+    aom_cdf_prob eob_flag_cdf64[PLANE_TYPES][2][8];
+    aom_cdf_prob eob_flag_cdf128[PLANE_TYPES][2][8];
+    aom_cdf_prob eob_flag_cdf256[PLANE_TYPES][2][8];
+    aom_cdf_prob eob_flag_cdf512[PLANE_TYPES][2][16];
+    aom_cdf_prob eob_flag_cdf1024[PLANE_TYPES][2][16];
+    aom_cdf_prob coeff_base_eob_cdf[TX_SIZES][PLANE_TYPES][SIG_COEF_CONTEXTS_EOB][CDF_SIZE(3)];
+    aom_cdf_prob coeff_base_cdf[TX_SIZES][PLANE_TYPES][SIG_COEF_CONTEXTS][CDF_SIZE(4) + 1];
+    aom_cdf_prob dc_sign_cdf[PLANE_TYPES][DC_SIGN_CONTEXTS][CDF_SIZE(2)];
+    RK_U16 dummy_2[2];
+    aom_cdf_prob coeff_br_cdf[TX_SIZES][PLANE_TYPES][LEVEL_CONTEXTS][CDF_SIZE(BR_CDF_SIZE) + 1];
+    RK_U16 dummy2[16];
+} AV1CDFs;
+
+typedef struct {
+    RK_U8 scaling_lut_y[256];
+    RK_U8 scaling_lut_cb[256];
+    RK_U8 scaling_lut_cr[256];
+    RK_S16 cropped_luma_grain_block[4096];
+    RK_S16 cropped_chroma_grain_block[1024 * 2];
+} AV1FilmGrainMemory;
+
+#endif  // __AV1COMMONDEC_H__

mpp/hal/vpu/av1d/film_grain_noise_table.c

@@ -0,0 +1,374 @@
+/*
+ * Copyright 2021 Rockchip Electronics Co. LTD
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "film_grain_noise_table.h"
+#include <stdint.h>
+#include <stdio.h>
+
+static const RK_S32 gaussian_sequence[2048] = {
+    56,    568,   -180,  172,   124,   -84,   172,   -64,   -900,  24,   820,
+    224,   1248,  996,   272,   -8,    -916,  -388,  -732,  -104,  -188, 800,
+    112,   -652,  -320,  -376,  140,   -252,  492,   -168,  44,    -788, 588,
+    -584,  500,   -228,  12,    680,   272,   -476,  972,   -100,  652,  368,
+    432,   -196,  -720,  -192,  1000,  -332,  652,   -136,  -552,  -604, -4,
+    192,   -220,  -136,  1000,  -52,   372,   -96,   -624,  124,   -24,  396,
+    540,   -12,   -104,  640,   464,   244,   -208,  -84,   368,   -528, -740,
+    248,   -968,  -848,  608,   376,   -60,   -292,  -40,   -156,  252,  -292,
+    248,   224,   -280,  400,   -244,  244,   -60,   76,    -80,   212,  532,
+    340,   128,   -36,   824,   -352,  -60,   -264,  -96,   -612,  416,  -704,
+    220,   -204,  640,   -160,  1220,  -408,  900,   336,   20,    -336, -96,
+    -792,  304,   48,    -28,   -1232, -1172, -448,  104,   -292,  -520, 244,
+    60,    -948,  0,     -708,  268,   108,   356,   -548,  488,   -344, -136,
+    488,   -196,  -224,  656,   -236,  -1128, 60,    4,     140,   276,  -676,
+    -376,  168,   -108,  464,   8,     564,   64,    240,   308,   -300, -400,
+    -456,  -136,  56,    120,   -408,  -116,  436,   504,   -232,  328,  844,
+    -164,  -84,   784,   -168,  232,   -224,  348,   -376,  128,   568,  96,
+    -1244, -288,  276,   848,   832,   -360,  656,   464,   -384,  -332, -356,
+    728,   -388,  160,   -192,  468,   296,   224,   140,   -776,  -100, 280,
+    4,     196,   44,    -36,   -648,  932,   16,    1428,  28,    528,  808,
+    772,   20,    268,   88,    -332,  -284,  124,   -384,  -448,  208,  -228,
+    -1044, -328,  660,   380,   -148,  -300,  588,   240,   540,   28,   136,
+    -88,   -436,  256,   296,   -1000, 1400,  0,     -48,   1056,  -136, 264,
+    -528,  -1108, 632,   -484,  -592,  -344,  796,   124,   -668,  -768, 388,
+    1296,  -232,  -188,  -200,  -288,  -4,    308,   100,   -168,  256,  -500,
+    204,   -508,  648,   -136,  372,   -272,  -120,  -1004, -552,  -548, -384,
+    548,   -296,  428,   -108,  -8,    -912,  -324,  -224,  -88,   -112, -220,
+    -100,  996,   -796,  548,   360,   -216,  180,   428,   -200,  -212, 148,
+    96,    148,   284,   216,   -412,  -320,  120,   -300,  -384,  -604, -572,
+    -332,  -8,    -180,  -176,  696,   116,   -88,   628,   76,    44,   -516,
+    240,   -208,  -40,   100,   -592,  344,   -308,  -452,  -228,  20,   916,
+    -1752, -136,  -340,  -804,  140,   40,    512,   340,   248,   184,  -492,
+    896,   -156,  932,   -628,  328,   -688,  -448,  -616,  -752,  -100, 560,
+    -1020, 180,   -800,  -64,   76,    576,   1068,  396,   660,   552,  -108,
+    -28,   320,   -628,  312,   -92,   -92,   -472,  268,   16,    560,  516,
+    -672,  -52,   492,   -100,  260,   384,   284,   292,   304,   -148, 88,
+    -152,  1012,  1064,  -228,  164,   -376,  -684,  592,   -392,  156,  196,
+    -524,  -64,   -884,  160,   -176,  636,   648,   404,   -396,  -436, 864,
+    424,   -728,  988,   -604,  904,   -592,  296,   -224,  536,   -176, -920,
+    436,   -48,   1176,  -884,  416,   -776,  -824,  -884,  524,   -548, -564,
+    -68,   -164,  -96,   692,   364,   -692,  -1012, -68,   260,   -480, 876,
+    -1116, 452,   -332,  -352,  892,   -1088, 1220,  -676,  12,    -292, 244,
+    496,   372,   -32,   280,   200,   112,   -440,  -96,   24,    -644, -184,
+    56,    -432,  224,   -980,  272,   -260,  144,   -436,  420,   356,  364,
+    -528,  76,    172,   -744,  -368,  404,   -752,  -416,  684,   -688, 72,
+    540,   416,   92,    444,   480,   -72,   -1416, 164,   -1172, -68,  24,
+    424,   264,   1040,  128,   -912,  -524,  -356,  64,    876,   -12,  4,
+    -88,   532,   272,   -524,  320,   276,   -508,  940,   24,    -400, -120,
+    756,   60,    236,   -412,  100,   376,   -484,  400,   -100,  -740, -108,
+    -260,  328,   -268,  224,   -200,  -416,  184,   -604,  -564,  -20,  296,
+    60,    892,   -888,  60,    164,   68,    -760,  216,   -296,  904,  -336,
+    -28,   404,   -356,  -568,  -208,  -1480, -512,  296,   328,   -360, -164,
+    -1560, -776,  1156,  -428,  164,   -504,  -112,  120,   -216,  -148, -264,
+    308,   32,    64,    -72,   72,    116,   176,   -64,   -272,  460,  -536,
+    -784,  -280,  348,   108,   -752,  -132,  524,   -540,  -776,  116,  -296,
+    -1196, -288,  -560,  1040,  -472,  116,   -848,  -1116, 116,   636,  696,
+    284,   -176,  1016,  204,   -864,  -648,  -248,  356,   972,   -584, -204,
+    264,   880,   528,   -24,   -184,  116,   448,   -144,  828,   524,  212,
+    -212,  52,    12,    200,   268,   -488,  -404,  -880,  824,   -672, -40,
+    908,   -248,  500,   716,   -576,  492,   -576,  16,    720,   -108, 384,
+    124,   344,   280,   576,   -500,  252,   104,   -308,  196,   -188, -8,
+    1268,  296,   1032,  -1196, 436,   316,   372,   -432,  -200,  -660, 704,
+    -224,  596,   -132,  268,   32,    -452,  884,   104,   -1008, 424,  -1348,
+    -280,  4,     -1168, 368,   476,   696,   300,   -8,    24,    180,  -592,
+    -196,  388,   304,   500,   724,   -160,  244,   -84,   272,   -256, -420,
+    320,   208,   -144,  -156,  156,   364,   452,   28,    540,   316,  220,
+    -644,  -248,  464,   72,    360,   32,    -388,  496,   -680,  -48,  208,
+    -116,  -408,  60,    -604,  -392,  548,   -840,  784,   -460,  656,  -544,
+    -388,  -264,  908,   -800,  -628,  -612,  -568,  572,   -220,  164,  288,
+    -16,   -308,  308,   -112,  -636,  -760,  280,   -668,  432,   364,  240,
+    -196,  604,   340,   384,   196,   592,   -44,   -500,  432,   -580, -132,
+    636,   -76,   392,   4,     -412,  540,   508,   328,   -356,  -36,  16,
+    -220,  -64,   -248,  -60,   24,    -192,  368,   1040,  92,    -24,  -1044,
+    -32,   40,    104,   148,   192,   -136,  -520,  56,    -816,  -224, 732,
+    392,   356,   212,   -80,   -424,  -1008, -324,  588,   -1496, 576,  460,
+    -816,  -848,  56,    -580,  -92,   -1372, -112,  -496,  200,   364,  52,
+    -140,  48,    -48,   -60,   84,    72,    40,    132,   -356,  -268, -104,
+    -284,  -404,  732,   -520,  164,   -304,  -540,  120,   328,   -76,  -460,
+    756,   388,   588,   236,   -436,  -72,   -176,  -404,  -316,  -148, 716,
+    -604,  404,   -72,   -88,   -888,  -68,   944,   88,    -220,  -344, 960,
+    472,   460,   -232,  704,   120,   832,   -228,  692,   -508,  132,  -476,
+    844,   -748,  -364,  -44,   1116,  -1104, -1056, 76,    428,   552,  -692,
+    60,    356,   96,    -384,  -188,  -612,  -576,  736,   508,   892,  352,
+    -1132, 504,   -24,   -352,  324,   332,   -600,  -312,  292,   508,  -144,
+    -8,    484,   48,    284,   -260,  -240,  256,   -100,  -292,  -204, -44,
+    472,   -204,  908,   -188,  -1000, -256,  92,    1164,  -392,  564,  356,
+    652,   -28,   -884,  256,   484,   -192,  760,   -176,  376,   -524, -452,
+    -436,  860,   -736,  212,   124,   504,   -476,  468,   76,    -472, 552,
+    -692,  -944,  -620,  740,   -240,  400,   132,   20,    192,   -196, 264,
+    -668,  -1012, -60,   296,   -316,  -828,  76,    -156,  284,   -768, -448,
+    -832,  148,   248,   652,   616,   1236,  288,   -328,  -400,  -124, 588,
+    220,   520,   -696,  1032,  768,   -740,  -92,   -272,  296,   448,  -464,
+    412,   -200,  392,   440,   -200,  264,   -152,  -260,  320,   1032, 216,
+    320,   -8,    -64,   156,   -1016, 1084,  1172,  536,   484,   -432, 132,
+    372,   -52,   -256,  84,    116,   -352,  48,    116,   304,   -384, 412,
+    924,   -300,  528,   628,   180,   648,   44,    -980,  -220,  1320, 48,
+    332,   748,   524,   -268,  -720,  540,   -276,  564,   -344,  -208, -196,
+    436,   896,   88,    -392,  132,   80,    -964,  -288,  568,   56,   -48,
+    -456,  888,   8,     552,   -156,  -292,  948,   288,   128,   -716, -292,
+    1192,  -152,  876,   352,   -600,  -260,  -812,  -468,  -28,   -120, -32,
+    -44,   1284,  496,   192,   464,   312,   -76,   -516,  -380,  -456, -1012,
+    -48,   308,   -156,  36,    492,   -156,  -808,  188,   1652,  68,   -120,
+    -116,  316,   160,   -140,  352,   808,   -416,  592,   316,   -480, 56,
+    528,   -204,  -568,  372,   -232,  752,   -344,  744,   -4,    324,  -416,
+    -600,  768,   268,   -248,  -88,   -132,  -420,  -432,  80,    -288, 404,
+    -316,  -1216, -588,  520,   -108,  92,    -320,  368,   -480,  -216, -92,
+    1688,  -300,  180,   1020,  -176,  820,   -68,   -228,  -260,  436,  -904,
+    20,    40,    -508,  440,   -736,  312,   332,   204,   760,   -372, 728,
+    96,    -20,   -632,  -520,  -560,  336,   1076,  -64,   -532,  776,  584,
+    192,   396,   -728,  -520,  276,   -188,  80,    -52,   -612,  -252, -48,
+    648,   212,   -688,  228,   -52,   -260,  428,   -412,  -272,  -404, 180,
+    816,   -796,  48,    152,   484,   -88,   -216,  988,   696,   188,  -528,
+    648,   -116,  -180,  316,   476,   12,    -564,  96,    476,   -252, -364,
+    -376,  -392,  556,   -256,  -576,  260,   -352,  120,   -16,   -136, -260,
+    -492,  72,    556,   660,   580,   616,   772,   436,   424,   -32,  -324,
+    -1268, 416,   -324,  -80,   920,   160,   228,   724,   32,    -516, 64,
+    384,   68,    -128,  136,   240,   248,   -204,  -68,   252,   -932, -120,
+    -480,  -628,  -84,   192,   852,   -404,  -288,  -132,  204,   100,  168,
+    -68,   -196,  -868,  460,   1080,  380,   -80,   244,   0,     484,  -888,
+    64,    184,   352,   600,   460,   164,   604,   -196,  320,   -64,  588,
+    -184,  228,   12,    372,   48,    -848,  -344,  224,   208,   -200, 484,
+    128,   -20,   272,   -468,  -840,  384,   256,   -720,  -520,  -464, -580,
+    112,   -120,  644,   -356,  -208,  -608,  -528,  704,   560,   -424, 392,
+    828,   40,    84,    200,   -152,  0,     -144,  584,   280,   -120, 80,
+    -556,  -972,  -196,  -472,  724,   80,    168,   -32,   88,    160,  -688,
+    0,     160,   356,   372,   -776,  740,   -128,  676,   -248,  -480, 4,
+    -364,  96,    544,   232,   -1032, 956,   236,   356,   20,    -40,  300,
+    24,    -676,  -596,  132,   1120,  -104,  532,   -1096, 568,   648,  444,
+    508,   380,   188,   -376,  -604,  1488,  424,   24,    756,   -220, -192,
+    716,   120,   920,   688,   168,   44,    -460,  568,   284,   1144, 1160,
+    600,   424,   888,   656,   -356,  -320,  220,   316,   -176,  -724, -188,
+    -816,  -628,  -348,  -228,  -380,  1012,  -452,  -660,  736,   928,  404,
+    -696,  -72,   -268,  -892,  128,   184,   -344,  -780,  360,   336,  400,
+    344,   428,   548,   -112,  136,   -228,  -216,  -820,  -516,  340,  92,
+    -136,  116,   -300,  376,   -244,  100,   -316,  -520,  -284,  -12,  824,
+    164,   -548,  -180,  -128,  116,   -924,  -828,  268,   -368,  -580, 620,
+    192,   160,   0,     -1676, 1068,  424,   -56,   -360,  468,   -156, 720,
+    288,   -528,  556,   -364,  548,   -148,  504,   316,   152,   -648, -620,
+    -684,  -24,   -376,  -384,  -108,  -920,  -1032, 768,   180,   -264, -508,
+    -1268, -260,  -60,   300,   -240,  988,   724,   -376,  -576,  -212, -736,
+    556,   192,   1092,  -620,  -880,  376,   -56,   -4,    -216,  -32,  836,
+    268,   396,   1332,  864,   -600,  100,   56,    -412,  -92,   356,  180,
+    884,   -468,  -436,  292,   -388,  -804,  -704,  -840,  368,   -348, 140,
+    -724,  1536,  940,   372,   112,   -372,  436,   -480,  1136,  296,  -32,
+    -228,  132,   -48,   -220,  868,   -1016, -60,   -1044, -464,  328,  916,
+    244,   12,    -736,  -296,  360,   468,   -376,  -108,  -92,   788,  368,
+    -56,   544,   400,   -672,  -420,  728,   16,    320,   44,    -284, -380,
+    -796,  488,   132,   204,   -596,  -372,  88,    -152,  -908,  -636, -572,
+    -624,  -116,  -692,  -200,  -56,   276,   -88,   484,   -324,  948,  864,
+    1000,  -456,  -184,  -276,  292,   -296,  156,   676,   320,   160,  908,
+    -84,   -1236, -288,  -116,  260,   -372,  -644,  732,   -756,  -96,  84,
+    344,   -520,  348,   -688,  240,   -84,   216,   -1044, -136,  -676, -396,
+    -1500, 960,   -40,   176,   168,   1516,  420,   -504,  -344,  -364, -360,
+    1216,  -940,  -380,  -212,  252,   -660,  -708,  484,   -444,  -152, 928,
+    -120,  1112,  476,   -260,  560,   -148,  -344,  108,   -196,  228,  -288,
+    504,   560,   -328,  -88,   288,   -1008, 460,   -228,  468,   -836, -196,
+    76,    388,   232,   412,   -1168, -716,  -644,  756,   -172,  -356, -504,
+    116,   432,   528,   48,    476,   -168,  -608,  448,   160,   -532, -272,
+    28,    -676,  -12,   828,   980,   456,   520,   104,   -104,  256,  -344,
+    -4,    -28,   -368,  -52,   -524,  -572,  -556,  -200,  768,   1124, -208,
+    -512,  176,   232,   248,   -148,  -888,  604,   -600,  -304,  804,  -156,
+    -212,  488,   -192,  -804,  -256,  368,   -360,  -916,  -328,  228,  -240,
+    -448,  -472,  856,   -556,  -364,  572,   -12,   -156,  -368,  -340, 432,
+    252,   -752,  -152,  288,   268,   -580,  -848,  -592,  108,   -76,  244,
+    312,   -716,  592,   -80,   436,   360,   4,     -248,  160,   516,  584,
+    732,   44,    -468,  -280,  -292,  -156,  -588,  28,    308,   912,  24,
+    124,   156,   180,   -252,  944,   -924,  -772,  -520,  -428,  -624, 300,
+    -212,  -1144, 32,    -724,  800,   -1128, -212,  -1288, -848,  180,  -416,
+    440,   192,   -576,  -792,  -76,   -1080, 80,    -532,  -352,  -132, 380,
+    -820,  148,   1112,  128,   164,   456,   700,   -924,  144,   -668, -384,
+    648,   -832,  508,   552,   -52,   -100,  -656,  208,   -568,  748,  -88,
+    680,   232,   300,   192,   -408,  -1012, -152,  -252,  -268,  272,  -876,
+    -664,  -648,  -332,  -136,  16,    12,    1152,  -28,   332,   -536, 320,
+    -672,  -460,  -316,  532,   -260,  228,   -40,   1052,  -816,  180,  88,
+    -496,  -556,  -672,  -368,  428,   92,    356,   404,   -408,  252,  196,
+    -176,  -556,  792,   268,   32,    372,   40,    96,    -332,  328,  120,
+    372,   -900,  -40,   472,   -264,  -592,  952,   128,   656,   112,  664,
+    -232,  420,   4,     -344,  -464,  556,   244,   -416,  -32,   252,  0,
+    -412,  188,   -696,  508,   -476,  324,   -1096, 656,   -312,  560,  264,
+    -136,  304,   160,   -64,   -580,  248,   336,   -720,  560,   -348, -288,
+    -276,  -196,  -500,  852,   -544,  -236,  -1128, -992,  -776,  116,  56,
+    52,    860,   884,   212,   -12,   168,   1020,  512,   -552,  924,  -148,
+    716,   188,   164,   -340,  -520,  -184,  880,   -152,  -680,  -208, -1156,
+    -300,  -528,  -472,  364,   100,   -744,  -1056, -32,   540,   280,  144,
+    -676,  -32,   -232,  -280,  -224,  96,    568,   -76,   172,   148,  148,
+    104,   32,    -296,  -32,   788,   -80,   32,    -16,   280,   288,  944,
+    428,   -484
+};
+
+static inline RK_S32 Clamp(RK_S32 value, RK_S32 low, RK_S32 high)
+{
+    return value < low ? low : (value > high ? high : value);
+}
+
+static inline RK_S32 RoundPowerOfTwo(const RK_S32 val, RK_S32 n)
+{
+    const RK_S32 a = (RK_S32)1 << (n - 1);
+    return (val + a) >> n;
+}
+
+// Reset random_register
+static void InitRandomGenerator(RK_U8 luma_num, RK_U16 seed, RK_U16 *random_register)
+{
+    RK_U16 random_reg = seed;
+    random_reg ^= ((luma_num * 37 + 178) & 255) << 8;
+    random_reg ^= ((luma_num * 173 + 105) & 255);
+    *random_register = random_reg;
+}
+
+// Update random_register as LFSR
+static inline void UpdateRandomRegister(RK_U16 *random_register)
+{
+    RK_U16 bit;
+    RK_U16 random_reg = *random_register;
+    bit = ((random_reg >> 0) ^ (random_reg >> 1) ^ (random_reg >> 3) ^
+           (random_reg >> 12)) &
+          1;
+    *random_register = (random_reg >> 1) | (bit << 15);
+}
+
+static inline RK_S32 GetRandomNumber(RK_U16 random_register)
+{
+    return (random_register >> 5) & ((1 << 11) - 1);
+}
+
+void GenerateLumaGrainBlock(RK_S32 luma_grain_block[][82], RK_S32 bitdepth,
+                            RK_U8 num_y_points, RK_S32 grain_scale_shift,
+                            RK_S32 ar_coeff_lag, RK_S32 ar_coeffs_y[],
+                            RK_S32 ar_coeff_shift, RK_S32 grain_min, RK_S32 grain_max,
+                            RK_U16 random_seed)
+{
+    RK_S32 gauss_sec_shift = 12 - bitdepth + grain_scale_shift;
+    RK_U16 grain_random_register = random_seed;
+    RK_S32 i, j;
+    for (i = 0; i < 73; i++) {
+        for (j = 0; j < 82; j++) {
+            if (num_y_points > 0) {
+                UpdateRandomRegister(&grain_random_register);
+                luma_grain_block[i][j] = RoundPowerOfTwo(
+                                             gaussian_sequence[GetRandomNumber(grain_random_register)],
+                                             gauss_sec_shift);
+            } else {
+                luma_grain_block[i][j] = 0;
+            }
+        }
+    }
+
+    for (i = 3; i < 73; i++)
+        for (j = 3; j < 82 - 3; j++) {
+            RK_S32 pos = 0;
+            RK_S32 wsum = 0;
+            RK_S32 deltaRow, deltaCol;
+            for (deltaRow = -ar_coeff_lag; deltaRow <= 0; deltaRow++) {
+                for (deltaCol = -ar_coeff_lag; deltaCol <= ar_coeff_lag;
+                     deltaCol++) {
+                    if (deltaRow == 0 && deltaCol == 0) break;
+                    wsum = wsum + ar_coeffs_y[pos] *
+                           luma_grain_block[i + deltaRow][j + deltaCol];
+                    ++pos;
+                }
+            }
+            luma_grain_block[i][j] =
+                Clamp(luma_grain_block[i][j] + RoundPowerOfTwo(wsum, ar_coeff_shift),
+                      grain_min, grain_max);
+        }
+}
+
+// Calculate chroma grain noise once per frame
+void GenerateChromaGrainBlock(
+    RK_S32 luma_grain_block[][82], RK_S32 cb_grain_block[][44],
+    RK_S32 cr_grain_block[][44], RK_S32 bitdepth, RK_U8 num_y_points, RK_U8 num_cb_points,
+    RK_U8 num_cr_points, RK_S32 grain_scale_shift, RK_S32 ar_coeff_lag,
+    RK_S32 ar_coeffs_cb[], RK_S32 ar_coeffs_cr[], RK_S32 ar_coeff_shift, RK_S32 grain_min,
+    RK_S32 grain_max, RK_U8 chroma_scaling_from_luma, RK_U16 random_seed)
+{
+    RK_S32 gauss_sec_shift = 12 - bitdepth + grain_scale_shift;
+    RK_U16 grain_random_register = 0;
+    RK_S32 i, j;
+
+    InitRandomGenerator(7, random_seed, &grain_random_register);
+    for ( i = 0; i < 38; i++) {
+        for (j = 0; j < 44; j++) {
+            if (num_cb_points || chroma_scaling_from_luma) {
+                UpdateRandomRegister(&grain_random_register);
+                cb_grain_block[i][j] = RoundPowerOfTwo(
+                                           gaussian_sequence[GetRandomNumber(grain_random_register)],
+                                           gauss_sec_shift);
+            } else {
+                cb_grain_block[i][j] = 0;
+            }
+        }
+    }
+
+    InitRandomGenerator(11, random_seed, &grain_random_register);
+    for (i = 0; i < 38; i++) {
+        for (j = 0; j < 44; j++) {
+            if (num_cr_points || chroma_scaling_from_luma) {
+                UpdateRandomRegister(&grain_random_register);
+                cr_grain_block[i][j] = RoundPowerOfTwo(
+                                           gaussian_sequence[GetRandomNumber(grain_random_register)],
+                                           gauss_sec_shift);
+            } else {
+                cr_grain_block[i][j] = 0;
+            }
+        }
+    }
+
+    for (i = 3; i < 38; i++)
+        for (j = 3; j < 44 - 3; j++) {
+            RK_S32 wsum_cb = 0;
+            RK_S32 wsum_cr = 0;
+            RK_S32 pos = 0;
+            RK_S32 deltaRow, deltaCol;
+
+            for ( deltaRow = -ar_coeff_lag; deltaRow <= 0; deltaRow++) {
+                for ( deltaCol = -ar_coeff_lag; deltaCol <= ar_coeff_lag;
+                      deltaCol++) {
+                    if (deltaRow == 0 && deltaCol == 0) break;
+                    wsum_cb = wsum_cb + ar_coeffs_cb[pos] *
+                              cb_grain_block[i + deltaRow][j + deltaCol];
+                    wsum_cr = wsum_cr + ar_coeffs_cr[pos] *
+                              cr_grain_block[i + deltaRow][j + deltaCol];
+                    ++pos;
+                }
+            }
+
+            if (num_y_points > 0) {
+                RK_S32 av_luma = 0;
+                RK_S32 luma_coord_y = (i << 1) - 3;
+                RK_S32 luma_coord_x = (j << 1) - 3;
+
+                av_luma += luma_grain_block[luma_coord_y][luma_coord_x];
+                av_luma += luma_grain_block[luma_coord_y][luma_coord_x + 1];
+                av_luma += luma_grain_block[luma_coord_y + 1][luma_coord_x];
+                av_luma += luma_grain_block[luma_coord_y + 1][luma_coord_x + 1];
+                av_luma = RoundPowerOfTwo(av_luma, 2);
+
+                wsum_cb = wsum_cb + ar_coeffs_cb[pos] * av_luma;
+                wsum_cr = wsum_cr + ar_coeffs_cr[pos] * av_luma;
+            }
+
+            if (num_cb_points || chroma_scaling_from_luma) {
+                cb_grain_block[i][j] = Clamp(
+                                           cb_grain_block[i][j] + RoundPowerOfTwo(wsum_cb, ar_coeff_shift),
+                                           grain_min, grain_max);
+            }
+            if (num_cr_points || chroma_scaling_from_luma) {
+                cr_grain_block[i][j] = Clamp(
+                                           cr_grain_block[i][j] + RoundPowerOfTwo(wsum_cr, ar_coeff_shift),
+                                           grain_min, grain_max);
+            }
+        }
+}

mpp/hal/vpu/av1d/film_grain_noise_table.h

@@ -0,0 +1,33 @@
+/*
+ * Copyright 2021 Rockchip Electronics Co. LTD
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __FILM_GRAIN_NOISE_TABLE_H__
+#define __FILM_GRAIN_NOISE_TABLE_H__
+#include "rk_type.h"
+
+void GenerateLumaGrainBlock(RK_S32 luma_grain_block[][82], RK_S32 bitdepth,
+                            RK_U8 num_y_points, RK_S32 grain_scale_shift,
+                            RK_S32 ar_coeff_lag, RK_S32 ar_coeffs_y[],
+                            RK_S32 ar_coeff_shift, RK_S32 grain_min, RK_S32 grain_max,
+                            RK_U16 random_seed);
+
+void GenerateChromaGrainBlock(
+    RK_S32 luma_grain_block[][82], RK_S32 cb_grain_block[][44],
+    RK_S32 cr_grain_block[][44], RK_S32 bitdepth, RK_U8 num_y_points, RK_U8 num_cb_points,
+    RK_U8 num_cr_points, RK_S32 grain_scale_shift, RK_S32 ar_coeff_lag,
+    RK_S32 ar_coeffs_cb[], RK_S32 ar_coeffs_cr[], RK_S32 ar_coeff_shift, RK_S32 grain_min,
+    RK_S32 grain_max, RK_U8 chroma_scaling_from_luma, RK_U16 random_seed);
+
+#endif  //__FILM_GRAIN_NOISE_TABLE_H__

mpp/hal/vpu/av1d/hal_av1d_api.c

@@ -0,0 +1,187 @@
+/*
+ * Copyright 2021 Rockchip Electronics Co. LTD
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define MODULE_TAG "hal_av1d_api"
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <dlfcn.h>
+#include <unistd.h>
+
+#include "mpp_log.h"
+#include "mpp_mem.h"
+#include "mpp_env.h"
+#include "mpp_platform.h"
+#include "mpp_common.h"
+
+#include "dxva_syntax.h"
+
+#include "hal_av1d_vdpu_reg.h"
+#include "hal_av1d_vdpu.h"
+#include "hal_av1d_common.h"
+
+RK_U32 hal_av1d_debug = 0;
+
+MPP_RET hal_av1d_init(void *hal, MppHalCfg *cfg)
+{
+    MPP_RET ret         = MPP_OK;
+    Av1dHalCtx *p_hal   = (Av1dHalCtx *)hal;
+    RK_U32 vcodec_type  = mpp_get_vcodec_type();
+    MppClientType type  = VPU_CLIENT_AV1DEC;
+
+    INP_CHECK(ret, NULL == p_hal);
+    memset(p_hal, 0, sizeof(Av1dHalCtx));
+    mpp_env_get_u32("hal_av1d_debug", &hal_av1d_debug, 0);
+
+    // check codec_type first
+    if (!(vcodec_type & (HAVE_RKVDEC | HAVE_VDPU1 | HAVE_VDPU2))) {
+        mpp_err_f("can not found av1 decoder hardware on platform %x\n", vcodec_type);
+        return ret;
+    }
+
+    p_hal->api = &hal_av1d_vdpu;
+
+    //!< callback function to parser module
+    p_hal->dec_cb = cfg->dec_cb;
+
+    ret = mpp_dev_init(&cfg->dev, type);
+    if (ret) {
+        mpp_err("mpp_dev_init failed ret: %d\n", ret);
+        goto __FAILED;
+    }
+
+    //< get buffer group
+    if (p_hal->buf_group == NULL) {
+        FUN_CHECK(ret = mpp_buffer_group_get_internal
+                        (&p_hal->buf_group, MPP_BUFFER_TYPE_ION));
+    }
+
+    p_hal->dev          = cfg->dev;
+    p_hal->cfg          = cfg->cfg;
+    p_hal->slots  = cfg->frame_slots;
+    p_hal->packet_slots = cfg->packet_slots;
+    p_hal->fast_mode    = cfg->cfg->base.fast_parse;
+
+    if (p_hal->buf_group == NULL) {
+        FUN_CHECK(ret = mpp_buffer_group_get_internal
+                        (&p_hal->buf_group, MPP_BUFFER_TYPE_ION));
+    }
+    //!< run init funtion
+    FUN_CHECK(ret = p_hal->api->init(hal, cfg));
+
+__RETURN:
+    return MPP_OK;
+__FAILED:
+    return ret;
+}
+
+MPP_RET hal_av1d_deinit(void *hal)
+{
+    MPP_RET ret         = MPP_ERR_UNKNOW;
+    Av1dHalCtx *p_hal   = (Av1dHalCtx *)hal;
+
+    FUN_CHECK(ret = p_hal->api->deinit(hal));
+
+    if (p_hal->dev) {
+        mpp_dev_deinit(p_hal->dev);
+        p_hal->dev = NULL;
+    }
+
+    if (p_hal->buf_group) {
+        FUN_CHECK(ret = mpp_buffer_group_put(p_hal->buf_group));
+    }
+
+    return MPP_OK;
+__FAILED:
+    return ret;
+}
+
+MPP_RET hal_av1d_gen_regs(void *hal, HalTaskInfo *task)
+{
+    Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
+    MPP_RET ret = MPP_NOK;
+
+    if (p_hal && p_hal->api && p_hal->api->reg_gen)
+        ret = p_hal->api->reg_gen(hal, task);
+    return ret;
+}
+
+MPP_RET hal_av1d_start(void *hal, HalTaskInfo *task)
+{
+    Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
+    MPP_RET ret = MPP_NOK;
+
+    if (p_hal && p_hal->api && p_hal->api->start)
+        ret = p_hal->api->start(hal, task);
+    return ret;
+}
+
+MPP_RET hal_av1d_wait(void *hal, HalTaskInfo *task)
+{
+    Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
+    MPP_RET ret = MPP_NOK;
+
+    if (p_hal && p_hal->api && p_hal->api->wait)
+        ret = p_hal->api->wait(hal, task);
+    return ret;
+}
+
+MPP_RET hal_av1d_reset(void *hal)
+{
+    Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
+    MPP_RET ret = MPP_NOK;
+
+    if (p_hal && p_hal->api && p_hal->api->reset)
+        ret = p_hal->api->reset(hal);
+    return ret;
+}
+
+MPP_RET hal_av1d_flush(void *hal)
+{
+    Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
+    MPP_RET ret = MPP_NOK;
+
+    if (p_hal && p_hal->api && p_hal->api->flush)
+        ret = p_hal->api->flush(hal);
+    return ret;
+}
+
+MPP_RET hal_av1d_control(void *hal, MpiCmd cmd_type, void *param)
+{
+    Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
+    MPP_RET ret = MPP_NOK;
+
+    if (p_hal && p_hal->api && p_hal->api->control)
+        ret = p_hal->api->control(hal, cmd_type, param);
+    return ret;
+}
+
+const MppHalApi hal_api_av1d = {
+    .name       = "av1d_vdpu",
+    .type       = MPP_CTX_DEC,
+    .coding     = MPP_VIDEO_CodingAV1,
+    .ctx_size   = sizeof(Av1dHalCtx),
+    .flag       = 0,
+    .init       = hal_av1d_init,
+    .deinit     = hal_av1d_deinit,
+    .reg_gen    = hal_av1d_gen_regs,
+    .start      = hal_av1d_start,
+    .wait       = hal_av1d_wait,
+    .reset      = hal_av1d_reset,
+    .flush      = hal_av1d_flush,
+    .control    = hal_av1d_control,
+};

mpp/hal/vpu/av1d/hal_av1d_common.h

@@ -0,0 +1,194 @@
+/*
+ * Copyright 2020 Rockchip Electronics Co. LTD
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef __HAL_AV1D_GLOBAL_H__
+#define __HAL_AV1D_GLOBAL_H__
+
+#include "mpp_hal.h"
+#include "mpp_log.h"
+#include "mpp_device.h"
+#include "hal_bufs.h"
+
+#include "dxva_syntax.h"
+
+#define AV1D_DBG_ERROR             (0x00000001)
+#define AV1D_DBG_ASSERT            (0x00000002)
+#define AV1D_DBG_WARNNING          (0x00000004)
+#define AV1D_DBG_LOG               (0x00000008)
+
+#define AV1D_DBG_HARD_MODE         (0x00000010)
+
+extern RK_U32 hal_av1d_debug;
+
+
+#define AV1D_DBG(level, fmt, ...)\
+do {\
+    if (level & hal_av1d_debug)\
+        { mpp_log(fmt, ## __VA_ARGS__); }\
+} while (0)
+
+
+#define AV1D_ERR(fmt, ...)\
+do {\
+    if (AV1D_DBG_ERROR & hal_av1d_debug)\
+        { mpp_log(fmt, ## __VA_ARGS__); }\
+} while (0)
+
+#define ASSERT(val)\
+do {\
+    if (AV1D_DBG_ASSERT & hal_av1d_debug)\
+        { mpp_assert(val); }\
+} while (0)
+
+#define AV1D_WARNNING(fmt, ...)\
+do {\
+    if (AV1D_DBG_WARNNING & hal_av1d_debug)\
+        { mpp_log(fmt, ## __VA_ARGS__); }\
+} while (0)
+
+#define AV1D_LOG(fmt, ...)\
+do {\
+    if (AV1D_DBG_LOG & hal_av1d_debug)\
+        { mpp_log(fmt, ## __VA_ARGS__); }\
+} while (0)
+
+
+//!< vaule check
+#define VAL_CHECK(ret, val, ...)\
+do{\
+    if (!(val)){\
+        ret = MPP_ERR_VALUE; \
+        AV1D_WARNNING("value error(%d).\n", __LINE__); \
+        goto __FAILED; \
+}} while (0)
+//!< memory malloc check
+#define MEM_CHECK(ret, val, ...)\
+do{\
+    if (!(val)) {\
+        ret = MPP_ERR_MALLOC; \
+        AV1D_ERR("malloc buffer error(%d).\n", __LINE__); \
+        ASSERT(0); goto __FAILED; \
+}} while (0)
+
+#define BUF_CHECK(ret, val, ...)\
+do{\
+    if (val) {\
+        ret = MPP_ERR_BUFFER_FULL; \
+        AV1D_ERR("buffer get error(%d).\n", __LINE__); \
+        ASSERT(0); goto __FAILED; \
+}} while (0)
+
+#define BUF_PUT(val, ...)\
+do{\
+    if (val) {\
+        if (mpp_buffer_put(val)) {\
+            AV1D_ERR("buffer put error(%d).\n", __LINE__); \
+            ASSERT(0); \
+        }\
+}} while (0)
+
+//!< input check
+#define INP_CHECK(ret, val, ...)\
+do{\
+    if ((val)) {\
+        ret = MPP_ERR_INIT; \
+        AV1D_WARNNING("input empty(%d).\n", __LINE__); \
+        goto __RETURN; \
+}} while (0)
+//!< function return check
+#define FUN_CHECK(val)\
+do{\
+    if ((val) < 0) {\
+        AV1D_WARNNING("Function error(%d).\n", __LINE__); \
+        goto __FAILED; \
+}} while (0)
+
+#define MAX_MB_SEGMENTS 8
+
+enum Av1SegLevelFeatures {
+    SEG_AV1_LVL_ALT_Q,       // Use alternate Quantizer ....
+    SEG_AV1_LVL_ALT_LF_Y_V,  // Use alternate loop filter value on y plane
+    // vertical
+    SEG_AV1_LVL_ALT_LF_Y_H,  // Use alternate loop filter value on y plane
+    // horizontal
+    SEG_AV1_LVL_ALT_LF_U,    // Use alternate loop filter value on u plane
+    SEG_AV1_LVL_ALT_LF_V,    // Use alternate loop filter value on v plane
+    SEG_AV1_LVL_REF_FRAME,   // Optional Segment reference frame
+    SEG_AV1_LVL_SKIP,        // Optional Segment (0,0) + skip mode
+    SEG_AV1_LVL_GLOBALMV,
+    SEG_AV1_LVL_MAX
+};
+
+#define AV1_ACTIVE_REFS 3
+#define AV1_ACTIVE_REFS_EX 7
+#define AV1_REF_LIST_SIZE 8
+#define AV1_REF_SCALE_SHIFT 14
+
+enum MvReferenceFrame {
+    NONE              = -1,
+    INTRA_FRAME       = 0,
+    LAST_FRAME        = 1,
+    LAST2_FRAME_EX    = 2,
+    LAST3_FRAME_EX    = 3,
+    GOLDEN_FRAME_EX   = 4,
+    BWDREF_FRAME_EX   = 5,
+    ALTREF2_FRAME_EX  = 6,
+    ALTREF_FRAME_EX   = 7,
+    MAX_REF_FRAMES_EX = 8,
+    GOLDEN_FRAME      = 2,
+    ALTREF_FRAME      = 3,
+
+    MAX_REF_FRAMES    = 4
+};
+
+enum {
+    AV1_FRAME_KEY        = 0,
+    AV1_FRAME_INTER      = 1,
+    AV1_FRAME_INTRA_ONLY = 2,
+    AV1_FRAME_SWITCH     = 3,
+};
+
+#define AV1DEC_MAX_PIC_BUFFERS 24
+#define AV1DEC_DYNAMIC_PIC_LIMIT 10
+#define ALLOWED_REFS_PER_FRAME_EX 7
+
+typedef struct FilmGrainMemory_t {
+    RK_U8 scaling_lut_y[256];
+    RK_U8 scaling_lut_cb[256];
+    RK_U8 scaling_lut_cr[256];
+    RK_S16 cropped_luma_grain_block[4096];
+    RK_S16 cropped_chroma_grain_block[1024 * 2];
+} FilmGrainMemory;
+
+typedef struct av1d_hal_ctx_t {
+    const MppHalApi          *api;
+    RK_U8                    *bitstream;
+    RK_U32                   strm_len;
+
+    HalDecTask               *in_task;
+    MppBufSlots              slots;
+    MppBufSlots              packet_slots;
+    MppDecCfgSet             *cfg;
+    MppBufferGroup           buf_group;
+
+    MppCbCtx                 *dec_cb;
+    MppDev                   dev;
+    void                     *reg_ctx;
+    RK_U32                   fast_mode;
+} Av1dHalCtx;
+
+#endif /*__HAL_AV1D_GLOBAL_H__*/

mpp/hal/vpu/av1d/hal_av1d_vdpu.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright 2020 Rockchip Electronics Co. LTD
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __HAL_AV1D_VDPU_H__
+#define __HAL_AV1D_VDPU_H__
+
+#include "mpp_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const MppHalApi hal_av1d_vdpu;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HAL_H264D_VDPU34X_H__ */

osal/inc/mpp_dev_defs.h

@@ -27,6 +27,7 @@ typedef enum MppClientType_e {
     VPU_CLIENT_VDPU2        = 1,    /* 0x00000002 */
     VPU_CLIENT_VDPU1_PP     = 2,    /* 0x00000004 */
     VPU_CLIENT_VDPU2_PP     = 3,    /* 0x00000008 */
+    VPU_CLIENT_AV1DEC       = 4,    /* 0x00000010 */
 
     VPU_CLIENT_HEVC_DEC     = 8,    /* 0x00000100 */
     VPU_CLIENT_RKVDEC       = 9,    /* 0x00000200 */
@@ -49,6 +50,7 @@ typedef enum MppClientType_e {
 #define HAVE_VDPU2          (1 << VPU_CLIENT_VDPU2)         /* 0x00000002 */
 #define HAVE_VDPU1_PP       (1 << VPU_CLIENT_VDPU1_PP)      /* 0x00000004 */
 #define HAVE_VDPU2_PP       (1 << VPU_CLIENT_VDPU2_PP)      /* 0x00000008 */
+#define HAVE_AV1DEC         (1 << VPU_CLIENT_AV1DEC)        /* 0x00000008 */
 /* RK standalone decoder */
 #define HAVE_HEVC_DEC       (1 << VPU_CLIENT_HEVC_DEC)      /* 0x00000100 */
 #define HAVE_RKVDEC         (1 << VPU_CLIENT_RKVDEC)        /* 0x00000200 */

osal/inc/mpp_soc.h

@@ -81,7 +81,7 @@ typedef struct {
     const RK_U32            vcodec_type;
 
     /* Max 4 decoder cap */
-    const MppDecHwCap       *dec_caps[4];
+    const MppDecHwCap       *dec_caps[5];
     /* Max 4 encoder cap */
     const MppEncHwCap       *enc_caps[4];
 } MppSocInfo;

osal/mpp_soc.cpp

@@ -47,10 +47,12 @@
 #define HAVE_AVSP   ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVSPLUS))))
 #define HAVE_AVS    ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVS))))
 #define HAVE_AVS2   ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVS2))))
+#define HAVE_AV1    ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAV1))))
 
 #define CAP_CODING_VDPU         (HAVE_MPEG2|HAVE_H263|HAVE_MPEG4|HAVE_AVC|HAVE_MJPEG|HAVE_VP8)
 #define CAP_CODING_JPEGD_PP     (HAVE_MJPEG)
 #define CAP_CODING_AVSD         (HAVE_AVS)
+#define CAP_CODING_AV1D         (HAVE_AV1)
 #define CAP_CODING_HEVC         (HAVE_HEVC)
 #define CAP_CODING_VDPU341      (HAVE_AVC|HAVE_HEVC|HAVE_VP9)
 #define CAP_CODING_VDPU341_LITE (HAVE_AVC|HAVE_HEVC)
@@ -286,6 +288,20 @@ static const MppDecHwCap rkjpegd = {
     .reserved           = 0,
 };
 
+static const MppDecHwCap av1d = {
+    .cap_coding         = CAP_CODING_AV1D,
+    .type               = VPU_CLIENT_AV1DEC,
+    .cap_fbc            = 0,
+    .cap_4k             = 1,
+    .cap_8k             = 0,
+    .cap_colmv_buf      = 0,
+    .cap_hw_h265_rps    = 0,
+    .cap_hw_vp9_prob    = 0,
+    .cap_jpg_pp_out     = 0,
+    .cap_10bit          = 0,
+    .reserved           = 0,
+};
+
 static const MppEncHwCap vepu1 = {
     .cap_coding         = CAP_CODING_VEPU1,
     .type               = VPU_CLIENT_VEPU1,
@@ -402,21 +418,21 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rk3036",
         ROCKCHIP_SOC_RK3036,
         HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_HEVC_DEC,
-        {   &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, },
+        {   &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, },
         {   NULL, NULL, NULL, NULL, },
     },
     {   /* rk3066 has vpu1 only */
         "rk3066",
         ROCKCHIP_SOC_RK3066,
         HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1,
-        {   &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, },
+        {   &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
         {   &vepu1, NULL, NULL, NULL, },
     },
     {   /* rk3188 has vpu1 only */
         "rk3188",
         ROCKCHIP_SOC_RK3188,
         HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1,
-        {   &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, },
+        {   &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
         {   &vepu1, NULL, NULL, NULL, },
     },
     {   /*
@@ -427,7 +443,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rk3288",
         ROCKCHIP_SOC_RK3288,
         HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
-        {   &rk_hevc, &vdpu1_2160p, &vdpu1_jpeg_pp, NULL, },
+        {   &rk_hevc, &vdpu1_2160p, &vdpu1_jpeg_pp, NULL, NULL, },
         {   &vepu1, NULL, NULL, NULL, },
     },
     {   /*
@@ -438,7 +454,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rk3126",
         ROCKCHIP_SOC_RK312X,
         HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
-        {   &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, },
+        {   &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, },
         {   &vepu1, NULL, NULL, NULL, },
     },
     {   /*
@@ -450,7 +466,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rk3128h",
         ROCKCHIP_SOC_RK3128H,
         HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
-        {   &vdpu341_lite_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, },
+        {   &vdpu341_lite_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, },
         {   &vepu2_no_jpeg, NULL, NULL, NULL, },
     },
     {   /*
@@ -461,7 +477,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rk3128",
         ROCKCHIP_SOC_RK312X,
         HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
-        {   &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, },
+        {   &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, },
         {   &vepu1, NULL, NULL, NULL, },
     },
     {   /*
@@ -472,7 +488,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rk3368",
         ROCKCHIP_SOC_RK3368,
         HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
-        {   &rk_hevc, &vdpu1, &vdpu1_jpeg_pp, NULL, },
+        {   &rk_hevc, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, },
         {   &vepu1, NULL, NULL, NULL, },
     },
     {   /*
@@ -483,7 +499,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rk3399",
         ROCKCHIP_SOC_RK3399,
         HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
-        {   &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, },
+        {   &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, },
         {   &vepu2, NULL, NULL, NULL, },
     },
     {   /*
@@ -497,7 +513,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rk3228h",
         ROCKCHIP_SOC_RK3228H,
         HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_AVSDEC | HAVE_VEPU22,
-        {   &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, &avsd, },
+        {   &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, &avsd, NULL, },
         {   &vepu2_no_jpeg, &vepu22, NULL, NULL, },
     },
     {   /*
@@ -509,7 +525,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rk3328",
         ROCKCHIP_SOC_RK3328,
         HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_VEPU22,
-        {   &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, },
+        {   &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, },
         {   &vepu2, &vepu22, NULL, NULL, },
     },
     {   /*
@@ -521,7 +537,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rk3228",
         ROCKCHIP_SOC_RK3228,
         HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
-        {   &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, NULL, },
+        {   &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, },
         {   &vepu2_no_jpeg, NULL, NULL, NULL, },
     },
     {   /*
@@ -532,7 +548,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rk3229",
         ROCKCHIP_SOC_RK3229,
         HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
-        {   &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, },
+        {   &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, },
         {   &vepu2, NULL, NULL, NULL, },
     },
     {   /*
@@ -544,7 +560,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rv1108",
         ROCKCHIP_SOC_RV1108,
         HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC,
-        {   &vdpu2_jpeg, &vdpu341_h264, NULL, NULL, },
+        {   &vdpu2_jpeg, &vdpu341_h264, NULL, NULL, NULL, },
         {   &vepu2_jpeg, &vepu540p, NULL, NULL, },
     },
     {   /*
@@ -556,7 +572,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rv1109",
         ROCKCHIP_SOC_RV1109,
         HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC,
-        {   &vdpu2_jpeg, &vdpu341_lite, NULL, NULL, },
+        {   &vdpu2_jpeg, &vdpu341_lite, NULL, NULL, NULL, },
         {   &vepu2_jpeg, &vepu541, NULL, NULL, },
     },
     {   /*
@@ -568,7 +584,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rv1126",
         ROCKCHIP_SOC_RV1126,
         HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC,
-        {   &vdpu2_jpeg, &vdpu341_lite, NULL, NULL, },
+        {   &vdpu2_jpeg, &vdpu341_lite, NULL, NULL, NULL, },
         {   &vepu2_jpeg, &vepu541, NULL, NULL, },
     },
     {   /*
@@ -579,7 +595,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rk3326",
         ROCKCHIP_SOC_RK3326,
         HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_HEVC_DEC,
-        {   &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, },
+        {   &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, },
         {   &vepu2, NULL, NULL, NULL, },
     },
     {   /*
@@ -590,7 +606,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "px30",
         ROCKCHIP_SOC_RK3326,
         HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_HEVC_DEC,
-        {   &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, },
+        {   &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, },
         {   &vepu2, NULL, NULL, NULL, },
     },
     {   /*
@@ -599,7 +615,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rk1808",
         ROCKCHIP_SOC_RK1808,
         HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2,
-        {   &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, },
+        {   &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
         {   &vepu2, NULL, NULL, NULL, },
     },
     {   /*
@@ -612,7 +628,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rk3566",
         ROCKCHIP_SOC_RK3566,
         HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
-        {   &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, },
+        {   &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, NULL, },
         {   &vepu540, &vepu2, NULL, NULL, },
     },
     {   /*
@@ -625,7 +641,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         "rk3568",
         ROCKCHIP_SOC_RK3568,
         HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
-        {   &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, },
+        {   &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, NULL, },
         {   &vepu540, &vepu2, NULL, NULL, },
     },
     {   /*
@@ -637,8 +653,8 @@ static const MppSocInfo mpp_soc_infos[] = {
          */
         "rk3588",
         ROCKCHIP_SOC_RK3588,
-        HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
+        HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC | HAVE_AV1DEC,
-        {   &vdpu38x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, },
+        {   &vdpu38x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, &av1d},
         {   &vepu58x, &vepu2, &vepu2_jpeg, NULL, },
     },
 };