From a4ece5df051a4d23aea35f6d290112f3c3ae1e1b Mon Sep 17 00:00:00 2001 From: Yandong Lin Date: Thu, 25 Mar 2021 14:44:49 +0800 Subject: [PATCH] [hal_av1d]: Implement av1 decoder hal module Change-Id: I9dc410b55cc614e7a4a6353d52a70c806e467b2e Signed-off-by: Yandong Lin --- mpp/hal/CMakeLists.txt | 1 + mpp/hal/inc/hal_av1d_api.h | 32 + mpp/hal/mpp_hal.cpp | 4 + mpp/hal/vpu/CMakeLists.txt | 4 + mpp/hal/vpu/av1d/CMakeLists.txt | 22 + mpp/hal/vpu/av1d/av1d_common.h | 840 +++++++ mpp/hal/vpu/av1d/film_grain_noise_table.c | 374 ++++ mpp/hal/vpu/av1d/film_grain_noise_table.h | 33 + mpp/hal/vpu/av1d/hal_av1d_api.c | 187 ++ mpp/hal/vpu/av1d/hal_av1d_common.h | 194 ++ mpp/hal/vpu/av1d/hal_av1d_vdpu.c | 2368 ++++++++++++++++++++ mpp/hal/vpu/av1d/hal_av1d_vdpu.h | 32 + mpp/hal/vpu/av1d/hal_av1d_vdpu_reg.h | 2442 +++++++++++++++++++++ osal/inc/mpp_dev_defs.h | 2 + osal/inc/mpp_soc.h | 2 +- osal/mpp_soc.cpp | 62 +- 16 files changed, 6575 insertions(+), 24 deletions(-) create mode 100644 mpp/hal/inc/hal_av1d_api.h create mode 100644 mpp/hal/vpu/av1d/CMakeLists.txt create mode 100644 mpp/hal/vpu/av1d/av1d_common.h create mode 100644 mpp/hal/vpu/av1d/film_grain_noise_table.c create mode 100644 mpp/hal/vpu/av1d/film_grain_noise_table.h create mode 100644 mpp/hal/vpu/av1d/hal_av1d_api.c create mode 100644 mpp/hal/vpu/av1d/hal_av1d_common.h create mode 100644 mpp/hal/vpu/av1d/hal_av1d_vdpu.c create mode 100644 mpp/hal/vpu/av1d/hal_av1d_vdpu.h create mode 100644 mpp/hal/vpu/av1d/hal_av1d_vdpu_reg.h diff --git a/mpp/hal/CMakeLists.txt b/mpp/hal/CMakeLists.txt index 15fe4d4b..5e46e676 100755 --- a/mpp/hal/CMakeLists.txt +++ b/mpp/hal/CMakeLists.txt @@ -32,6 +32,7 @@ target_link_libraries(mpp_hal ${HAL_VP8D} ${HAL_VP9D} ${HAL_JPEGD} + ${HAL_AV1D} ${HAL_H264E} ${HAL_JPEGE} ${HAL_H265E} diff --git a/mpp/hal/inc/hal_av1d_api.h b/mpp/hal/inc/hal_av1d_api.h new file mode 100644 index 00000000..98cc9669 --- /dev/null +++ b/mpp/hal/inc/hal_av1d_api.h @@ -0,0 +1,32 @@ +/* + * Copyright 2021 Rockchip Electronics Co. LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_AV1D_API_H__ +#define __HAL_AV1D_API_H__ + +#include "mpp_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern const MppHalApi hal_api_av1d; + +#ifdef __cplusplus +} +#endif + +#endif /*__HAL_H265D_API_H__*/ diff --git a/mpp/hal/mpp_hal.cpp b/mpp/hal/mpp_hal.cpp index 662b0b4c..4b444cc5 100644 --- a/mpp/hal/mpp_hal.cpp +++ b/mpp/hal/mpp_hal.cpp @@ -33,6 +33,7 @@ #include "hal_m2vd_api.h" #include "hal_mpg4d_api.h" #include "hal_jpegd_api.h" +#include "hal_av1d_api.h" // for test and demo #include "hal_dummy_dec_api.h" @@ -68,6 +69,9 @@ static const MppHalApi *hw_apis[] = { #endif #if HAVE_JPEGD &hal_api_jpegd, +#endif +#if HAVE_AV1D + &hal_api_av1d, #endif &hal_api_dummy_dec, &hal_api_dummy_enc, diff --git a/mpp/hal/vpu/CMakeLists.txt b/mpp/hal/vpu/CMakeLists.txt index c079ff63..151e4610 100644 --- a/mpp/hal/vpu/CMakeLists.txt +++ b/mpp/hal/vpu/CMakeLists.txt @@ -22,6 +22,10 @@ if( HAVE_JPEGD ) add_subdirectory(jpegd) endif() +if( HAVE_AV1D ) + add_subdirectory(av1d) +endif() + if( HAVE_JPEGE ) add_subdirectory(jpege) endif() diff --git a/mpp/hal/vpu/av1d/CMakeLists.txt b/mpp/hal/vpu/av1d/CMakeLists.txt new file mode 100644 index 00000000..616ce7cf --- /dev/null +++ b/mpp/hal/vpu/av1d/CMakeLists.txt @@ -0,0 +1,22 @@ +# vim: syntax=cmake +# hal jpeg reg + +set(HAL_AV1D_HDR + hal_av1d_common.h + ) + +set(HAL_AV1D_SRC + hal_av1d_api.c + hal_av1d_vdpu.c + film_grain_noise_table.c + ) + +add_library(${HAL_AV1D} STATIC + ${HAL_AV1D_SRC} + ${HAL_AV1D_HDR} + ) + +set_target_properties(${HAL_AV1D} PROPERTIES FOLDER "mpp/hal") +target_link_libraries(${HAL_AV1D} mpp_base) + +#add_subdirectory(test) diff --git a/mpp/hal/vpu/av1d/av1d_common.h b/mpp/hal/vpu/av1d/av1d_common.h new file mode 100644 index 00000000..01e6066a --- /dev/null +++ b/mpp/hal/vpu/av1d/av1d_common.h @@ -0,0 +1,840 @@ +/* + * Copyright 2021 Rockchip Electronics Co. LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __AV1D_COMMON_H__ +#define __AV1D_COMMON_H__ + +#include "mpp_common.h" +#include "hal_av1d_common.h" +#define AV1_REF_SCALE_SHIFT 14 + +#define NUM_REF_FRAMES 8 +#define NUM_REF_FRAMES_LG2 3 + +// Max tiles for AV1 (custom size) for Level <= 6.x +#define AV1_MAX_TILES 128 +#define AV1_MAX_TILE_COL 64 +#define AV1_MAX_TILE_ROW 64 + +#define AV1_MIN_COMP_BASIS 8 +#define AV1_MAX_CODED_FRAME_SIZE \ + (8192 * 4352 * 10 * 6 / 32 / AV1_MIN_COMP_BASIS) /* approx 8 MB */ + +#define ALLOWED_REFS_PER_FRAME_EX 7 + +#define NUM_FRAME_CONTEXTS_LG2_EX 3 +#define NUM_FRAME_CONTEXTS_EX (1 << NUM_FRAME_CONTEXTS_LG2_EX) + +#define MIN_TILE_WIDTH 256 +#define MAX_TILE_WIDTH 4096 +#define MIN_TILE_WIDTH_SBS (MIN_TILE_WIDTH >> 6) +#define MAX_TILE_WIDTH_SBS (MAX_TILE_WIDTH >> 6) +#define FRAME_OFFSET_BITS 5 +#define MAX_TILE_AREA (4096 * 2304) +#define AV1_MAX_TILE_COLS 64 +#define AV1_MAX_TILE_ROWS 64 + +#define ALLOWED_REFS_PER_FRAME 3 + +#define NUM_FRAME_CONTEXTS_LG2 2 +#define NUM_FRAME_CONTEXTS (1 << NUM_FRAME_CONTEXTS_LG2) + +#define DCPREDSIMTHRESH 0 +#define DCPREDCNTTHRESH 3 + +#define PREDICTION_PROBS 3 + +#define DEFAULT_PRED_PROB_0 120 +#define DEFAULT_PRED_PROB_1 80 +#define DEFAULT_PRED_PROB_2 40 + +#define AV1_DEF_UPDATE_PROB 252 + +#define MBSKIP_CONTEXTS 3 + +#define MAX_MB_SEGMENTS 8 +#define MB_SEG_TREE_PROBS (MAX_MB_SEGMENTS - 1) + +#define MAX_REF_LF_DELTAS_EX 8 + +#define MAX_REF_LF_DELTAS 4 +#define MAX_MODE_LF_DELTAS 2 + +/* Segment Feature Masks */ +#define SEGMENT_DELTADATA 0 +#define SEGMENT_ABSDATA 1 +#define MAX_MV_REFS 9 + +#define AV1_SWITCHABLE_FILTERS 3 /* number of switchable filters */ +#define SWITCHABLE_FILTER_CONTEXTS ((AV1_SWITCHABLE_FILTERS + 1) * 4) +#ifdef DUAL_FILTER +#define AV1_SWITCHABLE_EXT_FILTERS 4 /* number of switchable filters */ +#endif + +#define COMP_PRED_CONTEXTS 2 + +#define COEF_UPDATE_PROB 252 +#define AV1_PROB_HALF 128 +#define AV1_NMV_UPDATE_PROB 252 +#define AV1_MV_UPDATE_PRECISION 7 +#define MV_JOINTS 4 +#define MV_FP_SIZE 4 +#define MV_CLASSES 11 +#define CLASS0_BITS 1 +#define CLASS0_SIZE (1 << CLASS0_BITS) +#define MV_OFFSET_BITS (MV_CLASSES + CLASS0_BITS - 2) + +#define MV_MAX_BITS (MV_CLASSES + CLASS0_BITS + 2) +#define MV_MAX ((1 << MV_MAX_BITS) - 1) +#define MV_VALS ((MV_MAX << 1) + 1) + +#define MAX_ENTROPY_TOKENS 12 +#define ENTROPY_NODES 11 + +/* The first nodes of the entropy probs are unconstrained, the rest are + * modeled with statistic distribution. */ +#define UNCONSTRAINED_NODES 3 +#define MODEL_NODES (ENTROPY_NODES - UNCONSTRAINED_NODES) +#define PIVOT_NODE 2 // which node is pivot +#define COEFPROB_MODELS 128 + +/* Entropy nodes above is divided in two parts, first three probs in part1 + * and the modeled probs in part2. Part1 is padded so that tables align with + * 32 byte addresses, so there is four bytes for each table. */ +#define ENTROPY_NODES_PART1 4 +#define ENTROPY_NODES_PART2 8 +#define INTER_MODE_CONTEXTS 7 +#define AV1_INTER_MODE_CONTEXTS 15 + +#define CFL_JOINT_SIGNS 8 +#define CFL_ALPHA_CONTEXTS 6 +#define CFL_ALPHABET_SIZE 16 + +#define NEWMV_MODE_CONTEXTS 6 +#define ZEROMV_MODE_CONTEXTS 2 +#define GLOBALMV_MODE_CONTEXTS 2 +#define REFMV_MODE_CONTEXTS 9 +#define DRL_MODE_CONTEXTS 3 +#define NMV_CONTEXTS 3 + +#define INTRA_INTER_CONTEXTS 4 +#define COMP_INTER_CONTEXTS 5 +#define REF_CONTEXTS 5 +#define AV1_REF_CONTEXTS 3 +#define FWD_REFS 4 +#define BWD_REFS 3 +#define SINGLE_REFS 7 + +#define BLOCK_TYPES 2 +#define REF_TYPES 2 // intra=0, inter=1 +#define COEF_BANDS 6 +#define PREV_COEF_CONTEXTS 6 + +#define MODULUS_PARAM 13 /* Modulus parameter */ + +#define ACTIVE_HT 110 // quantization stepsize threshold + +#define MAX_MV_REF_CANDIDATES 2 + +/* Coefficient token alphabet */ + +#define ZERO_TOKEN 0 /* 0 Extra Bits 0+0 */ +#define ONE_TOKEN 1 /* 1 Extra Bits 0+1 */ +#define TWO_TOKEN 2 /* 2 Extra Bits 0+1 */ +#define THREE_TOKEN 3 /* 3 Extra Bits 0+1 */ +#define FOUR_TOKEN 4 /* 4 Extra Bits 0+1 */ +#define DCT_VAL_CATEGORY1 5 /* 5-6 Extra Bits 1+1 */ +#define DCT_VAL_CATEGORY2 6 /* 7-10 Extra Bits 2+1 */ +#define DCT_VAL_CATEGORY3 7 /* 11-18 Extra Bits 3+1 */ +#define DCT_VAL_CATEGORY4 8 /* 19-34 Extra Bits 4+1 */ +#define DCT_VAL_CATEGORY5 9 /* 35-66 Extra Bits 5+1 */ +#define DCT_VAL_CATEGORY6 10 /* 67+ Extra Bits 13+1 */ +#define DCT_EOB_TOKEN 11 /* EOB Extra Bits 0+0 */ +#define MAX_ENTROPY_TOKENS 12 + +#define INTERINTRA_MODES 4 +#define INTER_COMPOUND_MODES 8 +#define COMPOUND_TYPES 3 +#define HEAD_TOKENS 5 +#define TAIL_TOKENS 9 +#define ONE_TOKEN_EOB 1 +#define ONE_TOKEN_NEOB 2 + +#define MULTICORE_LEFT_TILE 1 +#define MULTICORE_INNER_TILE 2 +#define MULTICORE_RIGHT_TILE 3 + +#define DCT_EOB_MODEL_TOKEN 3 /* EOB Extra Bits 0+0 */ + +typedef RK_U32 av1_coeff_count[REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS] +[UNCONSTRAINED_NODES + 1]; +typedef RK_U8 av1_coeff_probs[REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS] +[UNCONSTRAINED_NODES]; + +#define BLOCK_SIZE_GROUPS 4 + +// AV1 extended transforms (ext_tx) +#define EXT_TX_SETS_INTER 4 // Sets of transform selections for INTER +#define EXT_TX_SETS_INTRA 3 // Sets of transform selections for INTRA +#define EXTTX_SIZES 4 // ext_tx experiment tx sizes +#define EXT_TX_TYPES 16 + +#define EXT_TX_SIZES 3 + +#define TX_TYPES 4 + +#define ROUND_POWER_OF_TWO(value, n) (((value) + (1 << ((n)-1))) >> (n)) + +/* Shift down with rounding for use when n >= 0, value >= 0 for (64 bit) */ +#define ROUND_POWER_OF_TWO_64(value, n) \ + (((value) + ((((int64)1 << (n)) >> 1))) >> (n)) + +/* Shift down with rounding for signed integers, for use when n >= 0 (64 bit) */ +#define ROUND_POWER_OF_TWO_SIGNED_64(value, n) \ + (((value) < 0) ? -ROUND_POWER_OF_TWO_64(-(value), (n)) \ + : ROUND_POWER_OF_TWO_64((value), (n))) + +/* Shift down with rounding for signed integers, for use when n >= 0 */ +#define ROUND_POWER_OF_TWO_SIGNED(value, n) \ + (((value) < 0) ? -ROUND_POWER_OF_TWO(-(value), (n)) \ + : ROUND_POWER_OF_TWO((value), (n))) + +typedef RK_U16 av1_cdf; + +enum BlockSizeType { + BLOCK_SIZE_AB4X4, + BLOCK_SIZE_SB4X8, + BLOCK_SIZE_SB8X4, + BLOCK_SIZE_SB8X8, + BLOCK_SIZE_SB8X16, + BLOCK_SIZE_SB16X8, + BLOCK_SIZE_MB16X16, + BLOCK_SIZE_SB16X32, + BLOCK_SIZE_SB32X16, + BLOCK_SIZE_SB32X32, + BLOCK_SIZE_SB32X64, + BLOCK_SIZE_SB64X32, + BLOCK_SIZE_SB64X64, + BLOCK_SIZE_SB64X128, + BLOCK_SIZE_SB128X64, + BLOCK_SIZE_SB128X128, + BLOCK_SIZE_SB4X16, + BLOCK_SIZE_SB16X4, + BLOCK_SIZE_SB8X32, + BLOCK_SIZE_SB32X8, + BLOCK_SIZE_SB16X64, + BLOCK_SIZE_SB64X16, + BLOCK_SIZE_TYPES, + BLOCK_SIZES_ALL = BLOCK_SIZE_TYPES +}; + +enum PartitionType { + PARTITION_NONE, + PARTITION_HORZ, + PARTITION_VERT, + PARTITION_SPLIT, + /* + PARTITION_HORZ_A, + PARTITION_HORZ_B, + PARTITION_VERT_A, + PARTITION_VERT_B, + PARTITION_HORZ_4, + PARTITION_VERT_4, + */ + PARTITION_TYPES +}; + +#define PARTITION_PLOFFSET 4 // number of probability models per block size +#define NUM_PARTITION_CONTEXTS (4 * PARTITION_PLOFFSET) + +enum FrameType { + KEY_FRAME = 0, + INTER_FRAME = 1, + NUM_FRAME_TYPES, +}; + +enum MbPredictionMode { + DC_PRED, /* average of above and left pixels */ + V_PRED, /* vertical prediction */ + H_PRED, /* horizontal prediction */ + D45_PRED, /* Directional 45 deg prediction [anti-clockwise from 0 deg hor] */ + D135_PRED, /* Directional 135 deg prediction [anti-clockwise from 0 deg hor] + */ + D117_PRED, /* Directional 112 deg prediction [anti-clockwise from 0 deg hor] + */ + D153_PRED, /* Directional 157 deg prediction [anti-clockwise from 0 deg hor] + */ + D27_PRED, /* Directional 22 deg prediction [anti-clockwise from 0 deg hor] */ + D63_PRED, /* Directional 67 deg prediction [anti-clockwise from 0 deg hor] */ + SMOOTH_PRED, + TM_PRED_AV1 = SMOOTH_PRED, + SMOOTH_V_PRED, // Vertical interpolation + SMOOTH_H_PRED, // Horizontal interpolation + TM_PRED, /* Truemotion prediction */ + PAETH_PRED = TM_PRED, + NEARESTMV, + NEARMV, + ZEROMV, + NEWMV, + NEAREST_NEARESTMV, + NEAR_NEARMV, + NEAREST_NEWMV, + NEW_NEARESTMV, + NEAR_NEWMV, + NEW_NEARMV, + ZERO_ZEROMV, + NEW_NEWMV, + SPLITMV, + MB_MODE_COUNT +}; + +// Must match hardware/src/include/common_defs.h +#define AV1_INTRA_MODES 13 + +#define MAX_INTRA_MODES AV1_INTRA_MODES + +#define MAX_INTRA_MODES_DRAM_ALIGNED ((MAX_INTRA_MODES + 15) & (~15)) + +#define AV1_INTER_MODES (1 + NEWMV - NEARESTMV) + +#define MOTION_MODE_CONTEXTS 10 + +#define DIRECTIONAL_MODES 8 +#define MAX_ANGLE_DELTA 3 + +enum FilterIntraModeType { + FILTER_DC_PRED, + FILTER_V_PRED, + FILTER_H_PRED, + FILTER_D153_PRED, + FILTER_PAETH_PRED, + FILTER_INTRA_MODES, + FILTER_INTRA_UNUSED = 7 +}; + +#define FILTER_INTRA_SIZES 19 + +enum { SIMPLE_TRANSLATION, OBMC_CAUSAL, MOTION_MODE_COUNT }; + +#define SUBMVREF_COUNT 5 + +/* Integer pel reference mv threshold for use of high-precision 1/8 mv */ +#define COMPANDED_MVREF_THRESH 8 + +#define TX_SIZE_CONTEXTS 2 +#define AV1_TX_SIZE_CONTEXTS 3 +#define VARTX_PART_CONTEXTS 22 +#define TXFM_PARTITION_CONTEXTS 22 + +enum InterpolationFilterType { + EIGHTTAP_SMOOTH, + EIGHTTAP, + EIGHTTAP_SHARP, +#ifdef DUAL_FILTER + EIGHTTAP_SMOOTH2, + BILINEAR, + SWITCHABLE, /* should be the last one */ +#else + BILINEAR, + SWITCHABLE, /* should be the last one */ +#endif + MULTITAP_SHARP = EIGHTTAP_SHARP +}; + +static const int av1_literal_to_filter[4] = { + EIGHTTAP_SMOOTH, EIGHTTAP, + EIGHTTAP_SHARP, BILINEAR +}; + +extern const enum InterpolationFilterType +av1hwd_switchable_interp[AV1_SWITCHABLE_FILTERS]; + +enum CompPredModeType { + SINGLE_PREDICTION_ONLY = 0, + COMP_PREDICTION_ONLY = 1, + HYBRID_PREDICTION = 2, + NB_PREDICTION_TYPES = 3, +}; + +enum TxfmMode { + ONLY_4X4 = 0, + ALLOW_8X8 = 1, + ALLOW_16X16 = 2, + ALLOW_32X32 = 3, + TX_MODE_LARGEST = ALLOW_32X32, // AV1 + TX_MODE_SELECT = 4, + NB_TXFM_MODES = 5, +}; + +enum SegLevelFeatures { + SEG_LVL_ALT_Q = 0, + SEG_LVL_ALT_LF = 1, + SEG_LVL_REF_FRAME = 2, + SEG_LVL_SKIP = 3, + SEG_LVL_MAX = 4 +}; + +enum { AV1_SEG_FEATURE_DELTA, AV1_SEG_FEATURE_ABS }; + +static const int av1_seg_feature_data_signed[SEG_AV1_LVL_MAX] = { + 1, 1, 1, 1, + 1, 0, 0 +}; + +static const int av1_seg_feature_data_max[SEG_AV1_LVL_MAX] = { + 255, 63, 63, 63, + 63, 7, 0 +}; + +static const int av1_seg_feature_data_bits[SEG_AV1_LVL_MAX] = { + 8, 6, 6, 6, + 6, 3, 0 +}; + +enum TxSize { + TX_4X4 = 0, + TX_8X8 = 1, + TX_16X16 = 2, + TX_32X32 = 3, + TX_SIZE_MAX_SB, +}; +#define MAX_TX_DEPTH 2 + +enum TxType { DCT_DCT = 0, ADST_DCT = 1, DCT_ADST = 2, ADST_ADST = 3 }; + +enum SplitMvPartitioningType { + PARTITIONING_16X8 = 0, + PARTITIONING_8X16, + PARTITIONING_8X8, + PARTITIONING_4X4, + NB_PARTITIONINGS, +}; + +enum PredId { + PRED_SEG_ID = 0, + PRED_MBSKIP = 1, + PRED_SWITCHABLE_INTERP = 2, + PRED_INTRA_INTER = 3, + PRED_COMP_INTER_INTER = 4, + PRED_SINGLE_REF_P1 = 5, + PRED_SINGLE_REF_P2 = 6, + PRED_COMP_REF_P = 7, + PRED_TX_SIZE = 8 +}; + +/* Symbols for coding which components are zero jointly */ +enum MvJointType { + MV_JOINT_ZERO = 0, /* Zero vector */ + MV_JOINT_HNZVZ = 1, /* Vert zero, hor nonzero */ + MV_JOINT_HZVNZ = 2, /* Hor zero, vert nonzero */ + MV_JOINT_HNZVNZ = 3, /* Both components nonzero */ +}; + +/* Symbols for coding magnitude class of nonzero components */ +enum MvClassType { + MV_CLASS_0 = 0, /* (0, 2] integer pel */ + MV_CLASS_1 = 1, /* (2, 4] integer pel */ + MV_CLASS_2 = 2, /* (4, 8] integer pel */ + MV_CLASS_3 = 3, /* (8, 16] integer pel */ + MV_CLASS_4 = 4, /* (16, 32] integer pel */ + MV_CLASS_5 = 5, /* (32, 64] integer pel */ + MV_CLASS_6 = 6, /* (64, 128] integer pel */ + MV_CLASS_7 = 7, /* (128, 256] integer pel */ + MV_CLASS_8 = 8, /* (256, 512] integer pel */ + MV_CLASS_9 = 9, /* (512, 1024] integer pel */ + MV_CLASS_10 = 10, /* (1024,2048] integer pel */ +}; + +enum RefreshFrameContextModeAv1 { + /** + * AV1 Only, no refresh + */ + AV1_REFRESH_FRAME_CONTEXT_NONE, + /** + * Update frame context to values resulting from backward probability + * updates based on entropy/counts in the decoded frame + */ + AV1_REFRESH_FRAME_CONTEXT_BACKWARD +}; + +// 75B +struct NmvContext { + // Start at +27B offset + RK_U8 joints[MV_JOINTS - 1]; // 3B + RK_U8 sign[2]; // 2B + + // A+1 + RK_U8 class0[2][CLASS0_SIZE - 1]; // 2B + RK_U8 fp[2][MV_FP_SIZE - 1]; // 6B + RK_U8 class0_hp[2]; // 2B + RK_U8 hp[2]; // 2B + RK_U8 classes[2][MV_CLASSES - 1]; // 20B + + // A+2 + RK_U8 class0_fp[2][CLASS0_SIZE][MV_FP_SIZE - 1]; // 12B + RK_U8 bits[2][MV_OFFSET_BITS]; // 20B +}; + +struct NmvContextCounts { + // 8dw (u32) / DRAM word (u256) + RK_U32 joints[MV_JOINTS]; + RK_U32 sign[2][2]; + RK_U32 classes[2][MV_CLASSES]; + RK_U32 class0[2][CLASS0_SIZE]; + RK_U32 bits[2][MV_OFFSET_BITS][2]; + RK_U32 class0_fp[2][CLASS0_SIZE][4]; + RK_U32 fp[2][4]; + RK_U32 class0_hp[2][2]; + RK_U32 hp[2][2]; +}; + +typedef RK_U8 av1_prob; + +#define ICDF(x) (32768U - (x)) +#define CDF_SIZE(x) ((x)-1) + +#define AV1HWPAD(x, y) RK_U8 x[y] + +struct NmvJointSign { + RK_U8 joints[MV_JOINTS - 1]; // 3B + RK_U8 sign[2]; // 2B +}; + +struct NmvMagnitude { + RK_U8 class0[2][CLASS0_SIZE - 1]; + RK_U8 fp[2][MV_FP_SIZE - 1]; + RK_U8 class0_hp[2]; + RK_U8 hp[2]; + RK_U8 classes[2][MV_CLASSES - 1]; + RK_U8 class0_fp[2][CLASS0_SIZE][MV_FP_SIZE - 1]; + RK_U8 bits[2][MV_OFFSET_BITS]; +}; + +struct RefMvNmvContext { + // Starts at +4B offset (for mbskip) + struct NmvJointSign joints_sign[NMV_CONTEXTS]; // 15B + AV1HWPAD(pad1, 13); + + // A+1 + struct NmvMagnitude magnitude[NMV_CONTEXTS]; +}; + +/* Adaptive entropy contexts, padding elements are added to have + * 256 bit aligned tables for HW access. + * Compile with TRACE_PROB_TABLES to print bases for each table. */ +struct Av1AdaptiveEntropyProbs { + // address A (56) + + // Address A+0 + RK_U8 inter_mode_prob[INTER_MODE_CONTEXTS][4]; // 7*4 = 28B + RK_U8 intra_inter_prob[INTRA_INTER_CONTEXTS]; // 4B + + // Address A+1 + RK_U8 uv_mode_prob[MAX_INTRA_MODES] + [MAX_INTRA_MODES_DRAM_ALIGNED]; // 10*16/32 = 5 addrs + +#if ((MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32) + AV1HWPAD(pad1, + ((MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32 == 0) + ? 0 + : 32 - (MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32); +#endif + + // Address A+6 + RK_U8 tx8x8_prob[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB - 3]; // 2*(4-3) = 2B + RK_U8 tx16x16_prob[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB - 2]; // 2*(4-2) = 4B + RK_U8 tx32x32_prob[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB - 1]; // 2*(4-1) = 6B + + RK_U8 switchable_interp_prob[AV1_SWITCHABLE_FILTERS + 1] + [AV1_SWITCHABLE_FILTERS - 1]; // 8B + RK_U8 comp_inter_prob[COMP_INTER_CONTEXTS]; // 5B + + AV1HWPAD(pad6, 7); + + // Address A+7 + RK_U8 sb_ymode_prob[BLOCK_SIZE_GROUPS] + [MAX_INTRA_MODES_DRAM_ALIGNED]; // 4*16/32 = 2 addrs + + // Address A+9 + RK_U8 partition_prob[NUM_FRAME_TYPES][NUM_PARTITION_CONTEXTS] + [PARTITION_TYPES]; // 2*16*4 = 4 addrs + + // Address A+13 + AV1HWPAD(pad13, 24); + RK_U8 mbskip_probs[MBSKIP_CONTEXTS]; // 3B + struct NmvContext nmvc; + + // Address A+16 + RK_U8 single_ref_prob[REF_CONTEXTS][2]; // 10B + RK_U8 comp_ref_prob[REF_CONTEXTS]; // 5B + RK_U8 mb_segment_tree_probs[MB_SEG_TREE_PROBS]; // 7B + RK_U8 segment_pred_probs[PREDICTION_PROBS]; // 3B + AV1HWPAD(pad16, 7); + + // Address A+17 + RK_U8 prob_coeffs[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS] + [ENTROPY_NODES_PART1]; // 18 addrs + RK_U8 prob_coeffs8x8[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS] + [ENTROPY_NODES_PART1]; + RK_U8 prob_coeffs16x16[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS] + [ENTROPY_NODES_PART1]; + RK_U8 prob_coeffs32x32[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS] + [ENTROPY_NODES_PART1]; +}; + +/* Entropy contexts */ +struct Av1EntropyProbs { + /* Default keyframe probs */ + /* Table formatted for 256b memory, probs 0to7 for all tables followed by + * probs 8toN for all tables. + * Compile with TRACE_PROB_TABLES to print bases for each table. */ + + // In AOM code, this table is [M][M][M-1]; we pad to 16B so each entry is 1/2 + // DRAM word. + RK_U8 kf_bmode_prob[MAX_INTRA_MODES][MAX_INTRA_MODES] + [MAX_INTRA_MODES_DRAM_ALIGNED]; + +#if ((MAX_INTRA_MODES * MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32) + AV1HWPAD(pad0, (((MAX_INTRA_MODES * MAX_INTRA_MODES * + MAX_INTRA_MODES_DRAM_ALIGNED) % + 32) == 0) + ? 0 + : 32 - ((MAX_INTRA_MODES * MAX_INTRA_MODES * + MAX_INTRA_MODES_DRAM_ALIGNED) % + 32)); +#endif + + // Address 50 + AV1HWPAD(unused_bytes, 4); // 4B of padding to maintain the old alignments. + RK_U8 ref_pred_probs[PREDICTION_PROBS]; // 3B + RK_U8 ref_scores[MAX_REF_FRAMES]; // 4B + RK_U8 prob_comppred[COMP_PRED_CONTEXTS]; // 2B + + AV1HWPAD(pad1, 19); + + // Address 51 + RK_U8 kf_uv_mode_prob[MAX_INTRA_MODES][MAX_INTRA_MODES_DRAM_ALIGNED]; + +#if ((MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32) + AV1HWPAD(pad51, + ((MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32 == 0) + ? 0 + : 32 - (MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32); +#endif + + // Address 56 + struct Av1AdaptiveEntropyProbs a; // Probs with backward adaptation +}; + +/* Counters for adaptive entropy contexts */ +struct Av1EntropyCounts { + RK_U32 inter_mode_counts[INTER_MODE_CONTEXTS][AV1_INTER_MODES - 1][2]; + RK_U32 sb_ymode_counts[BLOCK_SIZE_GROUPS][MAX_INTRA_MODES]; + RK_U32 uv_mode_counts[MAX_INTRA_MODES][MAX_INTRA_MODES]; + RK_U32 partition_counts[NUM_PARTITION_CONTEXTS][PARTITION_TYPES]; + RK_U32 switchable_interp_counts[AV1_SWITCHABLE_FILTERS + 1] + [AV1_SWITCHABLE_FILTERS]; + RK_U32 intra_inter_count[INTRA_INTER_CONTEXTS][2]; + RK_U32 comp_inter_count[COMP_INTER_CONTEXTS][2]; + RK_U32 single_ref_count[REF_CONTEXTS][2][2]; + RK_U32 comp_ref_count[REF_CONTEXTS][2]; + RK_U32 tx32x32_count[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB]; + RK_U32 tx16x16_count[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB - 1]; + RK_U32 tx8x8_count[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB - 2]; + RK_U32 mbskip_count[MBSKIP_CONTEXTS][2]; + + struct NmvContextCounts nmvcount; + + RK_U32 count_coeffs[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS][UNCONSTRAINED_NODES + 1]; + RK_U32 count_coeffs8x8[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS][UNCONSTRAINED_NODES + 1]; + RK_U32 count_coeffs16x16[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS][UNCONSTRAINED_NODES + 1]; + RK_U32 count_coeffs32x32[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS][UNCONSTRAINED_NODES + 1]; + + RK_U32 count_eobs[TX_SIZE_MAX_SB][BLOCK_TYPES][REF_TYPES][COEF_BANDS] + [PREV_COEF_CONTEXTS]; +}; + +struct CoeffHeadCDFModel { + RK_U16 band0[3][5]; + RK_U16 bands[5][6][4]; +}; + +struct CoeffTailCDFModel { + RK_U16 band0[3][9]; + RK_U16 bands[5][6][9]; +}; + +// 135 +typedef struct CoeffHeadCDFModel coeff_head_cdf_model[BLOCK_TYPES][REF_TYPES]; +// 297 +typedef struct CoeffTailCDFModel coeff_tail_cdf_model[BLOCK_TYPES][REF_TYPES]; + +//#define PALETTE_BLOCK_SIZES (BLOCK_SIZE_SB64X64 - BLOCK_SIZE_SB8X8 + 1) +#define PALETTE_BLOCK_SIZES 7 +#define PALETTE_SIZES 7 +#define PALETTE_Y_MODE_CONTEXTS 3 +#define PALETTE_UV_MODE_CONTEXTS 2 +#define PALETTE_COLOR_INDEX_CONTEXTS 5 +#define PALETTE_IDX_CONTEXTS 18 +#define PALETTE_COLORS 8 +#define KF_MODE_CONTEXTS 5 + +#define PLANE_TYPES 2 +#define TX_SIZES 5 +#define TXB_SKIP_CONTEXTS 13 +#define DC_SIGN_CONTEXTS 3 +#define SIG_COEF_CONTEXTS_EOB 4 +#define SIG_COEF_CONTEXTS 42 +#define COEFF_BASE_CONTEXTS 42 +#define EOB_COEF_CONTEXTS 9 +#define LEVEL_CONTEXTS 21 +#define NUM_BASE_LEVELS 2 +#define BR_CDF_SIZE 4 +#define MOTION_MODES 3 +#define DELTA_Q_PROBS 3 +#define COMP_REF_TYPE_CONTEXTS 5 +#define UNI_COMP_REF_CONTEXTS 3 +#define UNIDIR_COMP_REFS 4 +//#define FILTER_INTRA_MODES 5 +#define SKIP_MODE_CONTEXTS 3 +#define SKIP_CONTEXTS 3 +#define COMP_INDEX_CONTEXTS 6 +#define COMP_GROUP_IDX_CONTEXTS 7 +#define MAX_TX_CATS 4 +#define CFL_ALLOWED_TYPES 2 +#define UV_INTRA_MODES 14 +#define EXT_PARTITION_TYPES 10 +#define AV1_PARTITION_CONTEXTS (5 * PARTITION_PLOFFSET) + +#define RESTORE_SWITCHABLE_TYPES 3 +#define DELTA_LF_PROBS 3 +#define FRAME_LF_COUNT 4 +#define MAX_SEGMENTS 8 +#define TOKEN_CDF_Q_CTXS 4 +#define SEG_TEMPORAL_PRED_CTXS 3 +#define SPATIAL_PREDICTION_PROBS 3 + +typedef RK_U16 aom_cdf_prob; + +typedef struct { + RK_U16 joint_cdf[3]; + RK_U16 sign_cdf[2]; + RK_U16 clsss_cdf[2][10]; + RK_U16 clsss0_fp_cdf[2][2][3]; + RK_U16 fp_cdf[2][3]; + RK_U16 class0_hp_cdf[2]; + RK_U16 hp_cdf[2]; + RK_U16 class0_cdf[2]; + RK_U16 bits_cdf[2][10]; +} MvCDFs; + +typedef struct { + RK_U16 partition_cdf[13][16]; + // 64 + RK_U16 kf_ymode_cdf[KF_MODE_CONTEXTS][KF_MODE_CONTEXTS][AV1_INTRA_MODES - 1]; + RK_U16 segment_pred_cdf[PREDICTION_PROBS]; + RK_U16 spatial_pred_seg_tree_cdf[SPATIAL_PREDICTION_PROBS][MAX_MB_SEGMENTS - 1]; + RK_U16 mbskip_cdf[MBSKIP_CONTEXTS]; + RK_U16 delta_q_cdf[DELTA_Q_PROBS]; + RK_U16 delta_lf_multi_cdf[FRAME_LF_COUNT][DELTA_LF_PROBS]; + RK_U16 delta_lf_cdf[DELTA_LF_PROBS]; + RK_U16 skip_mode_cdf[SKIP_MODE_CONTEXTS]; + RK_U16 vartx_part_cdf[VARTX_PART_CONTEXTS][1]; + RK_U16 tx_size_cdf[MAX_TX_CATS][AV1_TX_SIZE_CONTEXTS][MAX_TX_DEPTH]; + RK_U16 if_ymode_cdf[BLOCK_SIZE_GROUPS][AV1_INTRA_MODES - 1]; + RK_U16 uv_mode_cdf[2][AV1_INTRA_MODES][AV1_INTRA_MODES - 1 + 1]; + RK_U16 intra_inter_cdf[INTRA_INTER_CONTEXTS]; + RK_U16 comp_inter_cdf[COMP_INTER_CONTEXTS]; + RK_U16 single_ref_cdf[AV1_REF_CONTEXTS][SINGLE_REFS - 1]; + RK_U16 comp_ref_type_cdf[COMP_REF_TYPE_CONTEXTS][1]; + RK_U16 uni_comp_ref_cdf[UNI_COMP_REF_CONTEXTS][UNIDIR_COMP_REFS - 1][1]; + RK_U16 comp_ref_cdf[AV1_REF_CONTEXTS][FWD_REFS - 1]; + RK_U16 comp_bwdref_cdf[AV1_REF_CONTEXTS][BWD_REFS - 1]; + RK_U16 newmv_cdf[NEWMV_MODE_CONTEXTS]; + RK_U16 zeromv_cdf[ZEROMV_MODE_CONTEXTS]; + RK_U16 refmv_cdf[REFMV_MODE_CONTEXTS]; + RK_U16 drl_cdf[DRL_MODE_CONTEXTS]; + RK_U16 interp_filter_cdf[SWITCHABLE_FILTER_CONTEXTS][AV1_SWITCHABLE_FILTERS - 1]; + + MvCDFs mv_cdf; + + RK_U16 obmc_cdf[BLOCK_SIZE_TYPES]; + RK_U16 motion_mode_cdf[BLOCK_SIZE_TYPES][2]; + + RK_U16 inter_compound_mode_cdf[AV1_INTER_MODE_CONTEXTS][INTER_COMPOUND_MODES - 1]; + RK_U16 compound_type_cdf[BLOCK_SIZE_TYPES][CDF_SIZE(COMPOUND_TYPES - 1)]; + RK_U16 interintra_cdf[BLOCK_SIZE_GROUPS]; + RK_U16 interintra_mode_cdf[BLOCK_SIZE_GROUPS][INTERINTRA_MODES - 1]; + RK_U16 wedge_interintra_cdf[BLOCK_SIZE_TYPES]; + RK_U16 wedge_idx_cdf[BLOCK_SIZE_TYPES][CDF_SIZE(16)]; + + RK_U16 palette_y_mode_cdf[PALETTE_BLOCK_SIZES][PALETTE_Y_MODE_CONTEXTS][1]; + RK_U16 palette_uv_mode_cdf[PALETTE_UV_MODE_CONTEXTS][1]; + RK_U16 palette_y_size_cdf[PALETTE_BLOCK_SIZES][PALETTE_SIZES - 1]; + RK_U16 palette_uv_size_cdf[PALETTE_BLOCK_SIZES][PALETTE_SIZES - 1]; + + RK_U16 cfl_sign_cdf[CFL_JOINT_SIGNS - 1]; + RK_U16 cfl_alpha_cdf[CFL_ALPHA_CONTEXTS][CFL_ALPHABET_SIZE - 1]; + + RK_U16 intrabc_cdf[1]; + RK_U16 angle_delta_cdf[DIRECTIONAL_MODES][6]; + + RK_U16 filter_intra_mode_cdf[FILTER_INTRA_MODES - 1]; + RK_U16 filter_intra_cdf[BLOCK_SIZES_ALL]; + RK_U16 comp_group_idx_cdf[COMP_GROUP_IDX_CONTEXTS][CDF_SIZE(2)]; + RK_U16 compound_idx_cdf[COMP_INDEX_CONTEXTS][CDF_SIZE(2)]; + + RK_U16 dummy0[14]; + + // Palette index contexts; sizes 1/7, 2/6, 3/5 packed together + RK_U16 palette_y_color_index_cdf[PALETTE_IDX_CONTEXTS][8]; + RK_U16 palette_uv_color_index_cdf[PALETTE_IDX_CONTEXTS][8]; + // RK_U16 dummy1[0]; + + // Note: cdf space can be optimized (most sets have fewer than EXT_TX_TYPES + // symbols) + RK_U16 tx_type_intra0_cdf[EXTTX_SIZES][AV1_INTRA_MODES][8]; + RK_U16 tx_type_intra1_cdf[EXTTX_SIZES][AV1_INTRA_MODES][4]; + RK_U16 tx_type_inter_cdf[2][EXTTX_SIZES][EXT_TX_TYPES]; + + aom_cdf_prob txb_skip_cdf[TX_SIZES][TXB_SKIP_CONTEXTS][CDF_SIZE(2)]; + aom_cdf_prob eob_extra_cdf[TX_SIZES][PLANE_TYPES][EOB_COEF_CONTEXTS][CDF_SIZE(2)]; + RK_U16 dummy_[5]; + + aom_cdf_prob eob_flag_cdf16[PLANE_TYPES][2][4]; + aom_cdf_prob eob_flag_cdf32[PLANE_TYPES][2][8]; + aom_cdf_prob eob_flag_cdf64[PLANE_TYPES][2][8]; + aom_cdf_prob eob_flag_cdf128[PLANE_TYPES][2][8]; + aom_cdf_prob eob_flag_cdf256[PLANE_TYPES][2][8]; + aom_cdf_prob eob_flag_cdf512[PLANE_TYPES][2][16]; + aom_cdf_prob eob_flag_cdf1024[PLANE_TYPES][2][16]; + aom_cdf_prob coeff_base_eob_cdf[TX_SIZES][PLANE_TYPES][SIG_COEF_CONTEXTS_EOB][CDF_SIZE(3)]; + aom_cdf_prob coeff_base_cdf[TX_SIZES][PLANE_TYPES][SIG_COEF_CONTEXTS][CDF_SIZE(4) + 1]; + aom_cdf_prob dc_sign_cdf[PLANE_TYPES][DC_SIGN_CONTEXTS][CDF_SIZE(2)]; + RK_U16 dummy_2[2]; + aom_cdf_prob coeff_br_cdf[TX_SIZES][PLANE_TYPES][LEVEL_CONTEXTS][CDF_SIZE(BR_CDF_SIZE) + 1]; + RK_U16 dummy2[16]; +} AV1CDFs; + +typedef struct { + RK_U8 scaling_lut_y[256]; + RK_U8 scaling_lut_cb[256]; + RK_U8 scaling_lut_cr[256]; + RK_S16 cropped_luma_grain_block[4096]; + RK_S16 cropped_chroma_grain_block[1024 * 2]; +} AV1FilmGrainMemory; + +#endif // __AV1COMMONDEC_H__ diff --git a/mpp/hal/vpu/av1d/film_grain_noise_table.c b/mpp/hal/vpu/av1d/film_grain_noise_table.c new file mode 100644 index 00000000..9bd5379c --- /dev/null +++ b/mpp/hal/vpu/av1d/film_grain_noise_table.c @@ -0,0 +1,374 @@ +/* + * Copyright 2021 Rockchip Electronics Co. LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "film_grain_noise_table.h" +#include +#include + +static const RK_S32 gaussian_sequence[2048] = { + 56, 568, -180, 172, 124, -84, 172, -64, -900, 24, 820, + 224, 1248, 996, 272, -8, -916, -388, -732, -104, -188, 800, + 112, -652, -320, -376, 140, -252, 492, -168, 44, -788, 588, + -584, 500, -228, 12, 680, 272, -476, 972, -100, 652, 368, + 432, -196, -720, -192, 1000, -332, 652, -136, -552, -604, -4, + 192, -220, -136, 1000, -52, 372, -96, -624, 124, -24, 396, + 540, -12, -104, 640, 464, 244, -208, -84, 368, -528, -740, + 248, -968, -848, 608, 376, -60, -292, -40, -156, 252, -292, + 248, 224, -280, 400, -244, 244, -60, 76, -80, 212, 532, + 340, 128, -36, 824, -352, -60, -264, -96, -612, 416, -704, + 220, -204, 640, -160, 1220, -408, 900, 336, 20, -336, -96, + -792, 304, 48, -28, -1232, -1172, -448, 104, -292, -520, 244, + 60, -948, 0, -708, 268, 108, 356, -548, 488, -344, -136, + 488, -196, -224, 656, -236, -1128, 60, 4, 140, 276, -676, + -376, 168, -108, 464, 8, 564, 64, 240, 308, -300, -400, + -456, -136, 56, 120, -408, -116, 436, 504, -232, 328, 844, + -164, -84, 784, -168, 232, -224, 348, -376, 128, 568, 96, + -1244, -288, 276, 848, 832, -360, 656, 464, -384, -332, -356, + 728, -388, 160, -192, 468, 296, 224, 140, -776, -100, 280, + 4, 196, 44, -36, -648, 932, 16, 1428, 28, 528, 808, + 772, 20, 268, 88, -332, -284, 124, -384, -448, 208, -228, + -1044, -328, 660, 380, -148, -300, 588, 240, 540, 28, 136, + -88, -436, 256, 296, -1000, 1400, 0, -48, 1056, -136, 264, + -528, -1108, 632, -484, -592, -344, 796, 124, -668, -768, 388, + 1296, -232, -188, -200, -288, -4, 308, 100, -168, 256, -500, + 204, -508, 648, -136, 372, -272, -120, -1004, -552, -548, -384, + 548, -296, 428, -108, -8, -912, -324, -224, -88, -112, -220, + -100, 996, -796, 548, 360, -216, 180, 428, -200, -212, 148, + 96, 148, 284, 216, -412, -320, 120, -300, -384, -604, -572, + -332, -8, -180, -176, 696, 116, -88, 628, 76, 44, -516, + 240, -208, -40, 100, -592, 344, -308, -452, -228, 20, 916, + -1752, -136, -340, -804, 140, 40, 512, 340, 248, 184, -492, + 896, -156, 932, -628, 328, -688, -448, -616, -752, -100, 560, + -1020, 180, -800, -64, 76, 576, 1068, 396, 660, 552, -108, + -28, 320, -628, 312, -92, -92, -472, 268, 16, 560, 516, + -672, -52, 492, -100, 260, 384, 284, 292, 304, -148, 88, + -152, 1012, 1064, -228, 164, -376, -684, 592, -392, 156, 196, + -524, -64, -884, 160, -176, 636, 648, 404, -396, -436, 864, + 424, -728, 988, -604, 904, -592, 296, -224, 536, -176, -920, + 436, -48, 1176, -884, 416, -776, -824, -884, 524, -548, -564, + -68, -164, -96, 692, 364, -692, -1012, -68, 260, -480, 876, + -1116, 452, -332, -352, 892, -1088, 1220, -676, 12, -292, 244, + 496, 372, -32, 280, 200, 112, -440, -96, 24, -644, -184, + 56, -432, 224, -980, 272, -260, 144, -436, 420, 356, 364, + -528, 76, 172, -744, -368, 404, -752, -416, 684, -688, 72, + 540, 416, 92, 444, 480, -72, -1416, 164, -1172, -68, 24, + 424, 264, 1040, 128, -912, -524, -356, 64, 876, -12, 4, + -88, 532, 272, -524, 320, 276, -508, 940, 24, -400, -120, + 756, 60, 236, -412, 100, 376, -484, 400, -100, -740, -108, + -260, 328, -268, 224, -200, -416, 184, -604, -564, -20, 296, + 60, 892, -888, 60, 164, 68, -760, 216, -296, 904, -336, + -28, 404, -356, -568, -208, -1480, -512, 296, 328, -360, -164, + -1560, -776, 1156, -428, 164, -504, -112, 120, -216, -148, -264, + 308, 32, 64, -72, 72, 116, 176, -64, -272, 460, -536, + -784, -280, 348, 108, -752, -132, 524, -540, -776, 116, -296, + -1196, -288, -560, 1040, -472, 116, -848, -1116, 116, 636, 696, + 284, -176, 1016, 204, -864, -648, -248, 356, 972, -584, -204, + 264, 880, 528, -24, -184, 116, 448, -144, 828, 524, 212, + -212, 52, 12, 200, 268, -488, -404, -880, 824, -672, -40, + 908, -248, 500, 716, -576, 492, -576, 16, 720, -108, 384, + 124, 344, 280, 576, -500, 252, 104, -308, 196, -188, -8, + 1268, 296, 1032, -1196, 436, 316, 372, -432, -200, -660, 704, + -224, 596, -132, 268, 32, -452, 884, 104, -1008, 424, -1348, + -280, 4, -1168, 368, 476, 696, 300, -8, 24, 180, -592, + -196, 388, 304, 500, 724, -160, 244, -84, 272, -256, -420, + 320, 208, -144, -156, 156, 364, 452, 28, 540, 316, 220, + -644, -248, 464, 72, 360, 32, -388, 496, -680, -48, 208, + -116, -408, 60, -604, -392, 548, -840, 784, -460, 656, -544, + -388, -264, 908, -800, -628, -612, -568, 572, -220, 164, 288, + -16, -308, 308, -112, -636, -760, 280, -668, 432, 364, 240, + -196, 604, 340, 384, 196, 592, -44, -500, 432, -580, -132, + 636, -76, 392, 4, -412, 540, 508, 328, -356, -36, 16, + -220, -64, -248, -60, 24, -192, 368, 1040, 92, -24, -1044, + -32, 40, 104, 148, 192, -136, -520, 56, -816, -224, 732, + 392, 356, 212, -80, -424, -1008, -324, 588, -1496, 576, 460, + -816, -848, 56, -580, -92, -1372, -112, -496, 200, 364, 52, + -140, 48, -48, -60, 84, 72, 40, 132, -356, -268, -104, + -284, -404, 732, -520, 164, -304, -540, 120, 328, -76, -460, + 756, 388, 588, 236, -436, -72, -176, -404, -316, -148, 716, + -604, 404, -72, -88, -888, -68, 944, 88, -220, -344, 960, + 472, 460, -232, 704, 120, 832, -228, 692, -508, 132, -476, + 844, -748, -364, -44, 1116, -1104, -1056, 76, 428, 552, -692, + 60, 356, 96, -384, -188, -612, -576, 736, 508, 892, 352, + -1132, 504, -24, -352, 324, 332, -600, -312, 292, 508, -144, + -8, 484, 48, 284, -260, -240, 256, -100, -292, -204, -44, + 472, -204, 908, -188, -1000, -256, 92, 1164, -392, 564, 356, + 652, -28, -884, 256, 484, -192, 760, -176, 376, -524, -452, + -436, 860, -736, 212, 124, 504, -476, 468, 76, -472, 552, + -692, -944, -620, 740, -240, 400, 132, 20, 192, -196, 264, + -668, -1012, -60, 296, -316, -828, 76, -156, 284, -768, -448, + -832, 148, 248, 652, 616, 1236, 288, -328, -400, -124, 588, + 220, 520, -696, 1032, 768, -740, -92, -272, 296, 448, -464, + 412, -200, 392, 440, -200, 264, -152, -260, 320, 1032, 216, + 320, -8, -64, 156, -1016, 1084, 1172, 536, 484, -432, 132, + 372, -52, -256, 84, 116, -352, 48, 116, 304, -384, 412, + 924, -300, 528, 628, 180, 648, 44, -980, -220, 1320, 48, + 332, 748, 524, -268, -720, 540, -276, 564, -344, -208, -196, + 436, 896, 88, -392, 132, 80, -964, -288, 568, 56, -48, + -456, 888, 8, 552, -156, -292, 948, 288, 128, -716, -292, + 1192, -152, 876, 352, -600, -260, -812, -468, -28, -120, -32, + -44, 1284, 496, 192, 464, 312, -76, -516, -380, -456, -1012, + -48, 308, -156, 36, 492, -156, -808, 188, 1652, 68, -120, + -116, 316, 160, -140, 352, 808, -416, 592, 316, -480, 56, + 528, -204, -568, 372, -232, 752, -344, 744, -4, 324, -416, + -600, 768, 268, -248, -88, -132, -420, -432, 80, -288, 404, + -316, -1216, -588, 520, -108, 92, -320, 368, -480, -216, -92, + 1688, -300, 180, 1020, -176, 820, -68, -228, -260, 436, -904, + 20, 40, -508, 440, -736, 312, 332, 204, 760, -372, 728, + 96, -20, -632, -520, -560, 336, 1076, -64, -532, 776, 584, + 192, 396, -728, -520, 276, -188, 80, -52, -612, -252, -48, + 648, 212, -688, 228, -52, -260, 428, -412, -272, -404, 180, + 816, -796, 48, 152, 484, -88, -216, 988, 696, 188, -528, + 648, -116, -180, 316, 476, 12, -564, 96, 476, -252, -364, + -376, -392, 556, -256, -576, 260, -352, 120, -16, -136, -260, + -492, 72, 556, 660, 580, 616, 772, 436, 424, -32, -324, + -1268, 416, -324, -80, 920, 160, 228, 724, 32, -516, 64, + 384, 68, -128, 136, 240, 248, -204, -68, 252, -932, -120, + -480, -628, -84, 192, 852, -404, -288, -132, 204, 100, 168, + -68, -196, -868, 460, 1080, 380, -80, 244, 0, 484, -888, + 64, 184, 352, 600, 460, 164, 604, -196, 320, -64, 588, + -184, 228, 12, 372, 48, -848, -344, 224, 208, -200, 484, + 128, -20, 272, -468, -840, 384, 256, -720, -520, -464, -580, + 112, -120, 644, -356, -208, -608, -528, 704, 560, -424, 392, + 828, 40, 84, 200, -152, 0, -144, 584, 280, -120, 80, + -556, -972, -196, -472, 724, 80, 168, -32, 88, 160, -688, + 0, 160, 356, 372, -776, 740, -128, 676, -248, -480, 4, + -364, 96, 544, 232, -1032, 956, 236, 356, 20, -40, 300, + 24, -676, -596, 132, 1120, -104, 532, -1096, 568, 648, 444, + 508, 380, 188, -376, -604, 1488, 424, 24, 756, -220, -192, + 716, 120, 920, 688, 168, 44, -460, 568, 284, 1144, 1160, + 600, 424, 888, 656, -356, -320, 220, 316, -176, -724, -188, + -816, -628, -348, -228, -380, 1012, -452, -660, 736, 928, 404, + -696, -72, -268, -892, 128, 184, -344, -780, 360, 336, 400, + 344, 428, 548, -112, 136, -228, -216, -820, -516, 340, 92, + -136, 116, -300, 376, -244, 100, -316, -520, -284, -12, 824, + 164, -548, -180, -128, 116, -924, -828, 268, -368, -580, 620, + 192, 160, 0, -1676, 1068, 424, -56, -360, 468, -156, 720, + 288, -528, 556, -364, 548, -148, 504, 316, 152, -648, -620, + -684, -24, -376, -384, -108, -920, -1032, 768, 180, -264, -508, + -1268, -260, -60, 300, -240, 988, 724, -376, -576, -212, -736, + 556, 192, 1092, -620, -880, 376, -56, -4, -216, -32, 836, + 268, 396, 1332, 864, -600, 100, 56, -412, -92, 356, 180, + 884, -468, -436, 292, -388, -804, -704, -840, 368, -348, 140, + -724, 1536, 940, 372, 112, -372, 436, -480, 1136, 296, -32, + -228, 132, -48, -220, 868, -1016, -60, -1044, -464, 328, 916, + 244, 12, -736, -296, 360, 468, -376, -108, -92, 788, 368, + -56, 544, 400, -672, -420, 728, 16, 320, 44, -284, -380, + -796, 488, 132, 204, -596, -372, 88, -152, -908, -636, -572, + -624, -116, -692, -200, -56, 276, -88, 484, -324, 948, 864, + 1000, -456, -184, -276, 292, -296, 156, 676, 320, 160, 908, + -84, -1236, -288, -116, 260, -372, -644, 732, -756, -96, 84, + 344, -520, 348, -688, 240, -84, 216, -1044, -136, -676, -396, + -1500, 960, -40, 176, 168, 1516, 420, -504, -344, -364, -360, + 1216, -940, -380, -212, 252, -660, -708, 484, -444, -152, 928, + -120, 1112, 476, -260, 560, -148, -344, 108, -196, 228, -288, + 504, 560, -328, -88, 288, -1008, 460, -228, 468, -836, -196, + 76, 388, 232, 412, -1168, -716, -644, 756, -172, -356, -504, + 116, 432, 528, 48, 476, -168, -608, 448, 160, -532, -272, + 28, -676, -12, 828, 980, 456, 520, 104, -104, 256, -344, + -4, -28, -368, -52, -524, -572, -556, -200, 768, 1124, -208, + -512, 176, 232, 248, -148, -888, 604, -600, -304, 804, -156, + -212, 488, -192, -804, -256, 368, -360, -916, -328, 228, -240, + -448, -472, 856, -556, -364, 572, -12, -156, -368, -340, 432, + 252, -752, -152, 288, 268, -580, -848, -592, 108, -76, 244, + 312, -716, 592, -80, 436, 360, 4, -248, 160, 516, 584, + 732, 44, -468, -280, -292, -156, -588, 28, 308, 912, 24, + 124, 156, 180, -252, 944, -924, -772, -520, -428, -624, 300, + -212, -1144, 32, -724, 800, -1128, -212, -1288, -848, 180, -416, + 440, 192, -576, -792, -76, -1080, 80, -532, -352, -132, 380, + -820, 148, 1112, 128, 164, 456, 700, -924, 144, -668, -384, + 648, -832, 508, 552, -52, -100, -656, 208, -568, 748, -88, + 680, 232, 300, 192, -408, -1012, -152, -252, -268, 272, -876, + -664, -648, -332, -136, 16, 12, 1152, -28, 332, -536, 320, + -672, -460, -316, 532, -260, 228, -40, 1052, -816, 180, 88, + -496, -556, -672, -368, 428, 92, 356, 404, -408, 252, 196, + -176, -556, 792, 268, 32, 372, 40, 96, -332, 328, 120, + 372, -900, -40, 472, -264, -592, 952, 128, 656, 112, 664, + -232, 420, 4, -344, -464, 556, 244, -416, -32, 252, 0, + -412, 188, -696, 508, -476, 324, -1096, 656, -312, 560, 264, + -136, 304, 160, -64, -580, 248, 336, -720, 560, -348, -288, + -276, -196, -500, 852, -544, -236, -1128, -992, -776, 116, 56, + 52, 860, 884, 212, -12, 168, 1020, 512, -552, 924, -148, + 716, 188, 164, -340, -520, -184, 880, -152, -680, -208, -1156, + -300, -528, -472, 364, 100, -744, -1056, -32, 540, 280, 144, + -676, -32, -232, -280, -224, 96, 568, -76, 172, 148, 148, + 104, 32, -296, -32, 788, -80, 32, -16, 280, 288, 944, + 428, -484 +}; + +static inline RK_S32 Clamp(RK_S32 value, RK_S32 low, RK_S32 high) +{ + return value < low ? low : (value > high ? high : value); +} + +static inline RK_S32 RoundPowerOfTwo(const RK_S32 val, RK_S32 n) +{ + const RK_S32 a = (RK_S32)1 << (n - 1); + return (val + a) >> n; +} + +// Reset random_register +static void InitRandomGenerator(RK_U8 luma_num, RK_U16 seed, RK_U16 *random_register) +{ + RK_U16 random_reg = seed; + random_reg ^= ((luma_num * 37 + 178) & 255) << 8; + random_reg ^= ((luma_num * 173 + 105) & 255); + *random_register = random_reg; +} + +// Update random_register as LFSR +static inline void UpdateRandomRegister(RK_U16 *random_register) +{ + RK_U16 bit; + RK_U16 random_reg = *random_register; + bit = ((random_reg >> 0) ^ (random_reg >> 1) ^ (random_reg >> 3) ^ + (random_reg >> 12)) & + 1; + *random_register = (random_reg >> 1) | (bit << 15); +} + +static inline RK_S32 GetRandomNumber(RK_U16 random_register) +{ + return (random_register >> 5) & ((1 << 11) - 1); +} + +void GenerateLumaGrainBlock(RK_S32 luma_grain_block[][82], RK_S32 bitdepth, + RK_U8 num_y_points, RK_S32 grain_scale_shift, + RK_S32 ar_coeff_lag, RK_S32 ar_coeffs_y[], + RK_S32 ar_coeff_shift, RK_S32 grain_min, RK_S32 grain_max, + RK_U16 random_seed) +{ + RK_S32 gauss_sec_shift = 12 - bitdepth + grain_scale_shift; + RK_U16 grain_random_register = random_seed; + RK_S32 i, j; + for (i = 0; i < 73; i++) { + for (j = 0; j < 82; j++) { + if (num_y_points > 0) { + UpdateRandomRegister(&grain_random_register); + luma_grain_block[i][j] = RoundPowerOfTwo( + gaussian_sequence[GetRandomNumber(grain_random_register)], + gauss_sec_shift); + } else { + luma_grain_block[i][j] = 0; + } + } + } + + for (i = 3; i < 73; i++) + for (j = 3; j < 82 - 3; j++) { + RK_S32 pos = 0; + RK_S32 wsum = 0; + RK_S32 deltaRow, deltaCol; + for (deltaRow = -ar_coeff_lag; deltaRow <= 0; deltaRow++) { + for (deltaCol = -ar_coeff_lag; deltaCol <= ar_coeff_lag; + deltaCol++) { + if (deltaRow == 0 && deltaCol == 0) break; + wsum = wsum + ar_coeffs_y[pos] * + luma_grain_block[i + deltaRow][j + deltaCol]; + ++pos; + } + } + luma_grain_block[i][j] = + Clamp(luma_grain_block[i][j] + RoundPowerOfTwo(wsum, ar_coeff_shift), + grain_min, grain_max); + } +} + +// Calculate chroma grain noise once per frame +void GenerateChromaGrainBlock( + RK_S32 luma_grain_block[][82], RK_S32 cb_grain_block[][44], + RK_S32 cr_grain_block[][44], RK_S32 bitdepth, RK_U8 num_y_points, RK_U8 num_cb_points, + RK_U8 num_cr_points, RK_S32 grain_scale_shift, RK_S32 ar_coeff_lag, + RK_S32 ar_coeffs_cb[], RK_S32 ar_coeffs_cr[], RK_S32 ar_coeff_shift, RK_S32 grain_min, + RK_S32 grain_max, RK_U8 chroma_scaling_from_luma, RK_U16 random_seed) +{ + RK_S32 gauss_sec_shift = 12 - bitdepth + grain_scale_shift; + RK_U16 grain_random_register = 0; + RK_S32 i, j; + + InitRandomGenerator(7, random_seed, &grain_random_register); + for ( i = 0; i < 38; i++) { + for (j = 0; j < 44; j++) { + if (num_cb_points || chroma_scaling_from_luma) { + UpdateRandomRegister(&grain_random_register); + cb_grain_block[i][j] = RoundPowerOfTwo( + gaussian_sequence[GetRandomNumber(grain_random_register)], + gauss_sec_shift); + } else { + cb_grain_block[i][j] = 0; + } + } + } + + InitRandomGenerator(11, random_seed, &grain_random_register); + for (i = 0; i < 38; i++) { + for (j = 0; j < 44; j++) { + if (num_cr_points || chroma_scaling_from_luma) { + UpdateRandomRegister(&grain_random_register); + cr_grain_block[i][j] = RoundPowerOfTwo( + gaussian_sequence[GetRandomNumber(grain_random_register)], + gauss_sec_shift); + } else { + cr_grain_block[i][j] = 0; + } + } + } + + for (i = 3; i < 38; i++) + for (j = 3; j < 44 - 3; j++) { + RK_S32 wsum_cb = 0; + RK_S32 wsum_cr = 0; + RK_S32 pos = 0; + RK_S32 deltaRow, deltaCol; + + for ( deltaRow = -ar_coeff_lag; deltaRow <= 0; deltaRow++) { + for ( deltaCol = -ar_coeff_lag; deltaCol <= ar_coeff_lag; + deltaCol++) { + if (deltaRow == 0 && deltaCol == 0) break; + wsum_cb = wsum_cb + ar_coeffs_cb[pos] * + cb_grain_block[i + deltaRow][j + deltaCol]; + wsum_cr = wsum_cr + ar_coeffs_cr[pos] * + cr_grain_block[i + deltaRow][j + deltaCol]; + ++pos; + } + } + + if (num_y_points > 0) { + RK_S32 av_luma = 0; + RK_S32 luma_coord_y = (i << 1) - 3; + RK_S32 luma_coord_x = (j << 1) - 3; + + av_luma += luma_grain_block[luma_coord_y][luma_coord_x]; + av_luma += luma_grain_block[luma_coord_y][luma_coord_x + 1]; + av_luma += luma_grain_block[luma_coord_y + 1][luma_coord_x]; + av_luma += luma_grain_block[luma_coord_y + 1][luma_coord_x + 1]; + av_luma = RoundPowerOfTwo(av_luma, 2); + + wsum_cb = wsum_cb + ar_coeffs_cb[pos] * av_luma; + wsum_cr = wsum_cr + ar_coeffs_cr[pos] * av_luma; + } + + if (num_cb_points || chroma_scaling_from_luma) { + cb_grain_block[i][j] = Clamp( + cb_grain_block[i][j] + RoundPowerOfTwo(wsum_cb, ar_coeff_shift), + grain_min, grain_max); + } + if (num_cr_points || chroma_scaling_from_luma) { + cr_grain_block[i][j] = Clamp( + cr_grain_block[i][j] + RoundPowerOfTwo(wsum_cr, ar_coeff_shift), + grain_min, grain_max); + } + } +} diff --git a/mpp/hal/vpu/av1d/film_grain_noise_table.h b/mpp/hal/vpu/av1d/film_grain_noise_table.h new file mode 100644 index 00000000..58ee79c8 --- /dev/null +++ b/mpp/hal/vpu/av1d/film_grain_noise_table.h @@ -0,0 +1,33 @@ +/* + * Copyright 2021 Rockchip Electronics Co. LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __FILM_GRAIN_NOISE_TABLE_H__ +#define __FILM_GRAIN_NOISE_TABLE_H__ +#include "rk_type.h" + +void GenerateLumaGrainBlock(RK_S32 luma_grain_block[][82], RK_S32 bitdepth, + RK_U8 num_y_points, RK_S32 grain_scale_shift, + RK_S32 ar_coeff_lag, RK_S32 ar_coeffs_y[], + RK_S32 ar_coeff_shift, RK_S32 grain_min, RK_S32 grain_max, + RK_U16 random_seed); + +void GenerateChromaGrainBlock( + RK_S32 luma_grain_block[][82], RK_S32 cb_grain_block[][44], + RK_S32 cr_grain_block[][44], RK_S32 bitdepth, RK_U8 num_y_points, RK_U8 num_cb_points, + RK_U8 num_cr_points, RK_S32 grain_scale_shift, RK_S32 ar_coeff_lag, + RK_S32 ar_coeffs_cb[], RK_S32 ar_coeffs_cr[], RK_S32 ar_coeff_shift, RK_S32 grain_min, + RK_S32 grain_max, RK_U8 chroma_scaling_from_luma, RK_U16 random_seed); + +#endif //__FILM_GRAIN_NOISE_TABLE_H__ \ No newline at end of file diff --git a/mpp/hal/vpu/av1d/hal_av1d_api.c b/mpp/hal/vpu/av1d/hal_av1d_api.c new file mode 100644 index 00000000..1cae6b05 --- /dev/null +++ b/mpp/hal/vpu/av1d/hal_av1d_api.c @@ -0,0 +1,187 @@ +/* + * Copyright 2021 Rockchip Electronics Co. LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define MODULE_TAG "hal_av1d_api" + +#include +#include +#include +#include +#include + +#include "mpp_log.h" +#include "mpp_mem.h" +#include "mpp_env.h" +#include "mpp_platform.h" +#include "mpp_common.h" + +#include "dxva_syntax.h" + +#include "hal_av1d_vdpu_reg.h" +#include "hal_av1d_vdpu.h" +#include "hal_av1d_common.h" + +RK_U32 hal_av1d_debug = 0; + +MPP_RET hal_av1d_init(void *hal, MppHalCfg *cfg) +{ + MPP_RET ret = MPP_OK; + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + RK_U32 vcodec_type = mpp_get_vcodec_type(); + MppClientType type = VPU_CLIENT_AV1DEC; + + INP_CHECK(ret, NULL == p_hal); + memset(p_hal, 0, sizeof(Av1dHalCtx)); + mpp_env_get_u32("hal_av1d_debug", &hal_av1d_debug, 0); + + // check codec_type first + if (!(vcodec_type & (HAVE_RKVDEC | HAVE_VDPU1 | HAVE_VDPU2))) { + mpp_err_f("can not found av1 decoder hardware on platform %x\n", vcodec_type); + return ret; + } + + p_hal->api = &hal_av1d_vdpu; + + //!< callback function to parser module + p_hal->dec_cb = cfg->dec_cb; + + ret = mpp_dev_init(&cfg->dev, type); + if (ret) { + mpp_err("mpp_dev_init failed ret: %d\n", ret); + goto __FAILED; + } + + //< get buffer group + if (p_hal->buf_group == NULL) { + FUN_CHECK(ret = mpp_buffer_group_get_internal + (&p_hal->buf_group, MPP_BUFFER_TYPE_ION)); + } + + p_hal->dev = cfg->dev; + p_hal->cfg = cfg->cfg; + p_hal->slots = cfg->frame_slots; + p_hal->packet_slots = cfg->packet_slots; + p_hal->fast_mode = cfg->cfg->base.fast_parse; + + if (p_hal->buf_group == NULL) { + FUN_CHECK(ret = mpp_buffer_group_get_internal + (&p_hal->buf_group, MPP_BUFFER_TYPE_ION)); + } + //!< run init funtion + FUN_CHECK(ret = p_hal->api->init(hal, cfg)); + +__RETURN: + return MPP_OK; +__FAILED: + return ret; +} + +MPP_RET hal_av1d_deinit(void *hal) +{ + MPP_RET ret = MPP_ERR_UNKNOW; + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + + FUN_CHECK(ret = p_hal->api->deinit(hal)); + + if (p_hal->dev) { + mpp_dev_deinit(p_hal->dev); + p_hal->dev = NULL; + } + + if (p_hal->buf_group) { + FUN_CHECK(ret = mpp_buffer_group_put(p_hal->buf_group)); + } + + return MPP_OK; +__FAILED: + return ret; +} + +MPP_RET hal_av1d_gen_regs(void *hal, HalTaskInfo *task) +{ + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + MPP_RET ret = MPP_NOK; + + if (p_hal && p_hal->api && p_hal->api->reg_gen) + ret = p_hal->api->reg_gen(hal, task); + return ret; +} + +MPP_RET hal_av1d_start(void *hal, HalTaskInfo *task) +{ + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + MPP_RET ret = MPP_NOK; + + if (p_hal && p_hal->api && p_hal->api->start) + ret = p_hal->api->start(hal, task); + return ret; +} + +MPP_RET hal_av1d_wait(void *hal, HalTaskInfo *task) +{ + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + MPP_RET ret = MPP_NOK; + + if (p_hal && p_hal->api && p_hal->api->wait) + ret = p_hal->api->wait(hal, task); + return ret; +} + +MPP_RET hal_av1d_reset(void *hal) +{ + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + MPP_RET ret = MPP_NOK; + + if (p_hal && p_hal->api && p_hal->api->reset) + ret = p_hal->api->reset(hal); + return ret; +} + +MPP_RET hal_av1d_flush(void *hal) +{ + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + MPP_RET ret = MPP_NOK; + + if (p_hal && p_hal->api && p_hal->api->flush) + ret = p_hal->api->flush(hal); + return ret; +} + +MPP_RET hal_av1d_control(void *hal, MpiCmd cmd_type, void *param) +{ + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + MPP_RET ret = MPP_NOK; + + if (p_hal && p_hal->api && p_hal->api->control) + ret = p_hal->api->control(hal, cmd_type, param); + return ret; +} + +const MppHalApi hal_api_av1d = { + .name = "av1d_vdpu", + .type = MPP_CTX_DEC, + .coding = MPP_VIDEO_CodingAV1, + .ctx_size = sizeof(Av1dHalCtx), + .flag = 0, + .init = hal_av1d_init, + .deinit = hal_av1d_deinit, + .reg_gen = hal_av1d_gen_regs, + .start = hal_av1d_start, + .wait = hal_av1d_wait, + .reset = hal_av1d_reset, + .flush = hal_av1d_flush, + .control = hal_av1d_control, +}; diff --git a/mpp/hal/vpu/av1d/hal_av1d_common.h b/mpp/hal/vpu/av1d/hal_av1d_common.h new file mode 100644 index 00000000..a472d36c --- /dev/null +++ b/mpp/hal/vpu/av1d/hal_av1d_common.h @@ -0,0 +1,194 @@ +/* + * Copyright 2020 Rockchip Electronics Co. LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef __HAL_AV1D_GLOBAL_H__ +#define __HAL_AV1D_GLOBAL_H__ + +#include "mpp_hal.h" +#include "mpp_log.h" +#include "mpp_device.h" +#include "hal_bufs.h" + +#include "dxva_syntax.h" + +#define AV1D_DBG_ERROR (0x00000001) +#define AV1D_DBG_ASSERT (0x00000002) +#define AV1D_DBG_WARNNING (0x00000004) +#define AV1D_DBG_LOG (0x00000008) + +#define AV1D_DBG_HARD_MODE (0x00000010) + +extern RK_U32 hal_av1d_debug; + + +#define AV1D_DBG(level, fmt, ...)\ +do {\ + if (level & hal_av1d_debug)\ + { mpp_log(fmt, ## __VA_ARGS__); }\ +} while (0) + + +#define AV1D_ERR(fmt, ...)\ +do {\ + if (AV1D_DBG_ERROR & hal_av1d_debug)\ + { mpp_log(fmt, ## __VA_ARGS__); }\ +} while (0) + +#define ASSERT(val)\ +do {\ + if (AV1D_DBG_ASSERT & hal_av1d_debug)\ + { mpp_assert(val); }\ +} while (0) + +#define AV1D_WARNNING(fmt, ...)\ +do {\ + if (AV1D_DBG_WARNNING & hal_av1d_debug)\ + { mpp_log(fmt, ## __VA_ARGS__); }\ +} while (0) + +#define AV1D_LOG(fmt, ...)\ +do {\ + if (AV1D_DBG_LOG & hal_av1d_debug)\ + { mpp_log(fmt, ## __VA_ARGS__); }\ +} while (0) + + +//!< vaule check +#define VAL_CHECK(ret, val, ...)\ +do{\ + if (!(val)){\ + ret = MPP_ERR_VALUE; \ + AV1D_WARNNING("value error(%d).\n", __LINE__); \ + goto __FAILED; \ +}} while (0) +//!< memory malloc check +#define MEM_CHECK(ret, val, ...)\ +do{\ + if (!(val)) {\ + ret = MPP_ERR_MALLOC; \ + AV1D_ERR("malloc buffer error(%d).\n", __LINE__); \ + ASSERT(0); goto __FAILED; \ +}} while (0) + +#define BUF_CHECK(ret, val, ...)\ +do{\ + if (val) {\ + ret = MPP_ERR_BUFFER_FULL; \ + AV1D_ERR("buffer get error(%d).\n", __LINE__); \ + ASSERT(0); goto __FAILED; \ +}} while (0) + +#define BUF_PUT(val, ...)\ +do{\ + if (val) {\ + if (mpp_buffer_put(val)) {\ + AV1D_ERR("buffer put error(%d).\n", __LINE__); \ + ASSERT(0); \ + }\ +}} while (0) + +//!< input check +#define INP_CHECK(ret, val, ...)\ +do{\ + if ((val)) {\ + ret = MPP_ERR_INIT; \ + AV1D_WARNNING("input empty(%d).\n", __LINE__); \ + goto __RETURN; \ +}} while (0) +//!< function return check +#define FUN_CHECK(val)\ +do{\ + if ((val) < 0) {\ + AV1D_WARNNING("Function error(%d).\n", __LINE__); \ + goto __FAILED; \ +}} while (0) + +#define MAX_MB_SEGMENTS 8 + +enum Av1SegLevelFeatures { + SEG_AV1_LVL_ALT_Q, // Use alternate Quantizer .... + SEG_AV1_LVL_ALT_LF_Y_V, // Use alternate loop filter value on y plane + // vertical + SEG_AV1_LVL_ALT_LF_Y_H, // Use alternate loop filter value on y plane + // horizontal + SEG_AV1_LVL_ALT_LF_U, // Use alternate loop filter value on u plane + SEG_AV1_LVL_ALT_LF_V, // Use alternate loop filter value on v plane + SEG_AV1_LVL_REF_FRAME, // Optional Segment reference frame + SEG_AV1_LVL_SKIP, // Optional Segment (0,0) + skip mode + SEG_AV1_LVL_GLOBALMV, + SEG_AV1_LVL_MAX +}; + +#define AV1_ACTIVE_REFS 3 +#define AV1_ACTIVE_REFS_EX 7 +#define AV1_REF_LIST_SIZE 8 +#define AV1_REF_SCALE_SHIFT 14 + +enum MvReferenceFrame { + NONE = -1, + INTRA_FRAME = 0, + LAST_FRAME = 1, + LAST2_FRAME_EX = 2, + LAST3_FRAME_EX = 3, + GOLDEN_FRAME_EX = 4, + BWDREF_FRAME_EX = 5, + ALTREF2_FRAME_EX = 6, + ALTREF_FRAME_EX = 7, + MAX_REF_FRAMES_EX = 8, + GOLDEN_FRAME = 2, + ALTREF_FRAME = 3, + + MAX_REF_FRAMES = 4 +}; + +enum { + AV1_FRAME_KEY = 0, + AV1_FRAME_INTER = 1, + AV1_FRAME_INTRA_ONLY = 2, + AV1_FRAME_SWITCH = 3, +}; + +#define AV1DEC_MAX_PIC_BUFFERS 24 +#define AV1DEC_DYNAMIC_PIC_LIMIT 10 +#define ALLOWED_REFS_PER_FRAME_EX 7 + +typedef struct FilmGrainMemory_t { + RK_U8 scaling_lut_y[256]; + RK_U8 scaling_lut_cb[256]; + RK_U8 scaling_lut_cr[256]; + RK_S16 cropped_luma_grain_block[4096]; + RK_S16 cropped_chroma_grain_block[1024 * 2]; +} FilmGrainMemory; + +typedef struct av1d_hal_ctx_t { + const MppHalApi *api; + RK_U8 *bitstream; + RK_U32 strm_len; + + HalDecTask *in_task; + MppBufSlots slots; + MppBufSlots packet_slots; + MppDecCfgSet *cfg; + MppBufferGroup buf_group; + + MppCbCtx *dec_cb; + MppDev dev; + void *reg_ctx; + RK_U32 fast_mode; +} Av1dHalCtx; + +#endif /*__HAL_AV1D_GLOBAL_H__*/ diff --git a/mpp/hal/vpu/av1d/hal_av1d_vdpu.c b/mpp/hal/vpu/av1d/hal_av1d_vdpu.c new file mode 100644 index 00000000..b7a3ac05 --- /dev/null +++ b/mpp/hal/vpu/av1d/hal_av1d_vdpu.c @@ -0,0 +1,2368 @@ +/* + * Copyright 2020 Rockchip Electronics Co. LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define MODULE_TAG "hal_av1d_vdpu" + +#include +#include +#include + +#include "rk_type.h" +#include "mpp_err.h" +#include "mpp_mem.h" +#include "mpp_common.h" +#include "mpp_bitput.h" +#include "mpp_hal.h" +#include "mpp_dec_cb_param.h" +#include "mpp_device.h" +#include "hal_bufs.h" + +#include "hal_av1d_vdpu_reg.h" +#include "hal_av1d_common.h" +#include "av1d_syntax.h" +#include "film_grain_noise_table.h" +#include "av1d_common.h" + +#define VDPU_FAST_REG_SET_CNT 3 +#define AV1_MAX_TILES 128 +#define AV1_TILE_INFO_SIZE AV1_MAX_TILES * 16 +#define GM_GLOBAL_MODELS_PER_FRAME 7 +#define GLOBAL_MODEL_TOTAL_SIZE (6 * 4 + 4 * 2) +#define GLOBAL_MODEL_SIZE GM_GLOBAL_MODELS_PER_FRAME * GLOBAL_MODEL_TOTAL_SIZE +#define MaxTiles 128 + +#define DUMP_AV1_DATAS 0 + +typedef enum AV1D_FILT_TYPE_E { + DB_DATA_COL, + DB_CTRL_COL, + CDEF_COL, + SR_COL, + LR_COL, + RFC_COL, + FILT_TYPE_BUT, +} Av1dFiltType_e; + +typedef struct filt_info_t { + RK_U32 size; + RK_U32 offset; +} filtInfo; + +typedef struct av1d_rkv_buf_t { + RK_U32 valid; + VdpuAv1dRegSet *regs; +} av1dVdpuBuf; + +typedef struct VdpuAv1dRegCtx_t { + av1dVdpuBuf reg_buf[VDPU_FAST_REG_SET_CNT]; + MppBuffer prob_tbl_base; + MppBuffer prob_tbl_out_base; + MppBuffer tile_info; + MppBuffer film_grain_mem; + MppBuffer global_model; + MppBuffer filter_mem; + MppBuffer buf_tmp; + MppBuffer tile_buf; + filtInfo filt_info[FILT_TYPE_BUT]; + + AV1CDFs *cdfs; + MvCDFs *cdfs_ndvc; + AV1CDFs default_cdfs; + MvCDFs default_cdfs_ndvc; + AV1CDFs cdfs_last[NUM_REF_FRAMES]; + MvCDFs cdfs_last_ndvc[NUM_REF_FRAMES]; + RK_U32 refresh_frame_flags; + + RK_S32 width; + RK_S32 height; + RK_S32 hor_stride; + RK_S32 ver_stride; + RK_U32 luma_size ; + RK_U32 chroma_size; + + FilmGrainMemory fgsmem; + + RK_S8 prev_out_buffer_i; + RK_U8 fbc_en; + RK_U8 resolution_change; + RK_U8 tile_transpose; + RK_U32 ref_frame_sign_bias[AV1_REF_LIST_SIZE]; + + VdpuAv1dRegSet *regs; + HalBufs tile_out_bufs; + RK_U32 tile_out_count; + size_t tile_out_size; +} VdpuAv1dRegCtx; + +static RK_U32 rkv_ver_align(RK_U32 val) +{ + return MPP_ALIGN(val, 8); +} + +static RK_U32 rkv_hor_align(RK_U32 val) +{ + return MPP_ALIGN(val, 8); +} + +static RK_U32 rkv_len_align(RK_U32 val) +{ + return (2 * MPP_ALIGN(val, 128)); +} + +static RK_U32 rkv_len_align_422(RK_U32 val) +{ + return ((5 * MPP_ALIGN(val, 64)) / 2); +} + +static MPP_RET hal_av1d_alloc_res(void *hal) +{ + MPP_RET ret = MPP_OK; + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + RK_U32 max_cnt = p_hal->fast_mode ? VDPU_FAST_REG_SET_CNT : 1; + RK_U32 i = 0; + INP_CHECK(ret, NULL == p_hal); + + MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(VdpuAv1dRegCtx))); + VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx; + + //!< malloc buffers + for (i = 0; i < max_cnt; i++) { + reg_ctx->reg_buf[i].regs = mpp_calloc(VdpuAv1dRegSet, 1); + memset(reg_ctx->reg_buf[i].regs, 0, sizeof(VdpuAv1dRegSet)); + } + + if (!p_hal->fast_mode) { + reg_ctx->regs = reg_ctx->reg_buf[0].regs; + } + + BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, ®_ctx->prob_tbl_base, MPP_ALIGN(sizeof(AV1CDFs), 2048))); + BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, ®_ctx->prob_tbl_out_base, MPP_ALIGN(sizeof(AV1CDFs), 2048))); + BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, ®_ctx->tile_info, AV1_TILE_INFO_SIZE)); + BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, ®_ctx->film_grain_mem, MPP_ALIGN(sizeof(AV1FilmGrainMemory), 2048))); + BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, ®_ctx->global_model, MPP_ALIGN(GLOBAL_MODEL_SIZE, 2048))); + BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, ®_ctx->tile_buf, MPP_ALIGN(32 * MaxTiles, 4096))); + +__RETURN: + return ret; +__FAILED: + return ret; +} + +static void vdpu_av1d_filtermem_release(VdpuAv1dRegCtx *ctx) +{ + BUF_PUT(ctx->filter_mem); +} + +static MPP_RET vdpu_av1d_filtermem_alloc(Av1dHalCtx *p_hal, VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva) +{ + RK_U32 size = 0; + RK_U32 pic_height = MPP_ALIGN(dxva->height, 64); + RK_U32 height_in_sb = pic_height / 64; + RK_U32 stripe_num = ((pic_height + 8) + 63) / 64; + RK_U32 max_bit_depth = 10; + RK_U32 num_tile_cols = 1 << dxva->tile_cols_log2;//dxva->tiles.cols; + filtInfo *filt_info = ctx->filt_info; + + /* db tile col data buffer */ + // asic_buff->db_data_col_offset = 0; + // asic_buff->db_data_col_tsize = NEXT_MULTIPLE(pic_height * 12 * max_bit_depth / 8, 128); + // size = asic_buff->db_data_col_tsize * num_tile_cols; + // asic_buff->db_ctrl_col_offset = size; + + filt_info[DB_DATA_COL].offset = 0; + filt_info[DB_DATA_COL].size = MPP_ALIGN(pic_height * 12 * max_bit_depth / 8, 128); + size += filt_info[DB_DATA_COL].size * num_tile_cols; + + + /* db tile col ctrl buffer */ + filt_info[DB_CTRL_COL].offset = size; + filt_info[DB_CTRL_COL].size = MPP_ALIGN(pic_height * 2 * 16 / 4, 128); + size += filt_info[DB_CTRL_COL].size * num_tile_cols; + + // size += asic_buff->db_ctrl_col_tsize * num_tile_cols; + // asic_buff->cdef_col_offset = size; + + /* cdef tile col buffer */ + filt_info[CDEF_COL].offset = size; + filt_info[CDEF_COL].size = MPP_ALIGN(height_in_sb * 44 * max_bit_depth * 16 / 8, 128); + size += filt_info[CDEF_COL].size * num_tile_cols; + // asic_buff->cdef_col_tsize = NEXT_MULTIPLE(height_in_sb * 44 * max_bit_depth * 16 / 8, 128); + // size += asic_buff->cdef_col_tsize * num_tile_cols; + // asic_buff->sr_col_offset = size; + + /* sr tile col buffer */ + filt_info[SR_COL].offset = size; + filt_info[SR_COL].size = MPP_ALIGN(height_in_sb * (3040 + 1280), 128); + size += filt_info[SR_COL].size * num_tile_cols; + // asic_buff->sr_col_tsize = NEXT_MULTIPLE(height_in_sb * (3040 + 1280), 128); + // size += asic_buff->sr_col_tsize * num_tile_cols; + // asic_buff->lr_col_offset = size; + + /* lr tile col buffer */ + filt_info[LR_COL].offset = size; + filt_info[LR_COL].size = MPP_ALIGN(stripe_num * 1536 * max_bit_depth / 8, 128); + size += filt_info[LR_COL].size * num_tile_cols; + // asic_buff->lr_col_tsize = NEXT_MULTIPLE(stripe_num * 1536 * max_bit_depth / 8, 128); + // size += asic_buff->lr_col_tsize * num_tile_cols; + // if (dec_cont->use_multicore) { + // asic_buff->rfc_col_offset = size; + // asic_buff->rfc_col_size = NEXT_MULTIPLE(asic_buff->height, 8) / 8 * 16 * 2; + // size += asic_buff->rfc_col_size * num_tile_cols; + // } + if (!mpp_buffer_get(p_hal->buf_group, &ctx->filter_mem, MPP_ALIGN(size, SZ_4K))) + return MPP_NOK; + return MPP_OK; +} + +static void hal_av1d_release_res(void *hal) +{ + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx; + RK_U32 i = 0; + RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1; + + for (i = 0; i < loop; i++) + MPP_FREE(reg_ctx->reg_buf[i].regs); + + BUF_PUT(reg_ctx->prob_tbl_base); + BUF_PUT(reg_ctx->prob_tbl_out_base); + BUF_PUT(reg_ctx->tile_info); + BUF_PUT(reg_ctx->film_grain_mem); + BUF_PUT(reg_ctx->global_model); + BUF_PUT(reg_ctx->buf_tmp); + BUF_PUT(reg_ctx->tile_buf); + vdpu_av1d_filtermem_release(reg_ctx); + hal_bufs_deinit(reg_ctx->tile_out_bufs); + + MPP_FREE(p_hal->reg_ctx); +} + +MPP_RET vdpu_av1d_deinit(void *hal) +{ + hal_av1d_release_res(hal); + + return MPP_OK; +} + +MPP_RET vdpu_av1d_init(void *hal, MppHalCfg *cfg) +{ + MPP_RET ret = MPP_OK; + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + INP_CHECK(ret, NULL == p_hal); + + FUN_CHECK(hal_av1d_alloc_res(hal)); + + { + VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx; + + reg_ctx->cdfs = ®_ctx->default_cdfs; + reg_ctx->cdfs_ndvc = ®_ctx->default_cdfs_ndvc; + reg_ctx->tile_transpose = 1; + } + + mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, rkv_hor_align); + mpp_slots_set_prop(p_hal->slots, SLOTS_VER_ALIGN, rkv_ver_align); + mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align); + + (void)cfg; +__RETURN: + return MPP_OK; +__FAILED: + vdpu_av1d_deinit(hal); + + return ret; +} + +static void set_ref_width(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) +{ + if (i == 0) { + regs->swreg33.sw_ref0_width = val; + } else if (i == 1) { + regs->swreg34.sw_ref1_width = val; + } else if (i == 2) { + regs->swreg35.sw_ref2_width = val; + } else if (i == 3) { + regs->swreg43.sw_ref3_width = val; + } else if (i == 4) { + regs->swreg44.sw_ref4_width = val; + } else if (i == 5) { + regs->swreg45.sw_ref5_width = val; + } else if (i == 6) { + regs->swreg46.sw_ref6_width = val; + } else { + mpp_err("Error: trying to set invalid reference index."); + } +} + +static void set_ref_height(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) +{ + if (i == 0) { + regs->swreg33.sw_ref0_height = val; + } else if (i == 1) { + regs->swreg34.sw_ref1_height = val; + } else if (i == 2) { + regs->swreg35.sw_ref2_height = val; + } else if (i == 3) { + regs->swreg43.sw_ref3_height = val; + } else if (i == 4) { + regs->swreg44.sw_ref4_height = val; + } else if (i == 5) { + regs->swreg45.sw_ref5_height = val; + } else if (i == 6) { + regs->swreg46.sw_ref6_height = val; + } else { + mpp_err("Error: trying to set invalid reference index."); + } +} + +static void set_ref_hor_scale(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) +{ + if (i == 0) { + regs->swreg36.sw_ref0_hor_scale = val; + } else if (i == 1) { + regs->swreg37.sw_ref1_hor_scale = val; + } else if (i == 2) { + regs->swreg38.sw_ref2_hor_scale = val; + } else if (i == 3) { + regs->swreg39.sw_ref3_hor_scale = val; + } else if (i == 4) { + regs->swreg40.sw_ref4_hor_scale = val; + } else if (i == 5) { + regs->swreg41.sw_ref5_hor_scale = val; + } else if (i == 6) { + regs->swreg42.sw_ref6_hor_scale = val; + } else { + mpp_err("Error: trying to set invalid reference index."); + } +} + +static void set_ref_ver_scale(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) +{ + if (i == 0) { + regs->swreg36.sw_ref0_ver_scale = val; + } else if (i == 1) { + regs->swreg37.sw_ref1_ver_scale = val; + } else if (i == 2) { + regs->swreg38.sw_ref2_ver_scale = val; + } else if (i == 3) { + regs->swreg39.sw_ref3_ver_scale = val; + } else if (i == 4) { + regs->swreg40.sw_ref4_ver_scale = val; + } else if (i == 5) { + regs->swreg41.sw_ref5_ver_scale = val; + } else if (i == 6) { + regs->swreg42.sw_ref6_ver_scale = val; + } else { + mpp_err("Error: trying to set invalid reference index."); + } +} + +static void set_ref_lum_base(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val, HalBufs bufs) +{ + HalBuf *tile_out_buf; + tile_out_buf = hal_bufs_get_buf(bufs, val); + // MppBuffer framebuf = NULL; + // mpp_buf_slot_get_prop(slots, val, SLOT_BUFFER, &framebuf); + if (tile_out_buf == NULL) { + mpp_err_f("get slots frame buff fail"); + } + val = mpp_buffer_get_fd(tile_out_buf->buf[0]); + if (i == 0) { + regs->addr_cfg.swreg67.sw_refer0_ybase_lsb = val; + } else if (i == 1) { + regs->addr_cfg.swreg69.sw_refer1_ybase_lsb = val; + } else if (i == 2) { + regs->addr_cfg.swreg71.sw_refer2_ybase_lsb = val; + } else if (i == 3) { + regs->addr_cfg.swreg73.sw_refer3_ybase_lsb = val; + } else if (i == 4) { + regs->addr_cfg.swreg75.sw_refer4_ybase_lsb = val; + } else if (i == 5) { + regs->addr_cfg.swreg77.sw_refer5_ybase_lsb = val; + } else if (i == 6) { + regs->addr_cfg.swreg79.sw_refer6_ybase_lsb = val; + } else { + mpp_err( "Error: trying to set invalid reference index."); + } +} + +static void set_ref_lum_base_msb(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) +{ + if (i == 0) { + regs->addr_cfg.swreg66.sw_refer0_ybase_msb = val; + } else if (i == 1) { + regs->addr_cfg.swreg68.sw_refer1_ybase_msb = val; + } else if (i == 2) { + regs->addr_cfg.swreg70.sw_refer2_ybase_msb = val; + } else if (i == 3) { + regs->addr_cfg.swreg72.sw_refer3_ybase_msb = val; + } else if (i == 4) { + regs->addr_cfg.swreg74.sw_refer4_ybase_msb = val; + } else if (i == 5) { + regs->addr_cfg.swreg76.sw_refer5_ybase_msb = val; + } else if (i == 6) { + regs->addr_cfg.swreg78.sw_refer6_ybase_msb = val; + } else { + mpp_err("Error: trying to set invalid reference index."); + } +} + +static void set_ref_cb_base(Av1dHalCtx *p_hal, RK_S32 i, RK_S32 val, HalBufs bufs, RK_U32 offset) +{ + VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx; + VdpuAv1dRegSet *regs = ctx->regs; + HalBuf *tile_out_buf; + tile_out_buf = hal_bufs_get_buf(bufs, val); + // MppBuffer framebuf = NULL; + + // mpp_buf_slot_get_prop(slots, val, SLOT_BUFFER, &framebuf); + if (tile_out_buf == NULL) { + mpp_err_f("get slots frame buff fail"); + } + val = mpp_buffer_get_fd(tile_out_buf->buf[0]); + + if (i == 0) { + mpp_dev_set_reg_offset(p_hal->dev, 101, offset); + regs->addr_cfg.swreg101.sw_refer0_cbase_lsb = val; + } else if (i == 1) { + mpp_dev_set_reg_offset(p_hal->dev, 103, offset); + regs->addr_cfg.swreg103.sw_refer1_cbase_lsb = val; + } else if (i == 2) { + mpp_dev_set_reg_offset(p_hal->dev, 105, offset); + regs->addr_cfg.swreg105.sw_refer2_cbase_lsb = val; + } else if (i == 3) { + mpp_dev_set_reg_offset(p_hal->dev, 107, offset); + regs->addr_cfg.swreg107.sw_refer3_cbase_lsb = val; + } else if (i == 4) { + mpp_dev_set_reg_offset(p_hal->dev, 109, offset); + regs->addr_cfg.swreg109.sw_refer4_cbase_lsb = val; + } else if (i == 5) { + mpp_dev_set_reg_offset(p_hal->dev, 111, offset); + regs->addr_cfg.swreg111.sw_refer5_cbase_lsb = val; + } else if (i == 6) { + mpp_dev_set_reg_offset(p_hal->dev, 113, offset); + regs->addr_cfg.swreg113.sw_refer6_cbase_lsb = val; + } else { + mpp_err("Error: trying to set invalid reference index."); + } +} + +static void set_ref_cb_base_msb(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) +{ + if (i == 0) { + regs->addr_cfg.swreg100.sw_refer0_cbase_msb = val; + } else if (i == 1) { + regs->addr_cfg.swreg102.sw_refer1_cbase_msb = val; + } else if (i == 2) { + regs->addr_cfg.swreg104.sw_refer2_cbase_msb = val; + } else if (i == 3) { + regs->addr_cfg.swreg106.sw_refer3_cbase_msb = val; + } else if (i == 4) { + regs->addr_cfg.swreg108.sw_refer4_cbase_msb = val; + } else if (i == 5) { + regs->addr_cfg.swreg110.sw_refer5_cbase_msb = val; + } else if (i == 6) { + regs->addr_cfg.swreg112.sw_refer6_cbase_msb = val; + } else { + mpp_err("Error: trying to set invalid reference index."); + } +} + + +static void set_ref_dbase(Av1dHalCtx *p_hal, RK_S32 i, RK_S32 val, HalBufs bufs, RK_U32 offset) +{ + VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx; + VdpuAv1dRegSet *regs = ctx->regs; + HalBuf *tile_out_buf; + tile_out_buf = hal_bufs_get_buf(bufs, val); + // MppBuffer framebuf = NULL; + + // mpp_buf_slot_get_prop(slots, val, SLOT_BUFFER, &framebuf); + if (tile_out_buf == NULL) { + mpp_err_f("get slots frame buff fail"); + } + val = mpp_buffer_get_fd(tile_out_buf->buf[0]); + if (i == 0) { + mpp_dev_set_reg_offset(p_hal->dev, 135, offset); + regs->addr_cfg.swreg135.sw_refer0_dbase_lsb = val; + } else if (i == 1) { + mpp_dev_set_reg_offset(p_hal->dev, 137, offset); + regs->addr_cfg.swreg137.sw_refer1_dbase_lsb = val; + } else if (i == 2) { + mpp_dev_set_reg_offset(p_hal->dev, 139, offset); + regs->addr_cfg.swreg139.sw_refer2_dbase_lsb = val; + } else if (i == 3) { + mpp_dev_set_reg_offset(p_hal->dev, 141, offset); + regs->addr_cfg.swreg141.sw_refer3_dbase_lsb = val; + } else if (i == 4) { + mpp_dev_set_reg_offset(p_hal->dev, 143, offset); + regs->addr_cfg.swreg143.sw_refer4_dbase_lsb = val; + } else if (i == 5) { + mpp_dev_set_reg_offset(p_hal->dev, 145, offset); + regs->addr_cfg.swreg145.sw_refer5_dbase_lsb = val; + } else if (i == 6) { + mpp_dev_set_reg_offset(p_hal->dev, 147, offset); + regs->addr_cfg.swreg147.sw_refer6_dbase_lsb = val; + } else { + mpp_err("Error: trying to set invalid reference index."); + } +} + +static void set_ref_dbase_msb(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) +{ + if (i == 0) { + regs->addr_cfg.swreg134.sw_refer0_dbase_msb = val; + } else if (i == 1) { + regs->addr_cfg.swreg136.sw_refer1_dbase_msb = val; + } else if (i == 2) { + regs->addr_cfg.swreg138.sw_refer2_dbase_msb = val; + } else if (i == 3) { + regs->addr_cfg.swreg140.sw_refer3_dbase_msb = val; + } else if (i == 4) { + regs->addr_cfg.swreg142.sw_refer4_dbase_msb = val; + } else if (i == 5) { + regs->addr_cfg.swreg144.sw_refer5_dbase_msb = val; + } else if (i == 6) { + regs->addr_cfg.swreg146.sw_refer6_dbase_msb = val; + } else { + mpp_err("Error: trying to set invalid reference index."); + } +} + +static void set_ref_ty_base(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val, HalBufs bufs) +{ + // MppBuffer framebuf = NULL; + // mpp_buf_slot_get_prop(slots, val, SLOT_BUFFER, &framebuf); + HalBuf *tile_out_buf; + tile_out_buf = hal_bufs_get_buf(bufs, val); + + if (tile_out_buf == NULL) { + mpp_err_f("get slots frame buff fail"); + } + val = mpp_buffer_get_fd(tile_out_buf->buf[0]); + + if (i == 0) { + regs->swreg192.sw_refer0_tybase_lsb = val; + } else if (i == 1) { + regs->swreg194.sw_refer1_tybase_lsb = val; + } else if (i == 2) { + regs->swreg196.sw_refer2_tybase_lsb = val; + } else if (i == 3) { + regs->swreg198.sw_refer3_tybase_lsb = val; + } else if (i == 4) { + regs->swreg200.sw_refer4_tybase_lsb = val; + } else if (i == 5) { + regs->swreg202.sw_refer5_tybase_lsb = val; + } else if (i == 6) { + regs->swreg204.sw_refer6_tybase_lsb = val; + } else { + mpp_err("Error: trying to set invalid reference index."); + } +} + +static void set_ref_ty_base_msb(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) +{ + if (i == 0) { + regs->swreg191.sw_refer0_tybase_msb = val; + } else if (i == 1) { + regs->swreg193.sw_refer1_tybase_msb = val; + } else if (i == 2) { + regs->swreg195.sw_refer2_tybase_msb = val; + } else if (i == 3) { + regs->swreg197.sw_refer3_tybase_msb = val; + } else if (i == 4) { + regs->swreg199.sw_refer4_tybase_msb = val; + } else if (i == 5) { + regs->swreg201.sw_refer5_tybase_msb = val; + } else if (i == 6) { + regs->swreg203.sw_refer6_tybase_msb = val; + } else { + mpp_err(" trying to set invalid reference index."); + } +} + +static void set_ref_tc_base(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val, HalBufs bufs) +{ + // MppBuffer framebuf = NULL; + // mpp_buf_slot_get_prop(slots, val, SLOT_BUFFER, &framebuf); + HalBuf *tile_out_buf; + tile_out_buf = hal_bufs_get_buf(bufs, val); + + if (tile_out_buf == NULL) { + mpp_err_f("get slots frame buff fail"); + } + val = mpp_buffer_get_fd(tile_out_buf->buf[0]); + + if (i == 0) { + regs->swreg226.sw_refer0_tcbase_lsb = val; + } else if (i == 1) { + regs->swreg228.sw_refer1_tcbase_lsb = val; + } else if (i == 2) { + regs->swreg230.sw_refer2_tcbase_lsb = val; + } else if (i == 3) { + regs->swreg232.sw_refer3_tcbase_lsb = val; + } else if (i == 4) { + regs->swreg234.sw_refer4_tcbase_lsb = val; + } else if (i == 5) { + regs->swreg236.sw_refer5_tcbase_lsb = val; + } else if (i == 6) { + regs->swreg238.sw_refer6_tcbase_lsb = val; + } else { + mpp_err("Error: trying to set invalid reference index."); + } +} + + +static void set_ref_tc_base_msb(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) +{ + if (i == 0) { + regs->swreg225.sw_refer0_tcbase_msb = val; + } else if (i == 1) { + regs->swreg227.sw_refer1_tcbase_msb = val; + } else if (i == 2) { + regs->swreg229.sw_refer2_tcbase_msb = val; + } else if (i == 3) { + regs->swreg231.sw_refer3_tcbase_msb = val; + } else if (i == 4) { + regs->swreg233.sw_refer4_tcbase_msb = val; + } else if (i == 5) { + regs->swreg235.sw_refer5_tcbase_msb = val; + } else if (i == 6) { + regs->swreg237.sw_refer6_tcbase_msb = val; + } else { + mpp_err("Error: trying to set invalid reference index."); + } +} + +static void set_ref_sign_bias(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val) +{ + if (i == 0) { + regs->swreg59.sw_ref0_sign_bias = val; + } else if (i == 1) { + regs->swreg59.sw_ref1_sign_bias = val; + } else if (i == 2) { + regs->swreg59.sw_ref2_sign_bias = val; + } else if (i == 3) { + regs->swreg59.sw_ref3_sign_bias = val; + } else if (i == 4) { + regs->swreg9.sw_ref4_sign_bias = val; + } else if (i == 5) { + regs->swreg9.sw_ref5_sign_bias = val; + } else if (i == 6) { + regs->swreg9.sw_ref6_sign_bias = val; + } else { + mpp_err("Error: trying to set invalid reference index."); + } +} + +#define MAX_FRAME_DISTANCE 31 +#define MAX_ACTIVE_REFS AV1_ACTIVE_REFS_EX + +RK_S32 GetRelativeDist(DXVA_PicParams_AV1 *dxva, RK_S32 a, RK_S32 b) +{ + if (!dxva->order_hint_bits) return 0; + const RK_S32 bits = dxva->order_hint_bits - 1; + + RK_S32 diff = a - b; + RK_S32 m = 1 << bits; + diff = (diff & (m - 1)) - (diff & m); + return diff; +} + +#define POPULATE_REF_OFFSET(index) \ + { \ + RK_S32 ref_offset[MAX_REF_FRAMES_EX - 1]; \ + RK_S32 idx = refs_selected[(index) - 1]; \ + ref_offset[0] = GetRelativeDist(dxva, dxva->frame_refs[idx].order_hint, \ + dxva->frame_refs[idx].lst_frame_offset); \ + ref_offset[1] = GetRelativeDist(dxva, dxva->frame_refs[idx].order_hint, \ + dxva->frame_refs[idx].lst2_frame_offset); \ + ref_offset[2] = GetRelativeDist(dxva, dxva->frame_refs[idx].order_hint, \ + dxva->frame_refs[idx].lst3_frame_offset); \ + ref_offset[3] = GetRelativeDist(dxva, dxva->frame_refs[idx].order_hint, \ + dxva->frame_refs[idx].gld_frame_offset); \ + ref_offset[4] = GetRelativeDist(dxva, dxva->frame_refs[idx].order_hint, \ + dxva->frame_refs[idx].bwd_frame_offset); \ + ref_offset[5] = GetRelativeDist(dxva, dxva->frame_refs[idx].order_hint, \ + dxva->frame_refs[idx].alt2_frame_offset); \ + ref_offset[6] = GetRelativeDist(dxva, dxva->frame_refs[idx].order_hint, \ + dxva->frame_refs[idx].alt_frame_offset); \ + if(index == 1) { \ + regs->swreg20.sw_mf1_last_offset = ref_offset[0]; \ + regs->swreg21.sw_mf1_last2_offset = ref_offset[1]; \ + regs->swreg22.sw_mf1_last3_offset = ref_offset[2]; \ + regs->swreg23.sw_mf1_golden_offset = ref_offset[3]; \ + regs->swreg24.sw_mf1_bwdref_offset = ref_offset[4]; \ + regs->swreg25.sw_mf1_altref2_offset = ref_offset[5]; \ + regs->swreg26.sw_mf1_altref_offset = ref_offset[6]; \ + }else if(index == 2) { \ + regs->swreg27.sw_mf2_last_offset = ref_offset[0]; \ + regs->swreg47.sw_mf2_last2_offset = ref_offset[1]; \ + regs->swreg47.sw_mf2_last3_offset = ref_offset[2]; \ + regs->swreg47.sw_mf2_golden_offset = ref_offset[3]; \ + regs->swreg48.sw_mf2_bwdref_offset = ref_offset[4]; \ + regs->swreg48.sw_mf2_altref2_offset = ref_offset[5]; \ + regs->swreg48.sw_mf2_altref_offset = ref_offset[6]; \ + }else { \ + regs->swreg184.sw_mf3_last_offset = ref_offset[0]; \ + regs->swreg185.sw_mf3_last2_offset = ref_offset[1]; \ + regs->swreg186.sw_mf3_last3_offset = ref_offset[2]; \ + regs->swreg187.sw_mf3_golden_offset = ref_offset[3]; \ + regs->swreg188.sw_mf3_bwdref_offset = ref_offset[4]; \ + regs->swreg257.sw_mf3_altref2_offset = ref_offset[5]; \ + regs->swreg262.sw_mf3_altref_offset = ref_offset[6]; \ + } \ +} + + +void set_frame_sign_bias(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) +{ + RK_U32 i = 0; + VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx; + if (!dxva->order_hint || dxva->format.frame_type == AV1_FRAME_INTRA_ONLY || + dxva->format.frame_type == AV1_FRAME_KEY) { + for (i = 0; i < AV1_REF_LIST_SIZE; i++) { + reg_ctx->ref_frame_sign_bias[i] = 0; + } + return; + } + + // Identify the nearest forward and backward references. + for (i = 0; i < AV1_ACTIVE_REFS_EX; i++) { + if (dxva->frame_refs[i].Index >= 0) { + RK_S32 ref_frame_offset = dxva->frame_refs[i].order_hint; + RK_S32 rel_off = GetRelativeDist(dxva, ref_frame_offset, dxva->order_hint); + reg_ctx->ref_frame_sign_bias[i + 1] = (rel_off <= 0) ? 0 : 1; + } + } +} + +void vdpu_av1d_set_prob(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) +{ + VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx; + const int mv_cdf_offset = offsetof(AV1CDFs, mv_cdf); + void* prob_base = mpp_buffer_get_ptr(reg_ctx->prob_tbl_base); + VdpuAv1dRegSet *regs = reg_ctx->regs; + + memcpy(prob_base, dxva->cdfs, sizeof(AV1CDFs)); + if (dxva->format.frame_type == AV1_FRAME_INTRA_ONLY || + dxva->format.frame_type == AV1_FRAME_KEY) { + // Overwrite MV context area with intrabc MV context + memcpy(prob_base + mv_cdf_offset, dxva->cdfs_ndvc, sizeof(MvCDFs)); + } + + regs->addr_cfg.swreg171.sw_prob_tab_out_base_lsb = mpp_buffer_get_fd(reg_ctx->prob_tbl_out_base); + regs->addr_cfg.swreg173.sw_prob_tab_base_lsb = mpp_buffer_get_fd(reg_ctx->prob_tbl_base); +} + +void vdpu_av1d_set_reference_frames(Av1dHalCtx *p_hal, VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva) +{ + RK_U32 tmp1, tmp2, i; + RK_U32 cur_height, cur_width; + RK_U8 max_ref_frames = MAX_REF_FRAMES_EX; + RK_U8 prev_valid = 0; + + VdpuAv1dRegSet *regs = ctx->regs; + RK_S32 ref_count[AV1DEC_MAX_PIC_BUFFERS] = {0}; + + RK_U32 ref_scale_e = 0; + RK_U32 y_stride = ctx->luma_size; + RK_U32 uv_stride = y_stride / 2; + RK_U32 mv_offset = ctx->luma_size + ctx->chroma_size + 64; + + if (!dxva->coding.intrabc) { + for (i = 0; i < AV1_REF_LIST_SIZE - 1; i++) { + if (dxva->frame_refs[i].Index >= 0) + ref_count[dxva->frame_refs[i].Index]++; + } + + for (i = 0; i < AV1DEC_MAX_PIC_BUFFERS; i++) { + if (ref_count[i]) + regs->swreg4.sw_ref_frames++; + } + } else + regs->swreg4.sw_ref_frames = 1; + + cur_width = dxva->width; + cur_height = dxva->height; + + set_frame_sign_bias(p_hal, dxva); + + for (i = LAST_FRAME; i < max_ref_frames; i++) { + RK_U32 ref = i - 1; + RK_S32 idx = 0; + if (dxva->coding.intrabc) { + idx = dxva->CurrPicTextureIndex; + tmp1 = cur_width; + tmp2 = cur_height; + } else { + tmp1 = dxva->frame_refs[ref].width; + tmp2 = dxva->frame_refs[ref].height; + if (dxva->frame_refs[ref].Index > 0) { + idx = dxva->frame_refs[ref].Index; + } + } + + set_ref_width(regs, ref, tmp1); + set_ref_height(regs, ref, tmp2); + tmp1 = ((tmp1 << AV1_REF_SCALE_SHIFT) + cur_width / 2) / cur_width; + tmp2 = ((tmp2 << AV1_REF_SCALE_SHIFT) + cur_height / 2) / cur_height; + + set_ref_hor_scale(regs, ref, tmp1); + set_ref_ver_scale(regs, ref, tmp2); + if (tmp1 != (1 << AV1_REF_SCALE_SHIFT) || + tmp2 != (1 << AV1_REF_SCALE_SHIFT)) { + ref_scale_e = 1; + } + + if (idx == ctx->prev_out_buffer_i) { + prev_valid = 1; + } + + set_ref_lum_base(regs, ref, idx, ctx->tile_out_bufs); + set_ref_cb_base(p_hal, ref, idx, ctx->tile_out_bufs, y_stride); + set_ref_dbase (p_hal, ref, idx, ctx->tile_out_bufs, mv_offset); + + set_ref_lum_base_msb(regs, ref, 0); + set_ref_cb_base_msb(regs, ref, 0); + set_ref_dbase_msb (regs, ref, 0); + + if (0) { + set_ref_ty_base(regs, ref, idx, ctx->tile_out_bufs); + set_ref_tc_base(regs, ref, idx, ctx->tile_out_bufs); + set_ref_ty_base_msb(regs, ref, 0); + set_ref_tc_base_msb(regs, ref, 0); + } + set_ref_sign_bias(regs, ref, ctx->ref_frame_sign_bias[i]); + } + + regs->swreg184.sw_ref0_gm_mode = dxva->frame_refs[0].wmtype; + regs->swreg185.sw_ref1_gm_mode = dxva->frame_refs[1].wmtype; + regs->swreg186.sw_ref2_gm_mode = dxva->frame_refs[2].wmtype; + regs->swreg187.sw_ref3_gm_mode = dxva->frame_refs[3].wmtype; + regs->swreg188.sw_ref4_gm_mode = dxva->frame_refs[4].wmtype; + regs->swreg257.sw_ref5_gm_mode = dxva->frame_refs[5].wmtype; + regs->swreg262.sw_ref6_gm_mode = dxva->frame_refs[6].wmtype; + + + if (dxva->coding.intrabc) { + ctx->prev_out_buffer_i = dxva->CurrPicTextureIndex; + } else if (!prev_valid) { + ctx->prev_out_buffer_i = dxva->frame_refs[0].Index; // LAST + } + + { + RK_S32 gld_buf_idx = GOLDEN_FRAME_EX - LAST_FRAME; + RK_S32 alt_buf_idx = ALTREF_FRAME_EX - LAST_FRAME; + RK_S32 lst_buf_idx = LAST_FRAME - LAST_FRAME; + RK_S32 bwd_buf_idx = BWDREF_FRAME_EX - LAST_FRAME; + RK_S32 alt2_buf_idx = ALTREF2_FRAME_EX - LAST_FRAME; + RK_S32 lst2_buf_idx = LAST2_FRAME_EX - LAST_FRAME; + + RK_S32 cur_frame_offset = dxva->order_hint; + RK_S32 alt_frame_offset = 0; + RK_S32 gld_frame_offset = 0; + RK_S32 bwd_frame_offset = 0; + RK_S32 alt2_frame_offset = 0; + RK_S32 refs_selected[3] = {0, 0, 0}; + RK_S32 cur_mi_cols = (dxva->width + 7) >> 3; + RK_S32 cur_mi_rows = (dxva->height + 7) >> 3; + RK_U8 mf_types[3] = {0, 0, 0}; + RK_S32 ref_stamp = 2; + RK_S32 ref_ind = 0; + RK_S32 rf; + + if (dxva->frame_refs[alt_buf_idx].Index >= 0) + alt_frame_offset = dxva->frame_refs[alt_buf_idx].order_hint; + if (dxva->frame_refs[gld_buf_idx].Index >= 0) + gld_frame_offset = dxva->frame_refs[gld_buf_idx].order_hint; + if (dxva->frame_refs[bwd_buf_idx].Index >= 0) + bwd_frame_offset = dxva->frame_refs[bwd_buf_idx].order_hint; + if (dxva->frame_refs[alt2_buf_idx].Index >= 0) + alt2_frame_offset = dxva->frame_refs[alt2_buf_idx].order_hint; + + AV1D_DBG(AV1D_DBG_LOG, "frame_offset[%d %d %d %d] lst_idx %d alt_off %d\n", + alt_frame_offset, + gld_frame_offset, + bwd_frame_offset, + alt2_frame_offset, + dxva->frame_refs[lst_buf_idx].Index, + dxva->frame_refs[lst_buf_idx].alt_frame_offset); + + if (dxva->frame_refs[lst_buf_idx].Index >= 0) { + const RK_S32 alt_frame_offset_in_lst = + dxva->frame_refs[lst_buf_idx].alt_frame_offset; + + const RK_S32 is_lst_overlay = (alt_frame_offset_in_lst == gld_frame_offset); + if (!is_lst_overlay) { + RK_S32 lst_mi_cols = + (dxva->frame_refs[lst_buf_idx].width + 7) >> 3; + RK_S32 lst_mi_rows = + (dxva->frame_refs[lst_buf_idx].height + 7) >> 3; + // TODO(stan): what's the difference btw key_frame and intra_only? + RK_S32 lst_intra_only = + dxva->frame_refs[lst_buf_idx].intra_only || + dxva->frame_refs[lst_buf_idx].is_intra_frame; + if (lst_mi_cols == cur_mi_cols && lst_mi_rows == cur_mi_rows && + !lst_intra_only) { + mf_types[ref_ind] = LAST_FRAME; + refs_selected[ref_ind++] = lst_buf_idx; + } + } + ref_stamp--; + } + + if (GetRelativeDist(dxva, bwd_frame_offset, cur_frame_offset) > 0) { + RK_S32 bwd_mi_cols = + (dxva->frame_refs[bwd_buf_idx].width + 7) >> 3; + RK_S32 bwd_mi_rows = + (dxva->frame_refs[bwd_buf_idx].height + 7) >> 3; + RK_S32 bwd_intra_only = dxva->frame_refs[bwd_buf_idx].intra_only || + dxva->frame_refs[bwd_buf_idx].is_intra_frame; + if (bwd_mi_cols == cur_mi_cols && bwd_mi_rows == cur_mi_rows && + !bwd_intra_only) { + mf_types[ref_ind] = BWDREF_FRAME_EX; + refs_selected[ref_ind++] = bwd_buf_idx; + ref_stamp--; + } + } + + if (GetRelativeDist(dxva, alt2_frame_offset, cur_frame_offset) > 0) { + RK_S32 alt2_mi_cols = + (dxva->frame_refs[alt2_buf_idx].width + 7) >> 3; + RK_S32 alt2_mi_rows = + (dxva->frame_refs[alt2_buf_idx].height + 7) >> 3; + RK_S32 alt2_intra_only = + dxva->frame_refs[alt2_buf_idx].intra_only || + dxva->frame_refs[alt2_buf_idx].is_intra_frame; + if (alt2_mi_cols == cur_mi_cols && alt2_mi_rows == cur_mi_rows && + !alt2_intra_only) { + mf_types[ref_ind] = ALTREF2_FRAME_EX; + refs_selected[ref_ind++] = alt2_buf_idx; + ref_stamp--; + } + } + + if (GetRelativeDist(dxva, alt_frame_offset, cur_frame_offset) > 0 && + ref_stamp >= 0) { + RK_S32 alt_mi_cols = + (dxva->frame_refs[alt_buf_idx].width + 7) >> 3; + RK_S32 alt_mi_rows = + (dxva->frame_refs[alt_buf_idx].height + 7) >> 3; + RK_S32 alt_intra_only = dxva->frame_refs[alt_buf_idx].intra_only || + dxva->frame_refs[alt_buf_idx].is_intra_frame; + if (alt_mi_cols == cur_mi_cols && alt_mi_rows == cur_mi_rows && + !alt_intra_only) { + mf_types[ref_ind] = ALTREF_FRAME_EX; + refs_selected[ref_ind++] = alt_buf_idx; + ref_stamp--; + } + } + + if (ref_stamp >= 0 && dxva->frame_refs[lst2_buf_idx].Index >= 0) { + RK_S32 lst2_mi_cols = + (dxva->frame_refs[lst2_buf_idx].width + 7) >> 3; + RK_S32 lst2_mi_rows = + (dxva->frame_refs[lst2_buf_idx].height + 7) >> 3; + RK_S32 lst2_intra_only = + dxva->frame_refs[lst2_buf_idx].intra_only || + dxva->frame_refs[lst2_buf_idx].is_intra_frame; + if (lst2_mi_cols == cur_mi_cols && lst2_mi_rows == cur_mi_rows && + !lst2_intra_only) { + mf_types[ref_ind] = LAST2_FRAME_EX; + refs_selected[ref_ind++] = lst2_buf_idx; + ref_stamp--; + } + } + + RK_S32 cur_offset[MAX_REF_FRAMES_EX - 1]; + RK_S32 cur_roffset[MAX_REF_FRAMES_EX - 1]; + for ( rf = 0; rf < MAX_REF_FRAMES_EX - 1; ++rf) { + RK_S32 buf_idx = dxva->frame_refs[rf].Index; + if (buf_idx >= 0) { + cur_offset[rf] = + GetRelativeDist(dxva, cur_frame_offset, + dxva->frame_refs[rf].order_hint); + cur_roffset[rf] = + GetRelativeDist(dxva, dxva->frame_refs[rf].order_hint, + cur_frame_offset); + AV1D_DBG(AV1D_DBG_LOG, "buf_idx[%d]=%d offset[%d : %d] hin %d\n", rf, buf_idx, cur_offset[rf], cur_roffset[rf], dxva->frame_refs[rf].order_hint); + } else { + cur_offset[rf] = 0; + cur_roffset[rf] = 0; + } + } + + regs->swreg11.sw_use_temporal0_mvs = 0; + regs->swreg11.sw_use_temporal1_mvs = 0; + regs->swreg11.sw_use_temporal2_mvs = 0; + regs->swreg11.sw_use_temporal3_mvs = 0; + + if (dxva->coding.use_ref_frame_mvs && ref_ind > 0 && + cur_offset[mf_types[0] - LAST_FRAME] <= MAX_FRAME_DISTANCE && + cur_offset[mf_types[0] - LAST_FRAME] >= -MAX_FRAME_DISTANCE) { + regs->swreg11.sw_use_temporal0_mvs = 1; + POPULATE_REF_OFFSET(1) + } + + if (dxva->coding.use_ref_frame_mvs && ref_ind > 1 && + cur_offset[mf_types[1] - LAST_FRAME] <= MAX_FRAME_DISTANCE && + cur_offset[mf_types[1] - LAST_FRAME] >= -MAX_FRAME_DISTANCE) { + regs->swreg11.sw_use_temporal1_mvs = 1; + POPULATE_REF_OFFSET(2) + } + + if (dxva->coding.use_ref_frame_mvs && ref_ind > 2 && + cur_offset[mf_types[2] - LAST_FRAME] <= MAX_FRAME_DISTANCE && + cur_offset[mf_types[2] - LAST_FRAME] >= -MAX_FRAME_DISTANCE) { + regs->swreg11.sw_use_temporal2_mvs = 1; + POPULATE_REF_OFFSET(3) + } + + // Pass one additional frame that will contain the segment information + if (dxva->segmentation.enabled && + dxva->primary_ref_frame < ALLOWED_REFS_PER_FRAME_EX) { + // Primary ref frame is zero based + RK_S32 prim_buf_idx = dxva->frame_refs[dxva->primary_ref_frame].Index; + if (prim_buf_idx >= 0) { + MppBuffer buffer = NULL; + y_stride = ctx->luma_size ; + uv_stride = y_stride / 2; + mv_offset = y_stride + uv_stride + 64; + mpp_buf_slot_get_prop(p_hal->slots, dxva->RefFrameMapTextureIndex[dxva->primary_ref_frame], SLOT_BUFFER, &buffer); + regs->addr_cfg.swreg80.sw_segment_read_base_msb = 0; + regs->addr_cfg.swreg81.sw_segment_read_base_lsb = mpp_buffer_get_fd(buffer); + mpp_dev_set_reg_offset(p_hal->dev, 81, mv_offset); + regs->swreg11.sw_use_temporal3_mvs = 1; + } + } + if (dxva->primary_ref_frame < ALLOWED_REFS_PER_FRAME_EX) { + RK_S32 prim_buf_idx = dxva->primary_ref_frame; + ctx->resolution_change = + cur_mi_cols != + (RK_S32)((dxva->frame_refs[prim_buf_idx].width + 7) >> + 3) || + cur_mi_rows != + (RK_S32)((dxva->frame_refs[prim_buf_idx].height + 7) >> + 3); + } + + regs->swreg184.sw_cur_last_offset = cur_offset[0]; + regs->swreg185.sw_cur_last2_offset = cur_offset[1]; + regs->swreg186.sw_cur_last3_offset = cur_offset[2]; + regs->swreg187.sw_cur_golden_offset = cur_offset[3]; + regs->swreg188.sw_cur_bwdref_offset = cur_offset[4]; + regs->swreg257.sw_cur_altref2_offset = cur_offset[5]; + regs->swreg262.sw_cur_altref_offset = cur_offset[6]; + + regs->swreg184.sw_cur_last_roffset = cur_roffset[0]; + regs->swreg185.sw_cur_last2_roffset = cur_roffset[1]; + regs->swreg186.sw_cur_last3_roffset = cur_roffset[2]; + regs->swreg187.sw_cur_golden_roffset = cur_roffset[3]; + regs->swreg188.sw_cur_bwdref_roffset = cur_roffset[4]; + regs->swreg257.sw_cur_altref2_roffset = cur_roffset[5]; + regs->swreg262.sw_cur_altref_roffset = cur_roffset[6]; + + /* Index start from 0 */ + regs->swreg9.sw_mf1_type = mf_types[0] - LAST_FRAME; + regs->swreg9.sw_mf2_type = mf_types[1] - LAST_FRAME; + regs->swreg9.sw_mf3_type = mf_types[2] - LAST_FRAME; + AV1D_DBG(AV1D_DBG_LOG, "mf_types[%d %d %d]\n", mf_types[0], mf_types[1], mf_types[2]); + } + regs->swreg5.sw_ref_scaling_enable = ref_scale_e; +} +#undef MAX_FRAME_DISTANCE + +void vdpu_av1d_superres_params(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) +{ + // Compute and store scaling paramers needed for superres +#define SUPERRES_SCALE_BITS 3 +#define SCALE_NUMERATOR 8 +#define SUPERRES_SCALE_DENOMINATOR_MIN (SCALE_NUMERATOR + 1) + +#define RS_SUBPEL_BITS 6 +#define RS_SUBPEL_MASK ((1 << RS_SUBPEL_BITS) - 1) +#define RS_SCALE_SUBPEL_BITS 14 +#define RS_SCALE_SUBPEL_MASK ((1 << RS_SCALE_SUBPEL_BITS) - 1) +#define RS_SCALE_EXTRA_BITS (RS_SCALE_SUBPEL_BITS - RS_SUBPEL_BITS) +#define RS_SCALE_EXTRA_OFF (1 << (RS_SCALE_EXTRA_BITS - 1)) + VdpuAv1dRegCtx *ctx = p_hal->reg_ctx; + VdpuAv1dRegSet *regs = ctx->regs; + RK_U8 superres_scale_denominator = SCALE_NUMERATOR; + RK_U32 superres_luma_step = 0; + RK_U32 superres_chroma_step = 0; + RK_U32 superres_luma_step_invra = 0; + RK_U32 superres_chroma_step_invra = 0; + RK_U32 superres_init_luma_subpel_x = 0; + RK_U32 superres_init_chroma_subpel_x = 0; + RK_U32 superres_is_scaled = 1; + RK_U32 width = 0; + if (dxva->coding.superres) { + superres_scale_denominator = regs->swreg9.sw_scale_denom_minus9 + 9; + } + + if (superres_scale_denominator > SCALE_NUMERATOR) { + width = (dxva->upscaled_width * SCALE_NUMERATOR + + (superres_scale_denominator / 2)) / + superres_scale_denominator; + RK_U32 min_w = MPP_MIN(16, dxva->upscaled_width); + if (width < min_w) width = min_w; + if (width == dxva->upscaled_width) { + superres_is_scaled = 0; + superres_luma_step = RS_SCALE_SUBPEL_BITS; + superres_chroma_step = RS_SCALE_SUBPEL_BITS; + superres_luma_step_invra = RS_SCALE_SUBPEL_BITS; + superres_chroma_step_invra = RS_SCALE_SUBPEL_BITS; + superres_init_luma_subpel_x = 0; + superres_init_chroma_subpel_x = 0; + goto end; + } + { + RK_S32 upscaledLumaPlaneW = dxva->upscaled_width; + RK_S32 downscaledLumaPlaneW = width; + + RK_S32 downscaledChromaPlaneW = (downscaledLumaPlaneW + 1) >> 1; + RK_S32 upscaledChromaPlaneW = (upscaledLumaPlaneW + 1) >> 1; + + RK_S32 stepLumaX = ((downscaledLumaPlaneW << RS_SCALE_SUBPEL_BITS) + + (upscaledLumaPlaneW / 2)) / + upscaledLumaPlaneW; + RK_S32 stepChromaX = ((downscaledChromaPlaneW << RS_SCALE_SUBPEL_BITS) + + (upscaledChromaPlaneW / 2)) / + upscaledChromaPlaneW; + RK_S32 errLuma = (upscaledLumaPlaneW * stepLumaX) - + (downscaledLumaPlaneW << RS_SCALE_SUBPEL_BITS); + RK_S32 errChroma = (upscaledChromaPlaneW * stepChromaX) - + (downscaledChromaPlaneW << RS_SCALE_SUBPEL_BITS); + RK_S32 initialLumaSubpelX = + ((-((upscaledLumaPlaneW - downscaledLumaPlaneW) + << (RS_SCALE_SUBPEL_BITS - 1)) + + upscaledLumaPlaneW / 2) / + upscaledLumaPlaneW + + (1 << (RS_SCALE_EXTRA_BITS - 1)) - errLuma / 2) & + RS_SCALE_SUBPEL_MASK; + RK_S32 initialChromaSubpelX = + ((-((upscaledChromaPlaneW - downscaledChromaPlaneW) + << (RS_SCALE_SUBPEL_BITS - 1)) + + upscaledChromaPlaneW / 2) / + upscaledChromaPlaneW + + (1 << (RS_SCALE_EXTRA_BITS - 1)) - errChroma / 2) & + RS_SCALE_SUBPEL_MASK; + + superres_luma_step = stepLumaX; + superres_chroma_step = stepChromaX; + superres_luma_step_invra = + ((upscaledLumaPlaneW << RS_SCALE_SUBPEL_BITS) + + (downscaledLumaPlaneW / 2)) / + downscaledLumaPlaneW; + superres_chroma_step_invra = + ((upscaledChromaPlaneW << RS_SCALE_SUBPEL_BITS) + + (downscaledChromaPlaneW / 2)) / + downscaledChromaPlaneW; + superres_init_luma_subpel_x = initialLumaSubpelX; + superres_init_chroma_subpel_x = initialChromaSubpelX; + } + } else { + superres_luma_step = RS_SCALE_SUBPEL_BITS; + superres_chroma_step = RS_SCALE_SUBPEL_BITS; + superres_luma_step_invra = RS_SCALE_SUBPEL_BITS; + superres_chroma_step_invra = RS_SCALE_SUBPEL_BITS; + superres_init_luma_subpel_x = 0; + superres_init_chroma_subpel_x = 0; + superres_is_scaled = 0; + } +end: + regs->swreg51.sw_superres_luma_step = superres_luma_step; + regs->swreg51.sw_superres_chroma_step = superres_chroma_step; + regs->swreg298.sw_superres_luma_step_invra = superres_luma_step_invra; + regs->swreg298.sw_superres_chroma_step_invra = superres_chroma_step_invra; + regs->swreg52.sw_superres_init_luma_subpel_x = superres_init_luma_subpel_x; + regs->swreg52.sw_superres_init_chroma_subpel_x = superres_init_chroma_subpel_x; + regs->swreg5.sw_superres_is_scaled = superres_is_scaled; + + regs->addr_cfg.swreg89.sw_superres_colbuf_base_lsb = mpp_buffer_get_fd(ctx->filter_mem); + mpp_dev_set_reg_offset(p_hal->dev, 89, ctx->filt_info[SR_COL].offset); +} + + +void vdpu_av1d_set_picture_dimensions(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) +{ + /* Write dimensions for the current picture + (This is needed when scaling is used) */ + VdpuAv1dRegCtx *ctx = p_hal->reg_ctx; + VdpuAv1dRegSet *regs = ctx->regs; + + regs->swreg4.sw_pic_width_in_cbs = MPP_ALIGN(dxva->width, 8) >> 3; + regs->swreg4.sw_pic_height_in_cbs = MPP_ALIGN(dxva->height, 8) >> 3; + regs->swreg12.sw_pic_width_pad = MPP_ALIGN(dxva->width, 8) - dxva->width; + regs->swreg12.sw_pic_height_pad = MPP_ALIGN(dxva->height, 8) - dxva->height; + + regs->swreg8.sw_superres_pic_width = dxva->upscaled_width; + regs->swreg9.sw_scale_denom_minus9 = dxva->superres_denom; + + vdpu_av1d_superres_params(p_hal, dxva); +} + +void vdpu_av1d_set_segmentation(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva) +{ + RK_U32 segval[MAX_MB_SEGMENTS][SEG_AV1_LVL_MAX]; + VdpuAv1dRegSet *regs = ctx->regs; + RK_U8 s, i, j; + RK_U8 segsign = 0; + RK_U8 preskip_segid = 0; + RK_U8 last_active_seg = 0; + /* Segmentation */ + regs->swreg13.sw_segment_temp_upd_e = dxva->segmentation.update_data; + regs->swreg13.sw_segment_upd_e = dxva->segmentation.update_map; + regs->swreg13.sw_segment_e = dxva->segmentation.enabled; + + //dec->error_resilient || dec->resolution_change; + regs->swreg5.sw_error_resilient = dxva->coding.error_resilient_mode; + + if ((!dxva->format.frame_type || dxva->format.frame_type == AV1_FRAME_INTRA_ONLY) + || regs->swreg5.sw_error_resilient) { + regs->swreg11.sw_use_temporal3_mvs = 0; + } + + regs->swreg14.sw_filt_level0 = dxva->loop_filter.filter_level[0]; + regs->swreg15.sw_filt_level1 = dxva->loop_filter.filter_level[1]; + regs->swreg16.sw_filt_level2 = dxva->loop_filter.filter_level_u; + regs->swreg17.sw_filt_level3 = dxva->loop_filter.filter_level_v; + + /* Set filter level and QP for every segment ID. Initialize all + * segments with default QP and filter level. */ + for (s = 0; s < MAX_MB_SEGMENTS; s++) { + segval[s][SEG_AV1_LVL_ALT_Q] = 0; + segval[s][SEG_AV1_LVL_ALT_LF_Y_V] = 0; + segval[s][SEG_AV1_LVL_ALT_LF_Y_H] = 0; + segval[s][SEG_AV1_LVL_ALT_LF_U] = 0; + segval[s][SEG_AV1_LVL_ALT_LF_V] = 0; + segval[s][SEG_AV1_LVL_REF_FRAME] = 0; /* segment ref_frame disabled */ + segval[s][SEG_AV1_LVL_SKIP] = 0; /* segment skip disabled */ + segval[s][SEG_AV1_LVL_GLOBALMV] = 0; /* global motion */ + } + /* If a feature is enabled for a segment, overwrite the default. */ + if (dxva->segmentation.enabled) { + RK_S32 (*segdata)[SEG_AV1_LVL_MAX] = dxva->segmentation.feature_data; + + for (s = 0; s < MAX_MB_SEGMENTS; s++) { + if (dxva->segmentation.feature_mask[s] & (1 << SEG_AV1_LVL_ALT_Q)) { + segval[s][SEG_AV1_LVL_ALT_Q] = + MPP_CLIP3(0, 255, MPP_ABS(segdata[s][SEG_AV1_LVL_ALT_Q])); + segsign |= (segdata[s][SEG_AV1_LVL_ALT_Q] < 0) << s; + } + + if (dxva->segmentation.feature_mask[s] & (1 << SEG_AV1_LVL_ALT_LF_Y_V)) + segval[s][SEG_AV1_LVL_ALT_LF_Y_V] = + MPP_CLIP3(-63, 63, segdata[s][SEG_AV1_LVL_ALT_LF_Y_V]); + + if (dxva->segmentation.feature_mask[s] & (1 << SEG_AV1_LVL_ALT_LF_Y_H)) + segval[s][SEG_AV1_LVL_ALT_LF_Y_H] = + MPP_CLIP3(-63, 63, segdata[s][SEG_AV1_LVL_ALT_LF_Y_H]); + + if (dxva->segmentation.feature_mask[s] & (1 << SEG_AV1_LVL_ALT_LF_U)) + segval[s][SEG_AV1_LVL_ALT_LF_U] = + MPP_CLIP3(-63, 63, segdata[s][SEG_AV1_LVL_ALT_LF_U]); + + if (dxva->segmentation.feature_mask[s] & (1 << SEG_AV1_LVL_ALT_LF_V)) + segval[s][SEG_AV1_LVL_ALT_LF_V] = + MPP_CLIP3(-63, 63, segdata[s][SEG_AV1_LVL_ALT_LF_V]); + + if (dxva->format.frame_type && + dxva->segmentation.feature_mask[s] & (1 << SEG_AV1_LVL_REF_FRAME)) + segval[s][SEG_AV1_LVL_REF_FRAME] = + segdata[s][SEG_AV1_LVL_REF_FRAME] + 1; + + if (dxva->segmentation.feature_mask[s] & (1 << SEG_AV1_LVL_SKIP)) + segval[s][SEG_AV1_LVL_SKIP] = 1; + if (dxva->segmentation.feature_mask[s] & (1 << SEG_AV1_LVL_GLOBALMV)) + segval[s][SEG_AV1_LVL_GLOBALMV] = 1; + } + } + + for (i = 0; i < MAX_MB_SEGMENTS; i++) { + for (j = 0; j < SEG_AV1_LVL_MAX; j++) { + if (dxva->segmentation.feature_mask[i] & (1 << j)) { + preskip_segid |= j >= SEG_AV1_LVL_REF_FRAME; + last_active_seg = MPP_MAX(i, last_active_seg); + } + } + } + + regs->swreg9.sw_last_active_seg = last_active_seg; + regs->swreg5.sw_preskip_segid = preskip_segid; + + regs->swreg12.sw_seg_quant_sign = segsign; + /* Write QP, filter level, ref frame and skip for every segment */ + regs->swreg14.sw_quant_seg0 = segval[0][SEG_AV1_LVL_ALT_Q]; + regs->swreg14.sw_filt_level_delta0_seg0 = segval[0][SEG_AV1_LVL_ALT_LF_Y_V]; + regs->swreg20.sw_filt_level_delta1_seg0 = segval[0][SEG_AV1_LVL_ALT_LF_Y_H]; + regs->swreg20.sw_filt_level_delta2_seg0 = segval[0][SEG_AV1_LVL_ALT_LF_U]; + regs->swreg20.sw_filt_level_delta3_seg0 = segval[0][SEG_AV1_LVL_ALT_LF_V]; + regs->swreg14.sw_refpic_seg0 = segval[0][SEG_AV1_LVL_REF_FRAME]; + regs->swreg14.sw_skip_seg0 = segval[0][SEG_AV1_LVL_SKIP]; + regs->swreg20.sw_global_mv_seg0 = segval[0][SEG_AV1_LVL_GLOBALMV]; + + regs->swreg15.sw_quant_seg1 = segval[1][SEG_AV1_LVL_ALT_Q]; + regs->swreg15.sw_filt_level_delta0_seg1 = segval[1][SEG_AV1_LVL_ALT_LF_Y_V]; + regs->swreg21.sw_filt_level_delta1_seg1 = segval[1][SEG_AV1_LVL_ALT_LF_Y_H]; + regs->swreg21.sw_filt_level_delta2_seg1 = segval[1][SEG_AV1_LVL_ALT_LF_U]; + regs->swreg21.sw_filt_level_delta3_seg1 = segval[1][SEG_AV1_LVL_ALT_LF_V]; + regs->swreg15.sw_refpic_seg1 = segval[1][SEG_AV1_LVL_REF_FRAME]; + regs->swreg15.sw_skip_seg1 = segval[1][SEG_AV1_LVL_SKIP]; + regs->swreg21.sw_global_mv_seg1 = segval[1][SEG_AV1_LVL_GLOBALMV]; + + regs->swreg16.sw_quant_seg2 = segval[2][SEG_AV1_LVL_ALT_Q]; + regs->swreg16.sw_filt_level_delta0_seg2 = segval[2][SEG_AV1_LVL_ALT_LF_Y_V]; + regs->swreg22.sw_filt_level_delta1_seg2 = segval[2][SEG_AV1_LVL_ALT_LF_Y_H]; + regs->swreg22.sw_filt_level_delta2_seg2 = segval[2][SEG_AV1_LVL_ALT_LF_U]; + regs->swreg22.sw_filt_level_delta3_seg2 = segval[2][SEG_AV1_LVL_ALT_LF_V]; + regs->swreg16.sw_refpic_seg2 = segval[2][SEG_AV1_LVL_REF_FRAME]; + regs->swreg16.sw_skip_seg2 = segval[2][SEG_AV1_LVL_SKIP]; + regs->swreg22.sw_global_mv_seg2 = segval[2][SEG_AV1_LVL_GLOBALMV]; + + regs->swreg17.sw_quant_seg3 = segval[3][SEG_AV1_LVL_ALT_Q]; + regs->swreg17.sw_filt_level_delta0_seg3 = segval[3][SEG_AV1_LVL_ALT_LF_Y_V]; + regs->swreg23.sw_filt_level_delta1_seg3 = segval[3][SEG_AV1_LVL_ALT_LF_Y_H]; + regs->swreg23.sw_filt_level_delta2_seg3 = segval[3][SEG_AV1_LVL_ALT_LF_U]; + regs->swreg23.sw_filt_level_delta3_seg3 = segval[3][SEG_AV1_LVL_ALT_LF_V]; + regs->swreg17.sw_refpic_seg3 = segval[3][SEG_AV1_LVL_REF_FRAME]; + regs->swreg17.sw_skip_seg3 = segval[3][SEG_AV1_LVL_SKIP]; + regs->swreg23.sw_global_mv_seg3 = segval[3][SEG_AV1_LVL_GLOBALMV]; + + regs->swreg18.sw_quant_seg4 = segval[4][SEG_AV1_LVL_ALT_Q]; + regs->swreg18.sw_filt_level_delta0_seg4 = segval[4][SEG_AV1_LVL_ALT_LF_Y_V]; + regs->swreg24.sw_filt_level_delta1_seg4 = segval[4][SEG_AV1_LVL_ALT_LF_Y_H]; + regs->swreg24.sw_filt_level_delta2_seg4 = segval[4][SEG_AV1_LVL_ALT_LF_U]; + regs->swreg24.sw_filt_level_delta3_seg4 = segval[4][SEG_AV1_LVL_ALT_LF_V]; + regs->swreg18.sw_refpic_seg4 = segval[4][SEG_AV1_LVL_REF_FRAME]; + regs->swreg18.sw_skip_seg4 = segval[4][SEG_AV1_LVL_SKIP]; + regs->swreg24.sw_global_mv_seg4 = segval[4][SEG_AV1_LVL_GLOBALMV]; + + regs->swreg19.sw_quant_seg5 = segval[5][SEG_AV1_LVL_ALT_Q]; + regs->swreg19.sw_filt_level_delta0_seg5 = segval[5][SEG_AV1_LVL_ALT_LF_Y_V]; + regs->swreg25.sw_filt_level_delta1_seg5 = segval[5][SEG_AV1_LVL_ALT_LF_Y_H]; + regs->swreg25.sw_filt_level_delta2_seg5 = segval[5][SEG_AV1_LVL_ALT_LF_U]; + regs->swreg25.sw_filt_level_delta3_seg5 = segval[5][SEG_AV1_LVL_ALT_LF_V]; + regs->swreg19.sw_refpic_seg5 = segval[5][SEG_AV1_LVL_REF_FRAME]; + regs->swreg19.sw_skip_seg5 = segval[5][SEG_AV1_LVL_SKIP]; + regs->swreg25.sw_global_mv_seg5 = segval[5][SEG_AV1_LVL_GLOBALMV]; + + regs->swreg31.sw_quant_seg6 = segval[6][SEG_AV1_LVL_ALT_Q]; + regs->swreg31.sw_filt_level_delta0_seg6 = segval[6][SEG_AV1_LVL_ALT_LF_Y_V]; + regs->swreg26.sw_filt_level_delta1_seg6 = segval[6][SEG_AV1_LVL_ALT_LF_Y_H]; + regs->swreg26.sw_filt_level_delta2_seg6 = segval[6][SEG_AV1_LVL_ALT_LF_U]; + regs->swreg26.sw_filt_level_delta3_seg6 = segval[6][SEG_AV1_LVL_ALT_LF_V]; + regs->swreg31.sw_refpic_seg6 = segval[6][SEG_AV1_LVL_REF_FRAME]; + regs->swreg31.sw_skip_seg6 = segval[6][SEG_AV1_LVL_SKIP]; + regs->swreg26.sw_global_mv_seg6 = segval[6][SEG_AV1_LVL_GLOBALMV]; + + regs->swreg32.sw_quant_seg7 = segval[7][SEG_AV1_LVL_ALT_Q]; + regs->swreg32.sw_filt_level_delta0_seg7 = segval[7][SEG_AV1_LVL_ALT_LF_Y_V]; + regs->swreg27.sw_filt_level_delta1_seg7 = segval[7][SEG_AV1_LVL_ALT_LF_Y_H]; + regs->swreg27.sw_filt_level_delta2_seg7 = segval[7][SEG_AV1_LVL_ALT_LF_U]; + regs->swreg27.sw_filt_level_delta3_seg7 = segval[7][SEG_AV1_LVL_ALT_LF_V]; + regs->swreg32.sw_refpic_seg7 = segval[7][SEG_AV1_LVL_REF_FRAME]; + regs->swreg32.sw_skip_seg7 = segval[7][SEG_AV1_LVL_SKIP]; + regs->swreg27.sw_global_mv_seg7 = segval[7][SEG_AV1_LVL_GLOBALMV]; +} + +void vdpu_av1d_set_loopfilter(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) +{ + VdpuAv1dRegCtx *ctx = p_hal->reg_ctx; + VdpuAv1dRegSet *regs = ctx->regs; + regs->swreg3.sw_filtering_dis = (dxva->loop_filter.filter_level[0] == 0) && (dxva->loop_filter.filter_level[1] == 0); + regs->swreg5.sw_filt_level_base_gt32 = dxva->loop_filter.filter_level[0] > 32; + regs->swreg30.sw_filt_sharpness = dxva->loop_filter.sharpness_level; + if (dxva->loop_filter.mode_ref_delta_enabled) { + regs->swreg59.sw_filt_ref_adj_0 = dxva->loop_filter.ref_deltas[0]; + regs->swreg59.sw_filt_ref_adj_1 = dxva->loop_filter.ref_deltas[1]; + regs->swreg59.sw_filt_ref_adj_2 = dxva->loop_filter.ref_deltas[2]; + regs->swreg59.sw_filt_ref_adj_3 = dxva->loop_filter.ref_deltas[3]; + regs->swreg30.sw_filt_ref_adj_4 = dxva->loop_filter.ref_deltas[4]; + regs->swreg30.sw_filt_ref_adj_5 = dxva->loop_filter.ref_deltas[5]; + regs->swreg49.sw_filt_ref_adj_7 = dxva->loop_filter.ref_deltas[6]; + regs->swreg49.sw_filt_ref_adj_6 = dxva->loop_filter.ref_deltas[7]; + regs->swreg30.sw_filt_mb_adj_0 = dxva->loop_filter.mode_deltas[0]; + regs->swreg30.sw_filt_mb_adj_1 = dxva->loop_filter.mode_deltas[1]; + } else { + regs->swreg59.sw_filt_ref_adj_0 = 0; + regs->swreg59.sw_filt_ref_adj_1 = 0; + regs->swreg59.sw_filt_ref_adj_2 = 0; + regs->swreg59.sw_filt_ref_adj_3 = 0; + regs->swreg30.sw_filt_ref_adj_4 = 0; + regs->swreg30.sw_filt_ref_adj_5 = 0; + regs->swreg49.sw_filt_ref_adj_7 = 0; + regs->swreg49.sw_filt_ref_adj_6 = 0; + regs->swreg30.sw_filt_mb_adj_0 = 0; + regs->swreg30.sw_filt_mb_adj_1 = 0; + } + + regs->addr_cfg.swreg179.sw_dec_vert_filt_base_lsb = mpp_buffer_get_fd(ctx->filter_mem); + regs->addr_cfg.swreg183.sw_dec_bsd_ctrl_base_lsb = mpp_buffer_get_fd(ctx->filter_mem); + mpp_dev_set_reg_offset(p_hal->dev, 183, ctx->filt_info[DB_CTRL_COL].offset); +} + +void vdpu_av1d_set_global_model(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) +{ + VdpuAv1dRegCtx *ctx = p_hal->reg_ctx; + VdpuAv1dRegSet *regs = ctx->regs; + RK_U8 *dst = (RK_U8 *) mpp_buffer_get_ptr(ctx->global_model); + RK_S32 ref_frame, i; + for (ref_frame = 0; ref_frame < GM_GLOBAL_MODELS_PER_FRAME; ++ref_frame) { + mpp_assert(dxva->frame_refs[ref_frame].wmtype <= 3); + + /* In DDR wmmat order is 0, 1, 3, 2, 4, 5 */ + for (i = 0; i < 6; ++i) { + if (i == 2) + *(RK_S32 *)(dst) = dxva->frame_refs[ref_frame].wmmat[3]; + else if (i == 3) + *(RK_S32 *)(dst) = dxva->frame_refs[ref_frame].wmmat[2]; + else + *(RK_S32 *)(dst) = dxva->frame_refs[ref_frame].wmmat[i]; + dst += 4; + } + + *(RK_S16 *)(dst) = dxva->frame_refs[ref_frame].alpha;//-32768; + dst += 2; + *(RK_S16 *)(dst) = dxva->frame_refs[ref_frame].beta;//-32768; + dst += 2; + *(RK_S16 *)(dst) = dxva->frame_refs[ref_frame].gamma;//-32768; + dst += 2; + *(RK_S16 *)(dst) = dxva->frame_refs[ref_frame].delta;//-32768; + dst += 2; + } + + regs->addr_cfg.swreg82.sw_global_model_base_msb = 0; + regs->addr_cfg.swreg83.sw_global_model_base_lsb = mpp_buffer_get_fd(ctx->global_model); +} + +void vdpu_av1d_set_tile_info_regs(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva) +{ + int transpose = ctx->tile_transpose; + VdpuAv1dRegSet *regs = ctx->regs; + size_t context_update_tile_id = dxva->tiles.context_update_id; + size_t context_update_y = context_update_tile_id / dxva->tiles.cols; + size_t context_update_x = context_update_tile_id % dxva->tiles.cols; + + regs->swreg11.sw_multicore_expect_context_update = (0 == context_update_x); + if (transpose) { + context_update_tile_id = + context_update_x * dxva->tiles.rows + context_update_y; + } + regs->swreg10.sw_tile_enable = (dxva->tiles.cols > 1) || (dxva->tiles.rows > 1); + regs->swreg10.sw_num_tile_cols_8k = dxva->tiles.cols; + regs->swreg10.sw_num_tile_rows_8k_av1 = dxva->tiles.rows; + regs->swreg9.sw_context_update_tile_id = context_update_tile_id; + regs->swreg10.sw_tile_transpose = transpose; + regs->swreg11.sw_dec_tile_size_mag = dxva->tiles.tile_sz_mag; + if (regs->swreg10.sw_tile_enable) AV1D_DBG(AV1D_DBG_LOG, "NOTICE: tile enabled.\n"); + + regs->addr_cfg.swreg167.sw_tile_base_lsb = mpp_buffer_get_fd(ctx->tile_info);// + regs->addr_cfg.swreg166.sw_tile_base_msb = 0; +} + +static int check_tile_width(DXVA_PicParams_AV1 *dxva, RK_S32 width, RK_S32 leftmost) +{ + RK_S32 valid = 1; + if (!leftmost && dxva->coding.use_128x128_superblock == 0 && dxva->coding.superres && width == 1) { + AV1D_DBG(AV1D_DBG_LOG, "WARNING: Superres used and tile width == 64\n"); + valid = 0; + } + + const RK_S32 sb_size_log2 = dxva->coding.use_128x128_superblock ? 7 : 6; + RK_S32 tile_width_pixels = (width << sb_size_log2); + if (dxva->coding.superres) { + tile_width_pixels = + (tile_width_pixels * (9 + dxva->superres_denom) + 4) / 8; + } + if (tile_width_pixels > 4096) { + if (dxva->coding.superres) + AV1D_LOG("WARNING: Tile width after superres > 4096\n"); + else + AV1D_LOG("WARNING: Tile width > 4096\n"); + valid = 0; + } + return valid; +} + +void vdpu_av1d_set_tile_info_mem(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) +{ + VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx; + + RK_S32 transpose = ctx->tile_transpose; + RK_S32 tmp = dxva->frame_tag_size + dxva->offset_to_dct_parts; + RK_U32 stream_len = p_hal->strm_len - tmp; + RK_U8 *p1 = (RK_U8*)mpp_buffer_get_ptr(ctx->tile_info); + RK_S32 size0 = transpose ? dxva->tiles.cols : dxva->tiles.rows; + RK_S32 size1 = transpose ? dxva->tiles.rows : dxva->tiles.cols; + RK_S32 tile0, tile1; + RK_U32 not_valid_tile_dimension = 0; + + // Write tile dimensions + for (tile0 = 0; tile0 < size0; tile0++) { + for (tile1 = 0; tile1 < size1; tile1++) { + RK_S32 tile_y = transpose ? tile1 : tile0; + RK_S32 tile_x = transpose ? tile0 : tile1; + RK_S32 tile_id = transpose ? tile1 * size0 + tile0 : tile0 * size1 + tile1; + RK_U32 start, end; + + RK_U32 y0 = dxva->tiles.heights[tile_y]; + RK_U32 y1 = dxva->tiles.heights[tile_y + 1]; + RK_U32 x0 = dxva->tiles.widths[tile_x]; + RK_U32 x1 = dxva->tiles.widths[tile_x + 1]; + + RK_U8 leftmost = (tile_x == dxva->tiles.cols - 1); + if (!not_valid_tile_dimension) + not_valid_tile_dimension = !check_tile_width(dxva, x1 - x0, leftmost); + if ((x0 << (dxva->coding.use_128x128_superblock ? 7 : 6)) >= dxva->width || + (y0 << (dxva->coding.use_128x128_superblock ? 7 : 6)) >= dxva->height) + not_valid_tile_dimension = 1; + + // tile size in SB units (width,height) + *p1++ = x1 - x0; + *p1++ = 0; + *p1++ = 0; + *p1++ = 0; + *p1++ = y1 - y0; + *p1++ = 0; + *p1++ = 0; + *p1++ = 0; + + // tile start position (offset from sw_stream0_base) + start = dxva->tiles.tile_offset_start[tile_id]; + *p1++ = start & 255; + *p1++ = (start >> 8) & 255; + *p1++ = (start >> 16) & 255; + *p1++ = (start >> 24) & 255; + if (!not_valid_tile_dimension) { + if ((start + 1) > stream_len) + not_valid_tile_dimension = 1; + } + + // # of bytes in tile data + end = dxva->tiles.tile_offset_end[tile_id]; + *p1++ = end & 255; + *p1++ = (end >> 8) & 255; + *p1++ = (end >> 16) & 255; + *p1++ = (end >> 24) & 255; + if (!not_valid_tile_dimension) { + if (end > stream_len) + not_valid_tile_dimension = 1; + } + AV1D_DBG(AV1D_DBG_LOG, "tile_info[%d][%d]: start=%08x end=%08x x0:x1=%d:%d y0:y1=%d:%d\n", + tile0, tile1, start, end, x0, x1, y0, y1); + } + } +} + +void vdpu_av1d_set_cdef(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) +{ + RK_U32 luma_pri_strength = 0; + RK_U16 luma_sec_strength = 0; + RK_U32 chroma_pri_strength = 0; + RK_U16 chroma_sec_strength = 0; + VdpuAv1dRegCtx *ctx = p_hal->reg_ctx; + VdpuAv1dRegSet *regs = ctx->regs; + RK_S32 i; + + /* CDEF */ + regs->swreg7.sw_cdef_bits = dxva->cdef.bits; + regs->swreg7.sw_cdef_damping = dxva->cdef.damping; + + for (i = 0; i < 8; i++) { + if (i == (1 << (dxva->cdef.bits))) break; + luma_pri_strength |= dxva->cdef.y_strengths[i].primary << (i * 4); + luma_sec_strength |= dxva->cdef.y_strengths[i].secondary << (i * 2); + chroma_pri_strength |= dxva->cdef.uv_strengths[i].primary << (i * 4); + chroma_sec_strength |= dxva->cdef.uv_strengths[i].secondary << (i * 2); + } + + regs->swreg263.sw_cdef_luma_primary_strength = luma_pri_strength; + regs->swreg53.sw_cdef_luma_secondary_strength = luma_sec_strength; + regs->swreg264.sw_cdef_chroma_primary_strength = chroma_pri_strength; + regs->swreg53.sw_cdef_chroma_secondary_strength = chroma_sec_strength; + + // tile column buffer; repurpose some encoder specific base + regs->addr_cfg.swreg85.sw_cdef_colbuf_base_lsb = mpp_buffer_get_fd(ctx->filter_mem); + mpp_dev_set_reg_offset(p_hal->dev, 85, ctx->filt_info[CDEF_COL].offset); +} + +void vdpu_av1d_set_lr(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva) +{ + VdpuAv1dRegCtx *ctx = p_hal->reg_ctx; + VdpuAv1dRegSet *regs = ctx->regs; + RK_U16 lr_type = 0; + RK_U16 lr_unit_size = 0; + RK_S32 i = 0; + + for (i = 0; i < 3; i++) { + lr_type |= dxva->loop_filter.frame_restoration_type[i] << (i * 2); + lr_unit_size |= dxva->loop_filter.log2_restoration_unit_size[i] << (i * 2); + } + regs->swreg18.sw_lr_type = lr_type; + regs->swreg19.sw_lr_unit_size = lr_unit_size; + regs->addr_cfg.swreg91.sw_lr_colbuf_base_lsb = mpp_buffer_get_fd(ctx->filter_mem); + mpp_dev_set_reg_offset(p_hal->dev, 91, ctx->filt_info[LR_COL].offset); +} + +void init_scaling_function(RK_U8 scaling_points[][2], RK_U8 num_points, + RK_U8 scaling_lut[]) +{ + RK_S32 i, point; + + if (num_points == 0) { + memset(scaling_lut, 0, 256); + return; + } + + for (i = 0; i < scaling_points[0][0]; i++) + scaling_lut[i] = scaling_points[0][1]; + + for (point = 0; point < num_points - 1; point++) { + RK_S32 x ; + RK_S32 delta_y = scaling_points[point + 1][1] - scaling_points[point][1]; + RK_S32 delta_x = scaling_points[point + 1][0] - scaling_points[point][0]; + RK_S64 delta = + delta_x ? delta_y * ((65536 + (delta_x >> 1)) / delta_x) : 0; + for (x = 0; x < delta_x; x++) { + scaling_lut[scaling_points[point][0] + x] = + scaling_points[point][1] + (RK_S32)((x * delta + 32768) >> 16); + } + } + + for (i = scaling_points[num_points - 1][0]; i < 256; i++) + scaling_lut[i] = scaling_points[num_points - 1][1]; +} + +void vdpu_av1d_set_fgs(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva) +{ + VdpuAv1dRegSet *regs = ctx->regs; + RK_S32 ar_coeffs_y[24]; + RK_S32 ar_coeffs_cb[25]; + RK_S32 ar_coeffs_cr[25]; + RK_S32 luma_grain_block[73][82]; + RK_S32 cb_grain_block[38][44]; + RK_S32 cr_grain_block[38][44]; + RK_S32 ar_coeff_lag; + RK_S32 ar_coeff_shift; + RK_S32 grain_scale_shift; + RK_S32 bitdepth; + RK_S32 grain_center; + RK_S32 grain_min; + RK_S32 grain_max; + RK_S32 i, j; + RK_U8 *ptr = mpp_buffer_get_ptr(ctx->film_grain_mem); + if (!dxva->film_grain.apply_grain) { + regs->swreg7.sw_apply_grain = 0; + // store reset params + // asic_buff->fg_params[asic_buff->out_buffer_i] = dec->fg_params; + return; + } + /* struct Av1FilmGrainParams *fg_params = &dec->fg_params; + if (!dec->update_parameters) { + RK_S32 active_ref = dec->film_grain_params_ref_idx; + RK_S32 index_ref = Av1BufferQueueGetRef(dec_cont->bq, active_ref); + u16 random_seed = fg_params->random_seed; + *fg_params = asic_buff->fg_params[index_ref]; + fg_params->random_seed = random_seed; + } + asic_buff->fg_params[asic_buff->out_buffer_i] = *fg_params;*/ + + // film grain applied on secondary output + // sw_ctrl->sw_apply_grain = dec_cont->pp_enabled ? 1 : 0; + regs->swreg7.sw_num_y_points_b = dxva->film_grain.num_y_points > 0; + regs->swreg7.sw_num_cb_points_b = dxva->film_grain.num_cb_points > 0; + regs->swreg7.sw_num_cr_points_b = dxva->film_grain.num_cr_points > 0; + regs->swreg8.sw_scaling_shift = dxva->film_grain.scaling_shift_minus8 + 8; + if (! dxva->film_grain.chroma_scaling_from_luma) { + regs->swreg28.sw_cb_mult = dxva->film_grain.cb_mult - 128; + regs->swreg28.sw_cb_luma_mult = dxva->film_grain.cb_luma_mult - 128; + regs->swreg28.sw_cb_offset = dxva->film_grain.cb_offset - 256; + regs->swreg29.sw_cr_mult = dxva->film_grain.cr_mult - 128; + regs->swreg29.sw_cr_luma_mult = dxva->film_grain.cr_luma_mult - 128; + regs->swreg29.sw_cr_offset = dxva->film_grain.cr_offset - 256; + } else { + regs->swreg28.sw_cb_mult = 0; + regs->swreg28.sw_cb_luma_mult = 64; + regs->swreg28.sw_cb_offset = 0; + regs->swreg29.sw_cr_mult = 0; + regs->swreg29.sw_cr_luma_mult = 64; + regs->swreg29.sw_cr_offset = 0; + } + regs->swreg7.sw_overlap_flag = dxva->film_grain.overlap_flag; + regs->swreg7.sw_clip_to_restricted_range = dxva->film_grain.clip_to_restricted_range; + regs->swreg7.sw_chroma_scaling_from_luma = dxva->film_grain.chroma_scaling_from_luma; + regs->swreg7.sw_random_seed = dxva->film_grain.grain_seed; + + init_scaling_function(dxva->film_grain.scaling_points_y, dxva->film_grain.num_y_points, + ctx->fgsmem.scaling_lut_y); + + if (dxva->film_grain.chroma_scaling_from_luma) { + memcpy(ctx->fgsmem.scaling_lut_cb, ctx->fgsmem.scaling_lut_y, + sizeof(*ctx->fgsmem.scaling_lut_y) * 256); + memcpy(ctx->fgsmem.scaling_lut_cr, ctx->fgsmem.scaling_lut_y, + sizeof(*ctx->fgsmem.scaling_lut_y) * 256); + } else { + init_scaling_function(dxva->film_grain.scaling_points_cb, + dxva->film_grain.num_cb_points, ctx->fgsmem.scaling_lut_cb); + init_scaling_function(dxva->film_grain.scaling_points_cr, + dxva->film_grain.num_cr_points, ctx->fgsmem.scaling_lut_cr); + } + + + for (i = 0; i < 25; i++) { + if (i < 24) { + ar_coeffs_y[i] = dxva->film_grain.ar_coeffs_y[i] - 128; + } + ar_coeffs_cb[i] = dxva->film_grain.ar_coeffs_cb[i] - 128; + ar_coeffs_cr[i] = dxva->film_grain.ar_coeffs_cr[i] - 128; + } + + ar_coeff_lag = dxva->film_grain.ar_coeff_lag; + ar_coeff_shift = dxva->film_grain.ar_coeff_shift_minus6 + 6; + grain_scale_shift = dxva->film_grain.grain_scale_shift; + bitdepth = dxva->bitdepth; + grain_center = 128 << (bitdepth - 8); + grain_min = 0 - grain_center; + grain_max = (256 << (bitdepth - 8)) - 1 - grain_center; + + GenerateLumaGrainBlock(luma_grain_block, bitdepth, dxva->film_grain.num_y_points, + grain_scale_shift, ar_coeff_lag, ar_coeffs_y, + ar_coeff_shift, grain_min, grain_max, + dxva->film_grain.grain_seed); + + GenerateChromaGrainBlock( + luma_grain_block, cb_grain_block, cr_grain_block, bitdepth, + dxva->film_grain.num_y_points, dxva->film_grain.num_cb_points, + dxva->film_grain.num_cr_points, grain_scale_shift, ar_coeff_lag, ar_coeffs_cb, + ar_coeffs_cr, ar_coeff_shift, grain_min, grain_max, + dxva->film_grain.chroma_scaling_from_luma, dxva->film_grain.grain_seed); + + for (i = 0; i < 64; i++) { + for (j = 0; j < 64; j++) { + ctx->fgsmem.cropped_luma_grain_block[i * 64 + j] = + luma_grain_block[i + 9][j + 9]; + } + } + + for (i = 0; i < 32; i++) { + for (j = 0; j < 32; j++) { + ctx->fgsmem.cropped_chroma_grain_block[i * 64 + 2 * j] = + cb_grain_block[i + 6][j + 6]; + ctx->fgsmem.cropped_chroma_grain_block[i * 64 + 2 * j + 1] = + cr_grain_block[i + 6][j + 6]; + } + } + + memcpy(ptr, &ctx->fgsmem, sizeof(FilmGrainMemory)); + + regs->addr_cfg.swreg94.sw_filmgrain_base_msb = 0; + regs->addr_cfg.swreg95.sw_filmgrain_base_lsb = mpp_buffer_get_fd(ctx->film_grain_mem); + + if (regs->swreg7.sw_apply_grain) AV1D_DBG(AV1D_DBG_LOG, "NOTICE: filmgrain enabled.\n"); +} + +MPP_RET vdpu_av1d_gen_regs(void *hal, HalTaskInfo *task) +{ + MPP_RET ret = MPP_ERR_UNKNOW; + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx; + VdpuAv1dRegSet *regs = ctx->regs; + DXVA_PicParams_AV1 *dxva = (DXVA_PicParams_AV1*)task->dec.syntax.data; + MppFrame mframe; + MppBuffer buffer = NULL; + MppBuffer streambuf = NULL; + RK_U32 height = dxva->height; + RK_U32 width = dxva->width; + RK_U32 hor_stride; + RK_U32 ver_stride; + HalBuf *tile_out_buf; + // RK_U32 bit_depth = dxva->bitdepth; + ctx->width = width; + ctx->height = height; + INP_CHECK(ret, NULL == p_hal); + + ctx->refresh_frame_flags = dxva->refresh_frame_flags; + + if (task->dec.flags.parse_err || + task->dec.flags.ref_err) { + goto __RETURN; + } + + if (p_hal->fast_mode) { + RK_U32 i = 0; + for (i = 0; i < MPP_ARRAY_ELEMS(ctx->reg_buf); i++) { + if (!ctx->reg_buf[i].valid) { + task->dec.reg_index = i; + regs = ctx->reg_buf[i].regs; + ctx->reg_buf[i].valid = 1; + break; + } + } + } + memset(regs, 0, sizeof(*regs)); + + if (!ctx->tile_out_bufs) { + RK_U32 out_w = MPP_ALIGN(4 * width * dxva->bitdepth, 16 * 8) / 8; + RK_U32 num_sbs = ((width + 63) / 64 + 1) * ((height + 63) / 64 + 1); + RK_U32 dir_mvs_size = MPP_ALIGN(num_sbs * 24 * 128 / 8, 16); + RK_U32 out_h = height / 4; + RK_U32 luma_size = out_w * out_h; + RK_U32 chroma_size = luma_size / 2; + + ctx->hor_stride = out_w; + ctx->luma_size = luma_size; + ctx->chroma_size = chroma_size; + ctx->tile_out_size = luma_size + chroma_size + dir_mvs_size + 512; + + if (ctx->tile_out_bufs) { + hal_bufs_deinit(ctx->tile_out_bufs); + ctx->tile_out_bufs = NULL; + } + hal_bufs_init(&ctx->tile_out_bufs); + if (!ctx->tile_out_bufs) { + mpp_err_f("tile out bufs init fail\n"); + goto __RETURN; + } + ctx->tile_out_count = mpp_buf_slot_get_count(p_hal->slots); + hal_bufs_setup(ctx->tile_out_bufs, ctx->tile_out_count, 1, &ctx->tile_out_size); + } + + if (!ctx->filter_mem) { + ret = vdpu_av1d_filtermem_alloc(p_hal, ctx, dxva); + if (!ret) { + mpp_err("filt buffer get fail\n"); + vdpu_av1d_filtermem_release(ctx); + } + } + if (!ctx->buf_tmp) { + RK_U32 size = height * width * 2; + + mpp_buffer_get(p_hal->buf_group, &ctx->buf_tmp, size); + } + + mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_FRAME_PTR, &mframe); + mpp_buf_slot_get_prop(p_hal ->slots, task->dec.output, SLOT_BUFFER, &buffer); + mpp_buf_slot_get_prop(p_hal ->packet_slots, task->dec.input, SLOT_BUFFER, &streambuf); + tile_out_buf = hal_bufs_get_buf(ctx->tile_out_bufs, task->dec.output); + hor_stride = mpp_frame_get_hor_stride(mframe); + ver_stride = mpp_frame_get_ver_stride(mframe); + + ctx->ver_stride = ver_stride; + + p_hal->strm_len = (RK_S32)mpp_packet_get_length(task->dec.input_packet); + + ctx->fbc_en = !!MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe)); + + AV1D_DBG(AV1D_DBG_LOG, "bitdepth %d fmt %d [%d : %d] wxh [%d : %d] uxv [%d : %d]\n", + dxva->bitdepth, mpp_frame_get_fmt(mframe), + dxva->format.subsampling_x, dxva->format.subsampling_y, + ctx->width, ctx->height, + ctx->hor_stride, ctx->ver_stride); + + regs->swreg1.sw_dec_abort_e = 0; + regs->swreg1.sw_dec_e = 1; + regs->swreg1.sw_dec_tile_int_e = 0; + regs->swreg2.sw_dec_clk_gate_e = 1; + + regs->swreg3.sw_dec_mode = 17; // av1 mode + regs->swreg3.sw_skip_mode = dxva->coding.skip_mode; + regs->swreg3.sw_dec_out_ec_byte_word = 0; // word align + regs->swreg3.sw_write_mvs_e = 1; + regs->swreg3.sw_dec_out_ec_bypass = 1; + + regs->swreg5.sw_tempor_mvp_e = dxva->coding.use_ref_frame_mvs; + regs->swreg5.sw_delta_lf_res_log = dxva->loop_filter.delta_lf_res; + regs->swreg5.sw_delta_lf_multi = dxva->loop_filter.delta_lf_multi; + regs->swreg5.sw_delta_lf_present = dxva->loop_filter.delta_lf_present; + regs->swreg5.sw_disable_cdf_update = dxva->coding.disable_cdf_update; + regs->swreg5.sw_allow_warp = dxva->coding.warped_motion; + regs->swreg5.sw_show_frame = dxva->format.show_frame; + regs->swreg5.sw_switchable_motion_mode = dxva->coding.switchable_motion_mode; + regs->swreg5.sw_enable_cdef = dxva->coding.cdef_en; + regs->swreg5.sw_allow_masked_compound = dxva->coding.masked_compound; + regs->swreg5.sw_allow_interintra = dxva->coding.interintra_compound; + regs->swreg5.sw_enable_intra_edge_filter = dxva->coding.intra_edge_filter; + regs->swreg5.sw_allow_filter_intra = dxva->coding.filter_intra; + regs->swreg5.sw_enable_jnt_comp = dxva->coding.jnt_comp; + regs->swreg5.sw_enable_dual_filter = dxva->coding.dual_filter; + regs->swreg5.sw_reduced_tx_set_used = dxva->coding.reduced_tx_set; + regs->swreg5.sw_allow_screen_content_tools = dxva->coding.screen_content_tools; + regs->swreg5.sw_allow_intrabc = dxva->coding.intrabc; + + regs->swreg5.sw_force_interger_mv = dxva->coding.integer_mv; + + vdpu_av1d_set_global_model(p_hal, dxva); + vdpu_av1d_set_tile_info_mem(p_hal, dxva); + + if ((dxva->format.frame_type && (dxva->format.frame_type != AV1_FRAME_INTRA_ONLY)) + || dxva->coding.intrabc) { + vdpu_av1d_set_reference_frames(p_hal, ctx, dxva); + } + vdpu_av1d_set_segmentation(ctx, dxva); + vdpu_av1d_set_loopfilter(p_hal, dxva); + vdpu_av1d_set_picture_dimensions(p_hal, dxva); + vdpu_av1d_set_cdef(p_hal, dxva); + vdpu_av1d_set_lr(p_hal, dxva); + vdpu_av1d_set_fgs(ctx, dxva); + vdpu_av1d_set_prob(p_hal, dxva); + vdpu_av1d_set_tile_info_regs(ctx, dxva); + +#if DUMP_AV1_DATAS/* dump buffer */ + { + char name[128]; + char *path = "/data/video"; + static int g_frame_num = 0; + FILE *fp; + RK_U32 i; + RK_U32 *data; + RK_U32 size; + + data = mpp_buffer_get_ptr(ctx->global_model); + size = MPP_ALIGN(GLOBAL_MODEL_SIZE, 2048); + memset(name, 0, sizeof(name)); + sprintf(name, "%s/global_mode_%d.txt", path, g_frame_num); + fp = fopen(name, "wb"); + for ( i = 0; i < size / 4; i++) + fprintf(fp, "%08x\n", data[i]); + fflush(fp); + fclose(fp); + + data = mpp_buffer_get_ptr(ctx->tile_info); + size = AV1_TILE_INFO_SIZE; + memset(name, 0, sizeof(name)); + sprintf(name, "%s/tile_info_%d.txt", path, g_frame_num); + fp = fopen(name, "wb"); + for ( i = 0; i < size / 4; i++) + fprintf(fp, "%08x\n", data[i]); + fflush(fp); + fclose(fp); + + data = mpp_buffer_get_ptr(streambuf);// + (dxva->frame_tag_size & (~0xf)); + size = MPP_ALIGN(p_hal->strm_len, 128);//mpp_buffer_get_size(streambuf); + memset(name, 0, sizeof(name)); + sprintf(name, "%s/stream_%d.txt", path, g_frame_num); + fp = fopen(name, "wb"); + for ( i = 0; i < size / 4; i++) + fprintf(fp, "%08x\n", data[i]); + fflush(fp); + fclose(fp); + + data = mpp_buffer_get_ptr(ctx->film_grain_mem); + size = MPP_ALIGN(sizeof(AV1FilmGrainMemory), 2048); + memset(name, 0, sizeof(name)); + sprintf(name, "%s/film_grain_mem_%d.txt", path, g_frame_num); + fp = fopen(name, "wb"); + for ( i = 0; i < size / 4; i++) + fprintf(fp, "%08x\n", data[i]); + fflush(fp); + fclose(fp); + + data = mpp_buffer_get_ptr(ctx->prob_tbl_base); + size = MPP_ALIGN(sizeof(AV1CDFs), 2048); + memset(name, 0, sizeof(name)); + sprintf(name, "%s/prob_tbl_%d.txt", path, g_frame_num); + fp = fopen(name, "wb"); + for ( i = 0; i < size / 4; i++) + fprintf(fp, "%08x\n", data[i]); + fflush(fp); + fclose(fp); + + data = mpp_buffer_get_ptr(ctx->prob_tbl_out_base); + size = MPP_ALIGN(sizeof(AV1CDFs), 2048); + memset(name, 0, sizeof(name)); + sprintf(name, "%s/prob_tbl_out_%d.txt", path, g_frame_num); + fp = fopen(name, "wb"); + for ( i = 0; i < size / 4; i++) + fprintf(fp, "%08x\n", data[i]); + fflush(fp); + fclose(fp); + + g_frame_num ++; + } +#endif + + regs->swreg7.sw_blackwhite_e = dxva->format.mono_chrome; + regs->swreg7.sw_clip_to_restricted_range = dxva->film_grain.clip_to_restricted_range; + regs->swreg7.sw_delta_q_res_log = dxva->quantization.delta_q_res; + regs->swreg7.sw_delta_q_present = dxva->quantization.delta_q_present; + + regs->swreg8.sw_idr_pic_e = !dxva->format.frame_type; + regs->swreg8.sw_quant_base_qindex = dxva->quantization.base_qindex; + regs->swreg8.sw_bit_depth_y_minus8 = dxva->bitdepth - 8; + regs->swreg8.sw_bit_depth_c_minus8 = dxva->bitdepth - 8; + + regs->swreg11.sw_mcomp_filt_type = dxva->interp_filter; + regs->swreg11.sw_high_prec_mv_e = dxva->coding.high_precision_mv; + regs->swreg11.sw_comp_pred_mode = dxva->coding.reference_mode ? 2 : 0; + regs->swreg11.sw_transform_mode = dxva->coding.tx_mode; + regs->swreg12.sw_max_cb_size = dxva->coding.use_128x128_superblock ? 7 : 6;; + regs->swreg12.sw_min_cb_size = 3; + + /* unused in comdel */ + regs->swreg12.sw_av1_comp_pred_fixed_ref = 0; + regs->swreg13.sw_comp_pred_var_ref0_av1 = 0; + regs->swreg13.sw_comp_pred_var_ref1_av1 = 0; + regs->swreg14.sw_filt_level_seg0 = 0; + regs->swreg15.sw_filt_level_seg1 = 0; + regs->swreg16.sw_filt_level_seg2 = 0; + regs->swreg17.sw_filt_level_seg3 = 0; + regs->swreg18.sw_filt_level_seg4 = 0; + regs->swreg19.sw_filt_level_seg5 = 0; + regs->swreg31.sw_filt_level_seg6 = 0; + regs->swreg32.sw_filt_level_seg7 = 0; + + + regs->swreg13.sw_qp_delta_y_dc_av1 = dxva->quantization.y_dc_delta_q; + regs->swreg13.sw_qp_delta_ch_dc_av1 = dxva->quantization.u_dc_delta_q; + regs->swreg13.sw_qp_delta_ch_ac_av1 = dxva->quantization.u_ac_delta_q; + regs->swreg47.sw_qmlevel_y = dxva->quantization.qm_y; + regs->swreg48.sw_qmlevel_u = dxva->quantization.qm_u; + regs->swreg49.sw_qmlevel_v = dxva->quantization.qm_v; + + regs->swreg13.sw_lossless_e = dxva->coded_lossless; + regs->swreg28.sw_quant_delta_v_dc = dxva->quantization.v_dc_delta_q; + regs->swreg29.sw_quant_delta_v_ac = dxva->quantization.v_ac_delta_q; + + regs->swreg31.sw_skip_ref0 = dxva->skip_ref0 ? dxva->skip_ref0 : 1; + regs->swreg32.sw_skip_ref1 = dxva->skip_ref1 ? dxva->skip_ref1 : 1; + + /*input out put buf cfg*/ + { + // RK_U32 out_w = MPP_ALIGN(4 * width * bit_depth, 128) / 8; + // RK_U32 out_h = height / 4; + // RK_U32 y_stride = out_w * out_h; + // RK_U32 uv_stride = y_stride / 2; + + RK_U32 y_stride = ctx->luma_size; + RK_U32 uv_stride = y_stride / 2; + RK_U32 mv_offset = y_stride + uv_stride + 64; + RK_U32 offset = (dxva->frame_tag_size & (~0xf)); + + regs->addr_cfg.swreg65.sw_dec_out_ybase_lsb = mpp_buffer_get_fd(tile_out_buf->buf[0]);//mpp_buffer_get_fd(buffer); + regs->addr_cfg.swreg99.sw_dec_out_cbase_lsb = mpp_buffer_get_fd(tile_out_buf->buf[0]); + mpp_dev_set_reg_offset(p_hal->dev, 99, y_stride); + regs->addr_cfg.swreg133.sw_dec_out_dbase_lsb = mpp_buffer_get_fd(tile_out_buf->buf[0]); + mpp_dev_set_reg_offset(p_hal->dev, 133, mv_offset); + + /* if (ctx->fbc_en) { + regs->swreg190.sw_dec_out_tybase_lsb = 0;// TODO: + regs->swreg224.sw_dec_out_tcbase_lsb = 0;// TODO: + }*/ + + regs->swreg258.sw_strm_buffer_len = MPP_ALIGN(p_hal->strm_len, 128);// + regs->swreg5.sw_strm_start_bit = (dxva->frame_tag_size & 0xf) * 8; // bit start to decode + regs->swreg6.sw_stream_len = MPP_ALIGN(p_hal->strm_len, 128);//p_hal->strm_len - offset; + regs->swreg259.sw_strm_start_offset = 0; + regs->addr_cfg.swreg168.sw_stream_base_msb = 0; + regs->addr_cfg.swreg169.sw_stream_base_lsb = mpp_buffer_get_fd(streambuf); + mpp_dev_set_reg_offset(p_hal->dev, 169, offset); + + AV1D_DBG(AV1D_DBG_LOG, "stream len %d\n", p_hal->strm_len); + AV1D_DBG(AV1D_DBG_LOG, "stream offset %d\n", offset); + AV1D_DBG(AV1D_DBG_LOG, "stream tag_size %d\n", dxva->frame_tag_size); + AV1D_DBG(AV1D_DBG_LOG, "stream start_bit %d\n", regs->swreg5.sw_strm_start_bit); + } + regs->swreg314.sw_dec_alignment = 64; + + // regs->addr_cfg.swreg86.sw_cdef_left_colbuf_base_msb = 0;// TODO: + // regs->addr_cfg.swreg87.sw_cdef_left_colbuf_base_lsb = 0;// TODO: + // regs->addr_cfg.swreg92.sw_superres_left_colbuf_base_msb = 0;// TODO: + // regs->addr_cfg.swreg93.sw_superres_left_colbuf_base_lsb = 0;// TODO: + // regs->addr_cfg.swreg96.sw_lr_left_colbuf_base_msb = 0;// TODO: + // regs->addr_cfg.swreg97.sw_lr_left_colbuf_base_lsb = 0;// TODO: + // regs->addr_cfg.swreg174.sw_mc_sync_curr_base_msb = 0;// TODO: + regs->addr_cfg.swreg175.sw_mc_sync_curr_base_lsb = mpp_buffer_get_fd(ctx->tile_buf);// TODO: + // regs->addr_cfg.swreg176.sw_mc_sync_left_base_msb = 0;// TODO: + regs->addr_cfg.swreg177.sw_mc_sync_left_base_lsb = mpp_buffer_get_fd(ctx->tile_buf);// TODO: + // regs->addr_cfg.swreg114.sw_dec_left_vert_filt_base_msb = 0;// TODO: + // regs->addr_cfg.swreg115.sw_dec_left_vert_filt_base_lsb = 0;// TODO: + // regs->addr_cfg.swreg116.sw_dec_left_bsd_ctrl_base_msb = 0;// TODO: + // regs->addr_cfg.swreg117.sw_dec_left_bsd_ctrl_base_lsb = 0;// TODO: + + regs->swreg55.sw_apf_disable = 0; + regs->swreg55.sw_apf_threshold = 8; + regs->swreg58.sw_dec_buswidth = 2; + regs->swreg58.sw_dec_max_burst = 16; + regs->swreg266.sw_error_conceal_e = 0; + regs->swreg265.sw_axi_rd_ostd_threshold = 64; + regs->swreg265.sw_axi_wr_ostd_threshold = 64; + + regs->swreg318.sw_ext_timeout_cycles = 0xfffffff; + regs->swreg318.sw_ext_timeout_override_e = 1; + regs->swreg319.sw_timeout_cycles = 0xfffffff; + regs->swreg319.sw_timeout_override_e = 1; + + /* pp cfg */ + regs->vdpu_av1d_pp_cfg.swreg320.sw_pp_out_e = 1; + regs->vdpu_av1d_pp_cfg.swreg322.sw_pp_in_format = 0; + regs->vdpu_av1d_pp_cfg.swreg394.sw_pp0_dup_hor = 1; + regs->vdpu_av1d_pp_cfg.swreg394.sw_pp0_dup_ver = 1; + regs->vdpu_av1d_pp_cfg.swreg331.sw_pp_in_height = height / 2; + regs->vdpu_av1d_pp_cfg.swreg331.sw_pp_in_width = width / 2; + regs->vdpu_av1d_pp_cfg.swreg332.sw_pp_out_height = height; + regs->vdpu_av1d_pp_cfg.swreg332.sw_pp_out_width = width; + regs->vdpu_av1d_pp_cfg.swreg329.sw_pp_out_y_stride = hor_stride; + regs->vdpu_av1d_pp_cfg.swreg329.sw_pp_out_c_stride = hor_stride; + + // regs->vdpu_av1d_pp_cfg.swreg337.sw_pp_in_y_stride = hor_stride; + // regs->vdpu_av1d_pp_cfg.swreg337.sw_pp_in_c_stride = hor_stride; + if (ctx->fbc_en) { + regs->swreg58.sw_dec_axi_wd_id_e = 1; + regs->swreg58.sw_dec_axi_rd_id_e = 1; + regs->vdpu_av1d_pp_cfg.swreg320.sw_pp_out_tile_e = 1; + regs->vdpu_av1d_pp_cfg.swreg321.sw_pp_tile_size = 2; + + RK_U32 vir_left = 0, vir_right = 0, vir_top = 0, vir_bottom = 0; + vir_left = 0; + if (((vir_left + width) % 16)) + vir_right = 16 - ((vir_left + width) % 16); + else + vir_right = 0; + + vir_top = 8; + + if (((vir_top + height) % 16)) + vir_bottom = 16 - ((vir_top + height) % 16); + else + vir_bottom = 0; + + regs->vdpu_av1d_pp_cfg.swreg503.sw_pp0_virtual_top = vir_top; + regs->vdpu_av1d_pp_cfg.swreg503.sw_pp0_virtual_left = vir_left; + regs->vdpu_av1d_pp_cfg.swreg503.sw_pp0_virtual_bottom = vir_bottom; + regs->vdpu_av1d_pp_cfg.swreg503.sw_pp0_virtual_right = vir_right; + regs->vdpu_av1d_pp_cfg.swreg326.sw_pp_out_lu_base_lsb = mpp_buffer_get_fd(buffer); + regs->vdpu_av1d_pp_cfg.swreg328.sw_pp_out_ch_base_lsb = mpp_buffer_get_fd(buffer); + regs->vdpu_av1d_pp_cfg.swreg505.sw_pp0_afbc_tile_base_lsb = mpp_buffer_get_fd(buffer); + } else { + RK_U32 out_w = hor_stride; + RK_U32 out_h = ver_stride; + RK_U32 y_stride = out_w * out_h; + regs->vdpu_av1d_pp_cfg.swreg322.sw_pp_out_format = 3; + regs->vdpu_av1d_pp_cfg.swreg326.sw_pp_out_lu_base_lsb = mpp_buffer_get_fd(buffer); + regs->vdpu_av1d_pp_cfg.swreg328.sw_pp_out_ch_base_lsb = mpp_buffer_get_fd(buffer); + mpp_dev_set_reg_offset(p_hal->dev, 328, y_stride); + } + + /*RK_U32 i = 0; + for (i = 0; i < sizeof(VdpuAv1dRegSet) / sizeof(RK_U32); i++) + mpp_log("regs[%04d]=%08X\n", i, ((RK_U32 *)regs)[i]);*/ + + + //TODO: + +__RETURN: + return ret = MPP_OK; +} + +MPP_RET vdpu_av1d_start(void *hal, HalTaskInfo *task) +{ + MPP_RET ret = MPP_ERR_UNKNOW; + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + INP_CHECK(ret, NULL == p_hal); + if (task->dec.flags.parse_err || + task->dec.flags.ref_err) { + goto __RETURN; + } + + VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx; + VdpuAv1dRegSet *regs = p_hal->fast_mode ? + reg_ctx->reg_buf[task->dec.reg_index].regs : + reg_ctx->regs; + MppDev dev = p_hal->dev; +#if DUMP_AV1_DATAS + { + RK_U32 i = 0; + RK_U32 *p = (RK_U32*)regs; + char fname[128]; + FILE *fp_in = NULL; + static RK_U32 g_frame_no = 0; + + sprintf(fname, "/data/video/reg_%d_in.txt", g_frame_no++); + fp_in = fopen(fname, "wb"); + for (i = 0; i < sizeof(*regs) / 4; i ++ ) { + fprintf(fp_in, "reg[%3d] = %08x\n", i, *p); + AV1D_LOG("reg[%3d] = %08x", i, *p); + p++; + } + fflush(fp_in); + fclose(fp_in); + } +#endif + do { + MppDevRegWrCfg wr_cfg; + MppDevRegRdCfg rd_cfg; + + wr_cfg.reg = regs; + wr_cfg.size = sizeof(*regs); + wr_cfg.offset = 0; + ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg); + if (ret) { + mpp_err_f("set register write failed %d\n", ret); + break; + } + + rd_cfg.reg = regs; + rd_cfg.size = sizeof(*regs); + rd_cfg.offset = 0; + + ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg); + if (ret) { + mpp_err_f("set register read failed %d\n", ret); + break; + } + /* send request to hardware */ + ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL); + if (ret) { + mpp_err_f("send cmd failed %d\n", ret); + break; + } + } while (0); + +__RETURN: + return ret = MPP_OK; +} + +MPP_RET vdpu_av1d_wait(void *hal, HalTaskInfo *task) +{ + MPP_RET ret = MPP_ERR_UNKNOW; + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + + INP_CHECK(ret, NULL == p_hal); + VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx; + VdpuAv1dRegSet *p_regs = p_hal->fast_mode ? + reg_ctx->reg_buf[task->dec.reg_index].regs : + reg_ctx->regs; + + if (task->dec.flags.parse_err || + task->dec.flags.ref_err) { + goto __SKIP_HARD; + } + + ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL); + if (ret) + mpp_err_f("poll cmd failed %d\n", ret); +#if DUMP_AV1_DATAS + { + char fname[128]; + FILE *fp_in = NULL; + static RK_U32 g_frame_no = 0; + RK_U32 *p = (RK_U32*)p_regs; + RK_U32 i; + + sprintf(fname, "/data/video/reg_%d_out.txt", g_frame_no++); + fp_in = fopen(fname, "wb"); + for (i = 0; i < sizeof(*p_regs) / 4; i ++ ) { + fprintf(fp_in, "reg[%3d] = %08x\n", i, *p); + AV1D_LOG("reg[%3d] = %08x", i, *p); + p++; + } + fflush(fp_in); + fclose(fp_in); + } +#endif + +__SKIP_HARD: + if (p_hal->dec_cb) { + DecCbHalDone m_ctx; + RK_U32 *prob_out = (RK_U32*)mpp_buffer_get_ptr(reg_ctx->prob_tbl_out_base); + + m_ctx.task = mpp_buffer_get_ptr(reg_ctx->prob_tbl_out_base);//(void *)&task->dec; + m_ctx.regs = (RK_U32 *)prob_out; + if (!p_regs->swreg1.sw_dec_rdy_int/* decode err */) + m_ctx.hard_err = 1; + else + m_ctx.hard_err = 0; + + mpp_callback(p_hal->dec_cb, &m_ctx); + } + if (p_hal->fast_mode) + reg_ctx->reg_buf[task->dec.reg_index].valid = 0; + + (void)task; +__RETURN: + return ret = MPP_OK; +} + +MPP_RET vdpu_av1d_reset(void *hal) +{ + MPP_RET ret = MPP_ERR_UNKNOW; + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + + INP_CHECK(ret, NULL == p_hal); + + +__RETURN: + return ret = MPP_OK; +} + +MPP_RET vdpu_av1d_flush(void *hal) +{ + MPP_RET ret = MPP_ERR_UNKNOW; + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + + INP_CHECK(ret, NULL == p_hal); + +__RETURN: + return ret = MPP_OK; +} + +MPP_RET vdpu_av1d_control(void *hal, MpiCmd cmd_type, void *param) +{ + MPP_RET ret = MPP_ERR_UNKNOW; + Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; + + INP_CHECK(ret, NULL == p_hal); + + switch ((MpiCmd)cmd_type) { + case MPP_DEC_SET_FRAME_INFO: { + MppFrameFormat fmt = mpp_frame_get_fmt((MppFrame)param); + RK_U32 imgwidth = mpp_frame_get_width((MppFrame)param); + RK_U32 imgheight = mpp_frame_get_height((MppFrame)param); + + AV1D_DBG(AV1D_DBG_LOG, "control info: fmt %d, w %d, h %d\n", fmt, imgwidth, imgheight); + if ((fmt & MPP_FRAME_FMT_COLOR_MASK) == MPP_FMT_YUV422SP) { + mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align_422); + } + break; + } + case MPP_DEC_SET_OUTPUT_FORMAT: { + + } break; + default: + break; + } + +__RETURN: + return ret = MPP_OK; +} + +const MppHalApi hal_av1d_vdpu = { + .name = "av1d_vdpu", + .type = MPP_CTX_DEC, + .coding = MPP_VIDEO_CodingAV1, + .ctx_size = sizeof(VdpuAv1dRegCtx), + .flag = 0, + .init = vdpu_av1d_init, + .deinit = vdpu_av1d_deinit, + .reg_gen = vdpu_av1d_gen_regs, + .start = vdpu_av1d_start, + .wait = vdpu_av1d_wait, + .reset = vdpu_av1d_reset, + .flush = vdpu_av1d_flush, + .control = vdpu_av1d_control, +}; diff --git a/mpp/hal/vpu/av1d/hal_av1d_vdpu.h b/mpp/hal/vpu/av1d/hal_av1d_vdpu.h new file mode 100644 index 00000000..abefaf8e --- /dev/null +++ b/mpp/hal/vpu/av1d/hal_av1d_vdpu.h @@ -0,0 +1,32 @@ +/* + * Copyright 2020 Rockchip Electronics Co. LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_AV1D_VDPU_H__ +#define __HAL_AV1D_VDPU_H__ + +#include "mpp_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern const MppHalApi hal_av1d_vdpu; + +#ifdef __cplusplus +} +#endif + +#endif /* __HAL_H264D_VDPU34X_H__ */ \ No newline at end of file diff --git a/mpp/hal/vpu/av1d/hal_av1d_vdpu_reg.h b/mpp/hal/vpu/av1d/hal_av1d_vdpu_reg.h new file mode 100644 index 00000000..62a1c198 --- /dev/null +++ b/mpp/hal/vpu/av1d/hal_av1d_vdpu_reg.h @@ -0,0 +1,2442 @@ +/* + * Copyright 2020 Rockchip Electronics Co. LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __HAL_AV1D_VDPU_REG_H__ +#define __HAL_AV1D_VDPU_REG_H__ + +#include "mpp_device.h" + +/* swreg64 - swreg183 */ +typedef struct VdpuAv1dBase_t { + struct { + RK_U32 sw_dec_out_ybase_msb : 32; + } swreg64; + + struct { + RK_U32 sw_dec_out_ybase_lsb : 32; + } swreg65; + + struct { + RK_U32 sw_refer0_ybase_msb : 32; + } swreg66; + + struct { + RK_U32 sw_refer0_ybase_lsb : 32; + } swreg67; + + struct { + RK_U32 sw_refer1_ybase_msb : 32; + } swreg68; + + struct { + RK_U32 sw_refer1_ybase_lsb : 32; + } swreg69; + + struct { + RK_U32 sw_refer2_ybase_msb : 32; + } swreg70; + + struct { + RK_U32 sw_refer2_ybase_lsb : 32; + } swreg71; + + struct { + RK_U32 sw_refer3_ybase_msb : 32; + } swreg72; + + struct { + RK_U32 sw_refer3_ybase_lsb : 32; + } swreg73; + + struct { + RK_U32 sw_refer4_ybase_msb : 32; + } swreg74; + + struct { + RK_U32 sw_refer4_ybase_lsb : 32; + } swreg75; + + struct { + RK_U32 sw_refer5_ybase_msb : 32; + } swreg76; + + struct { + RK_U32 sw_refer5_ybase_lsb : 32; + } swreg77; + + struct { + RK_U32 sw_refer6_ybase_msb : 32; + } swreg78; + + struct { + RK_U32 sw_refer6_ybase_lsb : 32; + } swreg79; + + struct { + RK_U32 sw_segment_read_base_msb : 32; + } swreg80; + + struct { + RK_U32 sw_segment_read_base_lsb : 32; + } swreg81; + + struct { + RK_U32 sw_global_model_base_msb : 32; + } swreg82; + + struct { + RK_U32 sw_global_model_base_lsb : 32; + } swreg83; + + struct { + RK_U32 sw_cdef_colbuf_base_msb : 32; + } swreg84; + + struct { + RK_U32 sw_cdef_colbuf_base_lsb : 32; + } swreg85; + + struct { + RK_U32 sw_cdef_left_colbuf_base_msb : 32; + } swreg86; + + struct { + RK_U32 sw_cdef_left_colbuf_base_lsb : 32; + } swreg87; + + struct { + RK_U32 sw_superres_colbuf_base_msb : 32; + } swreg88; + + struct { + RK_U32 sw_superres_colbuf_base_lsb : 32; + } swreg89; + + struct { + RK_U32 sw_lr_colbuf_base_msb : 32; + } swreg90; + + struct { + RK_U32 sw_lr_colbuf_base_lsb : 32; + } swreg91; + + struct { + RK_U32 sw_superres_left_colbuf_base_msb : 32; + } swreg92; + + struct { + RK_U32 sw_superres_left_colbuf_base_lsb : 32; + } swreg93; + + struct { + RK_U32 sw_filmgrain_base_msb : 32; + } swreg94; + + struct { + RK_U32 sw_filmgrain_base_lsb : 32; + } swreg95; + + struct { + RK_U32 sw_lr_left_colbuf_base_msb : 32; + } swreg96; + + struct { + RK_U32 sw_lr_left_colbuf_base_lsb : 32; + } swreg97; + + struct { + RK_U32 sw_dec_out_cbase_msb : 32; + } swreg98; + + struct { + RK_U32 sw_dec_out_cbase_lsb : 32; + } swreg99; + + struct { + RK_U32 sw_refer0_cbase_msb : 32; + } swreg100; + + struct { + RK_U32 sw_refer0_cbase_lsb : 32; + } swreg101; + + struct { + RK_U32 sw_refer1_cbase_msb : 32; + } swreg102; + + struct { + RK_U32 sw_refer1_cbase_lsb : 32; + } swreg103; + + struct { + RK_U32 sw_refer2_cbase_msb : 32; + } swreg104; + + struct { + RK_U32 sw_refer2_cbase_lsb : 32; + } swreg105; + + struct { + RK_U32 sw_refer3_cbase_msb : 32; + } swreg106; + + struct { + RK_U32 sw_refer3_cbase_lsb : 32; + } swreg107; + + struct { + RK_U32 sw_refer4_cbase_msb : 32; + } swreg108; + + struct { + RK_U32 sw_refer4_cbase_lsb : 32; + } swreg109; + + struct { + RK_U32 sw_refer5_cbase_msb : 32; + } swreg110; + + struct { + RK_U32 sw_refer5_cbase_lsb : 32; + } swreg111; + + struct { + RK_U32 sw_refer6_cbase_msb : 32; + } swreg112; + + struct { + RK_U32 sw_refer6_cbase_lsb : 32; + } swreg113; + + struct { + RK_U32 sw_dec_left_vert_filt_base_msb : 32; + } swreg114; + + struct { + RK_U32 sw_dec_left_vert_filt_base_lsb : 32; + } swreg115; + + struct { + RK_U32 sw_dec_left_bsd_ctrl_base_msb : 32; + } swreg116; + + struct { + RK_U32 sw_dec_left_bsd_ctrl_base_lsb : 32; + } swreg117; + + RK_U32 reserved_118_131[14]; + struct { + RK_U32 sw_dec_out_dbase_msb : 32; + } swreg132; + + struct { + RK_U32 sw_dec_out_dbase_lsb : 32; + } swreg133; + + struct { + RK_U32 sw_refer0_dbase_msb : 32; + } swreg134; + + struct { + RK_U32 sw_refer0_dbase_lsb : 32; + } swreg135; + + struct { + RK_U32 sw_refer1_dbase_msb : 32; + } swreg136; + + struct { + RK_U32 sw_refer1_dbase_lsb : 32; + } swreg137; + + struct { + RK_U32 sw_refer2_dbase_msb : 32; + } swreg138; + + struct { + RK_U32 sw_refer2_dbase_lsb : 32; + } swreg139; + + struct { + RK_U32 sw_refer3_dbase_msb : 32; + } swreg140; + + struct { + RK_U32 sw_refer3_dbase_lsb : 32; + } swreg141; + + struct { + RK_U32 sw_refer4_dbase_msb : 32; + } swreg142; + + struct { + RK_U32 sw_refer4_dbase_lsb : 32; + } swreg143; + + struct { + RK_U32 sw_refer5_dbase_msb : 32; + } swreg144; + + struct { + RK_U32 sw_refer5_dbase_lsb : 32; + } swreg145; + + struct { + RK_U32 sw_refer6_dbase_msb : 32; + } swreg146; + + struct { + RK_U32 sw_refer6_dbase_lsb : 32; + } swreg147; + + RK_U32 reserved_148_165[18]; + struct { + RK_U32 sw_tile_base_msb : 32; + } swreg166; + + struct { + RK_U32 sw_tile_base_lsb : 32; + } swreg167; + + struct { + RK_U32 sw_stream_base_msb : 32; + } swreg168; + + struct { + RK_U32 sw_stream_base_lsb : 32; + } swreg169; + + struct { + RK_U32 sw_prob_tab_out_base_msb : 32; + } swreg170; + + struct { + RK_U32 sw_prob_tab_out_base_lsb : 32; + } swreg171; + + struct { + RK_U32 sw_prob_tab_base_msb : 32; + } swreg172; + + struct { + RK_U32 sw_prob_tab_base_lsb : 32; + } swreg173; + + struct { + RK_U32 sw_mc_sync_curr_base_msb : 32; + } swreg174; + + struct { + RK_U32 sw_mc_sync_curr_base_lsb : 32; + } swreg175; + + struct { + RK_U32 sw_mc_sync_left_base_msb : 32; + } swreg176; + + struct { + RK_U32 sw_mc_sync_left_base_lsb : 32; + } swreg177; + + struct { + RK_U32 sw_dec_vert_filt_base_msb : 32; + } swreg178; + + struct { + RK_U32 sw_dec_vert_filt_base_lsb : 32; + } swreg179; + + RK_U32 reserved_180_181[2]; + struct { + RK_U32 sw_dec_bsd_ctrl_base_msb : 32; + } swreg182; + + struct { + RK_U32 sw_dec_bsd_ctrl_base_lsb : 32; + } swreg183; +} VdpuAv1dBase; + +/* swreg320 - swreg511 */ +typedef struct VdpuAv1dPPCfg_t { + + struct { + RK_U32 sw_pp_out_e : 1; + RK_U32 sw_pp_cr_first : 1; + RK_U32 sw_pp_out_mode : 1; + RK_U32 sw_pp_out_tile_e : 1; + RK_U32 sw_pp_status : 4; + RK_U32 sw_pp_in_blk_size : 3; + RK_U32 sw_pp_out_p010_fmt : 2; + RK_U32 sw_pp_out_rgb_fmt : 5; + RK_U32 sw_rgb_range_max : 12; + RK_U32 sw_pp_rgb_planar : 1; + RK_U32 reserved0 : 1; + } swreg320; + + struct { + RK_U32 sw_rgb_range_min : 9; + RK_U32 sw_pp_tile_size : 2; + RK_U32 reserved0 : 5; + RK_U32 sw_pp_in_swap : 4; + RK_U32 sw_pp_out_swap : 4; + RK_U32 sw_pp_in_a1_swap : 4; + RK_U32 sw_pp_in_a2_swap : 4; + } swreg321; + + struct { + RK_U32 sw_scale_hratio : 18; + RK_U32 sw_pp_out_format : 5; + RK_U32 sw_ver_scale_mode : 2; + RK_U32 sw_hor_scale_mode : 2; + RK_U32 sw_pp_in_format : 5; + } swreg322; + + struct { + RK_U32 sw_scale_wratio : 18; + RK_U32 sw_rangemap_coef_c : 5; + RK_U32 sw_rangemap_coef_y : 5; + RK_U32 sw_pp_vc1_adv_e : 1; + RK_U32 sw_ycbcr_range : 1; + RK_U32 sw_rangemap_c_e : 1; + RK_U32 sw_rangemap_y_e : 1; + } swreg323; + + struct { + RK_U32 sw_hscale_invra : 16; + RK_U32 sw_wscale_invra : 16; + } swreg324; + + struct { + RK_U32 sw_pp_out_lu_base_msb : 32; + } swreg325; + + struct { + RK_U32 sw_pp_out_lu_base_lsb : 32; + } swreg326; + + struct { + RK_U32 sw_pp_out_ch_base_msb : 32; + } swreg327; + + struct { + RK_U32 sw_pp_out_ch_base_lsb : 32; + } swreg328; + + struct { + RK_U32 sw_pp_out_c_stride : 16; + RK_U32 sw_pp_out_y_stride : 16; + } swreg329; + + struct { + RK_U32 sw_crop_starty : 13; + RK_U32 sw_rotation_mode : 2; + RK_U32 reserved0 : 1; + RK_U32 sw_crop_startx : 13; + RK_U32 sw_flip_mode : 2; + RK_U32 sw_pad_sel : 1; + } swreg330; + + struct { + RK_U32 sw_pp_in_height : 16; + RK_U32 sw_pp_in_width : 16; + } swreg331; + + struct { + RK_U32 sw_pp_out_height : 16; + RK_U32 sw_pp_out_width : 16; + } swreg332; + + struct { + RK_U32 sw_pp_out_lu_bot_base_msb : 32; + } swreg333; + + struct { + RK_U32 sw_pp_out_lu_bot_base_lsb : 32; + } swreg334; + + struct { + RK_U32 sw_pp_crop2_starty : 13; + RK_U32 reserved0 : 3; + RK_U32 sw_pp_crop2_startx : 13; + RK_U32 reserved1 : 3; + // RK_U32 sw_pp_out_ch_bot_base_msb : 32; + } swreg335; + + struct { + RK_U32 sw_pp_crop2_out_height : 16; + RK_U32 sw_pp_crop2_out_width : 16; + // RK_U32 sw_pp_out_ch_bot_base_lsb : 32; + } swreg336; + + struct { + RK_U32 sw_pp_in_c_stride : 16; + RK_U32 sw_pp_in_y_stride : 16; + } swreg337; + + struct { + RK_U32 sw_pp_in_lu_base_msb : 32; + } swreg338; + + struct { + RK_U32 sw_pp_in_lu_base_lsb : 32; + } swreg339; + + struct { + RK_U32 sw_pp_in_ch_base_msb : 32; + } swreg340; + + struct { + RK_U32 sw_pp_in_ch_base_lsb : 32; + } swreg341; + + struct { + RK_U32 sw_pp1_out_e : 1; + RK_U32 sw_pp1_cr_first : 1; + RK_U32 sw_pp1_out_mode : 1; + RK_U32 sw_pp1_out_tile_e : 1; + RK_U32 reserved0 : 7; + RK_U32 sw_pp1_out_p010_fmt : 2; + RK_U32 sw_pp1_out_rgb_fmt : 5; + RK_U32 reserved1 : 12; + RK_U32 sw_pp1_rgb_planar : 1; + RK_U32 reserved2 : 1; + } swreg342; + + struct { + RK_U32 reserved0 : 9; + RK_U32 sw_pp1_tile_size : 2; + RK_U32 reserved1 : 9; + RK_U32 sw_pp1_out_swap : 4; + RK_U32 reserved2 : 8; + } swreg343; + + struct { + RK_U32 sw_pp1_scale_hratio : 18; + RK_U32 sw_pp1_out_format : 5; + RK_U32 sw_pp1_ver_scale_mode : 2; + RK_U32 sw_pp1_hor_scale_mode : 2; + RK_U32 reserved0 : 5; + } swreg344; + + struct { + RK_U32 sw_pp1_scale_wratio : 18; + RK_U32 reserved0 : 14; + } swreg345; + + struct { + RK_U32 sw_pp1_hscale_invra : 16; + RK_U32 sw_pp1_wscale_invra : 16; + } swreg346; + + struct { + RK_U32 sw_pp1_out_lu_base_msb : 32; + } swreg347; + + struct { + RK_U32 sw_pp1_out_lu_base_lsb : 32; + } swreg348; + + struct { + RK_U32 sw_pp1_out_ch_base_msb : 32; + } swreg349; + + struct { + RK_U32 sw_pp1_out_ch_base_lsb : 32; + } swreg350; + + struct { + RK_U32 sw_pp1_out_c_stride : 16; + RK_U32 sw_pp1_out_y_stride : 16; + } swreg351; + + struct { + RK_U32 sw_pp1_crop_starty : 13; + RK_U32 sw_pp1_rotation_mode : 2; + RK_U32 reserved0 : 1; + RK_U32 sw_pp1_crop_startx : 13; + RK_U32 sw_pp1_flip_mode : 2; + RK_U32 sw_pp1_pad_sel : 1; + } swreg352; + + struct { + RK_U32 sw_pp1_in_height : 16; + RK_U32 sw_pp1_in_width : 16; + } swreg353; + + struct { + RK_U32 sw_pp1_out_height : 16; + RK_U32 sw_pp1_out_width : 16; + } swreg354; + + struct { + RK_U32 sw_pp1_out_lu_bot_base_msb : 32; + } swreg355; + + struct { + RK_U32 sw_pp1_out_lu_bot_base_lsb : 32; + } swreg356; + + struct { + RK_U32 sw_pp1_crop2_starty : 13; + RK_U32 reserved0 : 3; + RK_U32 sw_pp1_crop2_startx : 13; + RK_U32 reserved1 : 3; + // RK_U32 sw_pp1_out_ch_bot_base_msb : 32; + } swreg357; + + struct { + RK_U32 sw_pp1_crop2_out_height : 16; + RK_U32 sw_pp1_crop2_out_width : 16; + // RK_U32 sw_pp1_out_ch_bot_base_lsb : 32; + } swreg358; + + struct { + RK_U32 sw_pp2_out_e : 1; + RK_U32 sw_pp2_cr_first : 1; + RK_U32 sw_pp2_out_mode : 1; + RK_U32 sw_pp2_out_tile_e : 1; + RK_U32 reserved0 : 7; + RK_U32 sw_pp2_out_p010_fmt : 2; + RK_U32 sw_pp2_out_rgb_fmt : 5; + RK_U32 reserved1 : 12; + RK_U32 sw_pp2_rgb_planar : 1; + RK_U32 reserved2 : 1; + } swreg359; + + struct { + RK_U32 reserved0 : 9; + RK_U32 sw_pp2_tile_size : 2; + RK_U32 reserved1 : 9; + RK_U32 sw_pp2_out_swap : 4; + RK_U32 reserved2 : 8; + } swreg360; + + struct { + RK_U32 sw_pp2_scale_hratio : 18; + RK_U32 sw_pp2_out_format : 5; + RK_U32 sw_pp2_ver_scale_mode : 2; + RK_U32 sw_pp2_hor_scale_mode : 2; + RK_U32 reserved0 : 5; + } swreg361; + + struct { + RK_U32 sw_pp2_scale_wratio : 18; + RK_U32 reserved0 : 5; + RK_U32 reserved1 : 5; + RK_U32 reserved2 : 1; + RK_U32 reserved4 : 1; + RK_U32 reserved3 : 1; + RK_U32 reserved5 : 1; + } swreg362; + + struct { + RK_U32 sw_pp2_hscale_invra : 16; + RK_U32 sw_pp2_wscale_invra : 16; + } swreg363; + + struct { + RK_U32 sw_pp2_out_lu_base_msb : 32; + } swreg364; + + struct { + RK_U32 sw_pp2_out_lu_base_lsb : 32; + } swreg365; + + struct { + RK_U32 sw_pp2_out_ch_base_msb : 32; + } swreg366; + + struct { + RK_U32 sw_pp2_out_ch_base_lsb : 32; + } swreg367; + + struct { + RK_U32 sw_pp2_out_c_stride : 16; + RK_U32 sw_pp2_out_y_stride : 16; + } swreg368; + + struct { + RK_U32 sw_pp2_crop_starty : 13; + RK_U32 sw_pp2_rotation_mode : 2; + RK_U32 reserved0 : 1; + RK_U32 sw_pp2_crop_startx : 13; + RK_U32 sw_pp2_flip_mode : 2; + RK_U32 sw_pp2_pad_sel : 1; + } swreg369; + + struct { + RK_U32 sw_pp2_in_height : 16; + RK_U32 sw_pp2_in_width : 16; + } swreg370; + + struct { + RK_U32 sw_pp2_out_height : 16; + RK_U32 sw_pp2_out_width : 16; + } swreg371; + + struct { + // RK_U32 sw_pp2_out_b_base_msb : 32; + RK_U32 sw_pp2_out_lu_bot_base_msb : 32; + } swreg372; + + struct { + // RK_U32 sw_pp2_out_b_base_lsb : 32; + RK_U32 sw_pp2_out_lu_bot_base_lsb : 32; + } swreg373; + + struct { + RK_U32 sw_pp2_crop2_starty : 13; + RK_U32 reserved0 : 3; + RK_U32 sw_pp2_crop2_startx : 13; + RK_U32 reserved1 : 3; + // RK_U32 sw_pp2_out_ch_bot_base_msb : 32; + } swreg374; + + struct { + RK_U32 sw_pp2_crop2_out_height : 16; + RK_U32 sw_pp2_crop2_out_width : 16; + // RK_U32 sw_pp2_out_ch_bot_base_lsb : 32; + } swreg375; + + struct { + RK_U32 sw_pp3_out_e : 1; + RK_U32 sw_pp3_cr_first : 1; + RK_U32 sw_pp3_out_mode : 1; + RK_U32 sw_pp3_out_tile_e : 1; + RK_U32 reserved0 : 7; + RK_U32 sw_pp3_out_p010_fmt : 2; + RK_U32 sw_pp3_out_rgb_fmt : 5; + RK_U32 reserved1 : 12; + RK_U32 sw_pp3_rgb_planar : 1; + RK_U32 reserved2 : 1; + } swreg376; + + struct { + RK_U32 reserved0 : 9; + RK_U32 sw_pp3_tile_size : 2; + RK_U32 reserved1 : 9; + RK_U32 sw_pp3_out_swap : 4; + RK_U32 reserved2 : 8; + } swreg377; + + struct { + RK_U32 sw_pp3_scale_hratio : 18; + RK_U32 sw_pp3_out_format : 5; + RK_U32 sw_pp3_ver_scale_mode : 2; + RK_U32 sw_pp3_hor_scale_mode : 2; + RK_U32 reserved0 : 5; + } swreg378; + + struct { + RK_U32 sw_pp3_scale_wratio : 18; + RK_U32 reserved0 : 5; + RK_U32 reserved1 : 5; + RK_U32 reserved2 : 1; + RK_U32 reserved4 : 1; + RK_U32 reserved3 : 1; + RK_U32 reserved5 : 1; + } swreg379; + + struct { + RK_U32 sw_pp3_hscale_invra : 16; + RK_U32 sw_pp3_wscale_invra : 16; + } swreg380; + + struct { + // RK_U32 sw_pp3_out_r_base_msb : 32; + RK_U32 sw_pp3_out_lu_base_msb : 32; + } swreg381; + + struct { + // RK_U32 sw_pp3_out_r_base_lsb : 32; + RK_U32 sw_pp3_out_lu_base_lsb : 32; + } swreg382; + + struct { + // RK_U32 sw_pp3_out_g_base_msb : 32; + RK_U32 sw_pp3_out_ch_base_msb : 32; + } swreg383; + + struct { + // RK_U32 sw_pp3_out_g_base_lsb : 32; + RK_U32 sw_pp3_out_ch_base_lsb : 32; + } swreg384; + + struct { + RK_U32 sw_pp3_out_c_stride : 16; + RK_U32 sw_pp3_out_y_stride : 16; + } swreg385; + + struct { + RK_U32 sw_pp3_crop_starty : 13; + RK_U32 sw_pp3_rotation_mode : 2; + RK_U32 reserved0 : 1; + RK_U32 sw_pp3_crop_startx : 13; + RK_U32 sw_pp3_flip_mode : 2; + RK_U32 sw_pp3_pad_sel : 1; + } swreg386; + + struct { + RK_U32 sw_pp3_in_height : 16; + RK_U32 sw_pp3_in_width : 16; + } swreg387; + + struct { + RK_U32 sw_pp3_out_height : 16; + RK_U32 sw_pp3_out_width : 16; + } swreg388; + + struct { + // RK_U32 sw_pp3_out_b_base_msb : 32; + RK_U32 sw_pp3_out_lu_bot_base_msb : 32; + } swreg389; + + struct { + // RK_U32 sw_pp3_out_b_base_lsb : 32; + RK_U32 sw_pp3_out_lu_bot_base_lsb : 32; + } swreg390; + + struct { + RK_U32 sw_pp3_crop2_starty : 13; + RK_U32 reserved0 : 3; + RK_U32 sw_pp3_crop2_startx : 13; + RK_U32 reserved1 : 3; + // RK_U32 sw_pp3_out_ch_bot_base_msb : 32; + } swreg391; + + struct { + RK_U32 sw_pp3_crop2_out_height : 16; + RK_U32 sw_pp3_crop2_out_width : 16; + // RK_U32 sw_pp3_out_ch_bot_base_lsb : 32; + } swreg392; + + struct { + RK_U32 sw_pp3_out_alpha : 8; + RK_U32 sw_pp2_out_alpha : 8; + RK_U32 sw_pp1_out_alpha : 8; + RK_U32 sw_pp0_out_alpha : 8; + } swreg393; + + struct { + RK_U32 sw_pp1_dup_ver : 8; + RK_U32 sw_pp1_dup_hor : 8; + RK_U32 sw_pp0_dup_ver : 8; + RK_U32 sw_pp0_dup_hor : 8; + } swreg394; + + struct { + RK_U32 sw_pp3_dup_ver : 8; + RK_U32 sw_pp3_dup_hor : 8; + RK_U32 sw_pp2_dup_ver : 8; + RK_U32 sw_pp2_dup_hor : 8; + } swreg395; + + struct { + RK_U32 sw_pp0_scale1_out_height : 16; + RK_U32 sw_pp0_scale1_out_width : 16; + } swreg396; + + struct { + RK_U32 sw_pp1_scale1_out_height : 16; + RK_U32 sw_pp1_scale1_out_width : 16; + } swreg397; + + struct { + RK_U32 sw_pp2_scale1_out_height : 16; + RK_U32 sw_pp2_scale1_out_width : 16; + } swreg398; + + struct { + RK_U32 sw_pp3_scale1_out_height : 16; + RK_U32 sw_pp3_scale1_out_width : 16; + } swreg399; + + struct { + RK_U32 sw_dec_in_pool_base_msb : 32; + } swreg400; + + struct { + RK_U32 sw_dec_in_pool_base_lsb : 32; + } swreg401; + + struct { + RK_U32 sw_dec_in_bufpool_size : 32; + } swreg402; + + struct { + RK_U32 sw_dec_out_pool_base_msb : 32; + } swreg403; + + struct { + RK_U32 sw_dec_out_pool_base_lsb : 32; + } swreg404; + + struct { + RK_U32 sw_dec_out_bufpool_size : 32; + } swreg405; + + struct { + RK_U32 sw_dec_priv_pool_base_msb : 32; + } swreg406; + + struct { + RK_U32 sw_dec_priv_pool_base_lsb : 32; + } swreg407; + + struct { + RK_U32 sw_dec_priv_pool_size : 32; + } swreg408; + + struct { + RK_U32 sw_dec_in_nsa_id : 4; + RK_U32 sw_dec_out_nsa_id : 4; + RK_U32 sw_dec_priv_nsa_id : 4; + RK_U32 sw_dec_pub_nsa_id : 4; + RK_U32 reserved0 : 16; + } swreg409; + + struct { + RK_U32 sw_contrast_off1 : 12; + RK_U32 sw_contrast_off2 : 12; + RK_U32 reserved0 : 2; + RK_U32 sw_dither_select_b : 2; + RK_U32 sw_dither_select_g : 2; + RK_U32 sw_dither_select_r : 2; + } swreg410; + + struct { + RK_U32 sw_color_coefff : 10; + RK_U32 sw_contrast_thr2 : 10; + RK_U32 sw_contrast_thr1 : 10; + RK_U32 reserved0 : 2; + } swreg411; + + struct { + RK_U32 sw_color_coeffa1 : 16; + RK_U32 sw_color_coeffa2 : 16; + } swreg412; + + struct { + RK_U32 sw_color_coeffb : 16; + RK_U32 sw_color_coeffc : 16; + } swreg413; + + struct { + RK_U32 sw_color_coeffd : 16; + RK_U32 sw_color_coeffe : 16; + } swreg414; + + struct { + RK_U32 sw_pp1_contrast_off1 : 12; + RK_U32 sw_pp1_contrast_off2 : 12; + RK_U32 reserved0 : 2; + RK_U32 sw_pp1_dither_select_b : 2; + RK_U32 sw_pp1_dither_select_g : 2; + RK_U32 sw_pp1_dither_select_r : 2; + } swreg415; + + struct { + RK_U32 sw_pp1_color_coefff : 10; + RK_U32 sw_pp1_contrast_thr2 : 10; + RK_U32 sw_pp1_contrast_thr1 : 10; + RK_U32 reserved0 : 2; + } swreg416; + + struct { + RK_U32 sw_pp1_color_coeffa1 : 16; + RK_U32 sw_pp1_color_coeffa2 : 16; + } swreg417; + + struct { + RK_U32 sw_pp1_color_coeffb : 16; + RK_U32 sw_pp1_color_coeffc : 16; + } swreg418; + + struct { + RK_U32 sw_pp1_color_coeffd : 16; + RK_U32 sw_pp1_color_coeffe : 16; + } swreg419; + + struct { + RK_U32 sw_pp2_contrast_off1 : 12; + RK_U32 sw_pp2_contrast_off2 : 12; + RK_U32 reserved0 : 2; + RK_U32 sw_pp2_dither_select_b : 2; + RK_U32 sw_pp2_dither_select_g : 2; + RK_U32 sw_pp2_dither_select_r : 2; + } swreg420; + + struct { + RK_U32 sw_pp2_color_coefff : 10; + RK_U32 sw_pp2_contrast_thr2 : 10; + RK_U32 sw_pp2_contrast_thr1 : 10; + RK_U32 reserved0 : 2; + } swreg421; + + struct { + RK_U32 sw_pp2_color_coeffa1 : 16; + RK_U32 sw_pp2_color_coeffa2 : 16; + } swreg422; + + struct { + RK_U32 sw_pp2_color_coeffb : 16; + RK_U32 sw_pp2_color_coeffc : 16; + } swreg423; + + struct { + RK_U32 sw_pp2_color_coeffd : 16; + RK_U32 sw_pp2_color_coeffe : 16; + } swreg424; + + struct { + RK_U32 sw_pp3_contrast_off1 : 12; + RK_U32 sw_pp3_contrast_off2 : 12; + RK_U32 reserved0 : 2; + RK_U32 sw_pp3_dither_select_b : 2; + RK_U32 sw_pp3_dither_select_g : 2; + RK_U32 sw_pp3_dither_select_r : 2; + } swreg425; + + struct { + RK_U32 sw_pp3_color_coefff : 10; + RK_U32 sw_pp3_contrast_thr2 : 10; + RK_U32 sw_pp3_contrast_thr1 : 10; + RK_U32 reserved0 : 2; + } swreg426; + + struct { + RK_U32 sw_pp3_color_coeffa1 : 16; + RK_U32 sw_pp3_color_coeffa2 : 16; + } swreg427; + + struct { + RK_U32 sw_pp3_color_coeffb : 16; + RK_U32 sw_pp3_color_coeffc : 16; + } swreg428; + + struct { + RK_U32 sw_pp3_color_coeffd : 16; + RK_U32 sw_pp3_color_coeffe : 16; + } swreg429; + + struct { + RK_U32 sw_delogo0_h : 10; + RK_U32 sw_delogo0_w : 10; + RK_U32 reserved0 : 8; + RK_U32 sw_delogo0_show_border : 1; + RK_U32 sw_delogo0_mode : 3; + } swreg430; + + struct { + RK_U32 sw_delogo0_y : 16; + RK_U32 sw_delogo0_x : 16; + } swreg431; + + struct { + RK_U32 sw_delogo0_fillV : 10; + RK_U32 sw_delogo0_fillU : 10; + RK_U32 sw_delogo0_fillY : 10; + RK_U32 reserved0 : 2; + } swreg432; + + struct { + RK_U32 sw_delogo1_h : 14; + RK_U32 sw_delogo1_w : 14; + RK_U32 sw_delogo1_show_border : 1; + RK_U32 sw_delogo1_mode : 3; + } swreg433; + + struct { + RK_U32 sw_delogo1_y : 16; + RK_U32 sw_delogo1_x : 16; + } swreg434; + + struct { + RK_U32 sw_delogo1_fillV : 10; + RK_U32 sw_delogo1_fillU : 10; + RK_U32 sw_delogo1_fillY : 10; + RK_U32 reserved0 : 2; + } swreg435; + + struct { + RK_U32 sw_delogo0_ratio_h : 16; + RK_U32 sw_delogo0_ratio_w : 16; + } swreg436; + + struct { + RK_U32 sw_pp1_hcale_invra_ext : 8; + RK_U32 sw_pp1_wscale_invra_ext : 8; + RK_U32 sw_pp0_hcale_invra_ext : 8; + RK_U32 sw_pp0_wscale_invra_ext : 8; + } swreg437; + + struct { + RK_U32 sw_pp0_x_filter_size : 12; + RK_U32 sw_pp0_y_filter_size : 12; + RK_U32 reserved0 : 8; + } swreg438; + + struct { + RK_U32 sw_pp0_lanczos_tbl_base_msb : 32; + } swreg439; + + struct { + RK_U32 sw_pp0_lanczos_tbl_base_lsb : 32; + } swreg440; + + struct { + RK_U32 sw_pp1_x_filter_size : 12; + RK_U32 sw_pp1_y_filter_size : 12; + RK_U32 reserved0 : 8; + } swreg441; + + struct { + RK_U32 sw_pp1_lanczos_tbl_base_msb : 32; + } swreg442; + + struct { + RK_U32 sw_pp1_lanczos_tbl_base_lsb : 32; + } swreg443; + + struct { + RK_U32 sw_pp3_hcale_invra_ext : 8; + RK_U32 sw_pp3_wscale_invra_ext : 8; + RK_U32 sw_pp2_hcale_invra_ext : 8; + RK_U32 sw_pp2_wscale_invra_ext : 8; + } swreg444; + + struct { + RK_U32 sw_pp2_x_filter_size : 12; + RK_U32 sw_pp2_y_filter_size : 12; + RK_U32 reserved0 : 8; + } swreg445; + + struct { + RK_U32 sw_pp2_lanczos_tbl_base_msb : 32; + } swreg446; + + struct { + RK_U32 sw_pp2_lanczos_tbl_base_lsb : 32; + } swreg447; + + struct { + RK_U32 sw_pp3_x_filter_size : 12; + RK_U32 sw_pp3_y_filter_size : 12; + RK_U32 reserved0 : 8; + } swreg448; + + struct { + RK_U32 sw_pp3_lanczos_tbl_base_msb : 32; + } swreg449; + + struct { + RK_U32 sw_pp3_lanczos_tbl_base_lsb : 32; + } swreg450; + + struct { + RK_U32 sw_pp4_out_e : 1; + RK_U32 sw_pp4_cr_first : 1; + RK_U32 sw_pp4_out_mode : 1; + RK_U32 sw_pp4_out_tile_e : 1; + RK_U32 reserved0 : 7; + RK_U32 sw_pp4_out_p010_fmt : 2; + RK_U32 sw_pp4_out_rgb_fmt : 5; + RK_U32 reserved1 : 12; + RK_U32 sw_pp4_rgb_planar : 1; + RK_U32 reserved2 : 1; + } swreg451; + + struct { + RK_U32 reserved0 : 20; + RK_U32 sw_pp4_out_swap : 4; + RK_U32 reserved1 : 8; + } swreg452; + + struct { + RK_U32 sw_pp4_scale_hratio : 18; + RK_U32 sw_pp4_out_format : 5; + RK_U32 sw_pp4_ver_scale_mode : 2; + RK_U32 sw_pp4_hor_scale_mode : 2; + RK_U32 reserved0 : 5; + } swreg453; + + struct { + RK_U32 sw_pp4_scale_wratio : 18; + RK_U32 reserved0 : 5; + RK_U32 reserved1 : 5; + RK_U32 reserved2 : 1; + RK_U32 reserved4 : 1; + RK_U32 reserved3 : 1; + RK_U32 reserved5 : 1; + } swreg454; + + struct { + RK_U32 sw_pp4_hscale_invra : 16; + RK_U32 sw_pp4_wscale_invra : 16; + } swreg455; + + struct { + // RK_U32 sw_pp4_out_r_base_msb : 32; + RK_U32 sw_pp4_out_lu_base_msb : 32; + } swreg456; + + struct { + // RK_U32 sw_pp4_out_r_base_lsb : 32; + RK_U32 sw_pp4_out_lu_base_lsb : 32; + } swreg457; + + struct { + // RK_U32 sw_pp4_out_g_base_msb : 32; + RK_U32 sw_pp4_out_ch_base_msb : 32; + } swreg458; + + struct { + // RK_U32 sw_pp4_out_g_base_lsb : 32; + RK_U32 sw_pp4_out_ch_base_lsb : 32; + } swreg459; + + struct { + RK_U32 sw_pp4_out_c_stride : 16; + RK_U32 sw_pp4_out_y_stride : 16; + } swreg460; + + struct { + RK_U32 sw_pp4_crop_starty : 13; + RK_U32 sw_pp4_rotation_mode : 2; + RK_U32 reserved0 : 1; + RK_U32 sw_pp4_crop_startx : 13; + RK_U32 sw_pp4_flip_mode : 2; + RK_U32 sw_pp4_pad_sel : 1; + } swreg461; + + struct { + RK_U32 sw_pp4_in_height : 16; + RK_U32 sw_pp4_in_width : 16; + } swreg462; + + struct { + RK_U32 sw_pp4_out_height : 16; + RK_U32 sw_pp4_out_width : 16; + } swreg463; + + struct { + // RK_U32 sw_pp4_out_b_base_msb : 32; + RK_U32 sw_pp4_out_lu_bot_base_msb : 32; + } swreg464; + + struct { + // RK_U32 sw_pp4_out_b_base_lsb : 32; + RK_U32 sw_pp4_out_lu_bot_base_lsb : 32; + } swreg465; + + struct { + RK_U32 sw_pp4_crop2_starty : 13; + RK_U32 reserved0 : 3; + RK_U32 sw_pp4_crop2_startx : 13; + RK_U32 reserved1 : 3; + // RK_U32 sw_pp4_out_ch_bot_base_msb : 32; + } swreg466; + + struct { + RK_U32 sw_pp4_crop2_out_height : 16; + RK_U32 sw_pp4_crop2_out_width : 16; + // RK_U32 sw_pp4_out_ch_bot_base_lsb : 32; + } swreg467; + + struct { + RK_U32 sw_pp4_contrast_off1 : 12; + RK_U32 sw_pp4_contrast_off2 : 12; + RK_U32 reserved0 : 2; + RK_U32 sw_pp4_dither_select_b : 2; + RK_U32 sw_pp4_dither_select_g : 2; + RK_U32 sw_pp4_dither_select_r : 2; + } swreg468; + + struct { + RK_U32 sw_pp4_color_coefff : 10; + RK_U32 sw_pp4_contrast_thr2 : 10; + RK_U32 sw_pp4_contrast_thr1 : 10; + RK_U32 reserved0 : 2; + } swreg469; + + struct { + RK_U32 sw_pp4_color_coeffa1 : 16; + RK_U32 sw_pp4_color_coeffa2 : 16; + } swreg470; + + struct { + RK_U32 sw_pp4_color_coeffb : 16; + RK_U32 sw_pp4_color_coeffc : 16; + } swreg471; + + struct { + RK_U32 sw_pp4_color_coeffd : 16; + RK_U32 sw_pp4_color_coeffe : 16; + } swreg472; + + struct { + RK_U32 sw_pp4_out_alpha : 8; + RK_U32 sw_pp4_dup_hor : 8; + RK_U32 sw_pp4_hcale_invra_ext : 8; + RK_U32 sw_pp4_wscale_invra_ext : 8; + } swreg473; + + struct { + RK_U32 sw_pp4_x_filter_size : 12; + RK_U32 sw_pp4_y_filter_size : 12; + RK_U32 reserved0 : 8; + } swreg474; + + struct { + RK_U32 sw_pp4_lanczos_tbl_base_msb : 32; + } swreg475; + + struct { + RK_U32 sw_pp4_lanczos_tbl_base_lsb : 32; + } swreg476; + + struct { + RK_U32 sw_pp5_out_e : 1; + RK_U32 sw_pp5_cr_first : 1; + RK_U32 sw_pp5_out_mode : 1; + RK_U32 sw_pp5_out_tile_e : 1; + RK_U32 reserved0 : 7; + RK_U32 sw_pp5_out_p010_fmt : 2; + RK_U32 sw_pp5_out_rgb_fmt : 5; + RK_U32 reserved1 : 12; + RK_U32 sw_pp5_rgb_planar : 1; + RK_U32 reserved2 : 1; + } swreg477; + + struct { + RK_U32 reserved0 : 20; + RK_U32 sw_pp5_out_swap : 4; + RK_U32 reserved1 : 8; + } swreg478; + + struct { + RK_U32 sw_pp5_scale_hratio : 18; + RK_U32 sw_pp5_out_format : 5; + RK_U32 sw_pp5_ver_scale_mode : 2; + RK_U32 sw_pp5_hor_scale_mode : 2; + RK_U32 reserved0 : 5; + } swreg479; + + struct { + RK_U32 sw_pp5_scale_wratio : 18; + RK_U32 reserved0 : 5; + RK_U32 reserved1 : 5; + RK_U32 reserved2 : 1; + RK_U32 reserved4 : 1; + RK_U32 reserved3 : 1; + RK_U32 reserved5 : 1; + } swreg480; + + struct { + RK_U32 sw_pp5_hscale_invra : 16; + RK_U32 sw_pp5_wscale_invra : 16; + } swreg481; + + struct { + // RK_U32 sw_pp5_out_r_base_msb : 32; + RK_U32 sw_pp5_out_lu_base_msb : 32; + } swreg482; + + struct { + // RK_U32 sw_pp5_out_r_base_lsb : 32; + RK_U32 sw_pp5_out_lu_base_lsb : 32; + } swreg483; + + struct { + // RK_U32 sw_pp5_out_g_base_msb : 32; + RK_U32 sw_pp5_out_ch_base_msb : 32; + } swreg484; + + struct { + // RK_U32 sw_pp5_out_g_base_lsb : 32; + RK_U32 sw_pp5_out_ch_base_lsb : 32; + } swreg485; + + struct { + RK_U32 sw_pp5_out_c_stride : 16; + RK_U32 sw_pp5_out_y_stride : 16; + } swreg486; + + struct { + RK_U32 sw_pp5_crop_starty : 13; + RK_U32 sw_pp5_rotation_mode : 2; + RK_U32 reserved0 : 1; + RK_U32 sw_pp5_crop_startx : 13; + RK_U32 sw_pp5_flip_mode : 2; + RK_U32 sw_pp5_pad_sel : 1; + } swreg487; + + struct { + RK_U32 sw_pp5_in_height : 16; + RK_U32 sw_pp5_in_width : 16; + } swreg488; + + struct { + RK_U32 sw_pp5_out_height : 16; + RK_U32 sw_pp5_out_width : 16; + } swreg489; + + struct { + // RK_U32 sw_pp5_out_b_base_msb : 32; + RK_U32 sw_pp5_out_lu_bot_base_msb : 32; + } swreg490; + + struct { + // RK_U32 sw_pp5_out_b_base_lsb : 32; + RK_U32 sw_pp5_out_lu_bot_base_lsb : 32; + } swreg491; + + struct { + RK_U32 sw_pp5_crop2_starty : 13; + RK_U32 reserved0 : 3; + RK_U32 sw_pp5_crop2_startx : 13; + RK_U32 reserved1 : 3; + // RK_U32 sw_pp5_out_ch_bot_base_msb : 32; + } swreg492; + + struct { + RK_U32 sw_pp5_crop2_out_height : 16; + RK_U32 sw_pp5_crop2_out_width : 16; + // RK_U32 sw_pp5_out_ch_bot_base_lsb : 32; + } swreg493; + + struct { + RK_U32 sw_pp5_contrast_off1 : 12; + RK_U32 sw_pp5_contrast_off2 : 12; + RK_U32 reserved0 : 2; + RK_U32 sw_pp5_dither_select_b : 2; + RK_U32 sw_pp5_dither_select_g : 2; + RK_U32 sw_pp5_dither_select_r : 2; + } swreg494; + + struct { + RK_U32 sw_pp5_color_coefff : 10; + RK_U32 sw_pp5_contrast_thr2 : 10; + RK_U32 sw_pp5_contrast_thr1 : 10; + RK_U32 reserved0 : 2; + } swreg495; + + struct { + RK_U32 sw_pp5_color_coeffa1 : 16; + RK_U32 sw_pp5_color_coeffa2 : 16; + } swreg496; + + struct { + RK_U32 sw_pp5_color_coeffb : 16; + RK_U32 sw_pp5_color_coeffc : 16; + } swreg497; + + struct { + RK_U32 sw_pp5_color_coeffd : 16; + RK_U32 sw_pp5_color_coeffe : 16; + } swreg498; + + struct { + RK_U32 sw_pp5_out_alpha : 8; + RK_U32 sw_pp5_dup_hor : 8; + RK_U32 sw_pp5_hcale_invra_ext : 8; + RK_U32 sw_pp5_wscale_invra_ext : 8; + } swreg499; + + struct { + RK_U32 sw_pp5_x_filter_size : 12; + RK_U32 sw_pp5_y_filter_size : 12; + RK_U32 reserved0 : 8; + } swreg500; + + struct { + RK_U32 sw_pp5_lanczos_tbl_base_msb : 32; + } swreg501; + + struct { + RK_U32 sw_pp5_lanczos_tbl_base_lsb : 32; + } swreg502; + + struct { + RK_U32 sw_pp1_virtual_top : 4; + RK_U32 sw_pp1_virtual_left : 4; + RK_U32 sw_pp1_virtual_bottom : 4; + RK_U32 sw_pp1_virtual_right : 4; + RK_U32 sw_pp0_virtual_top : 4; + RK_U32 sw_pp0_virtual_left : 4; + RK_U32 sw_pp0_virtual_bottom : 4; + RK_U32 sw_pp0_virtual_right : 4; + } swreg503; + + struct { + RK_U32 sw_pp0_afbc_tile_base_msb : 32; + } swreg504; + + struct { + RK_U32 sw_pp0_afbc_tile_base_lsb : 32; + } swreg505; + + struct { + RK_U32 sw_pp1_afbc_tile_base_msb : 32; + } swreg506; + + struct { + RK_U32 sw_pp1_afbc_tile_base_lsb : 32; + } swreg507; + + struct { + RK_U32 sw_pp0_padV : 10; + RK_U32 sw_pp0_padU : 10; + RK_U32 sw_pp0_padY : 10; + RK_U32 sw_pp0_src_sel_mode : 2; + } swreg508; + + struct { + RK_U32 sw_pp1_padV : 10; + RK_U32 sw_pp1_padU : 10; + RK_U32 sw_pp1_padY : 10; + RK_U32 sw_pp1_src_sel_mode : 2; + } swreg509; + + struct { + RK_U32 sw_pp2_padV : 10; + RK_U32 sw_pp2_padU : 10; + RK_U32 sw_pp2_padY : 10; + RK_U32 sw_pp2_src_sel_mode : 2; + } swreg510; + + struct { + RK_U32 sw_pp3_padV : 10; + RK_U32 sw_pp3_padU : 10; + RK_U32 sw_pp3_padY : 10; + RK_U32 sw_pp3_src_sel_mode : 2; + } swreg511; + +} VdpuAv1dPPCfg; + +typedef struct VdpuAv1dRegSet_t { + struct { + RK_U32 reserved0 : 4; + RK_U32 reserved1 : 8; + RK_U32 reserved2 : 4; + RK_U32 reserved3 : 4; + RK_U32 reserved4 : 12; + } swreg0; + + struct { + RK_U32 sw_dec_e : 1; + RK_U32 reserved0 : 1; + RK_U32 sw_dec_bus_int_dis : 1; + RK_U32 sw_dec_timeout_source : 1; + + RK_U32 sw_dec_irq_dis : 1; + RK_U32 sw_dec_abort_e : 1; + RK_U32 sw_dec_self_reset_dis : 1; + RK_U32 sw_dec_tile_int_e : 1; + + RK_U32 sw_dec_irq : 1; + RK_U32 reserved1 : 2; + RK_U32 sw_dec_abort_int : 1; + + RK_U32 sw_dec_rdy_int : 1; + RK_U32 sw_dec_bus_int : 1; + RK_U32 sw_dec_buffer_int : 1; + RK_U32 reserved2 : 1; + + RK_U32 sw_dec_error_int : 1; + RK_U32 reserved3 : 1; + RK_U32 sw_dec_timeout : 1; + RK_U32 reserved4 : 2; + RK_U32 sw_dec_ext_timeout_int : 1; + RK_U32 reserved5 : 1; + RK_U32 sw_dec_tile_int : 1; + + RK_U32 reserved6 : 8; + } swreg1; + + struct { + RK_U32 reserved0 : 4; + RK_U32 sw_drm_e : 1; + RK_U32 reserved1 : 5; + RK_U32 sw_dec_clk_gate_e : 1; + RK_U32 reserved2 : 1; + + RK_U32 sw_dec_tab_swap : 4; + RK_U32 reserved3 : 4; + RK_U32 sw_dec_dirmv_swap : 4; + RK_U32 sw_dec_pic_swap : 4; + RK_U32 sw_dec_strm_swap : 4; + } swreg2; + + struct { + RK_U32 reserved0 : 8; + RK_U32 sw_dec_out_ec_bypass : 1; + RK_U32 reserved1 : 3; + RK_U32 sw_write_mvs_e : 1; + RK_U32 reserved2 : 1; + RK_U32 sw_filtering_dis : 1; + RK_U32 sw_dec_out_dis : 1; + RK_U32 sw_dec_out_ec_byte_word : 1; + RK_U32 reserved3 : 9; + RK_U32 sw_skip_mode : 1; + RK_U32 sw_dec_mode : 5; + } swreg3; + + struct { + RK_U32 sw_ref_frames : 4; + RK_U32 reserved0 : 2; + RK_U32 sw_pic_height_in_cbs : 13; + RK_U32 sw_pic_width_in_cbs : 13; + } swreg4; + + struct { + RK_U32 sw_ref_scaling_enable : 1; + RK_U32 sw_filt_level_base_gt32 : 1; + RK_U32 sw_error_resilient : 1; + RK_U32 sw_force_interger_mv : 1; + + RK_U32 sw_allow_intrabc : 1; + RK_U32 sw_allow_screen_content_tools : 1; + RK_U32 sw_reduced_tx_set_used : 1; + RK_U32 sw_enable_dual_filter : 1; + + RK_U32 sw_enable_jnt_comp : 1; + RK_U32 sw_allow_filter_intra : 1; + RK_U32 sw_enable_intra_edge_filter : 1; + RK_U32 sw_tempor_mvp_e : 1;//RK_U32 reserved0 : 1; + + RK_U32 sw_allow_interintra : 1; + RK_U32 sw_allow_masked_compound : 1; + RK_U32 sw_enable_cdef : 1; + RK_U32 sw_switchable_motion_mode : 1; + + RK_U32 sw_show_frame : 1; + RK_U32 sw_superres_is_scaled : 1; + RK_U32 sw_allow_warp : 1; + RK_U32 sw_disable_cdf_update : 1; + + RK_U32 sw_preskip_segid : 1; + RK_U32 sw_delta_lf_present : 1; + RK_U32 sw_delta_lf_multi : 1; + RK_U32 sw_delta_lf_res_log : 2; + + // RK_U32 reserved1 : -14; + RK_U32 sw_strm_start_bit : 7; + } swreg5; + + struct { + RK_U32 sw_stream_len : 32; + } swreg6; + + struct { + RK_U32 sw_delta_q_present : 1; + RK_U32 sw_delta_q_res_log : 2; + RK_U32 sw_cdef_damping : 2; + RK_U32 sw_cdef_bits : 2; + RK_U32 sw_apply_grain : 1; + RK_U32 sw_num_y_points_b : 1; + RK_U32 sw_num_cb_points_b : 1; + RK_U32 sw_num_cr_points_b : 1; + RK_U32 sw_overlap_flag : 1; + RK_U32 sw_clip_to_restricted_range : 1; + RK_U32 sw_chroma_scaling_from_luma : 1; + RK_U32 sw_random_seed : 16; + RK_U32 sw_blackwhite_e : 1; + RK_U32 reserved0 : 1; + } swreg7; + + struct { + RK_U32 sw_scaling_shift : 4; + RK_U32 sw_bit_depth_c_minus8 : 2; + RK_U32 sw_bit_depth_y_minus8 : 2; + RK_U32 sw_quant_base_qindex : 8; + RK_U32 sw_idr_pic_e : 1; + RK_U32 sw_superres_pic_width : 15; + } swreg8; + + struct { + RK_U32 reserved0 : 2; + RK_U32 sw_ref4_sign_bias : 1; + RK_U32 sw_ref5_sign_bias : 1; + RK_U32 sw_ref6_sign_bias : 1; + RK_U32 sw_mf1_type : 3; + RK_U32 sw_mf2_type : 3; + RK_U32 sw_mf3_type : 3; + RK_U32 sw_scale_denom_minus9 : 3; + RK_U32 sw_last_active_seg : 3; + RK_U32 sw_context_update_tile_id : 12; + } swreg9; + + struct { + RK_U32 sw_tile_transpose : 1; + RK_U32 sw_tile_enable : 1; + RK_U32 sw_multicore_full_width : 8; + RK_U32 sw_num_tile_rows_8k_av1 : 7; + RK_U32 sw_num_tile_cols_8k : 7; + RK_U32 sw_multicore_tile_start_x : 8; + } swreg10; + + struct { + RK_U32 sw_use_temporal3_mvs : 1; + RK_U32 sw_use_temporal2_mvs : 1; + RK_U32 sw_use_temporal1_mvs : 1; + RK_U32 sw_use_temporal0_mvs : 1; + RK_U32 sw_comp_pred_mode : 2; + RK_U32 reserved0 : 1; + RK_U32 sw_high_prec_mv_e : 1; + RK_U32 sw_mcomp_filt_type : 3; + RK_U32 sw_multicore_expect_context_update : 1; + RK_U32 sw_multicore_sbx_offset : 7; + RK_U32 sw_multicore_tile_col : 7; + RK_U32 reserved1 : 1; + RK_U32 sw_transform_mode : 3; + RK_U32 sw_dec_tile_size_mag : 2; + } swreg11; + + struct { + RK_U32 reserved0 : 2; + RK_U32 sw_seg_quant_sign : 8; + RK_U32 sw_max_cb_size : 3; + RK_U32 sw_min_cb_size : 3; + RK_U32 sw_av1_comp_pred_fixed_ref : 3; + RK_U32 sw_multicore_tile_width : 7; + RK_U32 sw_pic_height_pad : 3; + RK_U32 sw_pic_width_pad : 3; + } swreg12; + + struct { + RK_U32 sw_segment_e : 1; + RK_U32 sw_segment_upd_e : 1; + RK_U32 sw_segment_temp_upd_e : 1; + RK_U32 sw_comp_pred_var_ref0_av1 : 3; + RK_U32 sw_comp_pred_var_ref1_av1 : 3; + RK_U32 sw_lossless_e : 1; + RK_U32 reserved0 : 1; + RK_U32 sw_qp_delta_ch_ac_av1 : 7; + RK_U32 sw_qp_delta_ch_dc_av1 : 7; + RK_U32 sw_qp_delta_y_dc_av1 : 7; + } swreg13; + + struct { + RK_U32 sw_quant_seg0 : 8; + RK_U32 sw_filt_level_seg0 : 6; + RK_U32 sw_skip_seg0 : 1; + RK_U32 sw_refpic_seg0 : 4; + RK_U32 sw_filt_level_delta0_seg0 : 7; + RK_U32 sw_filt_level0 : 6; + } swreg14; + + struct { + RK_U32 sw_quant_seg1 : 8; + RK_U32 sw_filt_level_seg1 : 6; + RK_U32 sw_skip_seg1 : 1; + RK_U32 sw_refpic_seg1 : 4; + RK_U32 sw_filt_level_delta0_seg1 : 7; + RK_U32 sw_filt_level1 : 6; + } swreg15; + + struct { + RK_U32 sw_quant_seg2 : 8; + RK_U32 sw_filt_level_seg2 : 6; + RK_U32 sw_skip_seg2 : 1; + RK_U32 sw_refpic_seg2 : 4; + RK_U32 sw_filt_level_delta0_seg2 : 7; + RK_U32 sw_filt_level2 : 6; + } swreg16; + + struct { + RK_U32 sw_quant_seg3 : 8; + RK_U32 sw_filt_level_seg3 : 6; + RK_U32 sw_skip_seg3 : 1; + RK_U32 sw_refpic_seg3 : 4; + RK_U32 sw_filt_level_delta0_seg3 : 7; + RK_U32 sw_filt_level3 : 6; + } swreg17; + + struct { + RK_U32 sw_quant_seg4 : 8; + RK_U32 sw_filt_level_seg4 : 6; + RK_U32 sw_skip_seg4 : 1; + RK_U32 sw_refpic_seg4 : 4; + RK_U32 sw_filt_level_delta0_seg4 : 7; + RK_U32 sw_lr_type : 6; + } swreg18; + + struct { + RK_U32 sw_quant_seg5 : 8; + RK_U32 sw_filt_level_seg5 : 6; + RK_U32 sw_skip_seg5 : 1; + RK_U32 sw_refpic_seg5 : 4; + RK_U32 sw_filt_level_delta0_seg5 : 7; + RK_U32 sw_lr_unit_size : 6; + } swreg19; + + struct { + RK_U32 sw_filt_level_delta1_seg0 : 7; + RK_U32 sw_filt_level_delta2_seg0 : 7; + RK_U32 sw_filt_level_delta3_seg0 : 7; + RK_U32 sw_global_mv_seg0 : 1; + RK_U32 sw_mf1_last_offset : 9; + RK_U32 reserved0 : 1; + } swreg20; + + struct { + RK_U32 sw_filt_level_delta1_seg1 : 7; + RK_U32 sw_filt_level_delta2_seg1 : 7; + RK_U32 sw_filt_level_delta3_seg1 : 7; + RK_U32 sw_global_mv_seg1 : 1; + RK_U32 sw_mf1_last2_offset : 9; + RK_U32 reserved0 : 1; + } swreg21; + + struct { + RK_U32 sw_filt_level_delta1_seg2 : 7; + RK_U32 sw_filt_level_delta2_seg2 : 7; + RK_U32 sw_filt_level_delta3_seg2 : 7; + RK_U32 sw_global_mv_seg2 : 1; + RK_U32 sw_mf1_last3_offset : 9; + RK_U32 reserved0 : 1; + } swreg22; + + struct { + RK_U32 sw_filt_level_delta1_seg3 : 7; + RK_U32 sw_filt_level_delta2_seg3 : 7; + RK_U32 sw_filt_level_delta3_seg3 : 7; + RK_U32 sw_global_mv_seg3 : 1; + RK_U32 sw_mf1_golden_offset : 9; + RK_U32 reserved0 : 1; + } swreg23; + + struct { + RK_U32 sw_filt_level_delta1_seg4 : 7; + RK_U32 sw_filt_level_delta2_seg4 : 7; + RK_U32 sw_filt_level_delta3_seg4 : 7; + RK_U32 sw_global_mv_seg4 : 1; + RK_U32 sw_mf1_bwdref_offset : 9; + RK_U32 reserved0 : 1; + } swreg24; + + struct { + RK_U32 sw_filt_level_delta1_seg5 : 7; + RK_U32 sw_filt_level_delta2_seg5 : 7; + RK_U32 sw_filt_level_delta3_seg5 : 7; + RK_U32 sw_global_mv_seg5 : 1; + RK_U32 sw_mf1_altref2_offset : 9; + RK_U32 reserved0 : 1; + } swreg25; + + struct { + RK_U32 sw_filt_level_delta1_seg6 : 7; + RK_U32 sw_filt_level_delta2_seg6 : 7; + RK_U32 sw_filt_level_delta3_seg6 : 7; + RK_U32 sw_global_mv_seg6 : 1; + RK_U32 sw_mf1_altref_offset : 9; + RK_U32 reserved0 : 1; + } swreg26; + + struct { + RK_U32 sw_filt_level_delta1_seg7 : 7; + RK_U32 sw_filt_level_delta2_seg7 : 7; + RK_U32 sw_filt_level_delta3_seg7 : 7; + RK_U32 sw_global_mv_seg7 : 1; + RK_U32 sw_mf2_last_offset : 9; + RK_U32 reserved0 : 1; + } swreg27; + + struct { + RK_U32 sw_cb_offset : 9; + RK_U32 sw_cb_luma_mult : 8; + RK_U32 sw_cb_mult : 8; + RK_U32 sw_quant_delta_v_dc : 7; + } swreg28; + + struct { + RK_U32 sw_cr_offset : 9; + RK_U32 sw_cr_luma_mult : 8; + RK_U32 sw_cr_mult : 8; + RK_U32 sw_quant_delta_v_ac : 7; + } swreg29; + + struct { + RK_U32 sw_filt_ref_adj_5 : 7; + RK_U32 sw_filt_ref_adj_4 : 7; + RK_U32 sw_filt_mb_adj_1 : 7; + RK_U32 sw_filt_mb_adj_0 : 7; + RK_U32 sw_filt_sharpness : 3; + RK_U32 reserved0 : 1; + } swreg30; + + struct { + RK_U32 sw_quant_seg6 : 8; + RK_U32 sw_filt_level_seg6 : 6; + RK_U32 sw_skip_seg6 : 1; + RK_U32 sw_refpic_seg6 : 4; + RK_U32 sw_filt_level_delta0_seg6 : 7; + RK_U32 sw_skip_ref0 : 4; + RK_U32 reserved0 : 2; + } swreg31; + + struct { + RK_U32 sw_quant_seg7 : 8; + RK_U32 sw_filt_level_seg7 : 6; + RK_U32 sw_skip_seg7 : 1; + RK_U32 sw_refpic_seg7 : 4; + RK_U32 sw_filt_level_delta0_seg7 : 7; + RK_U32 sw_skip_ref1 : 4; + RK_U32 reserved0 : 2; + } swreg32; + + struct { + RK_U32 sw_ref0_height : 16; + RK_U32 sw_ref0_width : 16; + } swreg33; + + struct { + RK_U32 sw_ref1_height : 16; + RK_U32 sw_ref1_width : 16; + } swreg34; + + struct { + RK_U32 sw_ref2_height : 16; + RK_U32 sw_ref2_width : 16; + } swreg35; + + struct { + RK_U32 sw_ref0_ver_scale : 16; + RK_U32 sw_ref0_hor_scale : 16; + } swreg36; + + struct { + RK_U32 sw_ref1_ver_scale : 16; + RK_U32 sw_ref1_hor_scale : 16; + } swreg37; + + struct { + RK_U32 sw_ref2_ver_scale : 16; + RK_U32 sw_ref2_hor_scale : 16; + } swreg38; + + struct { + RK_U32 sw_ref3_ver_scale : 16; + RK_U32 sw_ref3_hor_scale : 16; + } swreg39; + + struct { + RK_U32 sw_ref4_ver_scale : 16; + RK_U32 sw_ref4_hor_scale : 16; + } swreg40; + + struct { + RK_U32 sw_ref5_ver_scale : 16; + RK_U32 sw_ref5_hor_scale : 16; + } swreg41; + + struct { + RK_U32 sw_ref6_ver_scale : 16; + RK_U32 sw_ref6_hor_scale : 16; + } swreg42; + struct { + RK_U32 sw_ref3_height : 16; + RK_U32 sw_ref3_width : 16; + } swreg43; + + struct { + RK_U32 sw_ref4_height : 16; + RK_U32 sw_ref4_width : 16; + } swreg44; + + struct { + RK_U32 sw_ref5_height : 16; + RK_U32 sw_ref5_width : 16; + } swreg45; + + struct { + RK_U32 sw_ref6_height : 16; + RK_U32 sw_ref6_width : 16; + } swreg46; + + struct { + RK_U32 sw_mf2_last2_offset : 9; + RK_U32 sw_mf2_last3_offset : 9; + RK_U32 sw_mf2_golden_offset : 9; + RK_U32 sw_qmlevel_y : 4; + RK_U32 reserved0 : 1; + } swreg47; + + struct { + RK_U32 sw_mf2_bwdref_offset : 9; + RK_U32 sw_mf2_altref2_offset : 9; + RK_U32 sw_mf2_altref_offset : 9; + RK_U32 sw_qmlevel_u : 4; + RK_U32 reserved0 : 1; + } swreg48; + + struct { + RK_U32 sw_filt_ref_adj_6 : 7; + RK_U32 sw_filt_ref_adj_7 : 7; + RK_U32 sw_qmlevel_v : 4; + RK_U32 reserved0 : 14; + } swreg49; + + struct { + RK_U32 SW_DEC_MAX_OWIDTH : 16; + RK_U32 SW_DEC_AV1_PROF : 1; + RK_U32 reserved0 : 15; + } swreg50; + + struct { + RK_U32 sw_superres_chroma_step : 14; + RK_U32 sw_superres_luma_step : 14; + RK_U32 reserved0 : 4; + } swreg51; + + struct { + RK_U32 sw_superres_init_chroma_subpel_x : 14; + RK_U32 sw_superres_init_luma_subpel_x : 14; + RK_U32 reserved0 : 4; + } swreg52; + + struct { + RK_U32 sw_cdef_chroma_secondary_strength : 16; + RK_U32 sw_cdef_luma_secondary_strength : 16; + } swreg53; + + struct { + RK_U32 reserved0 : 5; + RK_U32 SW_DEC_ADDR64_SUPPORTED : 1; + RK_U32 reserved1 : 11; + RK_U32 SW_DEC_RFC_EXIST : 2; + RK_U32 reserved2 : 13; + } swreg54; + + struct { + RK_U32 sw_apf_threshold : 16; + RK_U32 reserved0 : 14; + RK_U32 sw_apf_single_pu_mode : 1; + RK_U32 sw_apf_disable : 1; + } swreg55; + + struct { + RK_U32 SW_DEC_MAX_OHEIGHT : 15; + RK_U32 SW_DEC_DATA_S_W : 2; + RK_U32 SW_DEC_ADDR_S_W : 1; + RK_U32 SW_DEC_DATA_M_W : 2; + RK_U32 SW_DEC_ADDR_M_W : 1; + RK_U32 SW_DEC_SLAVE_BUS : 2; + RK_U32 SW_DEC_MASTER_BUS : 2; + RK_U32 SW_DEC_JOINT : 1; + RK_U32 reserved0 : 6; + } swreg56; + + struct { + RK_U32 reserved0 : 6; + RK_U32 fuse_dec_av1 : 1; + RK_U32 reserved1 : 25; + } swreg57; + + struct { + RK_U32 sw_dec_max_burst : 8; + RK_U32 sw_dec_buswidth : 3; + RK_U32 sw_dec_multicore_mode : 2; + RK_U32 sw_dec_axi_wd_id_e : 1; + RK_U32 sw_dec_axi_rd_id_e : 1; + RK_U32 reserved0 : 2; + RK_U32 sw_dec_mc_polltime : 10; + RK_U32 sw_dec_mc_pollmode : 2; + RK_U32 reserved1 : 3; + } swreg58; + + struct { + RK_U32 sw_filt_ref_adj_3 : 7; + RK_U32 sw_filt_ref_adj_2 : 7; + RK_U32 sw_filt_ref_adj_1 : 7; + RK_U32 sw_filt_ref_adj_0 : 7; + RK_U32 sw_ref0_sign_bias : 1; + RK_U32 sw_ref1_sign_bias : 1; + RK_U32 sw_ref2_sign_bias : 1; + RK_U32 sw_ref3_sign_bias : 1; + } swreg59; + + struct { + RK_U32 sw_dec_axi_rd_id : 16; + RK_U32 sw_dec_axi_wr_id : 16; + } swreg60; + + struct { + RK_U32 reserved0 : 12; + RK_U32 fuse_pp_maxw_352 : 1; + RK_U32 fuse_pp_maxw_720 : 1; + RK_U32 fuse_pp_maxw_1280 : 1; + RK_U32 fuse_pp_maxw_1920 : 1; + RK_U32 fuse_pp_maxw_4k : 1; + RK_U32 reserved1 : 12; + RK_U32 fuse_pp_ablend : 1; + RK_U32 fuse_pp_scaling : 1; + RK_U32 fuse_pp_pp : 1; + } swreg61; + + struct { + RK_U32 sw_cu_location_y : 16; + RK_U32 sw_cu_location_x : 16; + } swreg62; + + struct { + RK_U32 sw_perf_cycle_count : 32; + } swreg63; + + /* swreg64 - swreg183 */ + VdpuAv1dBase addr_cfg; + + struct { + RK_U32 sw_cur_last_roffset : 9; + RK_U32 sw_cur_last_offset : 9; + RK_U32 sw_mf3_last_offset : 9; + RK_U32 sw_ref0_gm_mode : 2; + RK_U32 reserved0 : 3; + } swreg184; + + struct { + RK_U32 sw_cur_last2_roffset : 9; + RK_U32 sw_cur_last2_offset : 9; + RK_U32 sw_mf3_last2_offset : 9; + RK_U32 sw_ref1_gm_mode : 2; + RK_U32 reserved0 : 3; + } swreg185; + + struct { + RK_U32 sw_cur_last3_roffset : 9; + RK_U32 sw_cur_last3_offset : 9; + RK_U32 sw_mf3_last3_offset : 9; + RK_U32 sw_ref2_gm_mode : 2; + RK_U32 reserved0 : 3; + } swreg186; + + struct { + RK_U32 sw_cur_golden_roffset : 9; + RK_U32 sw_cur_golden_offset : 9; + RK_U32 sw_mf3_golden_offset : 9; + RK_U32 sw_ref3_gm_mode : 2; + RK_U32 reserved0 : 3; + } swreg187; + + struct { + RK_U32 sw_cur_bwdref_roffset : 9; + RK_U32 sw_cur_bwdref_offset : 9; + RK_U32 sw_mf3_bwdref_offset : 9; + RK_U32 sw_ref4_gm_mode : 2; + RK_U32 reserved0 : 3; + } swreg188; + + struct { + RK_U32 sw_dec_out_tybase_msb : 32; + } swreg189; + + struct { + RK_U32 sw_dec_out_tybase_lsb : 32; + } swreg190; + + struct { + RK_U32 sw_refer0_tybase_msb : 32; + } swreg191; + + struct { + RK_U32 sw_refer0_tybase_lsb : 32; + } swreg192; + + struct { + RK_U32 sw_refer1_tybase_msb : 32; + } swreg193; + + struct { + RK_U32 sw_refer1_tybase_lsb : 32; + } swreg194; + + struct { + RK_U32 sw_refer2_tybase_msb : 32; + } swreg195; + + struct { + RK_U32 sw_refer2_tybase_lsb : 32; + } swreg196; + + struct { + RK_U32 sw_refer3_tybase_msb : 32; + } swreg197; + + struct { + RK_U32 sw_refer3_tybase_lsb : 32; + } swreg198; + + struct { + RK_U32 sw_refer4_tybase_msb : 32; + } swreg199; + + struct { + RK_U32 sw_refer4_tybase_lsb : 32; + } swreg200; + + struct { + RK_U32 sw_refer5_tybase_msb : 32; + } swreg201; + + struct { + RK_U32 sw_refer5_tybase_lsb : 32; + } swreg202; + + struct { + RK_U32 sw_refer6_tybase_msb : 32; + } swreg203; + + struct { + RK_U32 sw_refer6_tybase_lsb : 32; + } swreg204; + + RK_U32 reserved_205_222[18]; + struct { + RK_U32 sw_dec_out_tcbase_msb : 32; + } swreg223; + + struct { + RK_U32 sw_dec_out_tcbase_lsb : 32; + } swreg224; + + struct { + RK_U32 sw_refer0_tcbase_msb : 32; + } swreg225; + + struct { + RK_U32 sw_refer0_tcbase_lsb : 32; + } swreg226; + + struct { + RK_U32 sw_refer1_tcbase_msb : 32; + } swreg227; + + struct { + RK_U32 sw_refer1_tcbase_lsb : 32; + } swreg228; + + struct { + RK_U32 sw_refer2_tcbase_msb : 32; + } swreg229; + + struct { + RK_U32 sw_refer2_tcbase_lsb : 32; + } swreg230; + + struct { + RK_U32 sw_refer3_tcbase_msb : 32; + } swreg231; + + struct { + RK_U32 sw_refer3_tcbase_lsb : 32; + } swreg232; + + struct { + RK_U32 sw_refer4_tcbase_msb : 32; + } swreg233; + + struct { + RK_U32 sw_refer4_tcbase_lsb : 32; + } swreg234; + + struct { + RK_U32 sw_refer5_tcbase_msb : 32; + } swreg235; + + struct { + RK_U32 sw_refer5_tcbase_lsb : 32; + } swreg236; + + struct { + RK_U32 sw_refer6_tcbase_msb : 32; + } swreg237; + + struct { + RK_U32 sw_refer6_tcbase_lsb : 32; + } swreg238; + + RK_U32 reserved_239_256[18]; + struct { + RK_U32 sw_cur_altref2_roffset : 9; + RK_U32 sw_cur_altref2_offset : 9; + RK_U32 sw_mf3_altref2_offset : 9; + RK_U32 sw_ref5_gm_mode : 2; + RK_U32 reserved0 : 3; + } swreg257; + + struct { + RK_U32 sw_strm_buffer_len : 32; + } swreg258; + + struct { + RK_U32 sw_strm_start_offset : 32; + } swreg259; + + struct { + RK_U32 reserved0 : 21; + RK_U32 sw_ppd_blend_exist : 1; + RK_U32 reserved1 : 1; + RK_U32 sw_ppd_dith_exist : 1; + RK_U32 sw_ablend_crop_e : 1; + RK_U32 sw_pp_format_p010_e : 1; + RK_U32 sw_pp_format_customer1_e : 1; + RK_U32 sw_pp_crop_exist : 1; + RK_U32 sw_pp_up_level : 1; + RK_U32 sw_pp_down_level : 2; + RK_U32 sw_pp_exist : 1; + } swreg260; + + struct { + RK_U32 sw_dec_error_code : 8; + RK_U32 reserved0 : 24; + } swreg261; + + struct { + RK_U32 sw_cur_altref_roffset : 9; + RK_U32 sw_cur_altref_offset : 9; + RK_U32 sw_mf3_altref_offset : 9; + RK_U32 sw_ref6_gm_mode : 2; + RK_U32 reserved0 : 3; + } swreg262; + + struct { + RK_U32 sw_cdef_luma_primary_strength : 32; + } swreg263; + + struct { + RK_U32 sw_cdef_chroma_primary_strength : 32; + } swreg264; + + struct { + RK_U32 sw_axi_arqos : 4; + RK_U32 sw_axi_awqos : 4; + + RK_U32 sw_axi_wr_ostd_threshold : 10; + RK_U32 sw_axi_rd_ostd_threshold : 10; + + RK_U32 reserved0 : 3; + RK_U32 sw_axi_wr_4k_dis : 1; + } swreg265; + + struct { + RK_U32 reserved0 : 5; + RK_U32 sw_128bit_mode : 1; + RK_U32 reserved1 : 4; + RK_U32 sw_wr_shaper_bypass : 1; + RK_U32 reserved2 : 19; + RK_U32 sw_error_conceal_e : 1; + RK_U32 reserved3 : 1; + } swreg266; + + RK_U32 reserved_267_297[31]; + struct { + RK_U32 sw_superres_chroma_step_invra : 16; + RK_U32 sw_superres_luma_step_invra : 16; + } swreg298; + + struct { + RK_U32 sw_dec_pred_dataout_cnt : 32; + } swreg299; + + struct { + RK_U32 sw_dec_axi_r_len_cnt : 32; + } swreg300; + + struct { + RK_U32 sw_dec_axi_r_dat_cnt : 32; + } swreg301; + + struct { + RK_U32 sw_dec_axi_r_req_cnt : 32; + } swreg302; + + struct { + RK_U32 sw_dec_axi_rlast_cnt : 32; + } swreg303; + + struct { + RK_U32 sw_dec_axi_w_len_cnt : 32; + } swreg304; + + struct { + RK_U32 sw_dec_axi_w_dat_cnt : 32; + } swreg305; + + struct { + RK_U32 sw_dec_axi_w_req_cnt : 32; + } swreg306; + + struct { + RK_U32 sw_dec_axi_wlast_cnt : 32; + } swreg307; + + struct { + RK_U32 sw_dec_axi_w_ack : 32; + } swreg308; + + struct { + RK_U32 hw_build_id : 32; + } swreg309; + + struct { + RK_U32 hw_syn_id : 16; + RK_U32 reserved0 : 16; + } swreg310; + + struct { + RK_U32 reserved0 : 32; + } swreg311; + + struct { + RK_U32 reserved0 : 32; + } swreg312; + + struct { + RK_U32 reserved0 : 32; + } swreg313; + + struct { + RK_U32 sw_dec_alignment : 16; + RK_U32 reserved0 : 16; + } swreg314; + + struct { + RK_U32 sw_tile_left : 32; + } swreg315; + + RK_U32 reserved_316; + struct { + RK_U32 reserved0 : 28; + RK_U32 sw_pp_line_cnt_sel : 2; + RK_U32 reserved1 : 2; + } swreg317; + + struct { + RK_U32 sw_ext_timeout_cycles : 31; + RK_U32 sw_ext_timeout_override_e : 1; + } swreg318; + + struct { + RK_U32 sw_timeout_cycles : 31; + RK_U32 sw_timeout_override_e : 1; + } swreg319; + + VdpuAv1dPPCfg vdpu_av1d_pp_cfg; + +} VdpuAv1dRegSet; + +#endif diff --git a/osal/inc/mpp_dev_defs.h b/osal/inc/mpp_dev_defs.h index abd19ab2..2c275b33 100644 --- a/osal/inc/mpp_dev_defs.h +++ b/osal/inc/mpp_dev_defs.h @@ -27,6 +27,7 @@ typedef enum MppClientType_e { VPU_CLIENT_VDPU2 = 1, /* 0x00000002 */ VPU_CLIENT_VDPU1_PP = 2, /* 0x00000004 */ VPU_CLIENT_VDPU2_PP = 3, /* 0x00000008 */ + VPU_CLIENT_AV1DEC = 4, /* 0x00000010 */ VPU_CLIENT_HEVC_DEC = 8, /* 0x00000100 */ VPU_CLIENT_RKVDEC = 9, /* 0x00000200 */ @@ -49,6 +50,7 @@ typedef enum MppClientType_e { #define HAVE_VDPU2 (1 << VPU_CLIENT_VDPU2) /* 0x00000002 */ #define HAVE_VDPU1_PP (1 << VPU_CLIENT_VDPU1_PP) /* 0x00000004 */ #define HAVE_VDPU2_PP (1 << VPU_CLIENT_VDPU2_PP) /* 0x00000008 */ +#define HAVE_AV1DEC (1 << VPU_CLIENT_AV1DEC) /* 0x00000008 */ /* RK standalone decoder */ #define HAVE_HEVC_DEC (1 << VPU_CLIENT_HEVC_DEC) /* 0x00000100 */ #define HAVE_RKVDEC (1 << VPU_CLIENT_RKVDEC) /* 0x00000200 */ diff --git a/osal/inc/mpp_soc.h b/osal/inc/mpp_soc.h index dcdb9a03..2ea24435 100644 --- a/osal/inc/mpp_soc.h +++ b/osal/inc/mpp_soc.h @@ -81,7 +81,7 @@ typedef struct { const RK_U32 vcodec_type; /* Max 4 decoder cap */ - const MppDecHwCap *dec_caps[4]; + const MppDecHwCap *dec_caps[5]; /* Max 4 encoder cap */ const MppEncHwCap *enc_caps[4]; } MppSocInfo; diff --git a/osal/mpp_soc.cpp b/osal/mpp_soc.cpp index 7ce50862..0b257e00 100644 --- a/osal/mpp_soc.cpp +++ b/osal/mpp_soc.cpp @@ -47,10 +47,12 @@ #define HAVE_AVSP ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVSPLUS)))) #define HAVE_AVS ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVS)))) #define HAVE_AVS2 ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVS2)))) +#define HAVE_AV1 ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAV1)))) #define CAP_CODING_VDPU (HAVE_MPEG2|HAVE_H263|HAVE_MPEG4|HAVE_AVC|HAVE_MJPEG|HAVE_VP8) #define CAP_CODING_JPEGD_PP (HAVE_MJPEG) #define CAP_CODING_AVSD (HAVE_AVS) +#define CAP_CODING_AV1D (HAVE_AV1) #define CAP_CODING_HEVC (HAVE_HEVC) #define CAP_CODING_VDPU341 (HAVE_AVC|HAVE_HEVC|HAVE_VP9) #define CAP_CODING_VDPU341_LITE (HAVE_AVC|HAVE_HEVC) @@ -286,6 +288,20 @@ static const MppDecHwCap rkjpegd = { .reserved = 0, }; +static const MppDecHwCap av1d = { + .cap_coding = CAP_CODING_AV1D, + .type = VPU_CLIENT_AV1DEC, + .cap_fbc = 0, + .cap_4k = 1, + .cap_8k = 0, + .cap_colmv_buf = 0, + .cap_hw_h265_rps = 0, + .cap_hw_vp9_prob = 0, + .cap_jpg_pp_out = 0, + .cap_10bit = 0, + .reserved = 0, +}; + static const MppEncHwCap vepu1 = { .cap_coding = CAP_CODING_VEPU1, .type = VPU_CLIENT_VEPU1, @@ -402,21 +418,21 @@ static const MppSocInfo mpp_soc_infos[] = { "rk3036", ROCKCHIP_SOC_RK3036, HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_HEVC_DEC, - { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, }, + { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, }, { NULL, NULL, NULL, NULL, }, }, { /* rk3066 has vpu1 only */ "rk3066", ROCKCHIP_SOC_RK3066, HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1, - { &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, }, + { &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, }, { &vepu1, NULL, NULL, NULL, }, }, { /* rk3188 has vpu1 only */ "rk3188", ROCKCHIP_SOC_RK3188, HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1, - { &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, }, + { &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, }, { &vepu1, NULL, NULL, NULL, }, }, { /* @@ -427,7 +443,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rk3288", ROCKCHIP_SOC_RK3288, HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC, - { &rk_hevc, &vdpu1_2160p, &vdpu1_jpeg_pp, NULL, }, + { &rk_hevc, &vdpu1_2160p, &vdpu1_jpeg_pp, NULL, NULL, }, { &vepu1, NULL, NULL, NULL, }, }, { /* @@ -438,7 +454,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rk3126", ROCKCHIP_SOC_RK312X, HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC, - { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, }, + { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, }, { &vepu1, NULL, NULL, NULL, }, }, { /* @@ -450,7 +466,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rk3128h", ROCKCHIP_SOC_RK3128H, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC, - { &vdpu341_lite_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, }, + { &vdpu341_lite_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, }, { &vepu2_no_jpeg, NULL, NULL, NULL, }, }, { /* @@ -461,7 +477,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rk3128", ROCKCHIP_SOC_RK312X, HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC, - { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, }, + { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, }, { &vepu1, NULL, NULL, NULL, }, }, { /* @@ -472,7 +488,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rk3368", ROCKCHIP_SOC_RK3368, HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC, - { &rk_hevc, &vdpu1, &vdpu1_jpeg_pp, NULL, }, + { &rk_hevc, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, }, { &vepu1, NULL, NULL, NULL, }, }, { /* @@ -483,7 +499,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rk3399", ROCKCHIP_SOC_RK3399, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC, - { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, }, + { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, }, { &vepu2, NULL, NULL, NULL, }, }, { /* @@ -497,7 +513,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rk3228h", ROCKCHIP_SOC_RK3228H, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_AVSDEC | HAVE_VEPU22, - { &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, &avsd, }, + { &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, &avsd, NULL, }, { &vepu2_no_jpeg, &vepu22, NULL, NULL, }, }, { /* @@ -509,7 +525,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rk3328", ROCKCHIP_SOC_RK3328, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_VEPU22, - { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, }, + { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, }, { &vepu2, &vepu22, NULL, NULL, }, }, { /* @@ -521,7 +537,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rk3228", ROCKCHIP_SOC_RK3228, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC, - { &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, NULL, }, + { &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, }, { &vepu2_no_jpeg, NULL, NULL, NULL, }, }, { /* @@ -532,7 +548,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rk3229", ROCKCHIP_SOC_RK3229, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC, - { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, }, + { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, }, { &vepu2, NULL, NULL, NULL, }, }, { /* @@ -544,7 +560,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rv1108", ROCKCHIP_SOC_RV1108, HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC, - { &vdpu2_jpeg, &vdpu341_h264, NULL, NULL, }, + { &vdpu2_jpeg, &vdpu341_h264, NULL, NULL, NULL, }, { &vepu2_jpeg, &vepu540p, NULL, NULL, }, }, { /* @@ -556,7 +572,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rv1109", ROCKCHIP_SOC_RV1109, HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC, - { &vdpu2_jpeg, &vdpu341_lite, NULL, NULL, }, + { &vdpu2_jpeg, &vdpu341_lite, NULL, NULL, NULL, }, { &vepu2_jpeg, &vepu541, NULL, NULL, }, }, { /* @@ -568,7 +584,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rv1126", ROCKCHIP_SOC_RV1126, HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC, - { &vdpu2_jpeg, &vdpu341_lite, NULL, NULL, }, + { &vdpu2_jpeg, &vdpu341_lite, NULL, NULL, NULL, }, { &vepu2_jpeg, &vepu541, NULL, NULL, }, }, { /* @@ -579,7 +595,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rk3326", ROCKCHIP_SOC_RK3326, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_HEVC_DEC, - { &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, }, + { &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, }, { &vepu2, NULL, NULL, NULL, }, }, { /* @@ -590,7 +606,7 @@ static const MppSocInfo mpp_soc_infos[] = { "px30", ROCKCHIP_SOC_RK3326, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_HEVC_DEC, - { &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, }, + { &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, }, { &vepu2, NULL, NULL, NULL, }, }, { /* @@ -599,7 +615,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rk1808", ROCKCHIP_SOC_RK1808, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2, - { &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, }, + { &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, }, { &vepu2, NULL, NULL, NULL, }, }, { /* @@ -612,7 +628,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rk3566", ROCKCHIP_SOC_RK3566, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC, - { &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, }, + { &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, NULL, }, { &vepu540, &vepu2, NULL, NULL, }, }, { /* @@ -625,7 +641,7 @@ static const MppSocInfo mpp_soc_infos[] = { "rk3568", ROCKCHIP_SOC_RK3568, HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC, - { &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, }, + { &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, NULL, }, { &vepu540, &vepu2, NULL, NULL, }, }, { /* @@ -637,8 +653,8 @@ static const MppSocInfo mpp_soc_infos[] = { */ "rk3588", ROCKCHIP_SOC_RK3588, - HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC, - { &vdpu38x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, }, + HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC | HAVE_AV1DEC, + { &vdpu38x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp, &av1d}, { &vepu58x, &vepu2, &vepu2_jpeg, NULL, }, }, };