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chore[hal_h264e]: clean some unused code

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Change-Id: I4b653d72248788ae731ceccc1cca1e8b75390073
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
This commit is contained in:
Yandong Lin
2023-11-09 11:36:54 +08:00
parent 56df2c7409
commit a37666b014
3 changed files with 0 additions and 74 deletions
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33
mpp/hal/rkenc/h264e/hal_h264e_vepu540c.c
View File

@@ -86,9 +86,6 @@ typedef struct HalH264eVepu540cCtx_t {
MppBuffer ext_line_buf;
} HalH264eVepu540cCtx;
static RK_U32 dump_l1_reg = 0;
static RK_U32 dump_l2_reg = 0;
static RK_S32 h264_aq_tthd_default[16] = {
0, 0, 0, 0,
3, 3, 5, 5,
@@ -553,9 +550,6 @@ static void setup_vepu540c_codec(HalVepu540cRegSet *regs, H264eSps *sps,
regs->reg_base.enc_pic.enc_stnd = 0;
regs->reg_base.enc_pic.cur_frm_ref = slice->nal_reference_idc > 0;
regs->reg_base.enc_pic.bs_scp = 1;
//regs->reg013.lamb_mod_sel = (slice->slice_type == H264_I_SLICE) ? 0 : 1;
//regs->reg013.atr_thd_sel = 0;
// regs->reg_ctl.lkt_node_cfg.node_int = 0;
regs->reg_base.synt_nal.nal_ref_idc = slice->nal_reference_idc;
regs->reg_base.synt_nal.nal_unit_type = slice->nalu_type;
@@ -572,7 +566,6 @@ static void setup_vepu540c_codec(HalVepu540cRegSet *regs, H264eSps *sps,
regs->reg_base.synt_pps.pic_init_qp = pps->pic_init_qp;
regs->reg_base.synt_pps.cb_ofst = pps->chroma_qp_index_offset;
regs->reg_base.synt_pps.cr_ofst = pps->second_chroma_qp_index_offset;
// regs->reg_base.synt_pps.wght_pred = pps->weighted_pred;
regs->reg_base.synt_pps.dbf_cp_flg = pps->deblocking_filter_control;
regs->reg_base.synt_sli0.sli_type = (slice->slice_type == H264_I_SLICE) ? (2) : (0);
@@ -1443,18 +1436,6 @@ static void setup_vepu540c_l2(HalVepu540cRegSet *regs, H264eSlice *slice, MppEnc
}
}
mpp_env_get_u32("dump_l2_reg", &dump_l2_reg, 0);
if (dump_l2_reg) {
mpp_log("L2 reg dump start:\n");
RK_U32 *p = (RK_U32 *)regs;
for (i = 0; i < (sizeof(*regs) / sizeof(RK_U32)); i++)
mpp_log("%04x %08x\n", 4 + i * 4, p[i]);
mpp_log("L2 reg done\n");
}
hal_h264e_dbg_func("leave\n");
}
@@ -1520,20 +1501,6 @@ static MPP_RET hal_h264e_vepu540c_gen_regs(void *hal, HalEncTask *task)
vepu540c_set_roi(&ctx->regs_set->reg_rc_roi.roi_cfg, ctx->roi_data,
ctx->cfg->prep.width, ctx->cfg->prep.height);
mpp_env_get_u32("dump_l1_reg", &dump_l1_reg, 0);
if (dump_l1_reg) {
mpp_log("L1 reg dump start:\n");
RK_U32 *p = (RK_U32 *)regs;
RK_S32 n = 0x1D0 / sizeof(RK_U32);
RK_S32 i;
for (i = 0; i < n; i++)
mpp_log("%04x %08x\n", i * 4, p[i]);
mpp_log("L1 reg done\n");
}
ctx->frame_cnt++;
hal_h264e_dbg_func("leave %p\n", hal);

38
mpp/hal/rkenc/h264e/hal_h264e_vepu580.c
View File

@@ -141,8 +141,6 @@ static RK_U32 h264e_klut_weight[30] = {
0xFF83FFFF, 0x000001FF,
};
static RK_U32 dump_l1_reg = 0;
static RK_U32 dump_l2_reg = 0;
static RK_U32 disable_rcb_buf = 0;
static RK_U32 h264_mode_bias[16] = {
@@ -627,7 +625,6 @@ static MPP_RET hal_h264e_vepu580_get_task(void *hal, HalEncTask *task)
static void setup_vepu580_normal(HalVepu580RegSet *regs)
{
hal_h264e_dbg_func("enter\n");
/* reg000 VERSION is read only */
/* reg001 ENC_STRT */
regs->reg_ctl.enc_strt.lkt_num = 0;
@@ -640,9 +637,6 @@ static void setup_vepu580_normal(HalVepu580RegSet *regs)
regs->reg_ctl.enc_clr.safe_clr = 0;
regs->reg_ctl.enc_clr.force_clr = 0;
/* reg003 LKT_ADDR */
// regs->reg_ctl.lkt_addr = 0;
/* reg004 INT_EN */
regs->reg_ctl.int_en.enc_done_en = 1;
regs->reg_ctl.int_en.lkt_node_done_en = 1;
@@ -665,9 +659,6 @@ static void setup_vepu580_normal(HalVepu580RegSet *regs)
regs->reg_ctl.int_msk.rbus_err_msk = 0;
regs->reg_ctl.int_msk.wdg_msk = 0;
/* reg006 INT_CLR is not set */
/* reg007 INT_STA is read only */
/* reg008 ~ reg0011 gap */
regs->reg_ctl.enc_wdg.vs_load_thd = 0x1fffff;
regs->reg_ctl.enc_wdg.rfp_load_thd = 0;
@@ -886,9 +877,6 @@ static void setup_vepu580_codec(HalVepu580RegSet *regs, H264eSps *sps,
regs->reg_base.enc_pic.enc_stnd = 0;
regs->reg_base.enc_pic.cur_frm_ref = slice->nal_reference_idc > 0;
regs->reg_base.enc_pic.bs_scp = 1;
//regs->reg013.lamb_mod_sel = (slice->slice_type == H264_I_SLICE) ? 0 : 1;
//regs->reg013.atr_thd_sel = 0;
// regs->reg_ctl.lkt_node_cfg.node_int = 0;
regs->reg_base.synt_nal.nal_ref_idc = slice->nal_reference_idc;
regs->reg_base.synt_nal.nal_unit_type = slice->nalu_type;
@@ -2039,18 +2027,6 @@ static void setup_vepu580_l2(HalVepu580RegSet *regs, H264eSlice *slice, MppEncHw
}
}
mpp_env_get_u32("dump_l2_reg", &dump_l2_reg, 0);
if (dump_l2_reg) {
mpp_log("L2 reg dump start:\n");
RK_U32 *p = (RK_U32 *)regs;
for (i = 0; i < (sizeof(*regs) / sizeof(RK_U32)); i++)
mpp_log("%04x %08x\n", 4 + i * 4, p[i]);
mpp_log("L2 reg done\n");
}
hal_h264e_dbg_func("leave\n");
}
@@ -2179,20 +2155,6 @@ static MPP_RET hal_h264e_vepu580_gen_regs(void *hal, HalEncTask *task)
if (frm->use_pass1)
vepu580_h264e_use_pass1_patch(regs, ctx);
mpp_env_get_u32("dump_l1_reg", &dump_l1_reg, 0);
if (dump_l1_reg) {
mpp_log("L1 reg dump start:\n");
RK_U32 *p = (RK_U32 *)regs;
RK_S32 n = 0x1D0 / sizeof(RK_U32);
RK_S32 i;
for (i = 0; i < n; i++)
mpp_log("%04x %08x\n", i * 4, p[i]);
mpp_log("L1 reg done\n");
}
ctx->frame_cnt++;
hal_h264e_dbg_func("leave %p\n", hal);

3
mpp/hal/rkenc/h265e/hal_h265e_vepu540c_reg.h
View File

@@ -1135,9 +1135,6 @@ typedef struct HevcVepu540cWgt_t {
/* wgt_qp48_grpa */
/* 0x00001900 reg1600 */
RK_U32 rdo_wgta_qp_grpa_0_51[52];
/* 0x19d0 - 0x1ffc */
// RK_U32 reserved1652_2047[396];
} hevc_vepu540c_wgt;
typedef struct H265eV540cRegSet_t {