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[av1d_vdpu]: fix 10bit fbc confiure
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com> Change-Id: Ie6c387a6cd92ff62dd6c9e1b5e46463c5ec4986c
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@@ -2149,17 +2149,11 @@ MPP_RET vdpu_av1d_gen_regs(void *hal, HalTaskInfo *task)
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vir_right = 16 - ((vir_left + width) % 16);
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else
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vir_right = 0;
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if (!bypass_filter) {
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if (16 - (56 % 16))
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vir_top = 16 - (56 % 16);
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else
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vir_top = 0;
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} else {
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if (((64 - (height % 64))) % 16)
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vir_top = 16 - (((64 - (height % 64))) % 16);
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else
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vir_top = 0;
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}
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if (!bypass_filter)
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vir_top = 8;
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else
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vir_top = 0;
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if (((vir_top + height) % 16))
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vir_bottom = 16 - ((vir_top + height) % 16);
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@@ -2172,7 +2166,7 @@ MPP_RET vdpu_av1d_gen_regs(void *hal, HalTaskInfo *task)
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regs->vdpu_av1d_pp_cfg.swreg503.sw_pp0_virtual_right = vir_right;
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mpp_frame_set_offset_y(mframe, vir_top);
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mpp_frame_set_ver_stride(mframe, vir_top + height + vir_bottom);
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regs->vdpu_av1d_pp_cfg.swreg322.sw_pp_out_format = 3;
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regs->vdpu_av1d_pp_cfg.swreg322.sw_pp_out_format = 0;
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regs->vdpu_av1d_pp_cfg.swreg326.sw_pp_out_lu_base_lsb = mpp_buffer_get_fd(buffer);
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regs->vdpu_av1d_pp_cfg.swreg328.sw_pp_out_ch_base_lsb = mpp_buffer_get_fd(buffer);
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regs->vdpu_av1d_pp_cfg.swreg505.sw_pp0_afbc_tile_base_lsb = mpp_buffer_get_fd(buffer);
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@@ -2180,6 +2174,7 @@ MPP_RET vdpu_av1d_gen_regs(void *hal, HalTaskInfo *task)
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RK_U32 out_w = hor_stride;
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RK_U32 out_h = ver_stride;
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RK_U32 y_stride = out_w * out_h;
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regs->vdpu_av1d_pp_cfg.swreg322.sw_pp_out_format = 0;
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regs->vdpu_av1d_pp_cfg.swreg326.sw_pp_out_lu_base_lsb = mpp_buffer_get_fd(buffer);
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regs->vdpu_av1d_pp_cfg.swreg328.sw_pp_out_ch_base_lsb = mpp_buffer_get_fd(buffer);
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