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[hal_vdpu34x]: Add timeout register definition

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rk3588 vdpu38x (vdpu34x) add timeout register.

Change-Id: I0517c14054b52eb7179f8ec691bcc5dea5deef5f
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
This commit is contained in:
Ding Wei
2021-11-25 08:35:28 +08:00
committed by Herman Chen
parent 624d8493d5
commit 7e1a19a541
4 changed files with 9 additions and 0 deletions
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1
mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c
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@@ -644,6 +644,7 @@ static MPP_RET init_common_regs(Vdpu34xH264dRegSet *regs)
common->reg026.swreg_block_gating_e = 0xffff; common->reg026.swreg_block_gating_e = 0xffff;
common->reg026.block_gating_en_l2 = 0xf; common->reg026.block_gating_en_l2 = 0xf;
common->reg026.reg_cfg_gating_en = 1; common->reg026.reg_cfg_gating_en = 1;
common->reg032_timeout_threshold = 0x0fffffff;
common->reg011.dec_clkgate_e = 1; common->reg011.dec_clkgate_e = 1;
common->reg011.dec_e_strmd_clkgate_dis = 0; common->reg011.dec_e_strmd_clkgate_dis = 0;

1
mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
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@@ -1009,6 +1009,7 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
hw_regs->common.reg026.swreg_block_gating_e = 0xffff; hw_regs->common.reg026.swreg_block_gating_e = 0xffff;
hw_regs->common.reg026.block_gating_en_l2 = 0xf; hw_regs->common.reg026.block_gating_en_l2 = 0xf;
hw_regs->common.reg026.reg_cfg_gating_en = 1; hw_regs->common.reg026.reg_cfg_gating_en = 1;
hw_regs->common.reg032_timeout_threshold = 0x0fffffff;
valid_ref = hw_regs->common_addr.reg130_decout_base; valid_ref = hw_regs->common_addr.reg130_decout_base;
reg_cxt->error_index = dxva_cxt->pp.CurrPic.Index7Bits; reg_cxt->error_index = dxva_cxt->pp.CurrPic.Index7Bits;

5
mpp/hal/rkdec/inc/vdpu34x_com.h
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@@ -219,6 +219,11 @@ typedef struct Vdpu34xRegCommon_t {
RK_U32 reserve : 11; RK_U32 reserve : 11;
RK_U32 reg_cfg_gating_en : 1; RK_U32 reg_cfg_gating_en : 1;
} reg026; } reg026;
/* NOTE: reg027 ~ reg032 are added in vdpu38x at rk3588 */
RK_U32 reg027_031[5];
/* NOTE: timeout must be config in vdpu38x */
RK_U32 reg032_timeout_threshold;
} Vdpu34xRegCommon; } Vdpu34xRegCommon;
/* base: OFFSET_COMMON_ADDR_REGS */ /* base: OFFSET_COMMON_ADDR_REGS */

2
mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c
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@@ -740,6 +740,8 @@ static MPP_RET hal_vp9d_vdpu34x_gen_regs(void *hal, HalTaskInfo *task)
vp9_hw_regs->common.reg010.dec_e = 1; vp9_hw_regs->common.reg010.dec_e = 1;
vp9_hw_regs->common.reg011.dec_timeout_e = 1; vp9_hw_regs->common.reg011.dec_timeout_e = 1;
vp9_hw_regs->common.reg011.buf_empty_en = 1; vp9_hw_regs->common.reg011.buf_empty_en = 1;
vp9_hw_regs->common.reg013.timeout_mode = 1;
vp9_hw_regs->common.reg032_timeout_threshold = 0x0fffffff;
//last info update //last info update
hw_ctx->ls_info.abs_delta_last = pic_param->stVP9Segments.abs_delta; hw_ctx->ls_info.abs_delta_last = pic_param->stVP9Segments.abs_delta;