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fix[hal_h265d]: Allow reference missing for GDR

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1. Keep decoding when the reference frame is not valid.
2. For RK3588, improve decoding speed and result when decoding a
   non-IDR picture of a GDR stream.

Change-Id: Iae3ac63b05349e4ba923d6df03f89c2958ad72a1
Signed-off-by: Johnson Ding <johnson.ding@rock-chips.com>
This commit is contained in:
Johnson Ding
2024-08-13 17:08:10 +08:00
committed by Herman Chen
parent c367dd1609
commit 79b24a631b
4 changed files with 51 additions and 34 deletions
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2
mpp/hal/rkdec/h265d/hal_h265d_ctx.h
View File

@@ -87,6 +87,8 @@ typedef struct HalH265dCtx_t {
void *pps_buf;
void *sw_rps_buf;
HalBufs origin_bufs;
MppBuffer missing_ref_buf;
RK_U32 missing_ref_buf_size;
const MppDecHwCap *hw_info;
} HalH265dCtx;

78
mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
View File

@@ -192,6 +192,11 @@ static MPP_RET hal_h265d_vdpu34x_deinit(void *hal)
}
}
if (reg_ctx->missing_ref_buf) {
mpp_buffer_put(reg_ctx->missing_ref_buf);
reg_ctx->missing_ref_buf = NULL;
}
if (reg_ctx->group) {
mpp_buffer_group_put(reg_ctx->group);
reg_ctx->group = NULL;
@@ -1057,68 +1062,77 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
dxva_cxt->pp.RefPicList[i].bPicEntry != 0x7f) {
MppFrame mframe = NULL;
MppBuffer ref_buf = NULL;
hw_regs->h265d_param.reg67_82_ref_poc[i] = dxva_cxt->pp.PicOrderCntValList[i];
mpp_buf_slot_get_prop(reg_ctx->slots,
dxva_cxt->pp.RefPicList[i].Index7Bits,
SLOT_BUFFER, &framebuf);
SLOT_BUFFER, &ref_buf);
mpp_buf_slot_get_prop(reg_ctx->slots, dxva_cxt->pp.RefPicList[i].Index7Bits,
SLOT_FRAME_PTR, &mframe);
if (framebuf != NULL) {
hw_regs->h265d_addr.reg164_179_ref_base[i] = mpp_buffer_get_fd(framebuf);
if (!ref_buf && mpp_get_soc_type() == ROCKCHIP_SOC_RK3588 &&
reg_ctx->cfg->base.disable_error) {
if (reg_ctx->missing_ref_buf && reg_ctx->missing_ref_buf_size < mpp_buffer_get_size(framebuf)) {
mpp_buffer_put(reg_ctx->missing_ref_buf);
reg_ctx->missing_ref_buf = NULL;
}
if (!reg_ctx->missing_ref_buf) {
reg_ctx->missing_ref_buf_size = mpp_buffer_get_size(framebuf);
mpp_buffer_get(reg_ctx->group, &reg_ctx->missing_ref_buf, reg_ctx->missing_ref_buf_size);
if (!reg_ctx->missing_ref_buf) {
syn->dec.flags.ref_err = 1;
h265h_dbg(H265H_DBG_TASK_ERR, "Failed to generate missing ref buf\n");
return MPP_ERR_NOMEM;
}
}
ref_buf = reg_ctx->missing_ref_buf;
}
if (ref_buf) {
hw_regs->h265d_addr.reg164_179_ref_base[i] = mpp_buffer_get_fd(ref_buf);
valid_ref = hw_regs->h265d_addr.reg164_179_ref_base[i];
// mpp_log("cur poc %d, ref poc %d", dxva_cxt->pp.current_poc, dxva_cxt->pp.PicOrderCntValList[i]);
h265h_dbg(H265H_DBG_TASK_ERR, "cur poc %d, ref poc %d", dxva_cxt->pp.current_poc, dxva_cxt->pp.PicOrderCntValList[i]);
if ((pocdistance(dxva_cxt->pp.PicOrderCntValList[i], dxva_cxt->pp.current_poc) < distance)
&& (!mpp_frame_get_errinfo(mframe))) {
distance = pocdistance(dxva_cxt->pp.PicOrderCntValList[i], dxva_cxt->pp.current_poc);
hw_regs->common_addr.reg132_error_ref_base = hw_regs->h265d_addr.reg164_179_ref_base[i];
reg_ctx->error_index[syn->dec.reg_index] = dxva_cxt->pp.RefPicList[i].Index7Bits;
hw_regs->common.reg021.error_intra_mode = 0;
h265h_dbg(H265H_DBG_TASK_ERR, "update error ref to ref[%d] to poc %d, slot_idx %d, fd %d\n",
i, dxva_cxt->pp.PicOrderCntValList[i],
dxva_cxt->pp.RefPicList[i].Index7Bits,
hw_regs->common_addr.reg132_error_ref_base);
}
} else {
h265h_dbg(H265H_DBG_TASK_ERR, "ref[%d] buffer is empty, replace with fd %d\n", i, valid_ref);
hw_regs->h265d_addr.reg164_179_ref_base[i] = valid_ref;
}
mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, dxva_cxt->pp.RefPicList[i].Index7Bits);
hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
SET_REF_VALID(hw_regs->h265d_param, i, 1);
}
}
if ((reg_ctx->error_index[syn->dec.reg_index] == dxva_cxt->pp.CurrPic.Index7Bits) && !dxva_cxt->pp.IntraPicFlag) {
h265h_dbg(H265H_DBG_TASK_ERR, "current frm may be err, should skip process");
syn->dec.flags.ref_err = 1;
return MPP_OK;
}
if (hw_regs->common.reg013.h26x_error_mode &&
!hw_regs->common.reg021.error_intra_mode &&
(!ref_buf || mpp_frame_get_errinfo(mframe))) {
for (i = 0; i < (RK_S32)MPP_ARRAY_ELEMS(dxva_cxt->pp.RefPicList); i++) {
if (dxva_cxt->pp.RefPicList[i].bPicEntry != 0xff &&
dxva_cxt->pp.RefPicList[i].bPicEntry != 0x7f) {
if (!hw_regs->common.reg021.error_intra_mode) {
MppFrame mframe = NULL;
mpp_buf_slot_get_prop(reg_ctx->slots,
dxva_cxt->pp.RefPicList[i].Index7Bits,
SLOT_BUFFER, &framebuf);
mpp_buf_slot_get_prop(reg_ctx->slots, dxva_cxt->pp.RefPicList[i].Index7Bits,
SLOT_FRAME_PTR, &mframe);
if (framebuf == NULL || mpp_frame_get_errinfo(mframe)) {
mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]);
hw_regs->h265d_addr.reg164_179_ref_base[i] = hw_regs->common_addr.reg132_error_ref_base;
hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
}
mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]);
hw_regs->h265d_addr.reg164_179_ref_base[i] = hw_regs->common_addr.reg132_error_ref_base;
}
} else {
mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]);
hw_regs->h265d_addr.reg164_179_ref_base[i] = hw_regs->common_addr.reg132_error_ref_base;
hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
/* mark 3 to differ from current frame */
if (reg_ctx->error_index[syn->dec.reg_index] == dxva_cxt->pp.CurrPic.Index7Bits)
SET_POC_HIGNBIT_INFO(hw_regs->highpoc, i, poc_highbit, 3);
}
hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
}
if ((reg_ctx->error_index[syn->dec.reg_index] == dxva_cxt->pp.CurrPic.Index7Bits) &&
!dxva_cxt->pp.IntraPicFlag && !reg_ctx->cfg->base.disable_error) {
h265h_dbg(H265H_DBG_TASK_ERR, "current frm may be err, should skip process");
syn->dec.flags.ref_err = 1;
return MPP_OK;
}
trans_cfg.reg_idx = 161;

3
mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c
View File

@@ -877,7 +877,8 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal, HalTaskInfo *syn)
}
}
if ((reg_ctx->error_index[syn->dec.reg_index] == dxva_cxt->pp.CurrPic.Index7Bits) && !dxva_cxt->pp.IntraPicFlag) {
if ((reg_ctx->error_index[syn->dec.reg_index] == dxva_cxt->pp.CurrPic.Index7Bits) &&
!dxva_cxt->pp.IntraPicFlag && !reg_ctx->cfg->base.disable_error) {
h265h_dbg(H265H_DBG_TASK_ERR, "current frm may be err, should skip process");
syn->dec.flags.ref_err = 1;
return MPP_OK;

2
mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c
View File

@@ -1161,7 +1161,7 @@ static MPP_RET hal_h265d_vdpu383_gen_regs(void *hal, HalTaskInfo *syn)
}
if ((reg_ctx->error_index[syn->dec.reg_index] == dxva_ctx->pp.CurrPic.Index7Bits) &&
!dxva_ctx->pp.IntraPicFlag) {
!dxva_ctx->pp.IntraPicFlag && !reg_ctx->cfg->base.disable_error) {
h265h_dbg(H265H_DBG_TASK_ERR, "current frm may be err, should skip process");
syn->dec.flags.ref_err = 1;
return MPP_OK;