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[misc]: Add compatible for fbc header alignment

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Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: I0ae4ec4b8603648a7186d0cccf63aa3ea3fb29b3
This commit is contained in:
Herman Chen
2022-12-23 16:38:54 +08:00
parent f115d415b4
commit 5469f9d08b
14 changed files with 57 additions and 33 deletions
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1
inc/mpp_compat.h
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@@ -23,6 +23,7 @@
typedef enum MppCompatId_e { typedef enum MppCompatId_e {
MPP_COMPAT_INC_FBC_BUF_SIZE, MPP_COMPAT_INC_FBC_BUF_SIZE,
MPP_COMPAT_ENC_ASYNC_INPUT, MPP_COMPAT_ENC_ASYNC_INPUT,
MPP_COMPAT_DEC_FBC_HDR_256_ODD,
MPP_COMPAT_BUTT, MPP_COMPAT_BUTT,
} MppCompatId; } MppCompatId;

2
mpp/codec/dec/h264/h264d_init.c
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@@ -473,6 +473,8 @@ static MPP_RET dpb_mark_malloc(H264dVideoCtx_t *p_Vid, H264_StorePic_t *dec_pic)
impl->ver_stride += 16; impl->ver_stride += 16;
impl->fbc_hdr_stride = MPP_ALIGN(impl->width, 64); impl->fbc_hdr_stride = MPP_ALIGN(impl->width, 64);
if (*compat_ext_fbc_hdr_256_odd)
impl->fbc_hdr_stride = MPP_ALIGN(impl->width, 256) | 256;
} }
/* After cropped */ /* After cropped */

7
mpp/codec/dec/h265/h265d_refs.c
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@@ -100,6 +100,8 @@ static HEVCFrame *alloc_frame(HEVCContext *s)
mpp_frame_set_fmt(frame->frame, s->h265dctx->pix_fmt); mpp_frame_set_fmt(frame->frame, s->h265dctx->pix_fmt);
if (MPP_FRAME_FMT_IS_FBC(s->h265dctx->pix_fmt)) { if (MPP_FRAME_FMT_IS_FBC(s->h265dctx->pix_fmt)) {
RK_U32 fbc_hdr_stride = MPP_ALIGN(s->h265dctx->width, 64);
mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, hor_align_64); mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, hor_align_64);
mpp_frame_set_offset_x(frame->frame, 0); mpp_frame_set_offset_x(frame->frame, 0);
mpp_frame_set_offset_y(frame->frame, 4); mpp_frame_set_offset_y(frame->frame, 4);
@@ -107,7 +109,10 @@ static HEVCFrame *alloc_frame(HEVCContext *s)
if (*compat_ext_fbc_buf_size) if (*compat_ext_fbc_buf_size)
mpp_frame_set_ver_stride(frame->frame, s->h265dctx->coded_height + 16); mpp_frame_set_ver_stride(frame->frame, s->h265dctx->coded_height + 16);
mpp_frame_set_fbc_hdr_stride(frame->frame, MPP_ALIGN(s->h265dctx->width, 64)); if (*compat_ext_fbc_hdr_256_odd)
fbc_hdr_stride = MPP_ALIGN(s->h265dctx->width, 256) | 256;
mpp_frame_set_fbc_hdr_stride(frame->frame, fbc_hdr_stride);
} else { } else {
if ((s->h265dctx->cfg->base.enable_vproc & MPP_VPROC_MODE_DETECTION) && if ((s->h265dctx->cfg->base.enable_vproc & MPP_VPROC_MODE_DETECTION) &&
s->h265dctx->width <= 1920 && s->h265dctx->height <= 1088) s->h265dctx->width <= 1920 && s->h265dctx->height <= 1088)

9
mpp/codec/dec/vp9/vp9d_parser.c
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@@ -24,6 +24,7 @@
#include "mpp_common.h" #include "mpp_common.h"
#include "mpp_bitread.h" #include "mpp_bitread.h"
#include "mpp_packet_impl.h" #include "mpp_packet_impl.h"
#include "mpp_compat_impl.h"
#include "vp9data.h" #include "vp9data.h"
#include "vp9d_codec.h" #include "vp9d_codec.h"
@@ -402,9 +403,15 @@ static RK_S32 vp9_alloc_frame(Vp9CodecContext *ctx, VP9Frame *frame)
mpp_frame_set_poc(frame->f, s->cur_poc); mpp_frame_set_poc(frame->f, s->cur_poc);
if (MPP_FRAME_FMT_IS_FBC(s->cfg->base.out_fmt)) { if (MPP_FRAME_FMT_IS_FBC(s->cfg->base.out_fmt)) {
RK_U32 fbc_hdr_stride = MPP_ALIGN(ctx->width, 64);
mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, hor_align_64); mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, hor_align_64);
mpp_frame_set_fmt(frame->f, ctx->pix_fmt | ((s->cfg->base.out_fmt & (MPP_FRAME_FBC_MASK)))); mpp_frame_set_fmt(frame->f, ctx->pix_fmt | ((s->cfg->base.out_fmt & (MPP_FRAME_FBC_MASK))));
mpp_frame_set_fbc_hdr_stride(frame->f, MPP_ALIGN(ctx->width, 64));
if (*compat_ext_fbc_hdr_256_odd)
fbc_hdr_stride = MPP_ALIGN(ctx->width, 256) | 256;
mpp_frame_set_fbc_hdr_stride(frame->f, fbc_hdr_stride);
} else } else
mpp_frame_set_fmt(frame->f, ctx->pix_fmt); mpp_frame_set_fmt(frame->f, ctx->pix_fmt);

8
mpp/hal/rkdec/avs2d/hal_avs2d_rkv.c
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@@ -343,12 +343,12 @@ static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu34xAvs2dRegSet *p_regs,
AVS2D_HAL_TRACE("is_fbc %d y_virstride %d, hor_virstride %d, ver_virstride %d\n", is_fbc, y_virstride, hor_virstride, ver_virstride); AVS2D_HAL_TRACE("is_fbc %d y_virstride %d, hor_virstride %d, ver_virstride %d\n", is_fbc, y_virstride, hor_virstride, ver_virstride);
if (is_fbc) { if (is_fbc) {
RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64); RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
RK_U32 fbd_offset = MPP_ALIGN(pixel_width * (ver_virstride + 16) / 16, SZ_4K); RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K);
common->reg012.fbc_e = 1; common->reg012.fbc_e = 1;
common->reg018.y_hor_virstride = pixel_width / 16; common->reg018.y_hor_virstride = fbc_hdr_stride / 16;
common->reg019.uv_hor_virstride = pixel_width / 16; common->reg019.uv_hor_virstride = fbc_hdr_stride / 16;
common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4; common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
} else { } else {
common->reg012.fbc_e = 0; common->reg012.fbc_e = 0;

8
mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c
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@@ -346,12 +346,12 @@ static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu382Avs2dRegSet *p_regs,
AVS2D_HAL_TRACE("is_fbc %d y_virstride %d, hor_virstride %d, ver_virstride %d\n", is_fbc, y_virstride, hor_virstride, ver_virstride); AVS2D_HAL_TRACE("is_fbc %d y_virstride %d, hor_virstride %d, ver_virstride %d\n", is_fbc, y_virstride, hor_virstride, ver_virstride);
if (is_fbc) { if (is_fbc) {
RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64); RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
RK_U32 fbd_offset = MPP_ALIGN(pixel_width * (ver_virstride + 16) / 16, SZ_4K); RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K);
common->reg012.fbc_e = 1; common->reg012.fbc_e = 1;
common->reg018.y_hor_virstride = pixel_width / 16; common->reg018.y_hor_virstride = fbc_hdr_stride / 16;
common->reg019.uv_hor_virstride = pixel_width / 16; common->reg019.uv_hor_virstride = fbc_hdr_stride / 16;
common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4; common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
} else { } else {
common->reg012.fbc_e = 0; common->reg012.fbc_e = 0;

8
mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c
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@@ -552,12 +552,12 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal
y_virstride = hor_virstride * ver_virstride; y_virstride = hor_virstride * ver_virstride;
if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) { if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64); RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
RK_U32 fbd_offset = MPP_ALIGN(pixel_width * (ver_virstride + 16) / 16, SZ_4K); RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K);
common->reg012.fbc_e = 1; common->reg012.fbc_e = 1;
common->reg018.y_hor_virstride = pixel_width / 16; common->reg018.y_hor_virstride = fbc_hdr_stride / 16;
common->reg019.uv_hor_virstride = pixel_width / 16; common->reg019.uv_hor_virstride = fbc_hdr_stride / 16;
common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4; common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
} else { } else {
common->reg012.fbc_e = 0; common->reg012.fbc_e = 0;

8
mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c
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@@ -554,12 +554,12 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu382H264dRegSet *regs, Hal
y_virstride = hor_virstride * ver_virstride; y_virstride = hor_virstride * ver_virstride;
if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) { if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64); RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
RK_U32 fbd_offset = MPP_ALIGN(pixel_width * (ver_virstride + 16) / 16, SZ_4K); RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K);
common->reg012.fbc_e = 1; common->reg012.fbc_e = 1;
common->reg018.y_hor_virstride = pixel_width / 16; common->reg018.y_hor_virstride = fbc_hdr_stride / 16;
common->reg019.uv_hor_virstride = pixel_width / 16; common->reg019.uv_hor_virstride = fbc_hdr_stride / 16;
common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4; common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
} else { } else {
common->reg012.fbc_e = 0; common->reg012.fbc_e = 0;

9
mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
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@@ -954,13 +954,12 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal, HalTaskInfo *syn)
hw_regs->h265d_param.reg64.h26x_stream_mode = 0; hw_regs->h265d_param.reg64.h26x_stream_mode = 0;
if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) { if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64); RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
RK_U32 fbd_offset = MPP_ALIGN(pixel_width * (MPP_ALIGN(ver_virstride, 64) + 16) / 16, RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 64) / 16, SZ_4K);
SZ_4K);
hw_regs->common.reg012.fbc_e = 1; hw_regs->common.reg012.fbc_e = 1;
hw_regs->common.reg018.y_hor_virstride = pixel_width >> 4; hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4;
hw_regs->common.reg019.uv_hor_virstride = pixel_width >> 4; hw_regs->common.reg019.uv_hor_virstride = fbc_hdr_stride >> 4;
hw_regs->common.reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4; hw_regs->common.reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
} else { } else {
hw_regs->common.reg012.fbc_e = 0; hw_regs->common.reg012.fbc_e = 0;

9
mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c
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@@ -727,13 +727,12 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal, HalTaskInfo *syn)
hw_regs->h265d_param.reg64.h26x_stream_mode = 0; hw_regs->h265d_param.reg64.h26x_stream_mode = 0;
if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) { if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64); RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
RK_U32 fbd_offset = MPP_ALIGN(pixel_width * (MPP_ALIGN(ver_virstride, 64) + 16) / 16, RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 64) / 16, SZ_4K);
SZ_4K);
hw_regs->common.reg012.fbc_e = 1; hw_regs->common.reg012.fbc_e = 1;
hw_regs->common.reg018.y_hor_virstride = pixel_width >> 4; hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4;
hw_regs->common.reg019.uv_hor_virstride = pixel_width >> 4; hw_regs->common.reg019.uv_hor_virstride = fbc_hdr_stride >> 4;
hw_regs->common.reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4; hw_regs->common.reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
} else { } else {
hw_regs->common.reg012.fbc_e = 0; hw_regs->common.reg012.fbc_e = 0;

3
mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c
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@@ -598,7 +598,8 @@ static MPP_RET hal_vp9d_vdpu34x_gen_regs(void *hal, HalTaskInfo *task)
if (fbc_en) { if (fbc_en) {
RK_U32 w = MPP_ALIGN(mpp_frame_get_width(mframe), 64); RK_U32 w = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 64); RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 64);
RK_U32 fbd_offset = MPP_ALIGN(w * (h + 16) / 16, SZ_4K); RK_U32 fbd_offset = MPP_ALIGN(mpp_frame_get_fbc_hdr_stride(mframe) *
(h + 16) / 16, SZ_4K);
vp9_hw_regs->common.reg012.fbc_e = 1; vp9_hw_regs->common.reg012.fbc_e = 1;
vp9_hw_regs->common.reg018.y_hor_virstride = w >> 4; vp9_hw_regs->common.reg018.y_hor_virstride = w >> 4;

8
mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.c
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@@ -596,13 +596,13 @@ static MPP_RET hal_vp9d_vdpu382_gen_regs(void *hal, HalTaskInfo *task)
fbc_en = MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe)); fbc_en = MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe));
if (fbc_en) { if (fbc_en) {
RK_U32 w = MPP_ALIGN(mpp_frame_get_width(mframe), 64); RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 64); RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 64);
RK_U32 fbd_offset = MPP_ALIGN(w * (h + 16) / 16, SZ_4K); RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (h + 16) / 16, SZ_4K);
vp9_hw_regs->common.reg012.fbc_e = 1; vp9_hw_regs->common.reg012.fbc_e = 1;
vp9_hw_regs->common.reg018.y_hor_virstride = w >> 4; vp9_hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4;
vp9_hw_regs->common.reg019.uv_hor_virstride = w >> 4; vp9_hw_regs->common.reg019.uv_hor_virstride = fbc_hdr_stride >> 4;
vp9_hw_regs->common.reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4; vp9_hw_regs->common.reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
} else { } else {
sw_y_hor_virstride = (vp9_hor_align((pic_param->width * bit_depth) >> 3) >> 4); sw_y_hor_virstride = (vp9_hor_align((pic_param->width * bit_depth) >> 3) >> 4);

1
osal/inc/mpp_compat_impl.h
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@@ -21,5 +21,6 @@
extern RK_S32 *compat_ext_fbc_buf_size; extern RK_S32 *compat_ext_fbc_buf_size;
extern RK_S32 *compat_ext_async_input; extern RK_S32 *compat_ext_async_input;
extern RK_S32 *compat_ext_fbc_hdr_256_odd;
#endif /*__MPP_COMPAT_IMPL_H__*/ #endif /*__MPP_COMPAT_IMPL_H__*/

9
osal/mpp_compat.cpp
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@@ -48,10 +48,19 @@ static MppCompat compats[] = {
"support encoder async input mode", "support encoder async input mode",
NULL, NULL,
}, },
{
MPP_COMPAT_DEC_FBC_HDR_256_ODD,
MPP_COMPAT_BOOL,
0,
0,
"set decoder fbc header stride to 256 odd align",
NULL,
},
}; };
RK_S32 *compat_ext_fbc_buf_size = &compats[MPP_COMPAT_INC_FBC_BUF_SIZE].value_usr; RK_S32 *compat_ext_fbc_buf_size = &compats[MPP_COMPAT_INC_FBC_BUF_SIZE].value_usr;
RK_S32 *compat_ext_async_input = &compats[MPP_COMPAT_ENC_ASYNC_INPUT].value_usr; RK_S32 *compat_ext_async_input = &compats[MPP_COMPAT_ENC_ASYNC_INPUT].value_usr;
RK_S32 *compat_ext_fbc_hdr_256_odd = &compats[MPP_COMPAT_DEC_FBC_HDR_256_ODD].value_usr;
MppCompat *mpp_compat_query(void) MppCompat *mpp_compat_query(void)
{ {