diff --git a/inc/mpp_compat.h b/inc/mpp_compat.h
index 239b3d89..22a3f17d 100644
--- a/inc/mpp_compat.h
+++ b/inc/mpp_compat.h
@@ -23,6 +23,7 @@
 typedef enum MppCompatId_e {
     MPP_COMPAT_INC_FBC_BUF_SIZE,
     MPP_COMPAT_ENC_ASYNC_INPUT,
+    MPP_COMPAT_DEC_FBC_HDR_256_ODD,
     MPP_COMPAT_BUTT,
 } MppCompatId;
 
diff --git a/mpp/codec/dec/h264/h264d_init.c b/mpp/codec/dec/h264/h264d_init.c
index 69d2f585..47ee140e 100644
--- a/mpp/codec/dec/h264/h264d_init.c
+++ b/mpp/codec/dec/h264/h264d_init.c
@@ -473,6 +473,8 @@ static MPP_RET dpb_mark_malloc(H264dVideoCtx_t *p_Vid, H264_StorePic_t *dec_pic)
                     impl->ver_stride += 16;
 
                 impl->fbc_hdr_stride =  MPP_ALIGN(impl->width, 64);
+                if (*compat_ext_fbc_hdr_256_odd)
+                    impl->fbc_hdr_stride =  MPP_ALIGN(impl->width, 256) | 256;
             }
 
             /* After cropped */
diff --git a/mpp/codec/dec/h265/h265d_refs.c b/mpp/codec/dec/h265/h265d_refs.c
index fb2a7dcd..e9074845 100644
--- a/mpp/codec/dec/h265/h265d_refs.c
+++ b/mpp/codec/dec/h265/h265d_refs.c
@@ -100,6 +100,8 @@ static HEVCFrame *alloc_frame(HEVCContext *s)
         mpp_frame_set_fmt(frame->frame, s->h265dctx->pix_fmt);
 
         if (MPP_FRAME_FMT_IS_FBC(s->h265dctx->pix_fmt)) {
+            RK_U32 fbc_hdr_stride = MPP_ALIGN(s->h265dctx->width, 64);
+
             mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, hor_align_64);
             mpp_frame_set_offset_x(frame->frame, 0);
             mpp_frame_set_offset_y(frame->frame, 4);
@@ -107,7 +109,10 @@ static HEVCFrame *alloc_frame(HEVCContext *s)
             if (*compat_ext_fbc_buf_size)
                 mpp_frame_set_ver_stride(frame->frame, s->h265dctx->coded_height + 16);
 
-            mpp_frame_set_fbc_hdr_stride(frame->frame, MPP_ALIGN(s->h265dctx->width, 64));
+            if (*compat_ext_fbc_hdr_256_odd)
+                fbc_hdr_stride = MPP_ALIGN(s->h265dctx->width, 256) | 256;
+
+            mpp_frame_set_fbc_hdr_stride(frame->frame, fbc_hdr_stride);
         } else {
             if ((s->h265dctx->cfg->base.enable_vproc & MPP_VPROC_MODE_DETECTION) &&
                 s->h265dctx->width <= 1920 &&  s->h265dctx->height <= 1088)
diff --git a/mpp/codec/dec/vp9/vp9d_parser.c b/mpp/codec/dec/vp9/vp9d_parser.c
index e070ebe6..538b44b6 100644
--- a/mpp/codec/dec/vp9/vp9d_parser.c
+++ b/mpp/codec/dec/vp9/vp9d_parser.c
@@ -24,6 +24,7 @@
 #include "mpp_common.h"
 #include "mpp_bitread.h"
 #include "mpp_packet_impl.h"
+#include "mpp_compat_impl.h"
 
 #include "vp9data.h"
 #include "vp9d_codec.h"
@@ -402,9 +403,15 @@ static RK_S32 vp9_alloc_frame(Vp9CodecContext *ctx, VP9Frame *frame)
     mpp_frame_set_poc(frame->f, s->cur_poc);
 
     if (MPP_FRAME_FMT_IS_FBC(s->cfg->base.out_fmt)) {
+        RK_U32 fbc_hdr_stride = MPP_ALIGN(ctx->width, 64);
+
         mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, hor_align_64);
         mpp_frame_set_fmt(frame->f, ctx->pix_fmt | ((s->cfg->base.out_fmt & (MPP_FRAME_FBC_MASK))));
-        mpp_frame_set_fbc_hdr_stride(frame->f, MPP_ALIGN(ctx->width, 64));
+
+        if (*compat_ext_fbc_hdr_256_odd)
+            fbc_hdr_stride = MPP_ALIGN(ctx->width, 256) | 256;
+
+        mpp_frame_set_fbc_hdr_stride(frame->f, fbc_hdr_stride);
     } else
         mpp_frame_set_fmt(frame->f, ctx->pix_fmt);
 
diff --git a/mpp/hal/rkdec/avs2d/hal_avs2d_rkv.c b/mpp/hal/rkdec/avs2d/hal_avs2d_rkv.c
index 2c134540..11ab6542 100644
--- a/mpp/hal/rkdec/avs2d/hal_avs2d_rkv.c
+++ b/mpp/hal/rkdec/avs2d/hal_avs2d_rkv.c
@@ -343,12 +343,12 @@ static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu34xAvs2dRegSet *p_regs,
         AVS2D_HAL_TRACE("is_fbc %d y_virstride %d, hor_virstride %d, ver_virstride %d\n", is_fbc, y_virstride, hor_virstride, ver_virstride);
 
         if (is_fbc) {
-            RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
-            RK_U32 fbd_offset = MPP_ALIGN(pixel_width * (ver_virstride + 16) / 16, SZ_4K);
+            RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
+            RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K);
 
             common->reg012.fbc_e = 1;
-            common->reg018.y_hor_virstride = pixel_width / 16;
-            common->reg019.uv_hor_virstride = pixel_width / 16;
+            common->reg018.y_hor_virstride = fbc_hdr_stride / 16;
+            common->reg019.uv_hor_virstride = fbc_hdr_stride / 16;
             common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
         } else {
             common->reg012.fbc_e = 0;
diff --git a/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c
index 8b0945a5..86890238 100644
--- a/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c
+++ b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c
@@ -346,12 +346,12 @@ static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu382Avs2dRegSet *p_regs,
         AVS2D_HAL_TRACE("is_fbc %d y_virstride %d, hor_virstride %d, ver_virstride %d\n", is_fbc, y_virstride, hor_virstride, ver_virstride);
 
         if (is_fbc) {
-            RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
-            RK_U32 fbd_offset = MPP_ALIGN(pixel_width * (ver_virstride + 16) / 16, SZ_4K);
+            RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
+            RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K);
 
             common->reg012.fbc_e = 1;
-            common->reg018.y_hor_virstride = pixel_width / 16;
-            common->reg019.uv_hor_virstride = pixel_width / 16;
+            common->reg018.y_hor_virstride = fbc_hdr_stride / 16;
+            common->reg019.uv_hor_virstride = fbc_hdr_stride / 16;
             common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
         } else {
             common->reg012.fbc_e = 0;
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c
index 63c9699d..2bef9e3a 100644
--- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c
+++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c
@@ -552,12 +552,12 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu34xH264dRegSet *regs, Hal
         y_virstride = hor_virstride * ver_virstride;
 
         if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
-            RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
-            RK_U32 fbd_offset = MPP_ALIGN(pixel_width * (ver_virstride + 16) / 16, SZ_4K);
+            RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
+            RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K);
 
             common->reg012.fbc_e = 1;
-            common->reg018.y_hor_virstride = pixel_width / 16;
-            common->reg019.uv_hor_virstride = pixel_width / 16;
+            common->reg018.y_hor_virstride = fbc_hdr_stride / 16;
+            common->reg019.uv_hor_virstride = fbc_hdr_stride / 16;
             common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
         } else {
             common->reg012.fbc_e = 0;
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c
index 986679f8..0eecc6bc 100644
--- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c
+++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c
@@ -554,12 +554,12 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu382H264dRegSet *regs, Hal
         y_virstride = hor_virstride * ver_virstride;
 
         if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
-            RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
-            RK_U32 fbd_offset = MPP_ALIGN(pixel_width * (ver_virstride + 16) / 16, SZ_4K);
+            RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
+            RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K);
 
             common->reg012.fbc_e = 1;
-            common->reg018.y_hor_virstride = pixel_width / 16;
-            common->reg019.uv_hor_virstride = pixel_width / 16;
+            common->reg018.y_hor_virstride = fbc_hdr_stride / 16;
+            common->reg019.uv_hor_virstride = fbc_hdr_stride / 16;
             common->reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
         } else {
             common->reg012.fbc_e = 0;
diff --git a/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c b/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
index b8763772..4b8161f5 100644
--- a/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
+++ b/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
@@ -954,13 +954,12 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal,  HalTaskInfo *syn)
         hw_regs->h265d_param.reg64.h26x_stream_mode = 0;
 
         if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
-            RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
-            RK_U32 fbd_offset = MPP_ALIGN(pixel_width * (MPP_ALIGN(ver_virstride, 64) + 16) / 16,
-                                          SZ_4K);
+            RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
+            RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 64) / 16, SZ_4K);
 
             hw_regs->common.reg012.fbc_e = 1;
-            hw_regs->common.reg018.y_hor_virstride = pixel_width >> 4;
-            hw_regs->common.reg019.uv_hor_virstride = pixel_width >> 4;
+            hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4;
+            hw_regs->common.reg019.uv_hor_virstride = fbc_hdr_stride >> 4;
             hw_regs->common.reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
         } else {
             hw_regs->common.reg012.fbc_e = 0;
diff --git a/mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c b/mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c
index cde73140..28b09f1a 100644
--- a/mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c
+++ b/mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c
@@ -727,13 +727,12 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal,  HalTaskInfo *syn)
         hw_regs->h265d_param.reg64.h26x_stream_mode = 0;
 
         if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
-            RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
-            RK_U32 fbd_offset = MPP_ALIGN(pixel_width * (MPP_ALIGN(ver_virstride, 64) + 16) / 16,
-                                          SZ_4K);
+            RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
+            RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 64) / 16, SZ_4K);
 
             hw_regs->common.reg012.fbc_e = 1;
-            hw_regs->common.reg018.y_hor_virstride = pixel_width >> 4;
-            hw_regs->common.reg019.uv_hor_virstride = pixel_width >> 4;
+            hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4;
+            hw_regs->common.reg019.uv_hor_virstride = fbc_hdr_stride >> 4;
             hw_regs->common.reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
         } else {
             hw_regs->common.reg012.fbc_e = 0;
diff --git a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c
index ca05b6f6..cb5c663e 100644
--- a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c
+++ b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c
@@ -598,7 +598,8 @@ static MPP_RET hal_vp9d_vdpu34x_gen_regs(void *hal, HalTaskInfo *task)
         if (fbc_en) {
             RK_U32 w = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
             RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 64);
-            RK_U32 fbd_offset = MPP_ALIGN(w * (h + 16) / 16, SZ_4K);
+            RK_U32 fbd_offset = MPP_ALIGN(mpp_frame_get_fbc_hdr_stride(mframe) *
+                                          (h + 16) / 16, SZ_4K);
 
             vp9_hw_regs->common.reg012.fbc_e = 1;
             vp9_hw_regs->common.reg018.y_hor_virstride = w >> 4;
diff --git a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.c b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.c
index 3a7fc473..d6ba8ef4 100644
--- a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.c
+++ b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.c
@@ -596,13 +596,13 @@ static MPP_RET hal_vp9d_vdpu382_gen_regs(void *hal, HalTaskInfo *task)
         fbc_en = MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe));
 
         if (fbc_en) {
-            RK_U32 w = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
+            RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
             RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 64);
-            RK_U32 fbd_offset = MPP_ALIGN(w * (h + 16) / 16, SZ_4K);
+            RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (h + 16) / 16, SZ_4K);
 
             vp9_hw_regs->common.reg012.fbc_e = 1;
-            vp9_hw_regs->common.reg018.y_hor_virstride = w >> 4;
-            vp9_hw_regs->common.reg019.uv_hor_virstride = w >> 4;
+            vp9_hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4;
+            vp9_hw_regs->common.reg019.uv_hor_virstride = fbc_hdr_stride >> 4;
             vp9_hw_regs->common.reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
         } else {
             sw_y_hor_virstride = (vp9_hor_align((pic_param->width * bit_depth) >> 3) >> 4);
diff --git a/osal/inc/mpp_compat_impl.h b/osal/inc/mpp_compat_impl.h
index bf9d1d2c..1725ce47 100644
--- a/osal/inc/mpp_compat_impl.h
+++ b/osal/inc/mpp_compat_impl.h
@@ -21,5 +21,6 @@
 
 extern RK_S32 *compat_ext_fbc_buf_size;
 extern RK_S32 *compat_ext_async_input;
+extern RK_S32 *compat_ext_fbc_hdr_256_odd;
 
 #endif /*__MPP_COMPAT_IMPL_H__*/
diff --git a/osal/mpp_compat.cpp b/osal/mpp_compat.cpp
index 6a435da2..6967f3b7 100644
--- a/osal/mpp_compat.cpp
+++ b/osal/mpp_compat.cpp
@@ -48,10 +48,19 @@ static MppCompat compats[] = {
         "support encoder async input mode",
         NULL,
     },
+    {
+        MPP_COMPAT_DEC_FBC_HDR_256_ODD,
+        MPP_COMPAT_BOOL,
+        0,
+        0,
+        "set decoder fbc header stride to 256 odd align",
+        NULL,
+    },
 };
 
 RK_S32 *compat_ext_fbc_buf_size = &compats[MPP_COMPAT_INC_FBC_BUF_SIZE].value_usr;
 RK_S32 *compat_ext_async_input  = &compats[MPP_COMPAT_ENC_ASYNC_INPUT].value_usr;
+RK_S32 *compat_ext_fbc_hdr_256_odd  = &compats[MPP_COMPAT_DEC_FBC_HDR_256_ODD].value_usr;
 
 MppCompat *mpp_compat_query(void)
 {