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[mpp_soc] dec hw_cap add cap_colmv_compress

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Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Change-Id: I13b98c5227f03a235c48cfdb639286e7ee595b3f
This commit is contained in:
Chandler Chen
2022-10-11 09:44:49 +08:00
committed by Herman Chen
parent 726840336e
commit 4c14bb1556
10 changed files with 53 additions and 37 deletions
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1
mpp/hal/rkdec/avs2d/hal_avs2d_global.h
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@@ -107,6 +107,7 @@ typedef struct avs2d_hal_ctx_t {
MppBuffer scalist_buf; MppBuffer scalist_buf;
RK_U32 frame_no; RK_U32 frame_no;
const MppDecHwCap *hw_info;
} Avs2dHalCtx_t; } Avs2dHalCtx_t;
#endif /*__HAL_AVS2D_GLOBAL_H__*/ #endif /*__HAL_AVS2D_GLOBAL_H__*/

1
mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c
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@@ -610,6 +610,7 @@ MPP_RET hal_avs2d_vdpu382_init(void *hal, MppHalCfg *cfg)
mpp_assert(hw_info); mpp_assert(hw_info);
cfg->hw_info = hw_info; cfg->hw_info = hw_info;
p_hal->hw_info = hw_info;
} }
__RETURN: __RETURN:

2
mpp/hal/rkdec/h264d/hal_h264d_global.h
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@@ -132,6 +132,8 @@ typedef struct h264d_hal_ctx_t {
MppDev dev; MppDev dev;
void *reg_ctx; void *reg_ctx;
RK_U32 fast_mode; RK_U32 fast_mode;
const MppDecHwCap *hw_info;
} H264dHalCtx_t; } H264dHalCtx_t;
#endif /*__HAL_H264D_GLOBAL_H__*/ #endif /*__HAL_H264D_GLOBAL_H__*/

5
mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c
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@@ -540,7 +540,8 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu382H264dRegSet *regs, Hal
memset(&regs->h264d_highpoc, 0, sizeof(regs->h264d_highpoc)); memset(&regs->h264d_highpoc, 0, sizeof(regs->h264d_highpoc));
common->reg016_str_len = p_hal->strm_len; common->reg016_str_len = p_hal->strm_len;
common->reg013.cur_pic_is_idr = p_hal->slice_long->idr_flag; common->reg013.cur_pic_is_idr = p_hal->slice_long->idr_flag;
common->reg012.colmv_compress_en = (pp->frame_mbs_only_flag) ? 1 : 0; common->reg012.colmv_compress_en =
(p_hal->hw_info && p_hal->hw_info->cap_colmv_compress && pp->frame_mbs_only_flag) ? 1 : 0;
//!< caculate the yuv_frame_size //!< caculate the yuv_frame_size
{ {
MppFrame mframe = NULL; MppFrame mframe = NULL;
@@ -783,6 +784,8 @@ MPP_RET vdpu382_h264d_init(void *hal, MppHalCfg *cfg)
mpp_assert(hw_info); mpp_assert(hw_info);
cfg->hw_info = hw_info; cfg->hw_info = hw_info;
p_hal->hw_info = hw_info;
} }
__RETURN: __RETURN:

2
mpp/hal/rkdec/h265d/hal_h265d_ctx.h
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@@ -94,6 +94,8 @@ typedef struct HalH265dCtx_t {
RK_U32 sclst_offset; RK_U32 sclst_offset;
void *pps_buf; void *pps_buf;
void *sw_rps_buf; void *sw_rps_buf;
const MppDecHwCap *hw_info;
} HalH265dCtx; } HalH265dCtx;
typedef struct ScalingList { typedef struct ScalingList {

6
mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c
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@@ -175,6 +175,9 @@ static MPP_RET hal_h265d_vdpu382_init(void *hal, MppHalCfg *cfg)
mpp_assert(hw_info); mpp_assert(hw_info);
cfg->hw_info = hw_info; cfg->hw_info = hw_info;
//save hw_info to context
reg_cxt->hw_info = hw_info;
} }
#ifdef dump #ifdef dump
@@ -807,7 +810,8 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal, HalTaskInfo *syn)
aglin_offset); aglin_offset);
} }
hw_regs->common.reg010.dec_e = 1; hw_regs->common.reg010.dec_e = 1;
hw_regs->common.reg012.colmv_compress_en = 1; hw_regs->common.reg012.colmv_compress_en = reg_cxt->hw_info ?
reg_cxt->hw_info->cap_colmv_compress : 0;
hw_regs->common.reg024.cabac_err_en_lowbits = 0xffffdfff; hw_regs->common.reg024.cabac_err_en_lowbits = 0xffffdfff;
hw_regs->common.reg025.cabac_err_en_highbits = 0x3ffbf9ff; hw_regs->common.reg025.cabac_err_en_highbits = 0x3ffbf9ff;

2
mpp/hal/rkdec/vp9d/hal_vp9d_ctx.h
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@@ -61,6 +61,8 @@ typedef struct HalVp9dCtx_t {
MppCbCtx *dec_cb; MppCbCtx *dec_cb;
RK_U32 fast_mode; RK_U32 fast_mode;
void* hw_ctx; void* hw_ctx;
const MppDecHwCap *hw_info;
} HalVp9dCtx; } HalVp9dCtx;
#endif /*__HAL_VP9D_CTX_H__*/ #endif /*__HAL_VP9D_CTX_H__*/

1
mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.c
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@@ -264,6 +264,7 @@ static MPP_RET hal_vp9d_vdpu382_init(void *hal, MppHalCfg *cfg)
mpp_assert(hw_info); mpp_assert(hw_info);
cfg->hw_info = hw_info; cfg->hw_info = hw_info;
p_hal->hw_info = hw_info;
} }
return ret; return ret;

2
osal/inc/mpp_soc.h
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@@ -56,7 +56,7 @@ typedef struct MppDecHwCap_t {
RK_U32 cap_fbc : 4; RK_U32 cap_fbc : 4;
RK_U32 cap_4k : 1; RK_U32 cap_4k : 1;
RK_U32 cap_8k : 1; RK_U32 cap_8k : 1;
RK_U32 cap_colmv_buf : 1; RK_U32 cap_colmv_compress : 1;
RK_U32 cap_hw_h265_rps : 1; RK_U32 cap_hw_h265_rps : 1;
RK_U32 cap_hw_vp9_prob : 1; RK_U32 cap_hw_vp9_prob : 1;
RK_U32 cap_jpg_pp_out : 1; RK_U32 cap_jpg_pp_out : 1;

42
osal/mpp_soc.cpp
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@@ -71,7 +71,7 @@ static const MppDecHwCap vdpu1 = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 0, .cap_4k = 0,
.cap_8k = 0, .cap_8k = 0,
.cap_colmv_buf = 0, .cap_colmv_compress = 0,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -89,7 +89,7 @@ static const MppDecHwCap vdpu1_2160p = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 1, .cap_4k = 1,
.cap_8k = 0, .cap_8k = 0,
.cap_colmv_buf = 0, .cap_colmv_compress = 0,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -107,7 +107,7 @@ static const MppDecHwCap vdpu1_jpeg_pp = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 1, .cap_4k = 1,
.cap_8k = 1, .cap_8k = 1,
.cap_colmv_buf = 0, .cap_colmv_compress = 0,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 1, .cap_jpg_pp_out = 1,
@@ -125,7 +125,7 @@ static const MppDecHwCap vdpu2 = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 0, .cap_4k = 0,
.cap_8k = 0, .cap_8k = 0,
.cap_colmv_buf = 0, .cap_colmv_compress = 0,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -143,7 +143,7 @@ static const MppDecHwCap vdpu2_jpeg = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 0, .cap_4k = 0,
.cap_8k = 0, .cap_8k = 0,
.cap_colmv_buf = 0, .cap_colmv_compress = 0,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -161,7 +161,7 @@ static const MppDecHwCap vdpu2_jpeg_pp = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 0, .cap_4k = 0,
.cap_8k = 0, .cap_8k = 0,
.cap_colmv_buf = 0, .cap_colmv_compress = 0,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 1, .cap_jpg_pp_out = 1,
@@ -179,7 +179,7 @@ static const MppDecHwCap vdpu2_jpeg_fix = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 0, .cap_4k = 0,
.cap_8k = 0, .cap_8k = 0,
.cap_colmv_buf = 0, .cap_colmv_compress = 0,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -197,7 +197,7 @@ static const MppDecHwCap vdpu2_jpeg_pp_fix = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 0, .cap_4k = 0,
.cap_8k = 0, .cap_8k = 0,
.cap_colmv_buf = 0, .cap_colmv_compress = 0,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 1, .cap_jpg_pp_out = 1,
@@ -215,7 +215,7 @@ static const MppDecHwCap rk_hevc = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 1, .cap_4k = 1,
.cap_8k = 0, .cap_8k = 0,
.cap_colmv_buf = 0, .cap_colmv_compress = 0,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -233,7 +233,7 @@ static const MppDecHwCap rk_hevc_1080p = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 0, .cap_4k = 0,
.cap_8k = 0, .cap_8k = 0,
.cap_colmv_buf = 0, .cap_colmv_compress = 0,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -251,7 +251,7 @@ static const MppDecHwCap vdpu341 = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 1, .cap_4k = 1,
.cap_8k = 0, .cap_8k = 0,
.cap_colmv_buf = 0, .cap_colmv_compress = 1,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -269,7 +269,7 @@ static const MppDecHwCap vdpu341_lite = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 1, .cap_4k = 1,
.cap_8k = 0, .cap_8k = 0,
.cap_colmv_buf = 0, .cap_colmv_compress = 1,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -287,7 +287,7 @@ static const MppDecHwCap vdpu341_lite_1080p = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 0, .cap_4k = 0,
.cap_8k = 0, .cap_8k = 0,
.cap_colmv_buf = 0, .cap_colmv_compress = 1,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -305,7 +305,7 @@ static const MppDecHwCap vdpu341_h264 = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 1, .cap_4k = 1,
.cap_8k = 0, .cap_8k = 0,
.cap_colmv_buf = 0, .cap_colmv_compress = 1,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -324,7 +324,7 @@ static const MppDecHwCap vdpu34x = {
.cap_fbc = 2, .cap_fbc = 2,
.cap_4k = 1, .cap_4k = 1,
.cap_8k = 1, .cap_8k = 1,
.cap_colmv_buf = 1, .cap_colmv_compress = 1,
.cap_hw_h265_rps = 1, .cap_hw_h265_rps = 1,
.cap_hw_vp9_prob = 1, .cap_hw_vp9_prob = 1,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -342,7 +342,7 @@ static const MppDecHwCap vdpu38x = {
.cap_fbc = 2, .cap_fbc = 2,
.cap_4k = 1, .cap_4k = 1,
.cap_8k = 1, .cap_8k = 1,
.cap_colmv_buf = 1, .cap_colmv_compress = 1,
.cap_hw_h265_rps = 1, .cap_hw_h265_rps = 1,
.cap_hw_vp9_prob = 1, .cap_hw_vp9_prob = 1,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -360,7 +360,7 @@ static const MppDecHwCap vdpu382 = {
.cap_fbc = 2, .cap_fbc = 2,
.cap_4k = 1, .cap_4k = 1,
.cap_8k = 1, .cap_8k = 1,
.cap_colmv_buf = 1, .cap_colmv_compress = 1,
.cap_hw_h265_rps = 1, .cap_hw_h265_rps = 1,
.cap_hw_vp9_prob = 1, .cap_hw_vp9_prob = 1,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -378,7 +378,7 @@ static const MppDecHwCap vdpu382_lite = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 1, .cap_4k = 1,
.cap_8k = 1, .cap_8k = 1,
.cap_colmv_buf = 1, .cap_colmv_compress = 0,
.cap_hw_h265_rps = 1, .cap_hw_h265_rps = 1,
.cap_hw_vp9_prob = 1, .cap_hw_vp9_prob = 1,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -396,7 +396,7 @@ static const MppDecHwCap avspd = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 0, .cap_4k = 0,
.cap_8k = 0, .cap_8k = 0,
.cap_colmv_buf = 0, .cap_colmv_compress = 0,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -414,7 +414,7 @@ static const MppDecHwCap rkjpegd = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 1, .cap_4k = 1,
.cap_8k = 0, .cap_8k = 0,
.cap_colmv_buf = 0, .cap_colmv_compress = 0,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,
@@ -432,7 +432,7 @@ static const MppDecHwCap av1d = {
.cap_fbc = 0, .cap_fbc = 0,
.cap_4k = 1, .cap_4k = 1,
.cap_8k = 0, .cap_8k = 0,
.cap_colmv_buf = 0, .cap_colmv_compress = 0,
.cap_hw_h265_rps = 0, .cap_hw_h265_rps = 0,
.cap_hw_vp9_prob = 0, .cap_hw_vp9_prob = 0,
.cap_jpg_pp_out = 0, .cap_jpg_pp_out = 0,