diff --git a/mpp/hal/rkdec/avs2d/hal_avs2d_global.h b/mpp/hal/rkdec/avs2d/hal_avs2d_global.h index 509510ea..9a2c2d5b 100644 --- a/mpp/hal/rkdec/avs2d/hal_avs2d_global.h +++ b/mpp/hal/rkdec/avs2d/hal_avs2d_global.h @@ -107,6 +107,7 @@ typedef struct avs2d_hal_ctx_t { MppBuffer scalist_buf; RK_U32 frame_no; + const MppDecHwCap *hw_info; } Avs2dHalCtx_t; #endif /*__HAL_AVS2D_GLOBAL_H__*/ diff --git a/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c index 6d46029b..3fecd8b8 100644 --- a/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c +++ b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c @@ -610,6 +610,7 @@ MPP_RET hal_avs2d_vdpu382_init(void *hal, MppHalCfg *cfg) mpp_assert(hw_info); cfg->hw_info = hw_info; + p_hal->hw_info = hw_info; } __RETURN: diff --git a/mpp/hal/rkdec/h264d/hal_h264d_global.h b/mpp/hal/rkdec/h264d/hal_h264d_global.h index 4023e95b..ab11ef6a 100644 --- a/mpp/hal/rkdec/h264d/hal_h264d_global.h +++ b/mpp/hal/rkdec/h264d/hal_h264d_global.h @@ -132,6 +132,8 @@ typedef struct h264d_hal_ctx_t { MppDev dev; void *reg_ctx; RK_U32 fast_mode; + + const MppDecHwCap *hw_info; } H264dHalCtx_t; #endif /*__HAL_H264D_GLOBAL_H__*/ diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c index b96dcfee..9e000702 100644 --- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c +++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c @@ -540,7 +540,8 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu382H264dRegSet *regs, Hal memset(®s->h264d_highpoc, 0, sizeof(regs->h264d_highpoc)); common->reg016_str_len = p_hal->strm_len; common->reg013.cur_pic_is_idr = p_hal->slice_long->idr_flag; - common->reg012.colmv_compress_en = (pp->frame_mbs_only_flag) ? 1 : 0; + common->reg012.colmv_compress_en = + (p_hal->hw_info && p_hal->hw_info->cap_colmv_compress && pp->frame_mbs_only_flag) ? 1 : 0; //!< caculate the yuv_frame_size { MppFrame mframe = NULL; @@ -783,6 +784,8 @@ MPP_RET vdpu382_h264d_init(void *hal, MppHalCfg *cfg) mpp_assert(hw_info); cfg->hw_info = hw_info; + + p_hal->hw_info = hw_info; } __RETURN: diff --git a/mpp/hal/rkdec/h265d/hal_h265d_ctx.h b/mpp/hal/rkdec/h265d/hal_h265d_ctx.h index 37940687..f0217916 100644 --- a/mpp/hal/rkdec/h265d/hal_h265d_ctx.h +++ b/mpp/hal/rkdec/h265d/hal_h265d_ctx.h @@ -94,6 +94,8 @@ typedef struct HalH265dCtx_t { RK_U32 sclst_offset; void *pps_buf; void *sw_rps_buf; + + const MppDecHwCap *hw_info; } HalH265dCtx; typedef struct ScalingList { diff --git a/mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c b/mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c index 6c225b3c..b968bc90 100644 --- a/mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c +++ b/mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c @@ -175,6 +175,9 @@ static MPP_RET hal_h265d_vdpu382_init(void *hal, MppHalCfg *cfg) mpp_assert(hw_info); cfg->hw_info = hw_info; + + //save hw_info to context + reg_cxt->hw_info = hw_info; } #ifdef dump @@ -807,7 +810,8 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal, HalTaskInfo *syn) aglin_offset); } hw_regs->common.reg010.dec_e = 1; - hw_regs->common.reg012.colmv_compress_en = 1; + hw_regs->common.reg012.colmv_compress_en = reg_cxt->hw_info ? + reg_cxt->hw_info->cap_colmv_compress : 0; hw_regs->common.reg024.cabac_err_en_lowbits = 0xffffdfff; hw_regs->common.reg025.cabac_err_en_highbits = 0x3ffbf9ff; diff --git a/mpp/hal/rkdec/vp9d/hal_vp9d_ctx.h b/mpp/hal/rkdec/vp9d/hal_vp9d_ctx.h index 5684d72a..7532dfcc 100644 --- a/mpp/hal/rkdec/vp9d/hal_vp9d_ctx.h +++ b/mpp/hal/rkdec/vp9d/hal_vp9d_ctx.h @@ -61,6 +61,8 @@ typedef struct HalVp9dCtx_t { MppCbCtx *dec_cb; RK_U32 fast_mode; void* hw_ctx; + + const MppDecHwCap *hw_info; } HalVp9dCtx; #endif /*__HAL_VP9D_CTX_H__*/ diff --git a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.c b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.c index da5adcd3..92942832 100644 --- a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.c +++ b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.c @@ -264,6 +264,7 @@ static MPP_RET hal_vp9d_vdpu382_init(void *hal, MppHalCfg *cfg) mpp_assert(hw_info); cfg->hw_info = hw_info; + p_hal->hw_info = hw_info; } return ret; diff --git a/osal/inc/mpp_soc.h b/osal/inc/mpp_soc.h index 56c4d6eb..23bd30a6 100644 --- a/osal/inc/mpp_soc.h +++ b/osal/inc/mpp_soc.h @@ -51,21 +51,21 @@ typedef enum RockchipSocType_e { typedef struct MppDecHwCap_t { RK_U32 cap_coding; - MppClientType type : 8; + MppClientType type : 8; - RK_U32 cap_fbc : 4; - RK_U32 cap_4k : 1; - RK_U32 cap_8k : 1; - RK_U32 cap_colmv_buf : 1; - RK_U32 cap_hw_h265_rps : 1; - RK_U32 cap_hw_vp9_prob : 1; - RK_U32 cap_jpg_pp_out : 1; - RK_U32 cap_10bit : 1; - RK_U32 cap_down_scale : 1; - RK_U32 cap_lmt_linebuf : 1; - RK_U32 cap_core_num : 3; - RK_U32 cap_hw_jpg_fix : 1; - RK_U32 reserved : 8; + RK_U32 cap_fbc : 4; + RK_U32 cap_4k : 1; + RK_U32 cap_8k : 1; + RK_U32 cap_colmv_compress : 1; + RK_U32 cap_hw_h265_rps : 1; + RK_U32 cap_hw_vp9_prob : 1; + RK_U32 cap_jpg_pp_out : 1; + RK_U32 cap_10bit : 1; + RK_U32 cap_down_scale : 1; + RK_U32 cap_lmt_linebuf : 1; + RK_U32 cap_core_num : 3; + RK_U32 cap_hw_jpg_fix : 1; + RK_U32 reserved : 8; } MppDecHwCap; typedef struct MppEncHwCap_t { diff --git a/osal/mpp_soc.cpp b/osal/mpp_soc.cpp index 387f2bf4..2f3bd06a 100644 --- a/osal/mpp_soc.cpp +++ b/osal/mpp_soc.cpp @@ -71,7 +71,7 @@ static const MppDecHwCap vdpu1 = { .cap_fbc = 0, .cap_4k = 0, .cap_8k = 0, - .cap_colmv_buf = 0, + .cap_colmv_compress = 0, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 0, @@ -89,7 +89,7 @@ static const MppDecHwCap vdpu1_2160p = { .cap_fbc = 0, .cap_4k = 1, .cap_8k = 0, - .cap_colmv_buf = 0, + .cap_colmv_compress = 0, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 0, @@ -107,7 +107,7 @@ static const MppDecHwCap vdpu1_jpeg_pp = { .cap_fbc = 0, .cap_4k = 1, .cap_8k = 1, - .cap_colmv_buf = 0, + .cap_colmv_compress = 0, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 1, @@ -125,7 +125,7 @@ static const MppDecHwCap vdpu2 = { .cap_fbc = 0, .cap_4k = 0, .cap_8k = 0, - .cap_colmv_buf = 0, + .cap_colmv_compress = 0, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 0, @@ -143,7 +143,7 @@ static const MppDecHwCap vdpu2_jpeg = { .cap_fbc = 0, .cap_4k = 0, .cap_8k = 0, - .cap_colmv_buf = 0, + .cap_colmv_compress = 0, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 0, @@ -161,7 +161,7 @@ static const MppDecHwCap vdpu2_jpeg_pp = { .cap_fbc = 0, .cap_4k = 0, .cap_8k = 0, - .cap_colmv_buf = 0, + .cap_colmv_compress = 0, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 1, @@ -179,7 +179,7 @@ static const MppDecHwCap vdpu2_jpeg_fix = { .cap_fbc = 0, .cap_4k = 0, .cap_8k = 0, - .cap_colmv_buf = 0, + .cap_colmv_compress = 0, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 0, @@ -197,7 +197,7 @@ static const MppDecHwCap vdpu2_jpeg_pp_fix = { .cap_fbc = 0, .cap_4k = 0, .cap_8k = 0, - .cap_colmv_buf = 0, + .cap_colmv_compress = 0, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 1, @@ -215,7 +215,7 @@ static const MppDecHwCap rk_hevc = { .cap_fbc = 0, .cap_4k = 1, .cap_8k = 0, - .cap_colmv_buf = 0, + .cap_colmv_compress = 0, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 0, @@ -233,7 +233,7 @@ static const MppDecHwCap rk_hevc_1080p = { .cap_fbc = 0, .cap_4k = 0, .cap_8k = 0, - .cap_colmv_buf = 0, + .cap_colmv_compress = 0, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 0, @@ -251,7 +251,7 @@ static const MppDecHwCap vdpu341 = { .cap_fbc = 0, .cap_4k = 1, .cap_8k = 0, - .cap_colmv_buf = 0, + .cap_colmv_compress = 1, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 0, @@ -269,7 +269,7 @@ static const MppDecHwCap vdpu341_lite = { .cap_fbc = 0, .cap_4k = 1, .cap_8k = 0, - .cap_colmv_buf = 0, + .cap_colmv_compress = 1, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 0, @@ -287,7 +287,7 @@ static const MppDecHwCap vdpu341_lite_1080p = { .cap_fbc = 0, .cap_4k = 0, .cap_8k = 0, - .cap_colmv_buf = 0, + .cap_colmv_compress = 1, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 0, @@ -305,7 +305,7 @@ static const MppDecHwCap vdpu341_h264 = { .cap_fbc = 0, .cap_4k = 1, .cap_8k = 0, - .cap_colmv_buf = 0, + .cap_colmv_compress = 1, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 0, @@ -324,7 +324,7 @@ static const MppDecHwCap vdpu34x = { .cap_fbc = 2, .cap_4k = 1, .cap_8k = 1, - .cap_colmv_buf = 1, + .cap_colmv_compress = 1, .cap_hw_h265_rps = 1, .cap_hw_vp9_prob = 1, .cap_jpg_pp_out = 0, @@ -342,7 +342,7 @@ static const MppDecHwCap vdpu38x = { .cap_fbc = 2, .cap_4k = 1, .cap_8k = 1, - .cap_colmv_buf = 1, + .cap_colmv_compress = 1, .cap_hw_h265_rps = 1, .cap_hw_vp9_prob = 1, .cap_jpg_pp_out = 0, @@ -360,7 +360,7 @@ static const MppDecHwCap vdpu382 = { .cap_fbc = 2, .cap_4k = 1, .cap_8k = 1, - .cap_colmv_buf = 1, + .cap_colmv_compress = 1, .cap_hw_h265_rps = 1, .cap_hw_vp9_prob = 1, .cap_jpg_pp_out = 0, @@ -378,7 +378,7 @@ static const MppDecHwCap vdpu382_lite = { .cap_fbc = 0, .cap_4k = 1, .cap_8k = 1, - .cap_colmv_buf = 1, + .cap_colmv_compress = 0, .cap_hw_h265_rps = 1, .cap_hw_vp9_prob = 1, .cap_jpg_pp_out = 0, @@ -396,7 +396,7 @@ static const MppDecHwCap avspd = { .cap_fbc = 0, .cap_4k = 0, .cap_8k = 0, - .cap_colmv_buf = 0, + .cap_colmv_compress = 0, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 0, @@ -414,7 +414,7 @@ static const MppDecHwCap rkjpegd = { .cap_fbc = 0, .cap_4k = 1, .cap_8k = 0, - .cap_colmv_buf = 0, + .cap_colmv_compress = 0, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 0, @@ -432,7 +432,7 @@ static const MppDecHwCap av1d = { .cap_fbc = 0, .cap_4k = 1, .cap_8k = 0, - .cap_colmv_buf = 0, + .cap_colmv_compress = 0, .cap_hw_h265_rps = 0, .cap_hw_vp9_prob = 0, .cap_jpg_pp_out = 0,