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https://github.com/nyanmisaka/mpp.git
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[h265e]: add h265 encoder code
Change-Id: I08350dc76d3040bc1a16a3d8234f836f5fbf69d0 Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
This commit is contained in:
@@ -131,6 +131,7 @@ typedef enum {
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MPP_ENC_PRE_ALLOC_BUFF, /* allocate buffers before encoding */
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MPP_ENC_SET_QP_RANGE, /* used for adjusting qp range, the parameter can be 1 or 2 */
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MPP_ENC_SET_ROI_CFG, /* set MppEncROICfg structure */
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MPP_ENC_SET_CTU_QP, /* for H265 Encoder,set CTU's size and QP */
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MPP_ENC_CMD_END,
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MPP_ISP_CMD_BASE = CMD_MODULE_CODEC | CMD_CTX_ID_ISP,
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@@ -811,6 +812,77 @@ typedef struct MppEncH264Cfg_t {
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MppEncH264RefCfg ref;
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} MppEncH264Cfg;
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#define H265E_MAX_ROI_NUMBER 64
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typedef struct H265eRect_t {
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RK_S32 left;
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RK_S32 right;
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RK_S32 top;
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RK_S32 bottom;
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} H265eRect;
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typedef struct H265eRoi_Region_t {
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RK_U8 level;
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H265eRect rect;
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} H265eRoiRegion;
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/*
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* roi region only can be setting when rc_enable = 1
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*/
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typedef struct MppEncH265RoiCfg_t {
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/*
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* the value is defined by H265eCtuMethod
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*/
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RK_U8 method;
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/*
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* the number of roi,the value must less than H265E_MAX_ROI_NUMBER
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*/
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RK_S32 num;
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/* delat qp using in roi region*/
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RK_U32 delta_qp;
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/* roi region */
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H265eRoiRegion region[H265E_MAX_ROI_NUMBER];
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} MppEncH265RoiCfg;
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typedef struct H265eCtuQp_t {
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/* the qp value using in ctu region */
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RK_U32 qp;
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/*
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* define the ctu region
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* method = H265E_METHOD_CUT_SIZE, the value of rect is in ctu size
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* method = H264E_METHOD_COORDINATE,the value of rect is in coordinates
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*/
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H265eRect rect;
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} H265eCtu;
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typedef struct H265eCtuRegion_t {
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/*
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* the value is defined by H265eCtuMethod
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*/
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RK_U8 method;
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/*
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* the number of ctu,the value must less than H265E_MAX_ROI_NUMBER
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*/
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RK_S32 num;
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/* ctu region */
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H265eCtu ctu[H265E_MAX_ROI_NUMBER];
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} MppEncH265CtuCfg;
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/*
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* define the method when set CTU/ROI parameters
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* this value is using by method in H265eCtuRegion or H265eRoi struct
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*/
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typedef enum {
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H265E_METHOD_CTU_SIZE,
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H264E_METHOD_COORDINATE,
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} H265eCtuMethod;
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/*
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* H.265 configurable parameter
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*/
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@@ -827,6 +899,23 @@ typedef struct MppEncH265SeiCfg_t {
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RK_U32 change;
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} MppEncH265SeiCfg;
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typedef enum MppEncH265CfgChange_e {
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/* change on stream type */
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MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE = (1 << 0),
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MPP_ENC_H265_CFG_INTRA_QP_CHANGE = (1 << 1),
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MPP_ENC_H265_CFG_FRAME_RATE_CHANGE = (1 << 2),
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MPP_ENC_H265_CFG_BITRATE_CHANGE = (1 << 3),
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MPP_ENC_H265_CFG_GOP_SIZE = (1 << 4),
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MPP_ENC_H265_CFG_RC_QP_CHANGE = (1 << 5),
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MPP_ENC_H265_CFG_INTRA_REFRESH_CHANGE = (1 << 6),
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MPP_ENC_H265_CFG_INDEPEND_SLICE_CHANGE = (1 << 7),
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MPP_ENC_H265_CFG_DEPEND_SLICE_CHANGE = (1 << 8),
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MPP_ENC_H265_CFG_CTU_CHANGE = (1 << 9),
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MPP_ENC_H265_CFG_ROI_CHANGE = (1 << 10),
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MPP_ENC_H265_CFG_CHANGE_ALL = (0xFFFFFFFF),
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} MppEncH265CfgChange;
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typedef struct MppEncH265Cfg_t {
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RK_U32 change;
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@@ -845,6 +934,8 @@ typedef struct MppEncH265Cfg_t {
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RK_S32 max_qp;
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RK_S32 min_qp;
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RK_S32 max_delta_qp;
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RK_S32 intra_qp;
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RK_S32 gop_delta_qp;
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/* intra fresh config */
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RK_S32 intra_refresh_mode;
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@@ -859,6 +950,9 @@ typedef struct MppEncH265Cfg_t {
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/* extra info */
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MppEncH265VuiCfg vui;
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MppEncH265SeiCfg sei;
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MppEncH265CtuCfg ctu;
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MppEncH265RoiCfg roi;
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} MppEncH265Cfg;
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/*
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