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https://github.com/nyanmisaka/mpp.git
synced 2025-10-05 01:02:39 +08:00
[vp9d]: add errorinfo marking
1. dicard stream when has not got keyframe. 2. when frame is not intra, check the errinfo flag for refs. 3. when hard return is not ready, mark errinfo. 4. when reset setting, discard the frame remainng. Change-Id: Idd03a8476e76875176475167ca5890e247f75ee3 Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
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@@ -174,7 +174,7 @@ MPP_RET vp9d_prepare(void *ctx, MppPacket pkt, HalDecTask *task)
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consumed = vp9d_split_frame(ps, &out_data, &out_size, buf, length);
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pos += consumed;
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mpp_packet_set_pos(pkt, pos);
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vp9d_dbg(VP9D_DBG_STRMIN, "pkt_len=%d, pts=%lld\n", length, pts);
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vp9d_get_frame_stream(vp9_ctx, out_data, out_size);
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if (out_size > 0) {
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task->input_packet = vp9_ctx->pkt;
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@@ -395,6 +395,7 @@ static RK_S32 vp9_alloc_frame(Vp9CodecContext *ctx, VP9Frame *frame)
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mpp_frame_set_hor_stride(frame->f, ctx->width);
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mpp_frame_set_ver_stride(frame->f, ctx->height);
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mpp_frame_set_errinfo(frame->f, 0);
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mpp_frame_set_discard(frame->f, 0);
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mpp_frame_set_pts(frame->f, s->pts);
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#if 0
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mpp_frame_set_fmt(frame->frame, s->h265dctx->pix_fmt);
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@@ -684,6 +685,13 @@ static RK_S32 decode_parser_header(Vp9CodecContext *ctx,
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s->errorres = mpp_get_bit1(&s->gb);
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vp9d_dbg(VP9D_DBG_HEADER, "error_resilient_mode %d", s->errorres);
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s->use_last_frame_mvs = !s->errorres && !last_invisible;
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s->got_keyframes += s->keyframe ? 1 : 0;
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vp9d_dbg(VP9D_DBG_HEADER, "keyframe=%d, intraonly=%d, got_keyframes=%d\n",
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s->keyframe, s->intraonly, s->got_keyframes);
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if (!s->got_keyframes) {
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mpp_err_f("have not got keyframe.\n");
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return MPP_ERR_STREAM;
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}
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if (s->keyframe) {
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if (mpp_get_bits(&s->gb, 24) != VP9_SYNCCODE) { // synccode
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mpp_err("Invalid sync code\n");
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@@ -1619,20 +1627,25 @@ RK_S32 vp9_parser_frame(Vp9CodecContext *ctx, HalDecTask *task)
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vp9d_parser2_syntax(ctx);
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task->syntax.data = (void*)&ctx->pic_params;
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task->syntax.number = 1;
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task->valid = 1;
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task->output = s->frames[CUR_FRAME].slot_index;
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task->input_packet = ctx->pkt;
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for (i = 0; i < 3; i++) {
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if (s->refs[s->refidx[i]].slot_index < 0x7f) {
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MppFrame mframe = NULL;
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mpp_buf_slot_set_flag(s->slots, s->refs[s->refidx[i]].slot_index, SLOT_HAL_INPUT);
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task->refer[i] = s->refs[s->refidx[i]].slot_index;
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mpp_buf_slot_get_prop(s->slots, task->refer[i], SLOT_FRAME_PTR, &mframe);
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if (mframe)
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task->flags.had_error |= mpp_frame_get_errinfo(mframe);
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} else {
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task->refer[i] = -1;
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}
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}
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vp9d_dbg(VP9D_DBG_REF, "ref_errinfo=%d\n", task->flags.had_error);
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if (s->eos) {
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task->flags.eos = 1;
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}
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@@ -1641,7 +1654,8 @@ RK_S32 vp9_parser_frame(Vp9CodecContext *ctx, HalDecTask *task)
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mpp_buf_slot_set_flag(s->slots, s->frames[CUR_FRAME].slot_index, SLOT_QUEUE_USE);
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mpp_buf_slot_enqueue(s->slots, s->frames[CUR_FRAME].slot_index, QUEUE_DISPLAY);
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}
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vp9d_dbg(VP9D_DBG_REF, "s->refreshrefmask = %d s->frames[CUR_FRAME] = %d", s->refreshrefmask, s->frames[CUR_FRAME].slot_index);
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vp9d_dbg(VP9D_DBG_REF, "s->refreshrefmask = %d s->frames[CUR_FRAME] = %d",
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s->refreshrefmask, s->frames[CUR_FRAME].slot_index);
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for (i = 0; i < 3; i++) {
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if (s->refs[s->refidx[i]].ref != NULL) {
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vp9d_dbg(VP9D_DBG_REF, "ref buf select %d", s->refs[s->refidx[i]].slot_index);
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@@ -1672,6 +1686,8 @@ MPP_RET vp9d_paser_reset(Vp9CodecContext *ctx)
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VP9Context *s = ctx->priv_data;
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SplitContext_t *ps = (SplitContext_t *)ctx->priv_data2;
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VP9ParseContext *pc = (VP9ParseContext *)ps->priv_data;
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s->got_keyframes = 0;
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for (i = 0; i < 3; i++) {
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if (s->frames[i].ref) {
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vp9_unref_frame(s, &s->frames[i]);
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@@ -34,6 +34,7 @@ extern RK_U32 vp9d_debug;
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#define VP9D_DBG_HEADER (0x00000002)
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#define VP9D_DBG_REF (0x00000004)
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#define VP9D_DBG_PORBE (0x00000008)
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#define VP9D_DBG_STRMIN (0x00000010)
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@@ -139,7 +140,7 @@ typedef struct VP9Context {
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RK_U8 varcompref[2];
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VP9Frame frames[3];
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VP9Frame refs[8];
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RK_U32 got_keyframes;
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struct {
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RK_U8 level;
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@@ -868,11 +868,8 @@ MPP_RET hal_vp9d_wait(void *hal, HalTaskInfo *task)
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RK_U32 i;
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VP9_REGS *hw_regs = (VP9_REGS*)reg_cxt->hw_regs;
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RK_U8* p = (RK_U8*)hw_regs;
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MppBuffer framebuf = NULL;
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mpp_buf_slot_get_prop(reg_cxt->slots, task->dec.output, SLOT_BUFFER, &framebuf);
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ret = mpp_device_wait_reg(reg_cxt->vpu_socket, (RK_U32*)hw_regs, sizeof(VP9_REGS) / 4);
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for (i = 0; i < sizeof(VP9_REGS) / 4; i++) {
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if (i == 1) {
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vp9h_dbg(VP9H_DBG_REG, "RK_VP9_DEC: regs[%02d]=%08X\n", i, *((RK_U32*)p));
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@@ -881,6 +878,12 @@ MPP_RET hal_vp9d_wait(void *hal, HalTaskInfo *task)
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p += 4;
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}
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if (task->dec.flags.had_error || !hw_regs->swreg1_int.sw_dec_rdy_sta) {
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MppFrame mframe = NULL;
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mpp_buf_slot_get_prop(reg_cxt->slots, task->dec.output, SLOT_FRAME_PTR, &mframe);
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mpp_frame_set_errinfo(mframe, 1);
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}
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reg_cxt->ls_info.abs_delta_last = pic_param->stVP9Segments.abs_delta;
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for (i = 0 ; i < 4; i ++) {
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reg_cxt->ls_info.last_ref_deltas[i] = pic_param->ref_deltas[i];
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