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[meta]: Add qpmap for encoder roi direct config

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Change-Id: Ic64fa548f60f723e971c5574b6b290ddaf454809
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
This commit is contained in:
Herman Chen
2021-10-15 09:57:56 +08:00
parent d56760acd2
commit 02320fb506
4 changed files with 110 additions and 66 deletions
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25
inc/mpp_meta.h
View File

@@ -82,6 +82,31 @@ typedef enum MppMetaKey_e {
KEY_OSD_DATA2 = FOURCC_META('o', 's', 'd', '2'),
KEY_USER_DATA = FOURCC_META('u', 's', 'r', 'd'),
KEY_USER_DATAS = FOURCC_META('u', 'r', 'd', 's'),
/*
* qpmap for rv1109/1126 encoder qpmap config
* Input data is a MppBuffer which contains an array of 16bit Vepu541RoiCfg.
* And each 16bit represents a 16x16 block qp info.
*
* H.264 - 16x16 block qp is arranged in raster order:
* each value is a 16bit data
* 00 01 02 03 04 05 06 07 -> 00 01 02 03 04 05 06 07
* 10 11 12 13 14 15 16 17 10 11 12 13 14 15 16 17
* 20 21 22 23 24 25 26 27 20 21 22 23 24 25 26 27
* 30 31 32 33 34 35 36 37 30 31 32 33 34 35 36 37
*
* H.265 - 16x16 block qp is reorder to 64x64/32x32 ctu order then 64x64 / 32x32 ctu raster order
* 64x64 ctu
* 00 01 02 03 04 05 06 07 -> 00 01 02 03 10 11 12 13 20 21 22 23 30 31 32 33 04 05 06 07 14 15 16 17 24 25 26 27 34 35 36 37
* 10 11 12 13 14 15 16 17
* 20 21 22 23 24 25 26 27
* 30 31 32 33 34 35 36 37
* 32x32 ctu
* 00 01 02 03 04 05 06 07 -> 00 01 10 11 02 03 12 13 04 05 14 15 06 07 16 17
* 10 11 12 13 14 15 16 17 20 21 30 31 22 23 32 33 24 25 34 35 26 27 36 37
* 20 21 22 23 24 25 26 27
* 30 31 32 33 34 35 36 37
*/
KEY_QPMAP0 = FOURCC_META('e', 'q', 'm', '0'),
/* input motion list for smart p rate control */
KEY_MV_LIST = FOURCC_META('m', 'v', 'l', 't'),

1
mpp/base/mpp_meta.cpp
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@@ -49,6 +49,7 @@ static MppMetaDef meta_defs[] = {
{ KEY_OSD_DATA2, TYPE_PTR, },
{ KEY_USER_DATA, TYPE_PTR, },
{ KEY_USER_DATAS, TYPE_PTR, },
{ KEY_QPMAP0, TYPE_BUFFER, },
{ KEY_MV_LIST, TYPE_PTR, },
{ KEY_ENC_MARK_LTR, TYPE_S32, },

68
mpp/hal/rkenc/h264e/hal_h264e_vepu541.c
View File

@@ -71,6 +71,7 @@ typedef struct HalH264eVepu541Ctx_t {
MppBufferGroup roi_grp;
MppBuffer roi_buf;
RK_S32 roi_buf_size;
MppBuffer qpmap;
/* osd */
Vepu541OsdCfg osd_cfg;
@@ -338,6 +339,7 @@ static MPP_RET hal_h264e_vepu541_get_task(void *hal, HalEncTask *task)
mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
mpp_meta_get_ptr(meta, KEY_OSD_DATA, (void **)&ctx->osd_cfg.osd_data);
mpp_meta_get_ptr(meta, KEY_OSD_DATA2, (void **)&ctx->osd_cfg.osd_data2);
mpp_meta_get_buffer(meta, KEY_QPMAP0, &ctx->qpmap);
}
hal_h264e_dbg_func("leave %p\n", hal);
@@ -933,46 +935,52 @@ static void setup_vepu541_io_buf(Vepu541H264eRegSet *regs, MppDev dev,
static void setup_vepu541_roi(Vepu541H264eRegSet *regs, HalH264eVepu541Ctx *ctx)
{
MppEncROICfg *roi = ctx->roi_data;
RK_U32 w = ctx->sps->pic_width_in_mbs * 16;
RK_U32 h = ctx->sps->pic_height_in_mbs * 16;
hal_h264e_dbg_func("enter\n");
/* roi setup */
if (roi && roi->number && roi->regions) {
RK_S32 roi_buf_size = vepu541_get_roi_buf_size(w, h);
if (ctx->qpmap) {
regs->reg013.roi_enc = 1;
regs->reg073.roi_addr = mpp_buffer_get_fd(ctx->qpmap);
} else {
MppEncROICfg *roi = ctx->roi_data;
RK_U32 w = ctx->sps->pic_width_in_mbs * 16;
RK_U32 h = ctx->sps->pic_height_in_mbs * 16;
if (!ctx->roi_buf || roi_buf_size != ctx->roi_buf_size) {
if (NULL == ctx->roi_grp)
mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
else if (roi_buf_size != ctx->roi_buf_size) {
if (ctx->roi_buf) {
mpp_buffer_put(ctx->roi_buf);
ctx->roi_buf = NULL;
/* roi setup */
if (roi && roi->number && roi->regions) {
RK_S32 roi_buf_size = vepu541_get_roi_buf_size(w, h);
if (!ctx->roi_buf || roi_buf_size != ctx->roi_buf_size) {
if (NULL == ctx->roi_grp)
mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
else if (roi_buf_size != ctx->roi_buf_size) {
if (ctx->roi_buf) {
mpp_buffer_put(ctx->roi_buf);
ctx->roi_buf = NULL;
}
mpp_buffer_group_clear(ctx->roi_grp);
}
mpp_buffer_group_clear(ctx->roi_grp);
mpp_assert(ctx->roi_grp);
if (NULL == ctx->roi_buf)
mpp_buffer_get(ctx->roi_grp, &ctx->roi_buf, roi_buf_size);
ctx->roi_buf_size = roi_buf_size;
}
mpp_assert(ctx->roi_grp);
mpp_assert(ctx->roi_buf);
RK_S32 fd = mpp_buffer_get_fd(ctx->roi_buf);
void *buf = mpp_buffer_get_ptr(ctx->roi_buf);
if (NULL == ctx->roi_buf)
mpp_buffer_get(ctx->roi_grp, &ctx->roi_buf, roi_buf_size);
regs->reg013.roi_enc = 1;
regs->reg073.roi_addr = fd;
ctx->roi_buf_size = roi_buf_size;
vepu541_set_roi(buf, roi, w, h);
} else {
regs->reg013.roi_enc = 0;
regs->reg073.roi_addr = 0;
}
mpp_assert(ctx->roi_buf);
RK_S32 fd = mpp_buffer_get_fd(ctx->roi_buf);
void *buf = mpp_buffer_get_ptr(ctx->roi_buf);
regs->reg013.roi_enc = 1;
regs->reg073.roi_addr = fd;
vepu541_set_roi(buf, roi, w, h);
} else {
regs->reg013.roi_enc = 0;
regs->reg073.roi_addr = 0;
}
hal_h264e_dbg_func("leave\n");

82
mpp/hal/rkenc/h265e/hal_h265e_vepu541.c
View File

@@ -89,6 +89,8 @@ typedef struct H265eV541HalContext_t {
MppBufferGroup roi_grp;
MppBuffer roi_hw_buf;
RK_U32 roi_buf_size;
MppBuffer qpmap;
MppEncCfgSet *cfg;
MppBufferGroup tile_grp;
@@ -848,44 +850,50 @@ MPP_RET vepu541_h265_set_roi(void *dst_buf, void *src_buf, RK_S32 w, RK_S32 h)
static MPP_RET
vepu541_h265_set_roi_regs(H265eV541HalContext *ctx, H265eV541RegSet *regs)
{
MppEncROICfg *cfg = (MppEncROICfg*)ctx->roi_data;
RK_U32 h = ctx->cfg->prep.height;
RK_U32 w = ctx->cfg->prep.width;
RK_U8 *roi_base;
if (!cfg)
return MPP_OK;
if (cfg->number && cfg->regions) {
RK_U32 roi_buf_size = vepu541_get_roi_buf_size(w, h);
if (!ctx->roi_hw_buf || roi_buf_size != ctx->roi_buf_size) {
if (NULL == ctx->roi_grp)
mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
else if (roi_buf_size != ctx->roi_buf_size) {
if (ctx->roi_hw_buf) {
mpp_buffer_put(ctx->roi_hw_buf);
ctx->roi_hw_buf = NULL;
}
MPP_FREE(ctx->roi_buf);
mpp_buffer_group_clear(ctx->roi_grp);
}
mpp_assert(ctx->roi_grp);
if (NULL == ctx->roi_hw_buf)
mpp_buffer_get(ctx->roi_grp, &ctx->roi_hw_buf, roi_buf_size);
if (ctx->roi_buf == NULL)
ctx->roi_buf = mpp_malloc(RK_U8, roi_buf_size);
ctx->roi_buf_size = roi_buf_size;
}
if (ctx->qpmap) {
regs->enc_pic.roi_en = 1;
regs->roi_addr_hevc = mpp_buffer_get_fd(ctx->roi_hw_buf);
roi_base = (RK_U8 *)mpp_buffer_get_ptr(ctx->roi_hw_buf);
vepu541_set_roi(ctx->roi_buf, cfg, w, h);
vepu541_h265_set_roi(roi_base, ctx->roi_buf, w, h);
regs->roi_addr_hevc = mpp_buffer_get_fd(ctx->qpmap);
} else {
MppEncROICfg *cfg = (MppEncROICfg*)ctx->roi_data;
RK_U32 h = ctx->cfg->prep.height;
RK_U32 w = ctx->cfg->prep.width;
RK_U8 *roi_base;
if (!cfg)
return MPP_OK;
if (cfg->number && cfg->regions) {
RK_U32 roi_buf_size = vepu541_get_roi_buf_size(w, h);
if (!ctx->roi_hw_buf || roi_buf_size != ctx->roi_buf_size) {
if (NULL == ctx->roi_grp)
mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
else if (roi_buf_size != ctx->roi_buf_size) {
if (ctx->roi_hw_buf) {
mpp_buffer_put(ctx->roi_hw_buf);
ctx->roi_hw_buf = NULL;
}
MPP_FREE(ctx->roi_buf);
mpp_buffer_group_clear(ctx->roi_grp);
}
mpp_assert(ctx->roi_grp);
if (NULL == ctx->roi_hw_buf)
mpp_buffer_get(ctx->roi_grp, &ctx->roi_hw_buf, roi_buf_size);
if (ctx->roi_buf == NULL)
ctx->roi_buf = mpp_malloc(RK_U8, roi_buf_size);
ctx->roi_buf_size = roi_buf_size;
}
regs->enc_pic.roi_en = 1;
regs->roi_addr_hevc = mpp_buffer_get_fd(ctx->roi_hw_buf);
roi_base = (RK_U8 *)mpp_buffer_get_ptr(ctx->roi_hw_buf);
vepu541_set_roi(ctx->roi_buf, cfg, w, h);
vepu541_h265_set_roi(roi_base, ctx->roi_buf, w, h);
}
}
return MPP_OK;
}
@@ -1887,9 +1895,11 @@ MPP_RET hal_h265e_v541_get_task(void *hal, HalEncTask *task)
}
if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
MppMeta meta = mpp_frame_get_meta(frame);
mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
mpp_meta_get_ptr(meta, KEY_OSD_DATA, (void **)&ctx->osd_cfg.osd_data);
mpp_meta_get_ptr(meta, KEY_OSD_DATA2, (void **)&ctx->osd_cfg.osd_data2);
mpp_meta_get_buffer(meta, KEY_QPMAP0, &ctx->qpmap);
}
memset(&ctx->feedback, 0, sizeof(vepu541_h265_fbk));