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Update On Sat Aug 16 20:36:45 CEST 2025

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This commit is contained in:
github-action[bot]
2025-08-16 20:36:45 +02:00
parent 66af30d8fd
commit ef94c2e71c
84 changed files with 1317 additions and 930 deletions
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4
lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-fastrhino.dtsi
View File

@@ -452,10 +452,6 @@
status = "okay";
};
&rng {
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";

31
lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi
View File

@@ -96,31 +96,22 @@
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb: vcc5v0-usb {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "vcc5v0_usb";
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb_host: vcc5v0-usb-host {
vcc5v0_usb_otg: vcc5v0-usb-otg {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_host_en>;
pinctrl-0 = <&vcc5v0_usb_otg_en>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "vcc5v0_usb_host";
vin-supply = <&vcc5v0_usb>;
regulator-name = "vcc5v0_usb_otg";
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_pcie: vcc3v3-pcie {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_pcie";
@@ -498,7 +489,7 @@
};
usb {
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -517,10 +508,6 @@
status = "okay";
};
&rng {
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
@@ -587,7 +574,7 @@
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb_host>;
phy-supply = <&vcc5v0_usb_otg>;
status = "okay";
};
@@ -596,12 +583,12 @@
};
&usb2phy1_host {
phy-supply = <&vcc5v0_usb_host>;
phy-supply = <&vcc5v0_usb_otg>;
status = "okay";
};
&usb2phy1_otg {
phy-supply = <&vcc5v0_usb_host>;
phy-supply = <&vcc5v0_usb_otg>;
status = "okay";
};

20
lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s-plus.dts
View File

@@ -52,16 +52,6 @@
num-viewport = <4>;
reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
status = "okay";
pcie@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
r8125_1: pcie@01,0 {
reg = <0x000000 0 0 0 0>;
};
};
};
&pcie30phy {
@@ -73,16 +63,6 @@
num-viewport = <4>;
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
status = "okay";
pcie@0,0 {
reg = <0x00100000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
r8125_2: pcie@10,0 {
reg = <0x000000 0 0 0 0>;
};
};
};
&pcie3x2 {

12
lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dtsi
View File

@@ -16,7 +16,6 @@
stdout-path = "serial2:1500000n8";
};
#ifdef DTS_NO_LEGACY
hdmi-con {
compatible = "hdmi-connector";
type = "a";
@@ -27,7 +26,6 @@
};
};
};
#endif
dc_12v: dc-12v {
compatible = "regulator-fixed";
@@ -109,7 +107,6 @@
cpu-supply = <&vdd_cpu>;
};
#ifdef DTS_NO_LEGACY
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
@@ -136,7 +133,6 @@
&hdmi_sound {
status = "okay";
};
#endif
&i2c0 {
status = "okay";
@@ -379,11 +375,9 @@
};
};
#ifdef DTS_NO_LEGACY
&i2s0_8ch {
status = "okay";
};
#endif
&pinctrl {
pmic {
@@ -406,10 +400,6 @@
status = "okay";
};
&rng {
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
@@ -500,7 +490,6 @@
status = "okay";
};
#ifdef DTS_NO_LEGACY
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
@@ -517,4 +506,3 @@
remote-endpoint = <&hdmi_in_vp0>;
};
};
#endif

19
lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
View File

@@ -24,7 +24,6 @@
stdout-path = "serial2:1500000n8";
};
#ifdef DTS_NO_LEGACY
hdmi-con {
compatible = "hdmi-connector";
type = "a";
@@ -35,7 +34,6 @@
};
};
};
#endif
vdd_usbc: vdd-usbc-regulator {
compatible = "regulator-fixed";
@@ -162,7 +160,6 @@
cpu-supply = <&vdd_cpu>;
};
#ifdef DTS_NO_LEGACY
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
@@ -189,7 +186,6 @@
&hdmi_sound {
status = "okay";
};
#endif
&i2c0 {
status = "okay";
@@ -219,7 +215,7 @@
#clock-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
rockchip,system-power-controller;
system-power-controller;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
@@ -437,11 +433,9 @@
};
};
#ifdef DTS_NO_LEGACY
&i2s0_8ch {
status = "okay";
};
#endif
&pcie30phy {
data-lanes = <1 2>;
@@ -484,10 +478,6 @@
status = "okay";
};
&rng {
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
@@ -496,9 +486,12 @@
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
mmc-hs200-1_8v;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
@@ -579,7 +572,6 @@
status = "okay";
};
#ifdef DTS_NO_LEGACY
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
@@ -596,4 +588,3 @@
remote-endpoint = <&hdmi_in_vp0>;
};
};
#endif

4
lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h66k.dts
View File

@@ -9,7 +9,3 @@
model = "HINLINK OPC-H66K Board";
compatible = "hinlink,opc-h66k", "rockchip,rk3568";
};
&vcc3v3_pcie {
gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
};

22
lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts
View File

@@ -20,19 +20,20 @@
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy0>;
phy-mode = "rgmii-id";
phy-supply = <&vcc3v3_sys>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
tx_delay = <0x3c>;
rx_delay = <0x2f>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
@@ -41,36 +42,33 @@
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-id";
phy-supply = <&vcc3v3_sys>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
tx_delay = <0x4f>;
rx_delay = <0x26>;
phy-handle = <&rgmii_phy1>;
status = "okay";
};
&mdio0 {
rgmii_phy0: ethernet-phy@0 {
rgmii_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
reg = <0x1>;
};
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
reg = <0x1>;
};
};
&vcc3v3_pcie {
gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
};

12
lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h69k.dts
View File

@@ -88,6 +88,7 @@
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
@@ -95,19 +96,18 @@
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
tx_delay = <0x4f>;
rx_delay = <0x26>;
phy-handle = <&rgmii_phy1>;
status = "okay";
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
reg = <0x1>;
};
};
@@ -126,7 +126,3 @@
&sata0 {
target-supply = <&vcc5v0_ahci>;
};
&vcc3v3_pcie {
gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
};

4
lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
View File

@@ -365,10 +365,6 @@
status = "okay";
};
&rng {
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";

12
lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts
View File

@@ -62,7 +62,6 @@
};
};
#ifdef DTS_NO_LEGACY
hdmi-con {
compatible = "hdmi-connector";
type = "a";
@@ -73,7 +72,6 @@
};
};
};
#endif
pcie30_avdd0v9: pcie30-avdd0v9 {
compatible = "regulator-fixed";
@@ -216,7 +214,6 @@
status = "okay";
};
#ifdef DTS_NO_LEGACY
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
@@ -243,7 +240,6 @@
&hdmi_sound {
status = "okay";
};
#endif
&i2c0 {
status = "okay";
@@ -459,11 +455,9 @@
};
};
#ifdef DTS_NO_LEGACY
&i2s0_8ch {
status = "okay";
};
#endif
&mdio0 {
rgmii_phy0: phy@0 {
@@ -537,10 +531,6 @@
status = "okay";
};
&rng {
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";
@@ -631,7 +621,6 @@
status = "okay";
};
#ifdef DTS_NO_LEGACY
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
@@ -648,4 +637,3 @@
remote-endpoint = <&hdmi_in_vp0>;
};
};
#endif

4
lede/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-t68m.dts
View File

@@ -615,10 +615,6 @@
status = "okay";
};
&rng {
status = "okay";
};
&saradc {
vref-supply = <&vcca_1v8>;
status = "okay";

5
lede/target/linux/rockchip/patches-5.15/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch
View File

@@ -11,14 +11,13 @@ Signed-off-by: wevsty <ty@wevs.org>
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -279,6 +279,17 @@
@@ -279,6 +279,16 @@
status = "disabled";
};
+ rng: rng@ff060000 {
+ compatible = "rockchip,cryptov1-rng";
+ reg = <0x0 0xff060000 0x0 0x4000>;
+
+ clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
+ clock-names = "clk_crypto", "hclk_crypto";
+ assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
@@ -61,7 +60,7 @@ Signed-off-by: wevsty <ty@wevs.org>
+ clock-names = "clk_trng", "hclk_trng";
+ resets = <&cru SRST_TRNG_NS>;
+ reset-names = "reset";
+ status = "disabled";
+ status = "okay";
+ };
+
combphy0: phy@fe820000 {

5
lede/target/linux/rockchip/patches-6.1/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch
View File

@@ -11,14 +11,13 @@ Signed-off-by: wevsty <ty@wevs.org>
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -279,6 +279,17 @@
@@ -279,6 +279,16 @@
status = "disabled";
};
+ rng: rng@ff060000 {
+ compatible = "rockchip,cryptov1-rng";
+ reg = <0x0 0xff060000 0x0 0x4000>;
+
+ clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
+ clock-names = "clk_crypto", "hclk_crypto";
+ assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
@@ -61,7 +60,7 @@ Signed-off-by: wevsty <ty@wevs.org>
+ clock-names = "clk_trng", "hclk_trng";
+ resets = <&cru SRST_TRNG_NS>;
+ reset-names = "reset";
+ status = "disabled";
+ status = "okay";
+ };
+
combphy0: phy@fe820000 {

19
lede/target/linux/rockchip/patches-6.12/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch
View File

@@ -24,3 +24,22 @@ Signed-off-by: wevsty <ty@wevs.org>
resets = <&cru SRST_TRNG_NS>;
status = "disabled";
};
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1857,6 +1857,16 @@
status = "disabled";
};
+ rng: rng@fe378000 {
+ compatible = "rockchip,trngv1";
+ reg = <0x0 0xfe378000 0x0 0x200>;
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
+ clock-names = "hclk_trng";
+ resets = <&scmi_reset SRST_H_TRNG_NS>;
+ reset-names = "reset";
+ };
+
sdhci: mmc@fe2e0000 {
compatible = "rockchip,rk3588-dwcmshc";
reg = <0x0 0xfe2e0000 0x0 0x10000>;

5
lede/target/linux/rockchip/patches-6.6/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch
View File

@@ -11,14 +11,13 @@ Signed-off-by: wevsty <ty@wevs.org>
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -281,6 +281,17 @@
@@ -281,6 +281,16 @@
status = "disabled";
};
+ rng: rng@ff060000 {
+ compatible = "rockchip,cryptov1-rng";
+ reg = <0x0 0xff060000 0x0 0x4000>;
+
+ clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
+ clock-names = "clk_crypto", "hclk_crypto";
+ assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
@@ -61,7 +60,7 @@ Signed-off-by: wevsty <ty@wevs.org>
+ clock-names = "clk_trng", "hclk_trng";
+ resets = <&cru SRST_TRNG_NS>;
+ reset-names = "reset";
+ status = "disabled";
+ status = "okay";
+ };
+
combphy0: phy@fe820000 {