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1. Add rc model in when force skip frm 2. Fix ref frm error when force pskip 3. Disable pskip when cfg force idr 4. Support pskip frm as ref frm 5. Support force skip frm as is_ref or non_ref Change-Id: Ib138ab75a9df2c4521cb376e3a3d7fd30565ecd9 Signed-off-by: Yanjun Liao <yanjun.liao@rock-chips.com>
234 lines
6.6 KiB
C
234 lines
6.6 KiB
C
/*
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* Copyright 2016 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __MPP_RC_DEFS_H__
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#define __MPP_RC_DEFS_H__
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#include "rk_venc_ref.h"
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#define MAX_CPB_REFS (8)
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typedef enum EncFrmType_e {
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INTER_P_FRAME = 0,
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INTER_B_FRAME = 1,
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INTRA_FRAME = 2,
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INTER_VI_FRAME = 3,
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INTRA_RFH_FRAME = 4,
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} EncFrmType;
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/*
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* EncFrmStatus controls record the encoding frame status and also control
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* work flow of encoder. It is the communicat channel between encoder implement
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* module, rate control module and hardware module.
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*
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* bit 0 ~ 31 frame status
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* 0 ~ 15 current frame status
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* 16 ~ 31 reference frame status
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* bit 32 ~ 63 encoding flow control
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*/
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typedef union EncFrmStatus_u {
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struct {
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/*
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* bit 0 ~ 31 frame status
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*/
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/* status flag */
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RK_U32 valid : 1;
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/*
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* 0 - write the reconstructed frame pixel to memory
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* 1 - do not write the reconstructed frame pixel to memory
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*/
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RK_U32 non_recn : 1;
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/*
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* 0 - normal frame and normal dpb management
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* 1 - save recon frame as first pass extra frame. Used in two pass mode
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*/
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RK_U32 save_pass1 : 1;
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/*
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* 0 - use normal input source frame as input
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* 1 - use the previously stored first pass recon frame as input frame
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*/
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RK_U32 use_pass1 : 1;
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/* reference status flag */
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/*
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* 0 - inter frame
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* 1 - intra frame
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*/
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RK_U32 is_intra : 1;
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/*
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* Valid when is_intra is true
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* 0 - normal intra frame
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* 1 - IDR frame
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*/
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RK_U32 is_idr : 1;
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/*
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* 0 - mark as reference frame
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* 1 - mark as non-refernce frame
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*/
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RK_U32 is_non_ref : 1;
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/*
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* Valid when is_non_ref is false
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* 0 - mark as short-term reference frame
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* 1 - mark as long-term refernce frame
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*/
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RK_U32 is_lt_ref : 1;
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/* bit 8 - 15 */
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RK_U32 lt_idx : 4;
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RK_U32 temporal_id : 4;
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/* distance between current frame and reference frame */
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MppEncRefMode ref_mode : 6;
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RK_S32 ref_arg : 8;
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RK_S32 ref_dist : 2;
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/*
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* bit 32 ~ 63 encoder flow control flags
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*/
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/*
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* 0 - normal frame encoding
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* 1 - current frame will be dropped
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*/
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RK_U32 drop : 1;
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/*
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* 0 - rate control module does not change frame type parameter
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* 1 - rate control module changes frame type parameter reencode is needed
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* to reprocess the dpb process. Also this means dpb module will follow
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* the frame status parameter provided by rate control module.
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*/
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RK_U32 re_dpb_proc : 1;
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/*
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* 0 - current frame encoding is in normal flow
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* 1 - current frame encoding is in reencode flow
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*/
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RK_U32 reencode : 1;
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/*
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* When true current frame size is super large then the frame should be reencoded.
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*/
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RK_U32 super_frame : 1;
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/*
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* When true currnet frame is force to encoded as software skip frame
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*/
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RK_U32 force_pskip : 1;
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RK_U32 force_pskip_is_ref : 1;
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/*
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* Current frame is intra refresh frame
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*/
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RK_U32 is_i_refresh : 1;
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/*
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* Current frame needs add recovery point prefix
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*/
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RK_U32 is_i_recovery : 1;
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/* reencode times */
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RK_U32 reencode_times : 8;
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/* sequential index for each frame */
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RK_U32 seq_idx : 16;
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};
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RK_U64 val;
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} EncFrmStatus;
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typedef struct EncCpbStatus_t {
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RK_S32 seq_idx;
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EncFrmStatus curr;
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EncFrmStatus refr;
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/* initial cpb status for current frame encoding */
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EncFrmStatus init[MAX_CPB_REFS];
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/* final cpb status after current frame encoding */
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EncFrmStatus final[MAX_CPB_REFS];
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} EncCpbStatus;
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#define ENC_RC_FORCE_QP (0x00000001)
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typedef struct EncRcForceCfg_t {
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RK_U32 force_flag;
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RK_S32 force_qp;
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RK_U32 reserve[6];
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} EncRcForceCfg;
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/*
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* communication channel between rc / hal / hardware
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*
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* rc -> hal bit_target / bit_max / bit_min
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* hal -> hw quality_target / quality_max / quality_min
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* hw -> rc / hal bit_real / quality_real / madi / madp
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*/
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typedef struct EncRcCommonInfo_t {
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EncFrmType frame_type;
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/* rc to hal */
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RK_S32 bit_target;
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RK_S32 bit_target_fix;
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RK_S32 bit_max;
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RK_S32 bit_min;
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RK_S32 quality_target;
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RK_S32 quality_max;
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RK_S32 quality_min;
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/* rc from hardware */
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RK_S32 bit_real;
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RK_S32 quality_real;
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RK_S32 madi;
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RK_S32 madp;
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RK_U32 iblk4_prop; // scale 256
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RK_S64 sse;
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RK_U32 lvl64_inter_num;
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RK_U32 lvl32_inter_num;
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RK_U32 lvl16_inter_num;
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RK_U32 lvl8_inter_num;
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RK_U32 lvl32_intra_num;
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RK_U32 lvl16_intra_num;
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RK_U32 lvl8_intra_num;
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RK_U32 lvl4_intra_num;
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RK_U32 motion_level;
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RK_U32 complex_level;
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RK_S32 complex_scene;
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RK_S32 scene_mode;
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RK_S32 last_scene_mode;
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/* rc stats info: real time bits */
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RK_S32 rt_bits;
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RK_S32 reserve[4];
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} EncRcTaskInfo;
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typedef struct EncRcTask_s {
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EncCpbStatus cpb;
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EncFrmStatus frm;
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EncRcTaskInfo info;
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EncRcForceCfg force;
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MppFrame frame;
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} EncRcTask;
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#endif /* __MPP_RC_DEFS_H__ */
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