The encoder speed mode is in range of 0 ~ 3.
0 - normal mode with all mode decision path enabled.
1 - fast mode
2 - faster mode
3 - fastest mode
Signed-off-by: toby.zhang <toby.zhang@rock-chips.com>
Change-Id: I0c607adbc1e4cea4025fa8a3816dc3a1ec1f13a1
Signed-off-by: toby.zhang <toby.zhang@rock-chips.com>
Platform: General
Spec: h264/h265/avs2/avs2d/m2vd
MPP_DEC_SET_DISABLE_ERROR:
Comes with an error mark by default.
MPP_DEC_SET_DIS_ERR_CLR_MARK:
Takes effect when MPP_DEC_SET_DISABLE_ERROR is enabled and
is used to clear the error mark.
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
Change-Id: I82b00c737bb72bdc420267d36c28752a5e3ee9a6
Platform: General
Error case:
If the specification specifies a stride, it should be
configured according to the specification's stride rather
than calculated based on width and height, especially
in scenarios involving H.264 field-based sources.
For the case of FBC, hor_stride needs to be processed
based on pixels and is unrelated to bit depth.
Reported-by: Johnson Ding <johnson.ding@rock-chips.com>
Source: rk_32.h264
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
Change-Id: I02058432f2baeeea4c5a87c6845b24de8a78b276
1. Add rc model in when force skip frm
2. Fix ref frm error when force pskip
3. Disable pskip when cfg force idr
4. Support pskip frm as ref frm
5. Support force skip frm as is_ref or non_ref
Change-Id: Ib138ab75a9df2c4521cb376e3a3d7fd30565ecd9
Signed-off-by: Yanjun Liao <yanjun.liao@rock-chips.com>
1. No need to encode IDR when fps_in is changed. So remove it from
`check_resend_hdr`
2. If application do not want any IDR encoded when only fps is changed,
call `mpp_enc_cfg_s32(cfg, "rc:fps_chg_no_idr", 0);` when
initializing.
3. Keeping CPB when only SPS, PPS are updated without IDR encoded for
H.264 encoder.
Change-Id: I034dd789a3f24318004d942624eb10240f7db2e9
Signed-off-by: Johnson Ding <johnson.ding@rock-chips.com>
MppSysCfg is used to config and query mpp gloabl parameters.
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
Change-Id: I132746e07b55040b582878adaef209ce73147da1
Platform: General
Error case:
When info changing, setting the output format to fbc
causes buffer usage exceptions.
Solution:
Add the MPP_DEC_SET_FRAME_INFO command.
From: Product Department 2 czl
Change-Id: I779ca93b461bf220d64e3d4846128ce2f67ffc89
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
Deblur_en is more generic for upper application.
Change-Id: Ibe4e0f81851fdbbe8fb8b7d840a4a9380e0403b1
Signed-off-by: Tingjin Huang <timkingh.huang@rock-chips.com>
1. Add cu_qp_delta_depth cfg
2. Configure AQ regs for H.265
3. Configure regs according to scene mode
4. Support fixed frame level QP
5. Add RDO lambda table index
6. Update stat info for HEVC
7. Add tuning code for H.264 encoder
Change-Id: Id7dae4ed55e1b94622aee72cfce8f24c833d00e1
Signed-off-by: Tingjin Huang <timkingh.huang@rock-chips.com>
Now there are 2 mode for downscale thumbnail frame buffer
1.MPP_FRAME_THUMBNAIL_MIXED (already use on RK3528 box):
Each buffer contains original output frame and 2x2 downscale
small frame, small image's buffer offset will be set in frame
meta info;
2.MPP_FRAME_THUMBNAIL_ONLY (newly added for rk3576 8K video):
for rk3576: vop & gpu does not support 8K frame,
in this case, mpp use 4K downscale buffer as decoder output
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Change-Id: I3acf9486a657fa3e999ca16140f40b2a01ebcaf4
sync_begin - cache invalidate, should be called before cpu read
sync_end - cache flush, should be called after cpu write
MppBuffer sync flow:
1. hw access
2. sync_begin
3. cpu access (read / write)
4. sync_end
5. hw access
NOTE: readonly option is faster for read only buffer.
Signed-off-by: xueman.ruan <xueman.ruan@rock-chips.com>
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: I253a6139e9bb30808c07075d64f17b5cfad8519a
