sync_begin - cache invalidate, should be called before cpu read
sync_end - cache flush, should be called after cpu write
MppBuffer sync flow:
1. hw access
2. sync_begin
3. cpu access (read / write)
4. sync_end
5. hw access
NOTE: readonly option is faster for read only buffer.
Signed-off-by: xueman.ruan <xueman.ruan@rock-chips.com>
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: I253a6139e9bb30808c07075d64f17b5cfad8519a
1. add num of inter/intra different size predicted block info
2. add start qp info
3. add output pskip frame indicator
4. add SSE info
Change-Id: I664f0f87b862bf1c27b43f67c5c3e4b8b060c5b0
Signed-off-by: yanjun.liao <yanjun.liao@rock-chips.com>
fix MPP_FRAME_HDR bit mask conflicts with MPP_FRAME_FMT_LE_MASK
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I3a0df734f8cbc36da625d4b1a70658069809774f
Issue is introduced when user configs log2_max_frm_num.
1. use MppEncH264HwCfg instead of hw_poc_type.
2. slice_write can only use corresponding hardware config.
Signed-off-by: xueman.ruan <xueman.ruan@rock-chips.com>
Change-Id: Id5f3622512075eedc1e9dc99636c3f0dff43d6f1
1. Define more decoder frame error level.
2. Setup errInfo according to error type and level
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: I7d0e87d19fc5b24808cda6b2b1bdaa1e60d091f6
Add parameters required for intra refresh
Add rate control corresponding to intra refresh
Change-Id: I6dbaf70e3c50cd0debf909ded9fb5c4f30df26ec
Signed-off-by: Hongjin Li <vic.hong@rock-chips.com>
1. add viewid in struct VideoFrame for mvc output
2. modify reserved to int type for future
Signed-off-by: He Hua <hh@rock-chips.com>
Change-Id: Ib95999221bef8c9d385b70736ab7978926a78836
1. constraint the range of input argument.
2. add flip config, equal to vertical mirror transformation.
3. add mirroring_ext and rotation_ext to config set, for supporting
GET_CFG control.
Signed-off-by: xueman.ruan <xueman.ruan@rock-chips.com>
Change-Id: I01c0b9187a18851354e81b5f08afc6dcaaba8365
Auto tile cfg will let encoder auto split picture into tiles
according to platform encoder core number.
When enabled on RK3588 all picture will be splited into two tiles.
Encoder cfg string: h265:auto_tile
Change-Id: I3bd91a7781fc2c7e0b43bf2e3be775a5b8098d78
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
The dma_heap is introduced in kernel 5.10.
Change-Id: Id3c116d996da461467fe380a79434ba5ea875033
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
1. Move mpp_log.h to inc for external user.
2. Add mpp_debug.h for mpp internal logging.
3. Fix some warning.
4. Add log level setup function.
5. Check env log_level value in mpp_get_log_level call.
NOTE:
1. mpp internal module should use mpp_debug.h and mpp external user
should use mpp_log.h
2. Use mpp_get_log_level to update mpp_log_level when the env changed.
Change-Id: I90a55a02a72db177533013280dfe111ca3479229
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Split output flag is for low delay packet output mode.
Change-Id: I2f743f14b89864625406ebf94687f4f838f0df15
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
1. Remove next entry in MppFrame.
2. Add MppTask in MppFrame
Change-Id: Icdf4f451e54a30977c5725848c5f4357ae54e6d8
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
