package/mpp
1
0
Fork 0
mirror of https://github.com/nyanmisaka/mpp.git synced 2025-10-05 17:16:50 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

[mpp_device]: move dev_fd in mppDevCtx

Browse Source 
In order to separate the hardware and decoding protocols
more clearly, all API must be implemented in context.

Change-Id: I9f8128c5399149699b2e0a03bfa72ff902c25b87
Signed-off-by: Rimon Xu <rimon.xu@rock-chips.com>
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
This commit is contained in:
Rimon Xu
2018-04-28 11:07:04 +08:00
parent a1d76b96ce
commit ed620a310b
33 changed files with 478 additions and 329 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
mpp/hal/common/h264/hal_h264e_com.h
View File

@@ -408,7 +408,6 @@ typedef struct H264eMbRcCtx_t {
typedef struct H264eHalContext_t {
MppHalApi api;
RK_S32 vpu_fd;
IOInterruptCB int_cb;
MppDevCtx dev_ctx;
h264e_feedback feedback;

28
mpp/hal/rkdec/avsd/hal_avsd_api.c
View File

@@ -115,13 +115,16 @@ MPP_RET hal_avsd_init(void *decoder, MppHalCfg *cfg)
p_hal->init_cb = cfg->hal_int_cb;
//!< mpp_device_init
#ifdef RKPLATFORM
if (p_hal->vpu_socket <= 0) {
p_hal->vpu_socket = mpp_device_init(&p_hal->dev_ctx, MPP_CTX_DEC, MPP_VIDEO_CodingAVS);
if (p_hal->vpu_socket <= 0) {
mpp_err("p_hal->vpu_socket <= 0\n");
ret = MPP_ERR_UNKNOW;
goto __FAILED;
}
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingAVS, /* coding */
.platform = 0, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&p_hal->dev_ctx, &dev_cfg);
if (ret) {
mpp_err("mpp_device_init failed. ret: %d\n", ret);
return ret;
}
#endif
//< get buffer group
@@ -176,8 +179,11 @@ MPP_RET hal_avsd_deinit(void *decoder)
//!< mpp_device_init
#ifdef RKPLATFORM
if (p_hal->vpu_socket >= 0) {
mpp_device_deinit(p_hal->vpu_socket);
if (p_hal->dev_ctx) {
ret = mpp_device_deinit(p_hal->dev_ctx);
if (MPP_OK != ret) {
mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
}
}
#endif
if (p_hal->mv_buf) {
@@ -245,7 +251,7 @@ MPP_RET hal_avsd_start(void *decoder, HalTaskInfo *task)
p_hal->frame_no++;
#ifdef RKPLATFORM
if (mpp_device_send_reg(p_hal->vpu_socket, p_hal->p_regs, AVSD_REGISTERS)) {
if (mpp_device_send_reg(p_hal->dev_ctx, p_hal->p_regs, AVSD_REGISTERS)) {
ret = MPP_ERR_VPUHW;
mpp_err_f("Avs decoder FlushRegs fail. \n");
}
@@ -275,7 +281,7 @@ MPP_RET hal_avsd_wait(void *decoder, HalTaskInfo *task)
goto __SKIP_HARD;
}
#ifdef RKPLATFORM
mpp_device_wait_reg(p_hal->vpu_socket, p_hal->p_regs, AVSD_REGISTERS);
mpp_device_wait_reg(p_hal->dev_ctx, p_hal->p_regs, AVSD_REGISTERS);
#endif
__SKIP_HARD:

1
mpp/hal/rkdec/avsd/hal_avsd_reg.h
View File

@@ -102,7 +102,6 @@ typedef struct avsd_hal_ctx_t {
MppBufferGroup buf_group;
IOInterruptCB init_cb;
MppDevCtx dev_ctx;
RK_S32 vpu_socket;
AvsdSyntax_t syn;
RK_U32 *p_regs;
MppBuffer mv_buf;

25
mpp/hal/rkdec/h264d/hal_h264d_api.c
View File

@@ -174,14 +174,16 @@ MPP_RET hal_h264d_init(void *hal, MppHalCfg *cfg)
mpp_env_get_u32("rkv_h264d_debug", &rkv_h264d_hal_debug, 0);
//!< mpp_device_init
#ifdef RKPLATFORM
if (p_hal->vpu_socket <= 0) {
mpp_device_control(&p_hal->dev_ctx, MPP_DEV_SET_HARD_PLATFORM, &hard_platform);
p_hal->vpu_socket = mpp_device_init(&p_hal->dev_ctx, MPP_CTX_DEC, MPP_VIDEO_CodingAVC);
if (p_hal->vpu_socket <= 0) {
mpp_err("p_hal->vpu_socket <= 0\n");
ret = MPP_ERR_UNKNOW;
goto __FAILED;
}
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingAVC, /* coding */
.platform = hard_platform, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&p_hal->dev_ctx, &dev_cfg);
if (ret) {
mpp_err("mpp_device_init failed ret: %d\n", ret);
goto __FAILED;
}
#endif
//< get buffer group
@@ -219,8 +221,11 @@ MPP_RET hal_h264d_deinit(void *hal)
FUN_CHECK(ret = p_hal->hal_api.deinit(hal));
//!< mpp_device_init
#ifdef RKPLATFORM
if (p_hal->vpu_socket >= 0) {
mpp_device_deinit(p_hal->vpu_socket);
if (p_hal->dev_ctx) {
ret = mpp_device_deinit(p_hal->dev_ctx);
if (MPP_OK != ret) {
mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
}
}
#endif
if (p_hal->buf_group) {

1
mpp/hal/rkdec/h264d/hal_h264d_global.h
View File

@@ -125,7 +125,6 @@ typedef struct h264d_hal_ctx_t {
MppBufSlots packet_slots;
MppBufferGroup buf_group;
MppBuffer cabac_buf;
RK_S32 vpu_socket;
IOInterruptCB init_cb;
MppDevCtx dev_ctx;
} H264dHalCtx_t;

4
mpp/hal/rkdec/h264d/hal_h264d_rkv_reg.c
View File

@@ -658,7 +658,7 @@ MPP_RET rkv_h264d_start(void *hal, HalTaskInfo *task)
p_regs[1] |= 0x00000061; // run hardware, enable buf_empty_en
#ifdef RKPLATFORM
if (mpp_device_send_reg(p_hal->vpu_socket, (RK_U32 *)p_regs, DEC_RKV_REGISTERS)) {
if (mpp_device_send_reg(p_hal->dev_ctx, (RK_U32 *)p_regs, DEC_RKV_REGISTERS)) {
ret = MPP_ERR_VPUHW;
H264D_ERR("H264 RKV FlushRegs fail. \n");
}
@@ -690,7 +690,7 @@ MPP_RET rkv_h264d_wait(void *hal, HalTaskInfo *task)
#ifdef RKPLATFORM
{
RK_S32 wait_ret = -1;
wait_ret = mpp_device_wait_reg(p_hal->vpu_socket, (RK_U32 *)p_hal->regs, DEC_RKV_REGISTERS);
wait_ret = mpp_device_wait_reg(p_hal->dev_ctx, (RK_U32 *)p_hal->regs, DEC_RKV_REGISTERS);
if (wait_ret) {
ret = MPP_ERR_VPUHW;
H264D_ERR("H264 RKV FlushRegs fail. \n");

4
mpp/hal/rkdec/h264d/hal_h264d_vdpu1.c
View File

@@ -831,7 +831,7 @@ MPP_RET vdpu1_h264d_start(void *hal, HalTaskInfo *task)
p_regs->SwReg57.sw_paral_bus = 1;
#ifdef RKPLATFORM
if (mpp_device_send_reg(p_hal->vpu_socket, (RK_U32 *)p_hal->regs,
if (mpp_device_send_reg(p_hal->dev_ctx, (RK_U32 *)p_hal->regs,
DEC_VDPU1_REGISTERS)) {
ret = MPP_ERR_VPUHW;
mpp_err_f("H264 VDPU1 FlushRegs fail, pid=%d, hal_frame_no=%d. \n",
@@ -863,7 +863,7 @@ MPP_RET vdpu1_h264d_wait(void *hal, HalTaskInfo *task)
#ifdef RKPLATFORM
{
RK_S32 wait_ret = -1;
wait_ret = mpp_device_wait_reg(p_hal->vpu_socket, (RK_U32 *)p_hal->regs,
wait_ret = mpp_device_wait_reg(p_hal->dev_ctx, (RK_U32 *)p_hal->regs,
DEC_VDPU1_REGISTERS);
if (wait_ret) {
ret = MPP_ERR_VPUHW;

4
mpp/hal/rkdec/h264d/hal_h264d_vdpu2.c
View File

@@ -791,7 +791,7 @@ MPP_RET vdpu2_h264d_start(void *hal, HalTaskInfo *task)
p_regs->sw57.inter_dblspeed = 1;
p_regs->sw57.intra_dblspeed = 1;
#ifdef RKPLATFORM
if (mpp_device_send_reg(p_hal->vpu_socket, (RK_U32 *)p_hal->regs,
if (mpp_device_send_reg(p_hal->dev_ctx, (RK_U32 *)p_hal->regs,
DEC_VDPU_REGISTERS)) {
ret = MPP_ERR_VPUHW;
mpp_err("H264 VDPU FlushRegs fail, pid=%d.\n", getpid());
@@ -820,7 +820,7 @@ MPP_RET vdpu2_h264d_wait(void *hal, HalTaskInfo *task)
#ifdef RKPLATFORM
{
RK_S32 wait_ret = -1;
wait_ret = mpp_device_wait_reg(p_hal->vpu_socket, (RK_U32 *)p_hal->regs,
wait_ret = mpp_device_wait_reg(p_hal->dev_ctx, (RK_U32 *)p_hal->regs,
DEC_VDPU_REGISTERS);
if (wait_ret) {
ret = MPP_ERR_VPUHW;

31
mpp/hal/rkdec/h265d/hal_h265d_reg.c
View File

@@ -60,7 +60,6 @@ typedef struct h265d_reg_buf {
void* hw_regs;
} h265d_reg_buf_t;
typedef struct h265d_reg_context {
RK_S32 vpu_socket;
MppBufSlots slots;
MppBufSlots packet_slots;
MppBufferGroup group;
@@ -436,12 +435,16 @@ MPP_RET hal_h265d_init(void *hal, MppHalCfg *cfg)
reg_cxt->packet_slots = cfg->packet_slots;
///<- mpp_device_init
#ifdef RKPLATFORM
if (reg_cxt->vpu_socket <= 0) {
reg_cxt->vpu_socket = mpp_device_init(&reg_cxt->dev_ctx, MPP_CTX_DEC, MPP_VIDEO_CodingHEVC);
if (reg_cxt->vpu_socket <= 0) {
mpp_err("reg_cxt->vpu_socket <= 0\n");
return MPP_ERR_UNKNOW;
}
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingHEVC, /* coding */
.platform = 0, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&reg_cxt->dev_ctx, &dev_cfg);
if (ret) {
mpp_err("mpp_device_init failed. ret: %d\n", ret);
return ret;
}
#endif
if (reg_cxt->group == NULL) {
@@ -479,13 +482,15 @@ MPP_RET hal_h265d_deinit(void *hal)
{
RK_S32 ret = 0;
h265d_reg_context_t *reg_cxt = ( h265d_reg_context_t *)hal;
h265d_reg_context_t *reg_cxt = (h265d_reg_context_t *)hal;
///<- mpp_device_init
#ifdef RKPLATFORM
if (reg_cxt->vpu_socket >= 0) {
mpp_device_deinit(reg_cxt->vpu_socket);
if (reg_cxt->dev_ctx) {
ret = mpp_device_deinit(reg_cxt->dev_ctx);
if (MPP_OK != ret) {
mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
}
}
#endif
@@ -1523,7 +1528,7 @@ MPP_RET hal_h265d_start(void *hal, HalTaskInfo *task)
}
#ifdef RKPLATFORM
// 68 is the nb of uint32_t
ret = mpp_device_send_reg(reg_cxt->vpu_socket, (RK_U32*)hw_regs, 78);
ret = mpp_device_send_reg(reg_cxt->dev_ctx, (RK_U32*)hw_regs, 78);
if (ret != 0) {
mpp_err("RK_HEVC_DEC: ERROR: mpp_device_send_reg Failed!!!\n");
return MPP_ERR_VPUHW;
@@ -1551,7 +1556,7 @@ MPP_RET hal_h265d_wait(void *hal, HalTaskInfo *task)
hw_regs = ( H265d_REGS_t *)reg_cxt->hw_regs;
}
p = (RK_U8*)hw_regs;
ret = mpp_device_wait_reg(reg_cxt->vpu_socket, (RK_U32*)hw_regs, 78);
ret = mpp_device_wait_reg(reg_cxt->dev_ctx, (RK_U32*)hw_regs, 78);
if (hw_regs->sw_interrupt.sw_dec_error_sta
|| hw_regs->sw_interrupt.sw_dec_empty_sta) {

30
mpp/hal/rkdec/vp9d/hal_vp9d_api.c
View File

@@ -74,7 +74,6 @@ typedef struct vp9_dec_last_info {
} vp9_dec_last_info_t;
typedef struct hal_vp9_context {
RK_S32 vpu_socket;
MppBufSlots slots;
MppBufSlots packet_slots;
MppDevCtx dev_ctx;
@@ -132,13 +131,18 @@ MPP_RET hal_vp9d_init(void *hal, MppHalCfg *cfg)
reg_cxt->packet_slots = cfg->packet_slots;
///<- mpp_device_init
#ifdef RKPLATFORM
if (reg_cxt->vpu_socket <= 0) {
reg_cxt->vpu_socket = mpp_device_init(&reg_cxt->dev_ctx, MPP_CTX_DEC, MPP_VIDEO_CodingVP9);
if (reg_cxt->vpu_socket <= 0) {
mpp_err("vp9 reg_cxt->vpu_socket <= 0\n");
return MPP_ERR_UNKNOW;
}
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingVP9, /* coding */
.platform = 0, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&reg_cxt->dev_ctx, &dev_cfg);
if (ret) {
mpp_err("mpp_device_init failed. ret: %d\n", ret);
return ret;
}
#endif
if (reg_cxt->group == NULL) {
@@ -206,8 +210,11 @@ MPP_RET hal_vp9d_deinit(void *hal)
MPP_RET ret = MPP_OK;
hal_vp9_context_t *reg_cxt = (hal_vp9_context_t *)hal;
#ifdef RKPLATFORM
if (reg_cxt->vpu_socket >= 0) {
mpp_device_deinit(reg_cxt->vpu_socket);
if (reg_cxt->dev_ctx) {
ret = mpp_device_deinit(reg_cxt->dev_ctx);
if (MPP_OK != ret) {
mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
}
}
#endif
if (reg_cxt->probe_base) {
@@ -841,7 +848,7 @@ MPP_RET hal_vp9d_start(void *hal, HalTaskInfo *task)
}
#ifdef RKPLATFORM
#if 1
ret = mpp_device_send_reg(reg_cxt->vpu_socket, (RK_U32*)hw_regs, sizeof(VP9_REGS) / 4); // 68 is the nb of uint32_t
ret = mpp_device_send_reg(reg_cxt->dev_ctx, (RK_U32*)hw_regs, sizeof(VP9_REGS) / 4); // 68 is the nb of uint32_t
if (ret != 0) {
mpp_err("VP9H_DBG_REG: ERROR: mpp_device_send_reg Failed!!!\n");
return MPP_ERR_VPUHW;
@@ -869,7 +876,8 @@ MPP_RET hal_vp9d_wait(void *hal, HalTaskInfo *task)
VP9_REGS *hw_regs = (VP9_REGS*)reg_cxt->hw_regs;
RK_U8* p = (RK_U8*)hw_regs;
ret = mpp_device_wait_reg(reg_cxt->vpu_socket, (RK_U32*)hw_regs, sizeof(VP9_REGS) / 4);
ret = mpp_device_wait_reg(reg_cxt->dev_ctx, (RK_U32*)hw_regs, sizeof(VP9_REGS) / 4);
for (i = 0; i < sizeof(VP9_REGS) / 4; i++) {
if (i == 1) {
vp9h_dbg(VP9H_DBG_REG, "RK_VP9_DEC: regs[%02d]=%08X\n", i, *((RK_U32*)p));

51
mpp/hal/rkenc/h264e/hal_h264e_rkv.c
View File

@@ -305,6 +305,7 @@ static void h264e_rkv_reference_init( void *dpb, H264eHalParam *par)
MPP_RET hal_h264e_rkv_init(void *hal, MppHalCfg *cfg)
{
RK_U32 k = 0;
MPP_RET ret = MPP_OK;
H264eHalContext *ctx = (H264eHalContext *)hal;
H264eRkvDpbCtx *dpb_ctx = NULL;
h264e_hal_rkv_buffers *buffers = NULL;
@@ -335,14 +336,17 @@ MPP_RET hal_h264e_rkv_init(void *hal, MppHalCfg *cfg)
dpb_ctx->i_frame_cnt = 0;
dpb_ctx->i_frame_num = 0;
ctx->vpu_fd = -1;
#ifdef RKPLATFORM
if (ctx->vpu_fd <= 0) {
ctx->vpu_fd = mpp_device_init(&ctx->dev_ctx, MPP_CTX_ENC, MPP_VIDEO_CodingAVC);
if (ctx->vpu_fd <= 0) {
h264e_hal_err("get vpu_socket(%d) <=0, failed. \n", ctx->vpu_fd);
return MPP_ERR_UNKNOW;
}
MppDevCfg dev_cfg = {
.type = MPP_CTX_ENC, /* type */
.coding = MPP_VIDEO_CodingAVC, /* coding */
.platform = 0, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
if (ret != MPP_OK) {
h264e_hal_err("mpp_device_init failed. ret: %d\n", ret);
return ret;
}
#endif
@@ -361,6 +365,7 @@ MPP_RET hal_h264e_rkv_init(void *hal, MppHalCfg *cfg)
MPP_RET hal_h264e_rkv_deinit(void *hal)
{
MPP_RET ret = MPP_OK;
H264eHalContext *ctx = (H264eHalContext *)hal;
h264e_hal_enter();
@@ -422,18 +427,14 @@ MPP_RET hal_h264e_rkv_deinit(void *hal)
}
#ifdef RKPLATFORM
if (ctx->vpu_fd <= 0) {
h264e_hal_err("invalid vpu socket: %d", ctx->vpu_fd);
return MPP_NOK;
}
if (mpp_device_deinit(ctx->vpu_fd)) {
h264e_hal_err("mpp_device_deinit failed");
return MPP_ERR_VPUHW;
if (ctx->dev_ctx) {
ret = mpp_device_deinit(ctx->dev_ctx);
if (MPP_OK != ret) {
h264e_hal_err("mpp_device_deinit failed. ret: %d\n", ret);
}
}
#endif
h264e_hal_leave();
return MPP_OK;
}
@@ -1498,13 +1499,8 @@ MPP_RET hal_h264e_rkv_start(void *hal, HalTaskInfo *task)
(void)task;
#ifdef RKPLATFORM
if (ctx->vpu_fd <= 0) {
h264e_hal_err("invalid vpu socket: %d", ctx->vpu_fd);
return MPP_NOK;
}
h264e_hal_dbg(H264E_DBG_DETAIL, "vpu client is sending %d regs", length);
if (MPP_OK != mpp_device_send_reg(ctx->vpu_fd, (RK_U32 *)ioctl_info, length)) {
if (MPP_OK != mpp_device_send_reg(ctx->dev_ctx, (RK_U32 *)ioctl_info, length)) {
h264e_hal_err("mpp_device_send_reg Failed!!!");
return MPP_ERR_VPUHW;
} else {
@@ -1610,14 +1606,14 @@ static MPP_RET h264e_rkv_resend(H264eHalContext *ctx, RK_S32 mb_rc)
ioctl_info->frame_num) >> 2;
#ifdef RKPLATFORM
if (mpp_device_send_reg(ctx->vpu_fd, (RK_U32 *)ioctl_info, length)) {
if (mpp_device_send_reg(ctx->dev_ctx, (RK_U32 *)ioctl_info, length)) {
h264e_hal_err("mpp_device_send_reg Failed!!!");
return MPP_ERR_VPUHW;
} else {
h264e_hal_dbg(H264E_DBG_DETAIL, "mpp_device_send_reg successfully!");
}
hw_ret = mpp_device_wait_reg(ctx->vpu_fd, (RK_U32 *)reg_out, length);
hw_ret = mpp_device_wait_reg(ctx->dev_ctx, (RK_U32 *)reg_out, length);
#endif
if (hw_ret != MPP_OK) {
h264e_hal_err("hardware returns error:%d", hw_ret);
@@ -1679,15 +1675,10 @@ MPP_RET hal_h264e_rkv_wait(void *hal, HalTaskInfo *task)
}
#ifdef RKPLATFORM
if (ctx->vpu_fd <= 0) {
h264e_hal_err("invalid vpu socket: %d", ctx->vpu_fd);
return MPP_NOK;
}
h264e_hal_dbg(H264E_DBG_DETAIL, "mpp_device_wait_reg expect length %d\n",
length);
hw_ret = mpp_device_wait_reg(ctx->vpu_fd, (RK_U32 *)reg_out, length);
hw_ret = mpp_device_wait_reg(ctx->dev_ctx, (RK_U32 *)reg_out, length);
h264e_hal_dbg(H264E_DBG_DETAIL, "mpp_device_wait_reg: ret %d\n", hw_ret);

2
mpp/hal/rkenc/h264e/hal_h264e_rkv_utils.c
View File

@@ -30,7 +30,7 @@ MPP_RET h264e_rkv_set_osd_plt(H264eHalContext *ctx, void *param)
if (plt->buf) {
ctx->osd_plt_type = H264E_OSD_PLT_TYPE_USERDEF;
#ifdef RKPLATFORM
if (MPP_OK != mpp_device_send_reg_with_id(ctx->vpu_fd,
if (MPP_OK != mpp_device_send_reg_with_id(ctx->dev_ctx,
H264E_IOC_SET_OSD_PLT, param,
sizeof(MppEncOSDPlt))) {
h264e_hal_err("set osd plt error");

25
mpp/hal/vpu/h263d/hal_h263d_reg.c
View File

@@ -39,7 +39,6 @@ typedef struct h263d_reg_context {
MppDevCtx dev_ctx;
// save fd for curr/ref0/ref1 for reg_gen
RK_S32 vpu_fd;
RK_S32 fd_curr;
RK_S32 fd_ref0;
@@ -150,7 +149,6 @@ MPP_RET hal_vpu_h263d_init(void *hal, MppHalCfg *cfg)
MPP_RET ret = MPP_OK;
VpuH263dRegSet_t *regs = NULL;
hal_h263_ctx *ctx = (hal_h263_ctx *)hal;
RK_S32 vpu_fd = -1;
mpp_assert(hal);
@@ -162,9 +160,15 @@ MPP_RET hal_vpu_h263d_init(void *hal, MppHalCfg *cfg)
}
#ifdef RKPLATFORM
vpu_fd = mpp_device_init(&ctx->dev_ctx, MPP_CTX_DEC, MPP_VIDEO_CodingH263);
if (vpu_fd < 0) {
mpp_err_f("failed to open vpu client\n");
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingH263, /* coding */
.platform = 0, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
if (ret != MPP_OK) {
mpp_err_f("mpp_device_init failed. ret: %d\n", ret);
ret = MPP_ERR_UNKNOW;
goto ERR_RET;
}
@@ -192,7 +196,6 @@ MPP_RET hal_vpu_h263d_init(void *hal, MppHalCfg *cfg)
ctx->frm_slots = cfg->frame_slots;
ctx->pkt_slots = cfg->packet_slots;
ctx->int_cb = cfg->hal_int_cb;
ctx->vpu_fd = vpu_fd;
ctx->regs = regs;
mpp_env_get_u32("h263d_hal_debug", &h263d_hal_debug, 0);
@@ -220,9 +223,9 @@ MPP_RET hal_vpu_h263d_deinit(void *hal)
}
#ifdef RKPLATFORM
if (ctx->vpu_fd >= 0) {
mpp_device_deinit(ctx->vpu_fd);
ctx->vpu_fd = -1;
ret = mpp_device_deinit(ctx->dev_ctx);
if (MPP_OK != ret) {
mpp_err("mpp_device_deinit failed ret: %d\n", ret);
}
#endif
@@ -276,7 +279,7 @@ MPP_RET hal_vpu_h263d_start(void *hal, HalTaskInfo *task)
}
}
ret = mpp_device_send_reg(ctx->vpu_fd, regs, reg_count);
ret = mpp_device_send_reg(ctx->dev_ctx, regs, reg_count);
#endif
(void)hal;
(void)task;
@@ -292,7 +295,7 @@ MPP_RET hal_vpu_h263d_wait(void *hal, HalTaskInfo *task)
RK_U32* regs = (RK_U32 *)&reg_out;
RK_U32 reg_count = (sizeof(reg_out) / sizeof(RK_U32));
ret = mpp_device_wait_reg(ctx->vpu_fd, regs, (sizeof(reg_out) / sizeof(RK_U32)));
ret = mpp_device_wait_reg(ctx->dev_ctx, regs, (sizeof(reg_out) / sizeof(RK_U32)));
if (h263d_hal_debug & H263D_HAL_DBG_REG_GET) {
RK_U32 i = 0;

45
mpp/hal/vpu/h264e/hal_h264e_vepu1.c
View File

@@ -37,6 +37,7 @@ static RK_U32 hal_vpu_h264e_debug = 0;
MPP_RET hal_h264e_vepu1_init(void *hal, MppHalCfg *cfg)
{
MPP_RET ret = MPP_OK;
H264eHalContext *ctx = (H264eHalContext *)hal;
h264e_hal_enter();
@@ -51,15 +52,17 @@ MPP_RET hal_h264e_vepu1_init(void *hal, MppHalCfg *cfg)
h264e_vpu_init_extra_info(ctx->extra_info);
ctx->vpu_fd = -1;
h264e_hal_dbg(H264E_DBG_DETAIL, "vpu client: %d", ctx->vpu_fd);
#ifdef RKPLATFORM
if (ctx->vpu_fd <= 0) {
ctx->vpu_fd = mpp_device_init(&ctx->dev_ctx, MPP_CTX_ENC, MPP_VIDEO_CodingAVC);
if (ctx->vpu_fd <= 0) {
mpp_err("get vpu_fd(%d) <=0, failed. \n", ctx->vpu_fd);
return MPP_ERR_UNKNOW;
}
MppDevCfg dev_cfg = {
.type = MPP_CTX_ENC, /* type */
.coding = MPP_VIDEO_CodingAVC, /* coding */
.platform = 0, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
if (ret != MPP_OK) {
mpp_err("mpp_device_init failed. ret: %d\n", ret);
return ret;
}
#endif
ctx->hw_cfg.qp_prev = ctx->cfg->codec.h264.qp_init;
@@ -71,6 +74,7 @@ MPP_RET hal_h264e_vepu1_init(void *hal, MppHalCfg *cfg)
MPP_RET hal_h264e_vepu1_deinit(void *hal)
{
MPP_RET ret = MPP_OK;
H264eHalContext *ctx = (H264eHalContext *)hal;
h264e_hal_enter();
@@ -107,19 +111,14 @@ MPP_RET hal_h264e_vepu1_deinit(void *hal)
}
#ifdef RKPLATFORM
if (ctx->vpu_fd <= 0) {
mpp_err("invalid vpu socket: %d", ctx->vpu_fd);
return MPP_NOK;
}
if (mpp_device_deinit(ctx->vpu_fd)) {
mpp_err("mpp_device_deinit failed");
return MPP_ERR_VPUHW;
ret = mpp_device_deinit(ctx->dev_ctx);
if (ret) {
mpp_err("mpp_device_deinit failed ret: %d", ret);
}
#endif
h264e_hal_leave();
return MPP_OK;
return ret;
}
MPP_RET hal_h264e_vepu1_gen_regs(void *hal, HalTaskInfo *task)
@@ -429,11 +428,11 @@ MPP_RET hal_h264e_vepu1_start(void *hal, HalTaskInfo *task)
(void)task;
h264e_hal_enter();
#ifdef RKPLATFORM
if (ctx->vpu_fd > 0) {
if (ctx->dev_ctx) {
RK_U32 *p_regs = (RK_U32 *)ctx->regs;
h264e_hal_dbg(H264E_DBG_DETAIL, "vpu client is sending %d regs",
VEPU_H264E_VEPU1_NUM_REGS);
if (MPP_OK != mpp_device_send_reg(ctx->vpu_fd, p_regs,
if (MPP_OK != mpp_device_send_reg(ctx->dev_ctx, p_regs,
VEPU_H264E_VEPU1_NUM_REGS)) {
mpp_err("mpp_device_send_reg Failed!!!");
return MPP_ERR_VPUHW;
@@ -441,7 +440,7 @@ MPP_RET hal_h264e_vepu1_start(void *hal, HalTaskInfo *task)
h264e_hal_dbg(H264E_DBG_DETAIL, "mpp_device_send_reg successfully!");
}
} else {
mpp_err("invalid vpu socket: %d", ctx->vpu_fd);
mpp_err("invalid device ctx: %p", ctx->dev_ctx);
return MPP_NOK;
}
#endif
@@ -485,8 +484,8 @@ MPP_RET hal_h264e_vepu1_wait(void *hal, HalTaskInfo *task)
h264e_hal_enter();
#ifdef RKPLATFORM
if (ctx->vpu_fd > 0) {
RK_S32 hw_ret = mpp_device_wait_reg(ctx->vpu_fd, (RK_U32 *)reg_out,
if (ctx->dev_ctx) {
RK_S32 hw_ret = mpp_device_wait_reg(ctx->dev_ctx, (RK_U32 *)reg_out,
VEPU_H264E_VEPU1_NUM_REGS);
h264e_hal_dbg(H264E_DBG_DETAIL, "mpp_device_wait_reg: ret %d\n", hw_ret);
@@ -496,7 +495,7 @@ MPP_RET hal_h264e_vepu1_wait(void *hal, HalTaskInfo *task)
return MPP_ERR_VPUHW;
}
} else {
mpp_err("invalid vpu socket: %d", ctx->vpu_fd);
mpp_err("invalid device ctx: %p", ctx->dev_ctx);
return MPP_NOK;
}
#endif

46
mpp/hal/vpu/h264e/hal_h264e_vepu2.c
View File

@@ -257,13 +257,17 @@ MPP_RET hal_h264e_vepu2_init(void *hal, MppHalCfg *cfg)
h264e_vpu_open_dump_files(ctx->dump_files);
#endif
ctx->vpu_fd = -1;
#ifdef RKPLATFORM
ctx->vpu_fd = mpp_device_init(&ctx->dev_ctx, MPP_CTX_ENC, MPP_VIDEO_CodingAVC);
if (ctx->vpu_fd <= 0) {
mpp_err("get vpu_socket(%d) <=0, failed. \n", ctx->vpu_fd);
ret = MPP_ERR_UNKNOW;
MppDevCfg dev_cfg = {
.type = MPP_CTX_ENC, /* type */
.coding = MPP_VIDEO_CodingAVC, /* coding */
.platform = 0, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
if (ret) {
mpp_err("mpp_device_init failed. ret: %d\n", ret);
return ret;
}
#endif
ctx->hw_cfg.qp_prev = ctx->cfg->codec.h264.qp_init;
@@ -275,6 +279,7 @@ MPP_RET hal_h264e_vepu2_init(void *hal, MppHalCfg *cfg)
MPP_RET hal_h264e_vepu2_deinit(void *hal)
{
MPP_RET ret = MPP_OK;
H264eHalContext *ctx = (H264eHalContext *)hal;
h264e_hal_enter();
@@ -314,19 +319,14 @@ MPP_RET hal_h264e_vepu2_deinit(void *hal)
#endif
#ifdef RKPLATFORM
if (ctx->vpu_fd <= 0) {
mpp_err("invalid vpu socket: %d", ctx->vpu_fd);
return MPP_NOK;
}
if (mpp_device_deinit(ctx->vpu_fd)) {
mpp_err("mpp_device_deinit failed");
return MPP_ERR_VPUHW;
ret = mpp_device_deinit(ctx->dev_ctx);
if (ret) {
mpp_err("mpp_device_deinit failed, ret: %d", ret);
}
#endif
h264e_hal_leave();
return MPP_OK;
return ret;
}
MPP_RET hal_h264e_vepu2_gen_regs(void *hal, HalTaskInfo *task)
@@ -662,21 +662,23 @@ MPP_RET hal_h264e_vepu2_gen_regs(void *hal, HalTaskInfo *task)
MPP_RET hal_h264e_vepu2_start(void *hal, HalTaskInfo *task)
{
MPP_RET ret;
H264eHalContext *ctx = (H264eHalContext *)hal;
(void)task;
h264e_hal_enter();
#ifdef RKPLATFORM
if (ctx->vpu_fd > 0) {
if (ctx->dev_ctx) {
RK_U32 *p_regs = (RK_U32 *)ctx->regs;
h264e_hal_dbg(H264E_DBG_DETAIL, "vpu client is sending %d regs", VEPU2_H264E_NUM_REGS);
if (MPP_OK != mpp_device_send_reg(ctx->vpu_fd, p_regs, VEPU2_H264E_NUM_REGS)) {
ret = mpp_device_send_reg(ctx->dev_ctx, p_regs, VEPU2_H264E_NUM_REGS);
if (ret) {
mpp_err("mpp_device_send_reg Failed!!!");
return MPP_ERR_VPUHW;
return ret;
} else {
h264e_hal_dbg(H264E_DBG_DETAIL, "mpp_device_send_reg successfully!");
}
} else {
mpp_err("invalid vpu socket: %d", ctx->vpu_fd);
mpp_err("invalid device ctx: %p", ctx->dev_ctx);
return MPP_NOK;
}
#endif
@@ -720,8 +722,8 @@ MPP_RET hal_h264e_vepu2_wait(void *hal, HalTaskInfo *task)
h264e_hal_enter();
#ifdef RKPLATFORM
if (ctx->vpu_fd > 0) {
RK_S32 hw_ret = mpp_device_wait_reg(ctx->vpu_fd, (RK_U32 *)reg_out,
if (ctx->dev_ctx) {
RK_S32 hw_ret = mpp_device_wait_reg(ctx->dev_ctx, (RK_U32 *)reg_out,
VEPU2_H264E_NUM_REGS);
h264e_hal_dbg(H264E_DBG_DETAIL, "mpp_device_wait_reg: ret %d\n", hw_ret);
@@ -731,7 +733,7 @@ MPP_RET hal_h264e_vepu2_wait(void *hal, HalTaskInfo *task)
return MPP_ERR_VPUHW;
}
} else {
mpp_err("invalid vpu socket: %d", ctx->vpu_fd);
mpp_err("invalid device ctx: %p", ctx->dev_ctx);
return MPP_NOK;
}
#endif

1
mpp/hal/vpu/jpegd/hal_jpegd_base.h
View File

@@ -52,7 +52,6 @@ typedef struct JpegdHalCtx {
MppBufSlots packet_slots;
MppBufSlots frame_slots;
MppDevCtx dev_ctx;
RK_S32 vpu_socket;
void *regs;
MppBufferGroup group;
MppBuffer frame_buf;

57
mpp/hal/vpu/jpegd/hal_jpegd_vdpu1.c
View File

@@ -770,17 +770,16 @@ MPP_RET hal_jpegd_vdpu1_init(void *hal, MppHalCfg *cfg)
//get vpu socket
#ifdef RKPLATFORM
if (JpegHalCtx->vpu_socket <= 0) {
JpegHalCtx->vpu_socket = mpp_device_init(&JpegHalCtx->dev_ctx, MPP_CTX_DEC,
MPP_VIDEO_CodingMJPEG);
if (JpegHalCtx->vpu_socket <= 0) {
mpp_err_f("get vpu_socket(%d) <= 0, failed.\n",
JpegHalCtx->vpu_socket);
return MPP_ERR_UNKNOW;
} else {
jpegd_dbg_hal("get vpu_socket(%d), success.\n",
JpegHalCtx->vpu_socket);
}
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingMJPEG, /* coding */
.platform = 0, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&JpegHalCtx->dev_ctx, &dev_cfg);
if (ret) {
mpp_err("mpp_device_init failed. ret: %d\n", ret);
return ret;
}
#endif
@@ -856,8 +855,11 @@ MPP_RET hal_jpegd_vdpu1_deinit(void *hal)
JpegdHalCtx *JpegHalCtx = (JpegdHalCtx *)hal;
#ifdef RKPLATFORM
if (JpegHalCtx->vpu_socket >= 0) {
mpp_device_deinit(JpegHalCtx->vpu_socket);
if (JpegHalCtx->dev_ctx) {
ret = mpp_device_deinit(JpegHalCtx->dev_ctx);
if (MPP_OK != ret) {
mpp_err("mpp_device_deinit failed ret: %d\n", ret);
}
}
#endif
@@ -922,19 +924,20 @@ MPP_RET hal_jpegd_vdpu1_gen_regs(void *hal, HalTaskInfo *syn)
jpegd_setup_output_fmt(JpegHalCtx, syntax);
#ifdef RKPLATFORM
if (JpegHalCtx->set_output_fmt_flag && (JpegHalCtx->vpu_socket > 0)) {
mpp_device_deinit(JpegHalCtx->vpu_socket);
JpegHalCtx->vpu_socket = 0;
mpp_device_control(&JpegHalCtx->dev_ctx, MPP_DEV_ENABLE_POSTPROCCESS, NULL);
JpegHalCtx->vpu_socket = mpp_device_init(&JpegHalCtx->dev_ctx, MPP_CTX_DEC,
MPP_VIDEO_CodingMJPEG);
if (JpegHalCtx->vpu_socket <= 0) {
mpp_err_f("get vpu_socket(%d) <= 0, failed.\n",
JpegHalCtx->vpu_socket);
return MPP_ERR_UNKNOW;
if (JpegHalCtx->set_output_fmt_flag && (NULL != JpegHalCtx->dev_ctx)) {
mpp_device_deinit(JpegHalCtx->dev_ctx);
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingMJPEG, /* coding */
.platform = 0, /* platform */
.pp_enable = 1, /* pp_enable */
};
ret = mpp_device_init(&JpegHalCtx->dev_ctx, &dev_cfg);
if (ret) {
mpp_err("mpp_device_init failed. ret: %d\n", ret);
return ret;
} else {
jpegd_dbg_hal("get vpu_socket(%d), success.\n",
JpegHalCtx->vpu_socket);
jpegd_dbg_hal("mpp_device_init success.\n");
}
}
@@ -972,7 +975,7 @@ MPP_RET hal_jpegd_vdpu1_start(void *hal, HalTaskInfo *task)
#ifdef RKPLATFORM
RK_U32 *p_regs = (RK_U32 *)JpegHalCtx->regs;
ret = mpp_device_send_reg(JpegHalCtx->vpu_socket, p_regs,
ret = mpp_device_send_reg(JpegHalCtx->dev_ctx, p_regs,
sizeof(JpegdIocRegInfo) / sizeof(RK_U32));
if (ret != 0) {
mpp_err_f("mpp_device_send_reg Failed!!!\n");
@@ -999,7 +1002,7 @@ MPP_RET hal_jpegd_vdpu1_wait(void *hal, HalTaskInfo *task)
MppFrame tmp = NULL;
RK_U32 reg[164]; /* kernel will return 164 registers */
ret = mpp_device_wait_reg(JpegHalCtx->vpu_socket, reg,
ret = mpp_device_wait_reg(JpegHalCtx->dev_ctx, reg,
sizeof(reg) / sizeof(RK_U32));
reg_out = (JpegRegSet *)reg;
if (reg_out->reg1_interrupt.sw_dec_bus_int) {

59
mpp/hal/vpu/jpegd/hal_jpegd_vdpu2.c
View File

@@ -753,17 +753,18 @@ MPP_RET hal_jpegd_vdpu2_init(void *hal, MppHalCfg *cfg)
//get vpu socket
#ifdef RKPLATFORM
if (JpegHalCtx->vpu_socket <= 0) {
JpegHalCtx->vpu_socket = mpp_device_init(&JpegHalCtx->dev_ctx, MPP_CTX_DEC,
MPP_VIDEO_CodingMJPEG);
if (JpegHalCtx->vpu_socket <= 0) {
mpp_err_f("get vpu_socket(%d) <= 0, failed. \n",
JpegHalCtx->vpu_socket);
return MPP_ERR_UNKNOW;
} else {
jpegd_dbg_hal("get vpu_socket(%d), success. \n",
JpegHalCtx->vpu_socket);
}
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingMJPEG, /* coding */
.platform = 0, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&JpegHalCtx->dev_ctx, &dev_cfg);
if (ret) {
mpp_err("mpp_device_init failed. ret: %d\n", ret);
return ret;
} else {
jpegd_dbg_hal("mpp_device_init success. \n");
}
#endif
@@ -837,8 +838,11 @@ MPP_RET hal_jpegd_vdpu2_deinit(void *hal)
JpegdHalCtx *JpegHalCtx = (JpegdHalCtx *)hal;
#ifdef RKPLATFORM
if (JpegHalCtx->vpu_socket >= 0) {
mpp_device_deinit(JpegHalCtx->vpu_socket);
if (JpegHalCtx->dev_ctx) {
ret = mpp_device_deinit(JpegHalCtx->dev_ctx);
if (MPP_OK != ret) {
mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
}
}
#endif
@@ -901,19 +905,20 @@ MPP_RET hal_jpegd_vdpu2_gen_regs(void *hal, HalTaskInfo *syn)
jpegd_setup_output_fmt(JpegHalCtx, syntax);
#ifdef RKPLATFORM
if (JpegHalCtx->set_output_fmt_flag && (JpegHalCtx->vpu_socket > 0)) {
mpp_device_deinit(JpegHalCtx->vpu_socket);
JpegHalCtx->vpu_socket = 0;
mpp_device_control(&JpegHalCtx->dev_ctx, MPP_DEV_ENABLE_POSTPROCCESS, NULL);
JpegHalCtx->vpu_socket = mpp_device_init(&JpegHalCtx->dev_ctx, MPP_CTX_DEC,
MPP_VIDEO_CodingMJPEG);
if (JpegHalCtx->vpu_socket <= 0) {
mpp_err_f("get vpu_socket(%d) <= 0, failed. \n",
JpegHalCtx->vpu_socket);
return MPP_ERR_UNKNOW;
if (JpegHalCtx->set_output_fmt_flag && (NULL != JpegHalCtx->dev_ctx)) {
mpp_device_deinit(JpegHalCtx->dev_ctx);
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingMJPEG, /* coding */
.platform = 0, /* platform */
.pp_enable = 1, /* pp_enable */
};
ret = mpp_device_init(&JpegHalCtx->dev_ctx, &dev_cfg);
if (ret != MPP_OK) {
mpp_err("mpp_device_init failed. ret: %d\n", ret);
return ret;
} else {
jpegd_dbg_hal("get vpu_socket(%d), success. \n",
JpegHalCtx->vpu_socket);
jpegd_dbg_hal("mpp_device_init success. \n");
}
}
@@ -951,7 +956,7 @@ MPP_RET hal_jpegd_vdpu2_start(void *hal, HalTaskInfo *task)
#ifdef RKPLATFORM
RK_U32 *p_regs = (RK_U32 *)JpegHalCtx->regs;
ret = mpp_device_send_reg(JpegHalCtx->vpu_socket, p_regs,
ret = mpp_device_send_reg(JpegHalCtx->dev_ctx, p_regs,
sizeof(JpegdIocRegInfo) / sizeof(RK_U32));
if (ret != 0) {
mpp_err_f("mpp_device_send_reg Failed!!!\n");
@@ -978,7 +983,7 @@ MPP_RET hal_jpegd_vdpu2_wait(void *hal, HalTaskInfo *task)
MppFrame tmp = NULL;
RK_U32 reg[184];
ret = mpp_device_wait_reg(JpegHalCtx->vpu_socket, reg,
ret = mpp_device_wait_reg(JpegHalCtx->dev_ctx, reg,
sizeof(reg) / sizeof(RK_U32));
reg_out = (JpegRegSet *)reg;

2
mpp/hal/vpu/jpege/hal_jpege_base.h
View File

@@ -34,8 +34,6 @@ typedef struct JpegeIocRegInfo_t {
} JpegeIocRegInfo;
typedef struct hal_jpege_ctx_s {
RK_S32 vpu_fd;
IOInterruptCB int_cb;
MppDevCtx dev_ctx;
JpegeBits bits;

34
mpp/hal/vpu/jpege/hal_jpege_vepu1.c
View File

@@ -51,6 +51,7 @@ static const RK_U32 qp_reorder_table[64] = {
MPP_RET hal_jpege_vepu1_init(void *hal, MppHalCfg *cfg)
{
MPP_RET ret = MPP_OK;
HalJpegeCtx *ctx = (HalJpegeCtx *)hal;
mpp_env_get_u32("hal_jpege_debug", &hal_jpege_debug, 0);
@@ -59,10 +60,16 @@ MPP_RET hal_jpege_vepu1_init(void *hal, MppHalCfg *cfg)
ctx->int_cb = cfg->hal_int_cb;
#ifdef RKPLATFORM
ctx->vpu_fd = mpp_device_init(&ctx->dev_ctx, MPP_CTX_ENC, MPP_VIDEO_CodingMJPEG);
if (ctx->vpu_fd < 0) {
mpp_err_f("failed to open vpu client\n");
return MPP_NOK;
MppDevCfg dev_cfg = {
.type = MPP_CTX_ENC, /* type */
.coding = MPP_VIDEO_CodingMJPEG, /* coding */
.platform = 0, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
if (ret) {
mpp_err("mpp_device_init failed. ret: %d\n", ret);
return ret;
}
#endif
jpege_bits_init(&ctx->bits);
@@ -84,6 +91,7 @@ MPP_RET hal_jpege_vepu1_init(void *hal, MppHalCfg *cfg)
MPP_RET hal_jpege_vepu1_deinit(void *hal)
{
MPP_RET ret = MPP_OK;
HalJpegeCtx *ctx = (HalJpegeCtx *)hal;
hal_jpege_dbg_func("enter hal %p\n", hal);
@@ -94,15 +102,17 @@ MPP_RET hal_jpege_vepu1_deinit(void *hal)
}
#ifdef RKPLATFORM
if (ctx->vpu_fd >= 0) {
mpp_device_deinit(ctx->vpu_fd);
ctx->vpu_fd = -1;
if (ctx->dev_ctx) {
ret = mpp_device_deinit(ctx->dev_ctx);
if (ret) {
mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
}
}
#endif
mpp_free(ctx->ioctl_info.regs);
hal_jpege_dbg_func("leave hal %p\n", hal);
return MPP_OK;
return ret;
}
static MPP_RET hal_jpege_vepu1_set_extra_info(JpegeIocExtInfo *info, JpegeSyntax *syntax)
@@ -434,8 +444,8 @@ MPP_RET hal_jpege_vepu1_start(void *hal, HalTaskInfo *task)
memcpy(cache, ctx->ioctl_info.regs, reg_size);
memcpy(cache + reg_num, &(ctx->ioctl_info.extra_info), extra_size);
if (ctx->vpu_fd >= 0) {
ret = mpp_device_send_reg(ctx->vpu_fd, cache, reg_num + extra_num);
if (ctx->dev_ctx) {
ret = mpp_device_send_reg(ctx->dev_ctx, cache, reg_num + extra_num);
}
mpp_free(cache);
@@ -460,8 +470,8 @@ MPP_RET hal_jpege_vepu1_wait(void *hal, HalTaskInfo *task)
hal_jpege_dbg_func("enter hal %p\n", hal);
#ifdef RKPLATFORM
if (ctx->vpu_fd >= 0) {
ret = mpp_device_wait_reg(ctx->vpu_fd, regs, sizeof(jpege_vepu1_reg_set) / sizeof(RK_U32));
if (ctx->dev_ctx) {
ret = mpp_device_wait_reg(ctx->dev_ctx, regs, sizeof(jpege_vepu1_reg_set) / sizeof(RK_U32));
}
#endif
val = regs[1];

27
mpp/hal/vpu/jpege/hal_jpege_vepu2.c
View File

@@ -50,6 +50,7 @@ static const RK_U32 qp_reorder_table[64] = {
MPP_RET hal_jpege_vepu2_init(void *hal, MppHalCfg *cfg)
{
MPP_RET ret = MPP_OK;
HalJpegeCtx *ctx = (HalJpegeCtx *)hal;
mpp_env_get_u32("hal_jpege_debug", &hal_jpege_debug, 0);
@@ -58,10 +59,16 @@ MPP_RET hal_jpege_vepu2_init(void *hal, MppHalCfg *cfg)
ctx->int_cb = cfg->hal_int_cb;
#ifdef RKPLATFORM
ctx->vpu_fd = mpp_device_init(&ctx->dev_ctx, MPP_CTX_ENC, MPP_VIDEO_CodingMJPEG);
if (ctx->vpu_fd < 0) {
MppDevCfg dev_cfg = {
.type = MPP_CTX_ENC, /* type */
.coding = MPP_VIDEO_CodingMJPEG, /* coding */
.platform = 0, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
if (ret != MPP_OK) {
mpp_err_f("failed to open vpu client\n");
return MPP_NOK;
return ret;
}
#endif
jpege_bits_init(&ctx->bits);
@@ -93,9 +100,9 @@ MPP_RET hal_jpege_vepu2_deinit(void *hal)
}
#ifdef RKPLATFORM
if (ctx->vpu_fd >= 0) {
mpp_device_deinit(ctx->vpu_fd);
ctx->vpu_fd = -1;
if (ctx->dev_ctx) {
mpp_device_deinit(ctx->dev_ctx);
ctx->dev_ctx = NULL;
}
#endif
mpp_free(ctx->ioctl_info.regs);
@@ -419,8 +426,8 @@ MPP_RET hal_jpege_vepu2_start(void *hal, HalTaskInfo *task)
memcpy(cache, ctx->ioctl_info.regs, reg_size);
memcpy(cache + reg_num, &(ctx->ioctl_info.extra_info), extra_size);
if (ctx->vpu_fd >= 0) {
ret = mpp_device_send_reg(ctx->vpu_fd, cache, reg_num + extra_num);
if (ctx->dev_ctx) {
ret = mpp_device_send_reg(ctx->dev_ctx, cache, reg_num + extra_num);
}
mpp_free(cache);
@@ -446,8 +453,8 @@ MPP_RET hal_jpege_vepu2_wait(void *hal, HalTaskInfo *task)
hal_jpege_dbg_func("enter hal %p\n", hal);
#ifdef RKPLATFORM
if (ctx->vpu_fd >= 0) {
ret = mpp_device_wait_reg(ctx->vpu_fd, regs, sizeof(jpege_vepu2_reg_set) / sizeof(RK_U32));
if (ctx->dev_ctx) {
ret = mpp_device_wait_reg(ctx->dev_ctx, regs, sizeof(jpege_vepu2_reg_set) / sizeof(RK_U32));
}
#endif
val = regs[109];

28
mpp/hal/vpu/m2vd/hal_m2vd_reg.c
View File

@@ -66,12 +66,16 @@ MPP_RET hal_m2vd_init(void *hal, MppHalCfg *cfg)
mpp_env_get_u32("m2vh_debug", &m2vh_debug, 0);
//get vpu socket
#ifdef RKPLATFORM
if (p->vpu_socket <= 0) {
p->vpu_socket = mpp_device_init(&p->dev_ctx, MPP_CTX_DEC, MPP_VIDEO_CodingMPEG2);
if (p->vpu_socket <= 0) {
mpp_err("get vpu_socket(%d) <=0, failed. \n", p->vpu_socket);
return MPP_ERR_UNKNOW;
}
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingMPEG2, /* coding */
.platform = 0, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&p->dev_ctx, &dev_cfg);
if (ret) {
mpp_err("mpp_device_init failed. ret: %d\n", ret);
return ret;
}
#endif
if (p->group == NULL) {
@@ -148,8 +152,12 @@ MPP_RET hal_m2vd_deinit(void *hal)
M2VDHalContext *p = (M2VDHalContext *)hal;
#ifdef RKPLATFORM
if (p->vpu_socket >= 0)
mpp_device_deinit(p->vpu_socket);
if (p->dev_ctx) {
ret = mpp_device_deinit(p->dev_ctx);
if (MPP_OK != ret) {
mpp_err("mpp_device_deinit failed ret: %d\n", ret);
}
}
#endif
if (p->qp_table) {
ret = mpp_buffer_put(p->qp_table);
@@ -318,7 +326,7 @@ MPP_RET hal_m2vd_start(void *hal, HalTaskInfo *task)
M2VDHalContext *ctx = (M2VDHalContext *)hal;
RK_U32 *p_regs = (RK_U32 *)&ctx->regs;
FUN_T("FUN_I");
ret = mpp_device_send_reg(ctx->vpu_socket, p_regs, M2VD_REG_NUM);
ret = mpp_device_send_reg(ctx->dev_ctx, p_regs, M2VD_REG_NUM);
if (ret != 0) {
mpp_err("mpp_device_send_reg Failed!!!\n");
return MPP_ERR_VPUHW;
@@ -339,7 +347,7 @@ MPP_RET hal_m2vd_wait(void *hal, HalTaskInfo *task)
FUN_T("FUN_I");
memset(&reg_out, 0, sizeof(M2VDRegSet));
ret = mpp_device_wait_reg(ctx->vpu_socket, (RK_U32 *)&reg_out, M2VD_REG_NUM);
ret = mpp_device_wait_reg(ctx->dev_ctx, (RK_U32 *)&reg_out, M2VD_REG_NUM);
if (ctx->fp_reg_out) {
int k = 0;
RK_U32 *p_reg = (RK_U32*)&reg_out;

1
mpp/hal/vpu/m2vd/hal_m2vd_reg.h
View File

@@ -304,7 +304,6 @@ typedef struct M2VDRegSet_t {
typedef struct M2VDHalContext_t {
MppBufSlots packet_slots;
MppBufSlots frame_slots;
RK_S32 vpu_socket;
M2VDRegSet regs;
MppBufferGroup group;
MppBuffer qp_table;

1
mpp/hal/vpu/mpg4d/hal_m4vd_com.h
View File

@@ -34,7 +34,6 @@ typedef struct mpeg4d_reg_context {
IOInterruptCB int_cb;
MppDevCtx dev_ctx;
// save fd for curr/ref0/ref1 for reg_gen
RK_S32 vpu_fd;
RK_S32 fd_curr;
RK_S32 fd_ref0;
RK_S32 fd_ref1;

27
mpp/hal/vpu/mpg4d/hal_m4vd_vdpu1.c
View File

@@ -231,7 +231,6 @@ MPP_RET vdpu1_mpg4d_init(void *hal, MppHalCfg *cfg)
MppBuffer mv_buf = NULL;
MppBuffer qp_table = NULL;
hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal;
RK_S32 vpu_fd = -1;
mpp_assert(hal);
@@ -261,10 +260,15 @@ MPP_RET vdpu1_mpg4d_init(void *hal, MppHalCfg *cfg)
}
#ifdef RKPLATFORM
vpu_fd = mpp_device_init(&ctx->dev_ctx, MPP_CTX_DEC, MPP_VIDEO_CodingMPEG4);
if (vpu_fd < 0) {
mpp_err_f("failed to open vpu client\n");
ret = MPP_ERR_UNKNOW;
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingMPEG4, /* coding */
.platform = 0, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
if (ret) {
mpp_err_f("mpp_device_init failed. ret: %d\n", ret);
goto ERR_RET;
}
#endif
@@ -292,7 +296,6 @@ MPP_RET vdpu1_mpg4d_init(void *hal, MppHalCfg *cfg)
ctx->pkt_slots = cfg->packet_slots;
ctx->int_cb = cfg->hal_int_cb;
ctx->group = group;
ctx->vpu_fd = vpu_fd;
ctx->mv_buf = mv_buf;
ctx->qp_table = qp_table;
ctx->regs = regs;
@@ -352,9 +355,11 @@ MPP_RET vdpu1_mpg4d_deinit(void *hal)
}
#ifdef RKPLATFORM
if (ctx->vpu_fd >= 0) {
mpp_device_deinit(ctx->vpu_fd);
ctx->vpu_fd = -1;
if (ctx->dev_ctx) {
ret = mpp_device_deinit(ctx->dev_ctx);
if (MPP_OK != ret) {
mpp_err("mpp_device_deinit failed ret: %d\n", ret);
}
}
#endif
@@ -418,7 +423,7 @@ MPP_RET vdpu1_mpg4d_start(void *hal, HalTaskInfo *task)
}
}
ret = mpp_device_send_reg(ctx->vpu_fd, regs, reg_count);
ret = mpp_device_send_reg(ctx->dev_ctx, regs, reg_count);
#endif
(void)ret;
(void)hal;
@@ -435,7 +440,7 @@ MPP_RET vdpu1_mpg4d_wait(void *hal, HalTaskInfo *task)
RK_U32* regs = (RK_U32 *)&reg_out;
RK_U32 reg_count = (sizeof(reg_out) / sizeof(RK_U32));
ret = mpp_device_wait_reg(ctx->vpu_fd, regs, (sizeof(reg_out) / sizeof(RK_U32)));
ret = mpp_device_wait_reg(ctx->dev_ctx, regs, (sizeof(reg_out) / sizeof(RK_U32)));
if (mpg4d_hal_debug & MPG4D_HAL_DBG_REG_GET) {
RK_U32 i = 0;

27
mpp/hal/vpu/mpg4d/hal_m4vd_vdpu2.c
View File

@@ -229,7 +229,6 @@ MPP_RET vdpu2_mpg4d_init(void *hal, MppHalCfg *cfg)
MppBuffer mv_buf = NULL;
MppBuffer qp_table = NULL;
hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal;
RK_S32 vpu_fd = -1;
mpp_assert(hal);
@@ -259,10 +258,15 @@ MPP_RET vdpu2_mpg4d_init(void *hal, MppHalCfg *cfg)
}
#ifdef RKPLATFORM
vpu_fd = mpp_device_init(&ctx->dev_ctx, MPP_CTX_DEC, MPP_VIDEO_CodingMPEG4);
if (vpu_fd < 0) {
mpp_err_f("failed to open vpu client\n");
ret = MPP_ERR_UNKNOW;
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingMPEG4, /* coding */
.platform = 0, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
if (ret) {
mpp_err_f("mpp_device_init failed. ret: %d\n", ret);
goto ERR_RET;
}
#endif
@@ -290,7 +294,6 @@ MPP_RET vdpu2_mpg4d_init(void *hal, MppHalCfg *cfg)
ctx->pkt_slots = cfg->packet_slots;
ctx->int_cb = cfg->hal_int_cb;
ctx->group = group;
ctx->vpu_fd = vpu_fd;
ctx->mv_buf = mv_buf;
ctx->qp_table = qp_table;
ctx->regs = regs;
@@ -350,9 +353,11 @@ MPP_RET vdpu2_mpg4d_deinit(void *hal)
}
#ifdef RKPLATFORM
if (ctx->vpu_fd >= 0) {
mpp_device_deinit(ctx->vpu_fd);
ctx->vpu_fd = -1;
if (ctx->dev_ctx) {
ret = mpp_device_deinit(ctx->dev_ctx);
if (MPP_OK != ret) {
mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
}
}
#endif
@@ -416,7 +421,7 @@ MPP_RET vdpu2_mpg4d_start(void *hal, HalTaskInfo *task)
}
}
ret = mpp_device_send_reg(ctx->vpu_fd, regs, reg_count);
ret = mpp_device_send_reg(ctx->dev_ctx, regs, reg_count);
#endif
(void)ret;
(void)hal;
@@ -433,7 +438,7 @@ MPP_RET vdpu2_mpg4d_wait(void *hal, HalTaskInfo *task)
RK_U32* regs = (RK_U32 *)&reg_out;
RK_U32 reg_count = (sizeof(reg_out) / sizeof(RK_U32));
ret = mpp_device_wait_reg(ctx->vpu_fd, regs, (sizeof(reg_out) / sizeof(RK_U32)));
ret = mpp_device_wait_reg(ctx->dev_ctx, regs, (sizeof(reg_out) / sizeof(RK_U32)));
if (mpg4d_hal_debug & MPG4D_HAL_DBG_REG_GET) {
RK_U32 i = 0;

1
mpp/hal/vpu/vp8d/hal_vp8d_base.h
View File

@@ -43,7 +43,6 @@
typedef struct VP8DHalContext {
MppBufSlots packet_slots;
MppBufSlots frame_slots;
RK_S32 vpu_socket;
MppDevCtx dev_ctx;
void *regs;
RK_U8 reg_size;

30
mpp/hal/vpu/vp8d/hal_vp8d_vdpu1.c
View File

@@ -53,14 +53,17 @@ MPP_RET hal_vp8d_vdpu1_init(void *hal, MppHalCfg *cfg)
mpp_env_get_u32("vp8h_debug", &vp8h_debug, 0);
//get vpu socket
#ifdef RKPLATFORM
if (ctx->vpu_socket <= 0) {
ctx->vpu_socket = mpp_device_init(&ctx->dev_ctx, MPP_CTX_DEC, MPP_VIDEO_CodingVP8);
if (ctx->vpu_socket <= 0) {
mpp_err("get vpu_socket(%d) <=0, failed. \n", ctx->vpu_socket);
FUN_T("FUN_OUT");
return MPP_ERR_UNKNOW;
}
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingVP8, /* coding */
.platform = 0, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
if (ret) {
mpp_err("mpp_device_init failed, ret: %d\n", ret);
FUN_T("FUN_OUT");
return ret;
}
#endif
if (NULL == ctx->regs) {
@@ -112,8 +115,11 @@ MPP_RET hal_vp8d_vdpu1_deinit(void *hal)
FUN_T("FUN_IN");
VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
#ifdef RKPLATFORM
if (ctx->vpu_socket >= 0) {
mpp_device_deinit(ctx->vpu_socket);
if (ctx->dev_ctx) {
ret = mpp_device_deinit(ctx->dev_ctx);
if (MPP_OK != ret) {
mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
}
}
#endif
if (ctx->probe_table) {
@@ -614,7 +620,7 @@ MPP_RET hal_vp8d_vdpu1_start(void *hal, HalTaskInfo *task)
vp8h_dbg(VP8H_DBG_REG, "vp8d: regs[%02d]=%08X\n", i, *((RK_U32*)p));
p += 4;
}
ret = mpp_device_send_reg(ctx->vpu_socket, (RK_U32 *)regs, VP8D_REG_NUM);
ret = mpp_device_send_reg(ctx->dev_ctx, (RK_U32 *)regs, VP8D_REG_NUM);
if (ret != 0) {
mpp_err("mpp_device_send_reg Failed!!!\n");
return MPP_ERR_VPUHW;
@@ -637,7 +643,7 @@ MPP_RET hal_vp8d_vdpu1_wait(void *hal, HalTaskInfo *task)
FUN_T("FUN_IN");
memset(&reg_out, 0, sizeof(VP8DRegSet_t));
ret = mpp_device_wait_reg(ctx->vpu_socket, (RK_U32 *)&reg_out, VP8D_REG_NUM);
ret = mpp_device_wait_reg(ctx->dev_ctx, (RK_U32 *)&reg_out, VP8D_REG_NUM);
FUN_T("FUN_OUT");
#endif
(void)hal;

31
mpp/hal/vpu/vp8d/hal_vp8d_vdpu2.c
View File

@@ -53,15 +53,19 @@ MPP_RET hal_vp8d_vdpu2_init(void *hal, MppHalCfg *cfg)
mpp_env_get_u32("vp8h_debug", &vp8h_debug, 0);
//get vpu socket
#ifdef RKPLATFORM
if (ctx->vpu_socket <= 0) {
ctx->vpu_socket = mpp_device_init(&ctx->dev_ctx, MPP_CTX_DEC, MPP_VIDEO_CodingVP8);
if (ctx->vpu_socket <= 0) {
mpp_err("get vpu_socket(%d) <=0, failed. \n", ctx->vpu_socket);
FUN_T("FUN_OUT");
return MPP_ERR_UNKNOW;
}
MppDevCfg dev_cfg = {
.type = MPP_CTX_DEC, /* type */
.coding = MPP_VIDEO_CodingVP8, /* coding */
.platform = 0, /* platform */
.pp_enable = 0, /* pp_enable */
};
ret = mpp_device_init(&ctx->dev_ctx, &dev_cfg);
if (ret) {
mpp_err("mpp_device_init failed. ret: %d\n", ret);
FUN_T("FUN_OUT");
return ret;
}
#endif
if (NULL == ctx->regs) {
ctx->regs = mpp_calloc_size(void, sizeof(VP8DRegSet_t));
@@ -113,8 +117,11 @@ MPP_RET hal_vp8d_vdpu2_deinit(void *hal)
VP8DHalContext_t *ctx = (VP8DHalContext_t *)hal;
#ifdef RKPLATFORM
if (ctx->vpu_socket >= 0) {
mpp_device_deinit(ctx->vpu_socket);
if (ctx->dev_ctx) {
ret = mpp_device_deinit(ctx->dev_ctx);
if (MPP_OK != ret) {
mpp_err("mpp_device_deinit failed. ret: %d\n", ret);
}
}
#endif
if (ctx->probe_table) {
@@ -594,7 +601,7 @@ MPP_RET hal_vp8d_vdpu2_start(void *hal, HalTaskInfo *task)
vp8h_dbg(VP8H_DBG_REG, "vp8d: regs[%02d]=%08X\n", i, *((RK_U32*)p));
p += 4;
}
ret = mpp_device_send_reg(ctx->vpu_socket, (RK_U32 *)regs, VP8D_REG_NUM);
ret = mpp_device_send_reg(ctx->dev_ctx, (RK_U32 *)regs, VP8D_REG_NUM);
if (ret != 0) {
mpp_err("mpp_device_send_reg Failed!!!\n");
return MPP_ERR_VPUHW;
@@ -616,7 +623,7 @@ MPP_RET hal_vp8d_vdpu2_wait(void *hal, HalTaskInfo *task)
FUN_T("FUN_IN");
memset(&reg_out, 0, sizeof(VP8DRegSet_t));
ret = mpp_device_wait_reg(ctx->vpu_socket, (RK_U32 *)&reg_out, VP8D_REG_NUM);
ret = mpp_device_wait_reg(ctx->dev_ctx, (RK_U32 *)&reg_out, VP8D_REG_NUM);
FUN_T("FUN_OUT");
#endif
(void)hal;

30
mpp/hal/worker/inc/mpp_device.h
View File

@@ -40,33 +40,35 @@ typedef enum MppDevCmd_e {
MPP_DEV_PROP_BUTT,
} MppDevCmd;
typedef struct MppDevCtx_t {
MppCtxType coding;
MppCodingType type;
RK_S32 client_type;
RK_U32 platform; // platfrom for vcodec to init
RK_U32 mmu_status; // 0 disable, 1 enable
RK_U32 pp_enable; // postprocess, 0 disable, 1 enable
typedef struct MppDevCfg_t {
// input
MppCtxType type;
MppCodingType coding;
RK_U32 platform;
RK_U32 pp_enable;
} MppDevCfg;
typedef void* MppDevCtx;
} MppDevCtx;
/*
* hardware device open function
* coding and type for device name detection
*/
RK_S32 mpp_device_init(MppDevCtx *ctx, MppCtxType coding, MppCodingType type);
MPP_RET mpp_device_deinit(RK_S32 dev);
MPP_RET mpp_device_init(MppDevCtx *ctx, MppDevCfg *cfg);
MPP_RET mpp_device_deinit(MppDevCtx ctx);
/*
* control function for set or get device property
*/
RK_S32 mpp_device_control(MppDevCtx *ctx, MppDevCmd cmd, void *param);
RK_S32 mpp_device_control(MppDevCtx ctx, MppDevCmd cmd, void *param);
/*
* register access interface
*/
MPP_RET mpp_device_send_reg(RK_S32 dev, RK_U32 *regs, RK_U32 nregs);
MPP_RET mpp_device_wait_reg(RK_S32 dev, RK_U32 *regs, RK_U32 nregs);
MPP_RET mpp_device_send_reg_with_id(RK_S32 dev, RK_S32 id, void *param, RK_S32 size);
MPP_RET mpp_device_send_reg(MppDevCtx ctx, RK_U32 *regs, RK_U32 nregs);
MPP_RET mpp_device_wait_reg(MppDevCtx ctx, RK_U32 *regs, RK_U32 nregs);
MPP_RET mpp_device_send_reg_with_id(MppDevCtx ctx, RK_S32 id, void *param, RK_S32 size);
/*
* New interface

149
mpp/hal/worker/mpp_device/mpp_device.c
View File

@@ -27,6 +27,7 @@
#include "mpp_device.h"
#include "mpp_platform.h"
#include "mpp_mem.h"
#include "vpu.h"
@@ -45,6 +46,17 @@ typedef struct MppReq_t {
RK_U32 size;
} MppReq;
typedef struct MppDevCtxImpl_t {
MppCtxType type;
MppCodingType coding;
RK_S32 client_type;
RK_U32 platform; // platfrom for vcodec to init
RK_U32 mmu_status; // 0 disable, 1 enable
RK_U32 pp_enable; // postprocess, 0 disable, 1 enable
RK_S32 vpu_fd;
} MppDevCtxImpl;
static RK_U32 mpp_device_debug = 0;
static RK_S32 mpp_device_set_client_type(int dev, RK_S32 client_type)
@@ -80,15 +92,25 @@ static RK_S32 mpp_device_set_client_type(int dev, RK_S32 client_type)
return ret;
}
static RK_S32 mpp_device_get_client_type(MppDevCtx *ctx, MppCtxType coding, MppCodingType type)
static RK_S32 mpp_device_get_client_type(MppDevCtx ctx, MppCtxType type, MppCodingType coding)
{
RK_S32 client_type = -1;
MppDevCtxImpl *p;
if (coding == MPP_CTX_ENC)
if (NULL == ctx ||
(type >= MPP_CTX_BUTT || type < 0) ||
(coding >= MPP_VIDEO_CodingMax || coding <= MPP_VIDEO_CodingUnused)) {
mpp_err_f("found NULL input ctx %p coding %d type %d\n", ctx, coding, type);
return MPP_ERR_NULL_PTR;
}
p = (MppDevCtxImpl *)ctx;
if (type == MPP_CTX_ENC)
client_type = VPU_ENC;
else { /* MPP_CTX_DEC */
client_type = VPU_DEC;
if (ctx->pp_enable)
if (p->pp_enable)
client_type = VPU_DEC_PP;
}
@@ -97,51 +119,91 @@ static RK_S32 mpp_device_get_client_type(MppDevCtx *ctx, MppCtxType coding, MppC
return client_type;
}
RK_S32 mpp_device_init(MppDevCtx *ctx, MppCtxType coding, MppCodingType type)
MPP_RET mpp_device_init(MppDevCtx *ctx, MppDevCfg *cfg)
{
RK_S32 dev = -1;
const char *name = NULL;
MppDevCtxImpl *p;
if (NULL == ctx || NULL == cfg) {
mpp_err_f("found NULL input ctx %p cfg %p\n", ctx, cfg);
return MPP_ERR_NULL_PTR;
}
*ctx = NULL;
mpp_env_get_u32("mpp_device_debug", &mpp_device_debug, 0);
ctx->coding = coding;
ctx->type = type;
if (ctx->platform)
name = mpp_get_platform_dev_name(coding, type, ctx->platform);
p = mpp_calloc(MppDevCtxImpl, 1);
if (NULL == p) {
mpp_err_f("malloc failed\n");
return MPP_ERR_MALLOC;
}
p->coding = cfg->coding;
p->type = cfg->type;
p->platform = cfg->platform;
p->pp_enable = cfg->pp_enable;
if (p->platform)
name = mpp_get_platform_dev_name(p->type, p->coding, p->platform);
else
name = mpp_get_vcodec_dev_name(coding, type);
name = mpp_get_vcodec_dev_name(p->type, p->coding);
if (name) {
dev = open(name, O_RDWR);
if (dev > 0) {
RK_S32 client_type = mpp_device_get_client_type(ctx, coding, type);
RK_S32 client_type = mpp_device_get_client_type(p, p->type, p->coding);
RK_S32 ret = mpp_device_set_client_type(dev, client_type);
if (ret) {
close(dev);
dev = -2;
}
ctx->client_type = client_type;
p->client_type = client_type;
} else
mpp_err_f("failed to open device %s, errno %d, error msg: %s\n",
name, errno, strerror(errno));
} else
mpp_err_f("failed to find device for coding %d type %d\n", coding, type);
mpp_err_f("failed to find device for coding %d type %d\n", p->coding, p->type);
return dev;
}
MPP_RET mpp_device_deinit(RK_S32 dev)
{
if (dev > 0)
close(dev);
*ctx = p;
p->vpu_fd = dev;
return MPP_OK;
}
MPP_RET mpp_device_send_reg(RK_S32 dev, RK_U32 *regs, RK_U32 nregs)
MPP_RET mpp_device_deinit(MppDevCtx ctx)
{
MppDevCtxImpl *p;
if (NULL == ctx) {
mpp_err_f("found NULL input ctx %p\n", ctx);
return MPP_ERR_NULL_PTR;
}
p = (MppDevCtxImpl *)ctx;
if (p->vpu_fd > 0) {
close(p->vpu_fd);
} else {
mpp_err_f("invalid negtive file handle,\n");
}
mpp_free(p);
return MPP_OK;
}
MPP_RET mpp_device_send_reg(MppDevCtx ctx, RK_U32 *regs, RK_U32 nregs)
{
MPP_RET ret;
MppReq req;
MppDevCtxImpl *p;
if (NULL == ctx || NULL == regs) {
mpp_err_f("found NULL input ctx %p regs %p\n", ctx, regs);
return MPP_ERR_NULL_PTR;
}
p = (MppDevCtxImpl *)ctx;
if (mpp_device_debug) {
RK_U32 i;
@@ -154,7 +216,7 @@ MPP_RET mpp_device_send_reg(RK_S32 dev, RK_U32 *regs, RK_U32 nregs)
nregs *= sizeof(RK_U32);
req.req = regs;
req.size = nregs;
ret = (RK_S32)ioctl(dev, VPU_IOC_SET_REG, &req);
ret = (RK_S32)ioctl(p->vpu_fd, VPU_IOC_SET_REG, &req);
if (ret) {
mpp_err_f("ioctl VPU_IOC_SET_REG failed ret %d errno %d %s\n",
ret, errno, strerror(errno));
@@ -164,16 +226,23 @@ MPP_RET mpp_device_send_reg(RK_S32 dev, RK_U32 *regs, RK_U32 nregs)
return ret;
}
MPP_RET mpp_device_wait_reg(RK_S32 dev, RK_U32 *regs, RK_U32 nregs)
MPP_RET mpp_device_wait_reg(MppDevCtx ctx, RK_U32 *regs, RK_U32 nregs)
{
MPP_RET ret;
MppReq req;
MppDevCtxImpl *p;
if (NULL == ctx || NULL == regs) {
mpp_err_f("found NULL input ctx %p regs %p\n", ctx, regs);
return MPP_ERR_NULL_PTR;
}
p = (MppDevCtxImpl *)ctx;
nregs *= sizeof(RK_U32);
req.req = regs;
req.size = nregs;
ret = (RK_S32)ioctl(dev, VPU_IOC_GET_REG, &req);
ret = (RK_S32)ioctl(p->vpu_fd, VPU_IOC_GET_REG, &req);
if (ret) {
mpp_err_f("ioctl VPU_IOC_GET_REG failed ret %d errno %d %s\n",
ret, errno, strerror(errno));
@@ -192,17 +261,20 @@ MPP_RET mpp_device_wait_reg(RK_S32 dev, RK_U32 *regs, RK_U32 nregs)
return ret;
}
MPP_RET mpp_device_send_reg_with_id(RK_S32 dev, RK_S32 id, void *param,
MPP_RET mpp_device_send_reg_with_id(MppDevCtx ctx, RK_S32 id, void *param,
RK_S32 size)
{
MPP_RET ret = MPP_NOK;
MppDevCtxImpl *p;
if (param == NULL) {
mpp_err_f("input param is NULL");
return ret;
if (NULL == ctx || NULL == param) {
mpp_err_f("found NULL input ctx %p param %p\n", ctx, param);
return MPP_ERR_NULL_PTR;
}
ret = (RK_S32)ioctl(dev, VPU_IOC_WRITE(id, size), param);
p = (MppDevCtxImpl *)ctx;
ret = (RK_S32)ioctl(p->vpu_fd, VPU_IOC_WRITE(id, size), param);
if (ret) {
mpp_err_f("ioctl VPU_IOC_WRITE failed ret %d errno %d %s\n",
ret, errno, strerror(errno));
@@ -212,18 +284,27 @@ MPP_RET mpp_device_send_reg_with_id(RK_S32 dev, RK_S32 id, void *param,
return ret;
}
RK_S32 mpp_device_control(MppDevCtx *ctx, MppDevCmd cmd, void* param)
RK_S32 mpp_device_control(MppDevCtx ctx, MppDevCmd cmd, void* param)
{
MppDevCtxImpl *p;
if (NULL == ctx || NULL == param) {
mpp_err_f("found NULL input ctx %p param %p\n", ctx, param);
return MPP_ERR_NULL_PTR;
}
p = (MppDevCtxImpl *)ctx;
switch (cmd) {
case MPP_DEV_GET_MMU_STATUS : {
ctx->mmu_status = 1;
*((RK_U32 *)param) = ctx->mmu_status;
p->mmu_status = 1;
*((RK_U32 *)param) = p->mmu_status;
} break;
case MPP_DEV_ENABLE_POSTPROCCESS : {
ctx->pp_enable = 1;
p->pp_enable = 1;
} break;
case MPP_DEV_SET_HARD_PLATFORM : {
ctx->platform = *((RK_U32 *)param);
p->platform = *((RK_U32 *)param);
} break;
default : {
} break;

4
osal/mpp_platform.cpp
View File

@@ -427,9 +427,9 @@ const char *mpp_get_vcodec_dev_name(MppCtxType type, MppCodingType coding)
} else if (type == MPP_CTX_DEC) {
if (coding == MPP_VIDEO_CodingAVC ||
coding == MPP_VIDEO_CodingHEVC ||
coding == MPP_VIDEO_CodingVP9)
coding == MPP_VIDEO_CodingVP9) {
dev = mpp_find_device(mpp_rkvdec_dev);
else
} else
dev = mpp_find_device(mpp_vpu_dev);
}
} break;

0
osal/mpp_queue.cpp Executable file → Normal file
View File