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https://github.com/nyanmisaka/mpp.git
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[vepu54c_common]: Add common part code
Change-Id: Iaf7a025ab4b90fb73e4e65c81eed29842c6ac055 Signed-off-by: sayon.chen <sayon.chen@rock-chips.com> Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
This commit is contained in:
sayon.chen
@@ -5,6 +5,7 @@ include_directories(.)
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add_library(hal_vepu541_common STATIC
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add_library(hal_vepu541_common STATIC
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vepu541_common.c
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vepu541_common.c
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vepu5xx_common.c
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vepu5xx_common.c
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vepu540c_common.c
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)
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)
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target_link_libraries(hal_vepu541_common mpp_base)
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target_link_libraries(hal_vepu541_common mpp_base)
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261
mpp/hal/rkenc/common/vepu540c_common.c
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261
mpp/hal/rkenc/common/vepu540c_common.c
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@@ -0,0 +1,261 @@
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/*
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* Copyright 2021 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define MODULE_TAG "vepu540c_common"
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#include <linux/string.h>
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#include "mpp_log.h"
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#include "mpp_debug.h"
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#include "mpp_mem.h"
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#include "mpp_common.h"
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#include "jpege_syntax.h"
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#include "vepu541_common.h"
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#include "vepu540c_common.h"
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#include "hal_enc_task.h"
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#include "mpp_frame_impl.h"
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#include "mpp_packet.h"
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MPP_RET vepu540c_set_roi(void *roi_reg_base, MppEncROICfg * roi,
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RK_S32 w, RK_S32 h)
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{
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MppEncROIRegion *region = roi->regions;
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Vepu540cRoiCfg *roi_cfg = (Vepu540cRoiCfg *)roi_reg_base;
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Vepu540cRoiRegion *reg_regions = &roi_cfg->regions[0];
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MPP_RET ret = MPP_NOK;
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RK_S32 i = 0;
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memset(reg_regions, 0, sizeof(Vepu540cRoiRegion) * 8);
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if (NULL == roi_cfg || NULL == roi) {
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mpp_err_f("invalid buf %p roi %p\n", roi_cfg, roi);
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goto DONE;
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}
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if (roi->number > VEPU540C_MAX_ROI_NUM) {
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mpp_err_f("invalid region number %d\n", roi->number);
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goto DONE;
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}
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/* check region config */
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ret = MPP_OK;
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for (i = 0; i < (RK_S32) roi->number; i++, region++) {
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if (region->x + region->w > w || region->y + region->h > h)
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ret = MPP_NOK;
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if (region->intra > 1
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|| region->qp_area_idx >= VEPU541_MAX_ROI_NUM
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|| region->area_map_en > 1 || region->abs_qp_en > 1)
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ret = MPP_NOK;
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if ((region->abs_qp_en && region->quality > 51) ||
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(!region->abs_qp_en
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&& (region->quality > 51 || region->quality < -51)))
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ret = MPP_NOK;
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if (ret) {
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mpp_err_f("region %d invalid param:\n", i);
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mpp_err_f("position [%d:%d:%d:%d] vs [%d:%d]\n",
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region->x, region->y, region->w, region->h, w,
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h);
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mpp_err_f("force intra %d qp area index %d\n",
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region->intra, region->qp_area_idx);
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mpp_err_f("abs qp mode %d value %d\n",
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region->abs_qp_en, region->quality);
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goto DONE;
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}
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reg_regions->roi_pos_lt.roi_lt_x = MPP_ALIGN(region->x, 16) >> 4;
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reg_regions->roi_pos_lt.roi_lt_y = MPP_ALIGN(region->y, 16) >> 4;
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reg_regions->roi_pos_rb.roi_rb_x = MPP_ALIGN(region->x + region->w, 16) >> 4;
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reg_regions->roi_pos_rb.roi_rb_y = MPP_ALIGN(region->y + region->h, 16) >> 4;
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reg_regions->roi_base.roi_qp_value = region->quality;
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reg_regions->roi_base.roi_qp_adj_mode = region->abs_qp_en;
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reg_regions->roi_base.roi_en = 1;
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reg_regions->roi_base.roi_pri = 0x1f;
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if (region->intra) {
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reg_regions->roi_mdc.roi_mdc_intra16 = 1;
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reg_regions->roi_mdc.roi0_mdc_intra32_hevc = 1;
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}
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reg_regions++;
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}
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DONE:
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return ret;
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}
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static MPP_RET vepu540c_jpeg_set_patch_info(MppDev dev, JpegeSyntax *syn,
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Vepu541Fmt input_fmt,
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HalEncTask *task)
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{
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RK_U32 hor_stride = syn->hor_stride;
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RK_U32 ver_stride = syn->ver_stride ? syn->ver_stride : syn->height;
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RK_U32 frame_size = hor_stride * ver_stride;
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RK_U32 u_offset = 0, v_offset = 0;
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MPP_RET ret = MPP_OK;
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if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(task->frame))) {
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u_offset = mpp_frame_get_fbc_offset(task->frame);
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v_offset = 0;
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mpp_log("fbc case u_offset = %d", u_offset);
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} else {
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switch (input_fmt) {
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case VEPU541_FMT_YUV420P: {
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u_offset = frame_size;
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v_offset = frame_size * 5 / 4;
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} break;
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case VEPU541_FMT_YUV420SP:
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case VEPU541_FMT_YUV422SP: {
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u_offset = frame_size;
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v_offset = frame_size;
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} break;
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case VEPU541_FMT_YUV422P: {
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u_offset = frame_size;
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v_offset = frame_size * 3 / 2;
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} break;
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case VEPU541_FMT_YUYV422:
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case VEPU541_FMT_UYVY422: {
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u_offset = 0;
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v_offset = 0;
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} break;
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case VEPU541_FMT_BGR565:
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case VEPU541_FMT_BGR888:
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case VEPU541_FMT_BGRA8888: {
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u_offset = 0;
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v_offset = 0;
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} break;
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default: {
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mpp_err("unknown color space: %d\n", input_fmt);
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u_offset = frame_size;
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v_offset = frame_size * 5 / 4;
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}
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}
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}
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/* input cb addr */
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if (u_offset)
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mpp_dev_set_reg_offset(dev, 265, u_offset);
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/* input cr addr */
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if (v_offset)
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mpp_dev_set_reg_offset(dev, 266, u_offset);
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return ret;
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}
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MPP_RET vepu540c_set_jpeg_reg(Vepu540cJpegCfg *cfg)
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{
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HalEncTask *task = ( HalEncTask *)cfg->enc_task;
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JpegeSyntax *syn = (JpegeSyntax *)task->syntax.data;
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Vepu540cJpegReg *regs = (Vepu540cJpegReg *)cfg->jpeg_reg_base;
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VepuFmtCfg *fmt = (VepuFmtCfg *)cfg->input_fmt;
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RK_U32 pic_width_align8, pic_height_align8;
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RK_S32 stridey = 0;
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RK_S32 stridec = 0;
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pic_width_align8 = (syn->width + 7) & (~7);
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pic_height_align8 = (syn->height + 7) & (~7);
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regs->reg0264_adr_src0 = mpp_buffer_get_fd(task->input);
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regs->reg0265_adr_src1 = regs->reg0264_adr_src0;
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regs->reg0266_adr_src2 = regs->reg0264_adr_src0;
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vepu540c_jpeg_set_patch_info(cfg->dev, syn, (Vepu541Fmt) fmt->format, task);
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regs->reg0256_adr_bsbt = mpp_buffer_get_fd(task->output);
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regs->reg0257_adr_bsbb = regs->reg0256_adr_bsbt;
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regs->reg0258_adr_bsbr = regs->reg0256_adr_bsbt;
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regs->reg0259_adr_bsbs = regs->reg0256_adr_bsbt;
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mpp_dev_set_reg_offset(cfg->dev, 259, mpp_packet_get_length(task->packet));
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mpp_dev_set_reg_offset(cfg->dev, 256, mpp_buffer_get_size(task->output));
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regs->reg0272_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1;
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regs->reg0273_src_fill.pic_wfill = (syn->width & 0x7)
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? (8 - (syn->width & 0x7)) : 0;
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regs->reg0272_enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1;
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regs->reg0273_src_fill.pic_hfill = (syn->height & 0x7)
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? (8 - (syn->height & 0x7)) : 0;
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regs->reg0274_src_fmt.src_cfmt = fmt->format;
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regs->reg0274_src_fmt.alpha_swap = fmt->alpha_swap;
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regs->reg0274_src_fmt.rbuv_swap = fmt->rbuv_swap;
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regs->reg0274_src_fmt.src_range_trns_en = 0;
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regs->reg0274_src_fmt.src_range_trns_sel = 0;
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regs->reg0274_src_fmt.chroma_ds_mode = 0;
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regs->reg0274_src_fmt.out_fmt = 1;
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regs->reg0279_src_proc.src_mirr = 0 ;//prep_cfg->mirroring > 0;
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regs->reg0279_src_proc.src_rot = syn->rotation;
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if (syn->hor_stride) {
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stridey = syn->hor_stride;
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} else {
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if (regs->reg0274_src_fmt.src_cfmt == VEPU541_FMT_BGRA8888 )
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stridey = syn->width * 4;
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else if (regs->reg0274_src_fmt.src_cfmt == VEPU541_FMT_BGR888 )
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stridey = syn->width * 3;
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else if (regs->reg0274_src_fmt.src_cfmt == VEPU541_FMT_BGR565 ||
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regs->reg0274_src_fmt.src_cfmt == VEPU541_FMT_YUYV422 ||
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regs->reg0274_src_fmt.src_cfmt == VEPU541_FMT_UYVY422)
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stridey = syn->width * 2;
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}
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stridec = (regs->reg0274_src_fmt.src_cfmt == VEPU541_FMT_YUV422SP ||
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regs->reg0274_src_fmt.src_cfmt == VEPU541_FMT_YUV420SP) ?
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stridey : stridey / 2;
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if (regs->reg0274_src_fmt.src_cfmt < VEPU541_FMT_NONE) {
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regs->reg0275_src_udfy.csc_wgt_r2y = 66;
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regs->reg0275_src_udfy.csc_wgt_g2y = 129;
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regs->reg0275_src_udfy.csc_wgt_b2y = 25;
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regs->reg0276_src_udfu.csc_wgt_r2u = -38;
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regs->reg0276_src_udfu.csc_wgt_g2u = -74;
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regs->reg0276_src_udfu.csc_wgt_b2u = 112;
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regs->reg0277_src_udfv.csc_wgt_r2v = 112;
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regs->reg0277_src_udfv.csc_wgt_g2v = -94;
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regs->reg0277_src_udfv.csc_wgt_b2v = -18;
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regs->reg0278_src_udfo.csc_ofst_y = 16;
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regs->reg0278_src_udfo.csc_ofst_u = 128;
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regs->reg0278_src_udfo.csc_ofst_v = 128;
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}
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regs->reg0281_src_strd0.src_strd0 = stridey;
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regs->reg0282_src_strd1.src_strd1 = stridec;
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regs->reg0280_pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
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regs->reg0280_pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
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//to be done
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regs->reg0283_src_flt.pp_corner_filter_strength = 0;
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regs->reg0283_src_flt.pp_edge_filter_strength = 0;
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regs->reg0283_src_flt.pp_internal_filter_strength = 0;
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regs->reg0284_y_cfg.bias_y = 0;
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regs->reg0285_u_cfg.bias_u = 0;
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regs->reg0286_v_cfg.bias_v = 0;
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regs->reg0287_base_cfg.jpeg_ri = 0;
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regs->reg0287_base_cfg.jpeg_out_mode = 0;
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regs->reg0287_base_cfg.jpeg_start_rst_m = 0;
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regs->reg0287_base_cfg.jpeg_pic_last_ecs = 1;
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regs->reg0287_base_cfg.jpeg_slen_fifo = 0;
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regs->reg0287_base_cfg.jpeg_stnd = 1; //enable
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regs->reg0288_uvc_cfg.uvc_partition0_len = 0;
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regs->reg0288_uvc_cfg.uvc_partition_len = 0;
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regs->reg0288_uvc_cfg.uvc_skip_len = 0;
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return MPP_OK;
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}
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1788
mpp/hal/rkenc/common/vepu540c_common.h
Normal file
1788
mpp/hal/rkenc/common/vepu540c_common.h
Normal file
File diff suppressed because it is too large
Load Diff
@@ -18,5 +18,6 @@
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#define __VEPU5XX_H__
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#define __VEPU5XX_H__
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#define HWID_VEPU58X (0x50603312)
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#define HWID_VEPU58X (0x50603312)
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#define HWID_VEPU540C (0x50603313)
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#endif /* __VEPU5XX_H__ */
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#endif /* __VEPU5XX_H__ */
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