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[h265d]: Fix scaling_list address set issue

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Change-Id: I228981e9c0ca55fb57d61f6d8f0fa170cc7966e3
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
This commit is contained in:
sayon.chen
2021-06-23 09:23:38 +08:00
committed by Herman Chen
parent 4753cbc4e0
commit e3e2c2d6b0
1 changed files with 28 additions and 32 deletions
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32
mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
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@@ -416,7 +416,13 @@ static RK_S32 hal_h265d_v345_output_pps_packet(void *hal, void *dxva)
} }
} }
{ mpp_put_bits(&bp, 0, 32);
mpp_put_bits(&bp, 0, 70);
mpp_put_align(&bp, 64, 0xf);//128
}
if (dxva_cxt->pp.scaling_list_enabled_flag) {
MppDevRegOffsetCfg trans_cfg;
RK_U8 *ptr_scaling = (RK_U8 *)mpp_buffer_get_ptr(reg_cxt->bufs) + reg_cxt->sclst_offset; RK_U8 *ptr_scaling = (RK_U8 *)mpp_buffer_get_ptr(reg_cxt->bufs) + reg_cxt->sclst_offset;
if (dxva_cxt->pp.scaling_list_data_present_flag) { if (dxva_cxt->pp.scaling_list_data_present_flag) {
@@ -429,22 +435,13 @@ static RK_S32 hal_h265d_v345_output_pps_packet(void *hal, void *dxva)
hal_h265d_output_scalinglist_packet(hal, ptr_scaling + addr, dxva); hal_h265d_output_scalinglist_packet(hal, ptr_scaling + addr, dxva);
/* need to config addr */
if (addr) {
MppDevRegOffsetCfg trans_cfg;
trans_cfg.reg_idx = 180;
trans_cfg.offset = addr;
mpp_dev_ioctl(reg_cxt->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
}
mpp_put_bits(&bp, 0, 32);
hw_reg->h265d_addr.reg180_scanlist_addr = reg_cxt->bufs_fd; hw_reg->h265d_addr.reg180_scanlist_addr = reg_cxt->bufs_fd;
hw_reg->common.reg012.scanlist_addr_valid_en = 1; hw_reg->common.reg012.scanlist_addr_valid_en = 1;
mpp_put_bits(&bp, 0, 70); /* need to config addr */
mpp_put_align(&bp, 64, 0xf);//128 trans_cfg.reg_idx = 180;
} trans_cfg.offset = addr + reg_cxt->sclst_offset;
mpp_dev_ioctl(reg_cxt->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
} }
for (i = 0; i < 64; i++) for (i = 0; i < 64; i++)
@@ -478,10 +475,9 @@ static RK_S32 hal_h265d_output_pps_packet(void *hal, void *dxva)
void *pps_ptr = mpp_buffer_get_ptr(reg_cxt->bufs) + reg_cxt->spspps_offset; void *pps_ptr = mpp_buffer_get_ptr(reg_cxt->bufs) + reg_cxt->spspps_offset;
if (dxva_cxt->pp.ps_update_flag) { if (dxva_cxt->pp.ps_update_flag || dxva_cxt->pp.scaling_list_enabled_flag) {
RK_U64 *pps_packet = reg_cxt->pps_buf; RK_U64 *pps_packet = reg_cxt->pps_buf;
if (NULL == pps_ptr) { if (NULL == pps_ptr) {
mpp_err("pps_data get ptr error"); mpp_err("pps_data get ptr error");
return MPP_ERR_NOMEM; return MPP_ERR_NOMEM;
@@ -560,8 +556,8 @@ static RK_S32 hal_h265d_output_pps_packet(void *hal, void *dxva)
mpp_put_bits(&bp, dxva_cxt->pp.pps_slice_chroma_qp_offsets_present_flag , 1); mpp_put_bits(&bp, dxva_cxt->pp.pps_slice_chroma_qp_offsets_present_flag , 1);
mpp_put_bits(&bp, dxva_cxt->pp.weighted_pred_flag , 1); mpp_put_bits(&bp, dxva_cxt->pp.weighted_pred_flag , 1);
mpp_put_bits(&bp, dxva_cxt->pp.weighted_bipred_flag , 1); mpp_put_bits(&bp, dxva_cxt->pp.weighted_bipred_flag , 1);
mpp_put_bits(&bp, dxva_cxt->pp.transquant_bypass_enabled_flag , 1 ); mpp_put_bits(&bp, dxva_cxt->pp.transquant_bypass_enabled_flag , 1);
mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag , 1 ); mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag , 1);
mpp_put_bits(&bp, dxva_cxt->pp.entropy_coding_sync_enabled_flag , 1); mpp_put_bits(&bp, dxva_cxt->pp.entropy_coding_sync_enabled_flag , 1);
mpp_put_bits(&bp, dxva_cxt->pp.pps_loop_filter_across_slices_enabled_flag , 1); mpp_put_bits(&bp, dxva_cxt->pp.pps_loop_filter_across_slices_enabled_flag , 1);
mpp_put_bits(&bp, dxva_cxt->pp.loop_filter_across_tiles_enabled_flag , 1); mpp_put_bits(&bp, dxva_cxt->pp.loop_filter_across_tiles_enabled_flag , 1);