From e0e70e96d2d811dedb4d05f86ea6f64df29df25c Mon Sep 17 00:00:00 2001 From: Tingjin Huang Date: Wed, 21 Aug 2024 17:58:11 +0800 Subject: [PATCH] feat[vepu510]: Add anti-smear regs setup for H.264 Change-Id: I46ce011c215a632c871ea8816563a2eb598146e0 Signed-off-by: Tingjin Huang --- mpp/codec/enc/h264/h264e_api_v2.c | 1 + mpp/codec/enc/h265/h265e_api.c | 1 + mpp/hal/rkenc/common/vepu510_common.h | 7 +- mpp/hal/rkenc/h264e/hal_h264e_vepu510.c | 231 ++++++++++++++------ mpp/hal/rkenc/h264e/hal_h264e_vepu510_reg.h | 210 +++++++++--------- 5 files changed, 281 insertions(+), 169 deletions(-) diff --git a/mpp/codec/enc/h264/h264e_api_v2.c b/mpp/codec/enc/h264/h264e_api_v2.c index a7ac3409..060e220b 100644 --- a/mpp/codec/enc/h264/h264e_api_v2.c +++ b/mpp/codec/enc/h264/h264e_api_v2.c @@ -195,6 +195,7 @@ static void init_h264e_cfg_set(MppEncCfgSet *cfg, MppClientType type) cfg->tune.atr_str_i = 1; cfg->tune.atr_str_p = 1; cfg->tune.anti_flicker_str = 1; + cfg->tune.deblur_str = 3; } static void h264e_add_syntax(H264eCtx *ctx, H264eSyntaxType type, void *p) diff --git a/mpp/codec/enc/h265/h265e_api.c b/mpp/codec/enc/h265/h265e_api.c index 142da68e..042dcef4 100644 --- a/mpp/codec/enc/h265/h265e_api.c +++ b/mpp/codec/enc/h265/h265e_api.c @@ -118,6 +118,7 @@ static MPP_RET h265e_init(void *ctx, EncImplCfg *ctrlCfg) p->cfg->tune.atl_str = 1; p->cfg->tune.sao_str_i = 0; p->cfg->tune.sao_str_p = 1; + p->cfg->tune.deblur_str = 3; /* * default prep: diff --git a/mpp/hal/rkenc/common/vepu510_common.h b/mpp/hal/rkenc/common/vepu510_common.h index 6d3125ef..e5f8319f 100644 --- a/mpp/hal/rkenc/common/vepu510_common.h +++ b/mpp/hal/rkenc/common/vepu510_common.h @@ -1103,7 +1103,12 @@ typedef struct Vepu510Status_t { } st_bnum_b16; /* 0x000040a4 reg4137 */ - RK_U32 st_smear_cnt_reserved; + struct { + RK_U32 rdo_smear_cnt0 : 8; + RK_U32 rdo_smear_cnt1 : 8; + RK_U32 rdo_smear_cnt2 : 8; + RK_U32 rdo_smear_cnt3 : 8; + } st_smear_cnt; /* 0x000040a8 reg4138 */ RK_U32 madi16_sum; diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu510.c b/mpp/hal/rkenc/h264e/hal_h264e_vepu510.c index ba7ce853..1b25ac65 100644 --- a/mpp/hal/rkenc/h264e/hal_h264e_vepu510.c +++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu510.c @@ -40,6 +40,29 @@ typedef struct Vepu510RoiH264BsCfg_t { RK_U64 amv_en : 1; } Vepu510RoiH264BsCfg; +typedef struct Vepu510H264Fbk_t { + RK_U32 hw_status; /* 0:corret, 1:error */ + RK_U32 frame_type; + RK_U32 qp_sum; + RK_U32 out_strm_size; + RK_U32 out_hw_strm_size; + RK_S64 sse_sum; + RK_U32 st_lvl64_inter_num; + RK_U32 st_lvl32_inter_num; + RK_U32 st_lvl16_inter_num; + RK_U32 st_lvl8_inter_num; + RK_U32 st_lvl32_intra_num; + RK_U32 st_lvl16_intra_num; + RK_U32 st_lvl8_intra_num; + RK_U32 st_lvl4_intra_num; + RK_U32 st_cu_num_qp[52]; + RK_U32 st_madp; + RK_U32 st_madi; + RK_U32 st_mb_num; + RK_U32 st_ctu_num; + RK_U32 st_smear_cnt[5]; +} Vepu510H264Fbk; + typedef struct HalH264eVepu510Ctx_t { MppEncCfgSet *cfg; @@ -108,8 +131,12 @@ typedef struct HalH264eVepu510Ctx_t { RK_S32 poll_cfg_size; MppDevPollCfg *poll_cfgs; + Vepu510H264Fbk feedback; + Vepu510H264Fbk last_frame_fb; + void *tune; RK_S32 smart_en; + RK_S32 qpmap_en; } HalH264eVepu510Ctx; #include "hal_h264e_vepu510_tune.c" @@ -525,6 +552,9 @@ static MPP_RET hal_h264e_vepu510_get_task(void *hal, HalEncTask *task) hal_h264e_dbg_func("enter %p\n", hal); + ctx->smart_en = (ctx->cfg->rc.rc_mode == MPP_ENC_RC_MODE_SMTRC); + ctx->qpmap_en = ctx->cfg->tune.deblur_en; + if (updated & SYN_TYPE_FLAG(H264E_SYN_CFG)) setup_hal_bufs(ctx); @@ -533,6 +563,9 @@ static MPP_RET hal_h264e_vepu510_get_task(void *hal, HalEncTask *task) mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data); } + if (!frm_status->reencode) + ctx->last_frame_fb = ctx->feedback; + if (ctx->dpb) { h264e_dpb_hal_start(ctx->dpb, frms->curr_idx); h264e_dpb_hal_start(ctx->dpb, frms->refr_idx); @@ -1116,68 +1149,6 @@ static void setup_vepu510_rdo_pred(HalH264eVepu510Ctx *ctx, H264eSps *sps, hal_h264e_dbg_func("leave\n"); } -static void setup_vepu510_sqi(H264eVepu510Sqi *reg) -{ - hal_h264e_dbg_func("enter\n"); - - reg->smear_opt_cfg.rdo_smear_en = 0; - reg->smear_opt_cfg.rdo_smear_lvl16_multi = 9; - reg->smear_opt_cfg.rdo_smear_dlt_qp = 0 ; - reg->smear_opt_cfg.stated_mode = 0; - - reg->rdo_smear_madp_thd0.rdo_smear_madp_cur_thd0 = 0; - reg->rdo_smear_madp_thd0.rdo_smear_madp_cur_thd1 = 24; - reg->rdo_smear_madp_thd1.rdo_smear_madp_cur_thd2 = 48; - reg->rdo_smear_madp_thd1.rdo_smear_madp_cur_thd3 = 64; - reg->rdo_smear_madp_thd2.rdo_smear_madp_around_thd0 = 16; - reg->rdo_smear_madp_thd2.rdo_smear_madp_around_thd1 = 32; - reg->rdo_smear_madp_thd3.rdo_smear_madp_around_thd2 = 48; - reg->rdo_smear_madp_thd3.rdo_smear_madp_around_thd3 = 96; - reg->rdo_smear_madp_thd4.rdo_smear_madp_around_thd4 = 48; - reg->rdo_smear_madp_thd4.rdo_smear_madp_around_thd5 = 24; - reg->rdo_smear_madp_thd5.rdo_smear_madp_ref_thd0 = 96; - reg->rdo_smear_madp_thd5.rdo_smear_madp_ref_thd1 = 48; - - reg->rdo_smear_cnt_thd0.rdo_smear_cnt_cur_thd0 = 1; - reg->rdo_smear_cnt_thd0.rdo_smear_cnt_cur_thd1 = 3; - reg->rdo_smear_cnt_thd0.rdo_smear_cnt_cur_thd2 = 1; - reg->rdo_smear_cnt_thd0.rdo_smear_cnt_cur_thd3 = 3; - reg->rdo_smear_cnt_thd1.rdo_smear_cnt_around_thd0 = 1; - reg->rdo_smear_cnt_thd1.rdo_smear_cnt_around_thd1 = 4; - reg->rdo_smear_cnt_thd1.rdo_smear_cnt_around_thd2 = 1; - reg->rdo_smear_cnt_thd1.rdo_smear_cnt_around_thd3 = 4; - reg->rdo_smear_cnt_thd2.rdo_smear_cnt_around_thd4 = 0; - reg->rdo_smear_cnt_thd2.rdo_smear_cnt_around_thd5 = 3; - reg->rdo_smear_cnt_thd2.rdo_smear_cnt_around_thd6 = 0; - reg->rdo_smear_cnt_thd2.rdo_smear_cnt_around_thd7 = 3; - reg->rdo_smear_cnt_thd3.rdo_smear_cnt_ref_thd0 = 1 ; - reg->rdo_smear_cnt_thd3.rdo_smear_cnt_ref_thd1 = 3; - - reg->rdo_smear_resi_thd0.rdo_smear_resi_small_cur_th0 = 6; - reg->rdo_smear_resi_thd0.rdo_smear_resi_big_cur_th0 = 9; - reg->rdo_smear_resi_thd0.rdo_smear_resi_small_cur_th1 = 6; - reg->rdo_smear_resi_thd0.rdo_smear_resi_big_cur_th1 = 9; - reg->rdo_smear_resi_thd1.rdo_smear_resi_small_around_th0 = 6; - reg->rdo_smear_resi_thd1.rdo_smear_resi_big_around_th0 = 11; - reg->rdo_smear_resi_thd1.rdo_smear_resi_small_around_th1 = 6; - reg->rdo_smear_resi_thd1.rdo_smear_resi_big_around_th1 = 8; - reg->rdo_smear_resi_thd2.rdo_smear_resi_small_around_th2 = 9; - reg->rdo_smear_resi_thd2.rdo_smear_resi_big_around_th2 = 20; - reg->rdo_smear_resi_thd2.rdo_smear_resi_small_around_th3 = 6; - reg->rdo_smear_resi_thd2.rdo_smear_resi_big_around_th3 = 20; - reg->rdo_smear_resi_thd3.rdo_smear_resi_small_ref_th0 = 7; - reg->rdo_smear_resi_thd3.rdo_smear_resi_big_ref_th0 = 16; - reg->rdo_smear_resi_thd4.rdo_smear_resi_th0 = 10; - reg->rdo_smear_resi_thd4.rdo_smear_resi_th1 = 6; - - reg->rdo_smear_st_thd.rdo_smear_madp_cnt_th0 = 1; - reg->rdo_smear_st_thd.rdo_smear_madp_cnt_th1 = 5; - reg->rdo_smear_st_thd.rdo_smear_madp_cnt_th2 = 1; - reg->rdo_smear_st_thd.rdo_smear_madp_cnt_th3 = 3; - - hal_h264e_dbg_func("leave\n"); -} - static void setup_vepu510_rc_base(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ctx, EncRcTask *rc_task) { H264eSps *sps = ctx->sps; @@ -2036,6 +2007,129 @@ static void setup_vepu510_anti_flicker(HalH264eVepu510Ctx *ctx) reg->rdo_atf_resi_thd.small_th1 = 8; } +static void setup_vepu510_anti_smear(HalH264eVepu510Ctx *ctx) +{ + HalVepu510RegSet *regs = ctx->regs_set; + H264eVepu510Sqi *reg = ®s->reg_sqi; + H264eSlice *slice = ctx->slice; + Vepu510H264Fbk *last_fb = &ctx->last_frame_fb; + RK_U32 mb_cnt = last_fb->st_mb_num; + RK_U32 *smear_cnt = last_fb->st_smear_cnt; + RK_S32 deblur_str = ctx->cfg->tune.deblur_str; + RK_S32 delta_qp = 0; + RK_S32 flg0 = smear_cnt[4] < (mb_cnt >> 6); + RK_S32 flg1 = 1, flg2 = 0, flg3 = 0; + RK_S32 smear_multi[4] = { 9, 12, 16, 16 }; + + hal_h264e_dbg_func("enter\n"); + + if ((smear_cnt[3] < ((5 * mb_cnt) >> 10)) || + (smear_cnt[3] < ((1126 * MPP_MAX3(smear_cnt[0], smear_cnt[1], smear_cnt[2])) >> 10)) || + (deblur_str == 6) || (deblur_str == 7)) + flg1 = 0; + + flg3 = flg1 ? 3 : (smear_cnt[4] > ((102 * mb_cnt) >> 10)) ? 2 : + (smear_cnt[4] > ((66 * mb_cnt) >> 10)) ? 1 : 0; + + if (ctx->cfg->tune.scene_mode == MPP_ENC_SCENE_MODE_IPC) { + reg->smear_opt_cfg.rdo_smear_en = ctx->qpmap_en; + if (ctx->qpmap_en && deblur_str > 3) + reg->smear_opt_cfg.rdo_smear_lvl16_multi = smear_multi[flg3]; + else + reg->smear_opt_cfg.rdo_smear_lvl16_multi = flg0 ? 9 : 12; + } else { + reg->smear_opt_cfg.rdo_smear_en = 0; + reg->smear_opt_cfg.rdo_smear_lvl16_multi = 16; + } + + if (ctx->qpmap_en && deblur_str > 3) { + flg2 = 1; + if (smear_cnt[2] + smear_cnt[3] > (3 * smear_cnt[4] / 4)) + delta_qp = 1; + if (smear_cnt[4] < (mb_cnt >> 4)) + delta_qp -= 8; + else if (smear_cnt[4] < ((3 * mb_cnt) >> 5)) + delta_qp -= 7; + else + delta_qp -= 6; + + if (flg3 == 2) + delta_qp = 0; + else if (flg3 == 1) + delta_qp = -2; + } else { + if (smear_cnt[2] + smear_cnt[3] > smear_cnt[4] / 2) + delta_qp = 1; + if (smear_cnt[4] < (mb_cnt >> 8)) + delta_qp -= (deblur_str < 2) ? 6 : 8; + else if (smear_cnt[4] < (mb_cnt >> 7)) + delta_qp -= (deblur_str < 2) ? 5 : 6; + else if (smear_cnt[4] < (mb_cnt >> 6)) + delta_qp -= (deblur_str < 2) ? 3 : 4; + else + delta_qp -= 1; + } + reg->smear_opt_cfg.rdo_smear_dlt_qp = delta_qp; + + if ((H264_I_SLICE == slice->slice_type) || + (H264_I_SLICE == last_fb->frame_type)) + reg->smear_opt_cfg.stated_mode = 1; + else + reg->smear_opt_cfg.stated_mode = 2; + + reg->smear_madp_thd0.madp_cur_thd0 = 0; + reg->smear_madp_thd0.madp_cur_thd1 = flg2 ? 48 : 24; + reg->smear_madp_thd1.madp_cur_thd2 = flg2 ? 64 : 48; + reg->smear_madp_thd1.madp_cur_thd3 = flg2 ? 72 : 64; + reg->smear_madp_thd2.madp_around_thd0 = flg2 ? 4095 : 16; + reg->smear_madp_thd2.madp_around_thd1 = 32; + reg->smear_madp_thd3.madp_around_thd2 = 48; + reg->smear_madp_thd3.madp_around_thd3 = flg2 ? 0 : 96; + reg->smear_madp_thd4.madp_around_thd4 = 48; + reg->smear_madp_thd4.madp_around_thd5 = 24; + reg->smear_madp_thd5.madp_ref_thd0 = flg2 ? 64 : 96; + reg->smear_madp_thd5.madp_ref_thd1 = 48; + + reg->smear_cnt_thd0.cnt_cur_thd0 = flg2 ? 2 : 1; + reg->smear_cnt_thd0.cnt_cur_thd1 = flg2 ? 5 : 3; + reg->smear_cnt_thd0.cnt_cur_thd2 = 1; + reg->smear_cnt_thd0.cnt_cur_thd3 = 3; + reg->smear_cnt_thd1.cnt_around_thd0 = 1; + reg->smear_cnt_thd1.cnt_around_thd1 = 4; + reg->smear_cnt_thd1.cnt_around_thd2 = 1; + reg->smear_cnt_thd1.cnt_around_thd3 = 4; + reg->smear_cnt_thd2.cnt_around_thd4 = 0; + reg->smear_cnt_thd2.cnt_around_thd5 = 3; + reg->smear_cnt_thd2.cnt_around_thd6 = 0; + reg->smear_cnt_thd2.cnt_around_thd7 = 3; + reg->smear_cnt_thd3.cnt_ref_thd0 = 1; + reg->smear_cnt_thd3.cnt_ref_thd1 = 3; + + reg->smear_resi_thd0.resi_small_cur_th0 = 6; + reg->smear_resi_thd0.resi_big_cur_th0 = 9; + reg->smear_resi_thd0.resi_small_cur_th1 = 6; + reg->smear_resi_thd0.resi_big_cur_th1 = 9; + reg->smear_resi_thd1.resi_small_around_th0 = 6; + reg->smear_resi_thd1.resi_big_around_th0 = 11; + reg->smear_resi_thd1.resi_small_around_th1 = 6; + reg->smear_resi_thd1.resi_big_around_th1 = 8; + reg->smear_resi_thd2.resi_small_around_th2 = 9; + reg->smear_resi_thd2.resi_big_around_th2 = 20; + reg->smear_resi_thd2.resi_small_around_th3 = 6; + reg->smear_resi_thd2.resi_big_around_th3 = 20; + reg->smear_resi_thd3.resi_small_ref_th0 = 7; + reg->smear_resi_thd3.resi_big_ref_th0 = 16; + reg->smear_resi_thd4.resi_th0 = flg2 ? 0 : 10; + reg->smear_resi_thd4.resi_th1 = flg2 ? 0 : 6; + + reg->smear_st_thd.madp_cnt_th0 = flg2 ? 0 : 1; + reg->smear_st_thd.madp_cnt_th1 = flg2 ? 0 : 5; + reg->smear_st_thd.madp_cnt_th2 = flg2 ? 0 : 1; + reg->smear_st_thd.madp_cnt_th3 = flg2 ? 0 : 3; + + hal_h264e_dbg_func("leave\n"); +} + static MPP_RET hal_h264e_vepu510_gen_regs(void *hal, HalEncTask *task) { HalH264eVepu510Ctx *ctx = (HalH264eVepu510Ctx *)hal; @@ -2064,11 +2158,11 @@ static MPP_RET hal_h264e_vepu510_gen_regs(void *hal, HalEncTask *task) setup_vepu510_dual_core(ctx, slice->slice_type); setup_vepu510_codec(regs, sps, pps, slice); setup_vepu510_rdo_pred(ctx, sps, pps, slice); - setup_vepu510_sqi(®s->reg_sqi); setup_vepu510_aq(ctx); setup_vepu510_anti_stripe(ctx); setup_vepu510_anti_ringing(ctx); setup_vepu510_anti_flicker(ctx); + setup_vepu510_anti_smear(ctx); setup_vepu510_rc_base(regs, ctx, rc_task); setup_vepu510_io_buf(regs, ctx->offsets, task); @@ -2367,12 +2461,23 @@ static MPP_RET hal_h264e_vepu510_ret_task(void * hal, HalEncTask * task) HalH264eVepu510Ctx *ctx = (HalH264eVepu510Ctx *)hal; HalVepu510RegSet *regs = &ctx->regs_sets[task->flags.reg_idx]; EncRcTaskInfo *rc_info = &task->rc_task->info; + Vepu510H264Fbk *fb = &ctx->feedback; + Vepu510Status *reg_st = ®s->reg_st; RK_U32 mb_w = ctx->sps->pic_width_in_mbs; RK_U32 mb_h = ctx->sps->pic_height_in_mbs; RK_U32 mbs = mb_w * mb_h; hal_h264e_dbg_func("enter %p\n", hal); + fb->st_mb_num = mbs; + fb->st_smear_cnt[0] = reg_st->st_smear_cnt.rdo_smear_cnt0 * 4; + fb->st_smear_cnt[1] = reg_st->st_smear_cnt.rdo_smear_cnt1 * 4; + fb->st_smear_cnt[2] = reg_st->st_smear_cnt.rdo_smear_cnt2 * 4; + fb->st_smear_cnt[3] = reg_st->st_smear_cnt.rdo_smear_cnt3 * 4; + fb->st_smear_cnt[4] = fb->st_smear_cnt[0] + fb->st_smear_cnt[1] + + fb->st_smear_cnt[2] + fb->st_smear_cnt[3]; + fb->frame_type = ctx->slice->slice_type; + // update total hardware length task->length += task->hw_length; diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu510_reg.h b/mpp/hal/rkenc/h264e/hal_h264e_vepu510_reg.h index e74bb990..9b11af98 100644 --- a/mpp/hal/rkenc/h264e/hal_h264e_vepu510_reg.h +++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu510_reg.h @@ -428,156 +428,156 @@ typedef struct H264eVepu510SqiCfg_t { /* 0x00002018 reg2054 */ struct { - RK_U32 rdo_smear_madp_cur_thd0 : 12; - RK_U32 reserved : 4; - RK_U32 rdo_smear_madp_cur_thd1 : 12; - RK_U32 reserved1 : 4; - } rdo_smear_madp_thd0; + RK_U32 madp_cur_thd0 : 12; + RK_U32 reserved : 4; + RK_U32 madp_cur_thd1 : 12; + RK_U32 reserved1 : 4; + } smear_madp_thd0; /* 0x0000201c reg2055 */ struct { - RK_U32 rdo_smear_madp_cur_thd2 : 12; - RK_U32 reserved : 4; - RK_U32 rdo_smear_madp_cur_thd3 : 12; - RK_U32 reserved1 : 4; - } rdo_smear_madp_thd1; + RK_U32 madp_cur_thd2 : 12; + RK_U32 reserved : 4; + RK_U32 madp_cur_thd3 : 12; + RK_U32 reserved1 : 4; + } smear_madp_thd1; /* 0x00002020 reg2056 */ struct { - RK_U32 rdo_smear_madp_around_thd0 : 12; - RK_U32 reserved : 4; - RK_U32 rdo_smear_madp_around_thd1 : 12; - RK_U32 reserved1 : 4; - } rdo_smear_madp_thd2; + RK_U32 madp_around_thd0 : 12; + RK_U32 reserved : 4; + RK_U32 madp_around_thd1 : 12; + RK_U32 reserved1 : 4; + } smear_madp_thd2; /* 0x00002024 reg2057 */ struct { - RK_U32 rdo_smear_madp_around_thd2 : 12; - RK_U32 reserved : 4; - RK_U32 rdo_smear_madp_around_thd3 : 12; - RK_U32 reserved1 : 4; - } rdo_smear_madp_thd3; + RK_U32 madp_around_thd2 : 12; + RK_U32 reserved : 4; + RK_U32 madp_around_thd3 : 12; + RK_U32 reserved1 : 4; + } smear_madp_thd3; /* 0x00002028 reg2058 */ struct { - RK_U32 rdo_smear_madp_around_thd4 : 12; - RK_U32 reserved : 4; - RK_U32 rdo_smear_madp_around_thd5 : 12; - RK_U32 reserved1 : 4; - } rdo_smear_madp_thd4; + RK_U32 madp_around_thd4 : 12; + RK_U32 reserved : 4; + RK_U32 madp_around_thd5 : 12; + RK_U32 reserved1 : 4; + } smear_madp_thd4; /* 0x0000202c reg2059 */ struct { - RK_U32 rdo_smear_madp_ref_thd0 : 12; - RK_U32 reserved : 4; - RK_U32 rdo_smear_madp_ref_thd1 : 12; - RK_U32 reserved1 : 4; - } rdo_smear_madp_thd5; + RK_U32 madp_ref_thd0 : 12; + RK_U32 reserved : 4; + RK_U32 madp_ref_thd1 : 12; + RK_U32 reserved1 : 4; + } smear_madp_thd5; /* 0x00002030 reg2060 */ struct { - RK_U32 rdo_smear_cnt_cur_thd0 : 4; - RK_U32 reserved : 4; - RK_U32 rdo_smear_cnt_cur_thd1 : 4; - RK_U32 reserved1 : 4; - RK_U32 rdo_smear_cnt_cur_thd2 : 4; - RK_U32 reserved2 : 4; - RK_U32 rdo_smear_cnt_cur_thd3 : 4; - RK_U32 reserved3 : 4; - } rdo_smear_cnt_thd0; + RK_U32 cnt_cur_thd0 : 4; + RK_U32 reserved : 4; + RK_U32 cnt_cur_thd1 : 4; + RK_U32 reserved1 : 4; + RK_U32 cnt_cur_thd2 : 4; + RK_U32 reserved2 : 4; + RK_U32 cnt_cur_thd3 : 4; + RK_U32 reserved3 : 4; + } smear_cnt_thd0; /* 0x00002034 reg2061 */ struct { - RK_U32 rdo_smear_cnt_around_thd0 : 4; - RK_U32 reserved : 4; - RK_U32 rdo_smear_cnt_around_thd1 : 4; - RK_U32 reserved1 : 4; - RK_U32 rdo_smear_cnt_around_thd2 : 4; - RK_U32 reserved2 : 4; - RK_U32 rdo_smear_cnt_around_thd3 : 4; - RK_U32 reserved3 : 4; - } rdo_smear_cnt_thd1; + RK_U32 cnt_around_thd0 : 4; + RK_U32 reserved : 4; + RK_U32 cnt_around_thd1 : 4; + RK_U32 reserved1 : 4; + RK_U32 cnt_around_thd2 : 4; + RK_U32 reserved2 : 4; + RK_U32 cnt_around_thd3 : 4; + RK_U32 reserved3 : 4; + } smear_cnt_thd1; /* 0x00002038 reg2062 */ struct { - RK_U32 rdo_smear_cnt_around_thd4 : 4; - RK_U32 reserved : 4; - RK_U32 rdo_smear_cnt_around_thd5 : 4; - RK_U32 reserved1 : 4; - RK_U32 rdo_smear_cnt_around_thd6 : 4; - RK_U32 reserved2 : 4; - RK_U32 rdo_smear_cnt_around_thd7 : 4; - RK_U32 reserved3 : 4; - } rdo_smear_cnt_thd2; + RK_U32 cnt_around_thd4 : 4; + RK_U32 reserved : 4; + RK_U32 cnt_around_thd5 : 4; + RK_U32 reserved1 : 4; + RK_U32 cnt_around_thd6 : 4; + RK_U32 reserved2 : 4; + RK_U32 cnt_around_thd7 : 4; + RK_U32 reserved3 : 4; + } smear_cnt_thd2; /* 0x0000203c reg2063 */ struct { - RK_U32 rdo_smear_cnt_ref_thd0 : 4; - RK_U32 reserved : 4; - RK_U32 rdo_smear_cnt_ref_thd1 : 4; - RK_U32 reserved1 : 20; - } rdo_smear_cnt_thd3; + RK_U32 cnt_ref_thd0 : 4; + RK_U32 reserved : 4; + RK_U32 cnt_ref_thd1 : 4; + RK_U32 reserved1 : 20; + } smear_cnt_thd3; /* 0x00002040 reg2064 */ struct { - RK_U32 rdo_smear_resi_small_cur_th0 : 6; - RK_U32 reserved : 2; - RK_U32 rdo_smear_resi_big_cur_th0 : 6; - RK_U32 reserved1 : 2; - RK_U32 rdo_smear_resi_small_cur_th1 : 6; - RK_U32 reserved2 : 2; - RK_U32 rdo_smear_resi_big_cur_th1 : 6; - RK_U32 reserved3 : 2; - } rdo_smear_resi_thd0; + RK_U32 resi_small_cur_th0 : 6; + RK_U32 reserved : 2; + RK_U32 resi_big_cur_th0 : 6; + RK_U32 reserved1 : 2; + RK_U32 resi_small_cur_th1 : 6; + RK_U32 reserved2 : 2; + RK_U32 resi_big_cur_th1 : 6; + RK_U32 reserved3 : 2; + } smear_resi_thd0; /* 0x00002044 reg2065 */ struct { - RK_U32 rdo_smear_resi_small_around_th0 : 6; - RK_U32 reserved : 2; - RK_U32 rdo_smear_resi_big_around_th0 : 6; - RK_U32 reserved1 : 2; - RK_U32 rdo_smear_resi_small_around_th1 : 6; - RK_U32 reserved2 : 2; - RK_U32 rdo_smear_resi_big_around_th1 : 6; - RK_U32 reserved3 : 2; - } rdo_smear_resi_thd1; + RK_U32 resi_small_around_th0 : 6; + RK_U32 reserved : 2; + RK_U32 resi_big_around_th0 : 6; + RK_U32 reserved1 : 2; + RK_U32 resi_small_around_th1 : 6; + RK_U32 reserved2 : 2; + RK_U32 resi_big_around_th1 : 6; + RK_U32 reserved3 : 2; + } smear_resi_thd1; /* 0x00002048 reg2066 */ struct { - RK_U32 rdo_smear_resi_small_around_th2 : 6; - RK_U32 reserved : 2; - RK_U32 rdo_smear_resi_big_around_th2 : 6; - RK_U32 reserved1 : 2; - RK_U32 rdo_smear_resi_small_around_th3 : 6; - RK_U32 reserved2 : 2; - RK_U32 rdo_smear_resi_big_around_th3 : 6; - RK_U32 reserved3 : 2; - } rdo_smear_resi_thd2; + RK_U32 resi_small_around_th2 : 6; + RK_U32 reserved : 2; + RK_U32 resi_big_around_th2 : 6; + RK_U32 reserved1 : 2; + RK_U32 resi_small_around_th3 : 6; + RK_U32 reserved2 : 2; + RK_U32 resi_big_around_th3 : 6; + RK_U32 reserved3 : 2; + } smear_resi_thd2; /* 0x0000204c reg2067 */ struct { - RK_U32 rdo_smear_resi_small_ref_th0 : 6; - RK_U32 reserved : 2; - RK_U32 rdo_smear_resi_big_ref_th0 : 6; - RK_U32 reserved1 : 18; - } rdo_smear_resi_thd3; + RK_U32 resi_small_ref_th0 : 6; + RK_U32 reserved : 2; + RK_U32 resi_big_ref_th0 : 6; + RK_U32 reserved1 : 18; + } smear_resi_thd3; /* 0x00002050 reg2068 */ struct { - RK_U32 rdo_smear_resi_th0 : 8; - RK_U32 reserved : 8; - RK_U32 rdo_smear_resi_th1 : 8; - RK_U32 reserved1 : 8; - } rdo_smear_resi_thd4; + RK_U32 resi_th0 : 8; + RK_U32 reserved : 8; + RK_U32 resi_th1 : 8; + RK_U32 reserved1 : 8; + } smear_resi_thd4; /* 0x00002054 reg2069 */ struct { - RK_U32 rdo_smear_madp_cnt_th0 : 4; - RK_U32 rdo_smear_madp_cnt_th1 : 4; - RK_U32 rdo_smear_madp_cnt_th2 : 4; - RK_U32 rdo_smear_madp_cnt_th3 : 4; - RK_U32 reserved : 16; - } rdo_smear_st_thd; + RK_U32 madp_cnt_th0 : 4; + RK_U32 madp_cnt_th1 : 4; + RK_U32 madp_cnt_th2 : 4; + RK_U32 madp_cnt_th3 : 4; + RK_U32 reserved : 16; + } smear_st_thd; /* 0x2058 - 0x206c */ RK_U32 reserved2070_2075[6];