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[h265d] add wr_ddr_align_en in swreg[1]

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when frame is not tiled mode, set wr_ddr_align_en enable.

Change-Id: I5135eca50785e744b83bc98c0913ee909e9ce445
Signed-off-by: leo.ding <leo.ding@rock-chips.com>
This commit is contained in:
leo.ding
2016-11-15 18:42:45 +08:00
parent 38172cb6e2
commit dfd39167bb
2 changed files with 4 additions and 1 deletions
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2
mpp/hal/rkdec/h265d/hal_h265d_reg.c
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@@ -1453,6 +1453,7 @@ MPP_RET hal_h265d_gen_regs(void *hal, HalTaskInfo *syn)
}
hw_regs->sw_interrupt.sw_dec_e = 1;
hw_regs->sw_interrupt.sw_dec_timeout_e = 1;
hw_regs->sw_interrupt.sw_wr_ddr_align_en = dxva_cxt->pp.tiles_enabled_flag ? 0 : 1;
///find s->rps_model[i] position, and set register
@@ -1523,7 +1524,6 @@ MPP_RET hal_h265d_start(void *hal, HalTaskInfo *task)
}
#ifdef RKPLATFORM
ret = VPUClientSendReg(reg_cxt->vpu_socket, (RK_U32*)hw_regs, 78); // 68 is the nb of uint32_t
if (ret != 0) {
mpp_err("RK_HEVC_DEC: ERROR: VPUClientSendReg Failed!!!\n");
return MPP_ERR_VPUHW;

3
mpp/hal/rkdec/h265d/hal_h265d_reg.h
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@@ -66,6 +66,9 @@ typedef struct {
RK_U32 sw_softrst_en_p : 1 ;
RK_U32 sw_force_softreset_valid: 1 ;
RK_U32 sw_softreset_rdy : 1 ;
RK_U32 sw_wr_ddr_align_en : 1;
RK_U32 sw_scl_down_en : 1;
RK_U32 sw_allow_not_wr_unref_bframe : 1;
} sw_interrupt; ///<- zrh: do nothing in C Model
struct swreg_sysctrl {