mirror of
https://github.com/nyanmisaka/mpp.git
synced 2025-10-05 01:02:39 +08:00
fix[mpp_enc]: Add encoder speed mode setup
The encoder speed mode is in range of 0 ~ 3. 0 - normal mode with all mode decision path enabled. 1 - fast mode 2 - faster mode 3 - fastest mode Signed-off-by: toby.zhang <toby.zhang@rock-chips.com> Change-Id: I0c607adbc1e4cea4025fa8a3816dc3a1ec1f13a1 Signed-off-by: toby.zhang <toby.zhang@rock-chips.com>
This commit is contained in:
@@ -1541,6 +1541,7 @@ typedef enum MppEncFineTuneCfgChange_e {
|
|||||||
MPP_ENC_TUNE_CFG_CHANGE_MADP16_TH = (1 << 19),
|
MPP_ENC_TUNE_CFG_CHANGE_MADP16_TH = (1 << 19),
|
||||||
MPP_ENC_TUNE_CFG_CHANGE_SKIP16_WGT = (1 << 20),
|
MPP_ENC_TUNE_CFG_CHANGE_SKIP16_WGT = (1 << 20),
|
||||||
MPP_ENC_TUNE_CFG_CHANGE_SKIP32_WGT = (1 << 21),
|
MPP_ENC_TUNE_CFG_CHANGE_SKIP32_WGT = (1 << 21),
|
||||||
|
MPP_ENC_TUNE_CFG_CHANGE_SPEED = (1 << 22),
|
||||||
MPP_ENC_TUNE_CFG_CHANGE_ALL = (0xFFFFFFFF),
|
MPP_ENC_TUNE_CFG_CHANGE_ALL = (0xFFFFFFFF),
|
||||||
} MppEncFineTuneCfgChange;
|
} MppEncFineTuneCfgChange;
|
||||||
|
|
||||||
@@ -1570,7 +1571,7 @@ typedef struct MppEncFineTuneCfg_t {
|
|||||||
RK_S32 skip16_wgt; /* weight for skip16, 0 or [3, 8] */
|
RK_S32 skip16_wgt; /* weight for skip16, 0 or [3, 8] */
|
||||||
RK_S32 skip32_wgt; /* weight for skip32, 0 or [3, 8] */
|
RK_S32 skip32_wgt; /* weight for skip32, 0 or [3, 8] */
|
||||||
RK_S32 qpmap_en;
|
RK_S32 qpmap_en;
|
||||||
RK_S32 enc_spd;/*enc speed [0..3] , 0:full mode; 1:fast; 2:faster; 3:fastest */
|
RK_S32 speed; /*enc speed [0..3], 0:full mode; 1:fast; 2:faster; 3:fastest */
|
||||||
RK_S32 reserved[4];
|
RK_S32 reserved[4];
|
||||||
} MppEncFineTuneCfg;
|
} MppEncFineTuneCfg;
|
||||||
|
|
||||||
|
@@ -269,11 +269,11 @@ public:
|
|||||||
ENTRY(tune, anti_flicker_str,S32, MPP_ENC_TUNE_CFG_CHANGE_ANTI_FLICKER_STR,tune, anti_flicker_str) \
|
ENTRY(tune, anti_flicker_str,S32, MPP_ENC_TUNE_CFG_CHANGE_ANTI_FLICKER_STR,tune, anti_flicker_str) \
|
||||||
ENTRY(tune, lambda_idx_i, S32, MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_I, tune, lambda_idx_i) \
|
ENTRY(tune, lambda_idx_i, S32, MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_I, tune, lambda_idx_i) \
|
||||||
ENTRY(tune, lambda_idx_p, S32, MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_P, tune, lambda_idx_p) \
|
ENTRY(tune, lambda_idx_p, S32, MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_P, tune, lambda_idx_p) \
|
||||||
ENTRY(tune, atr_str_i, S32, MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_I, tune, atr_str_i) \
|
ENTRY(tune, atr_str_i, S32, MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_I, tune, atr_str_i) \
|
||||||
ENTRY(tune, atr_str_p, S32, MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_P, tune, atr_str_p) \
|
ENTRY(tune, atr_str_p, S32, MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_P, tune, atr_str_p) \
|
||||||
ENTRY(tune, atl_str, S32, MPP_ENC_TUNE_CFG_CHANGE_ATL_STR, tune, atl_str) \
|
ENTRY(tune, atl_str, S32, MPP_ENC_TUNE_CFG_CHANGE_ATL_STR, tune, atl_str) \
|
||||||
ENTRY(tune, sao_str_i, S32, MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_I, tune, sao_str_i) \
|
ENTRY(tune, sao_str_i, S32, MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_I, tune, sao_str_i) \
|
||||||
ENTRY(tune, sao_str_p, S32, MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_P, tune, sao_str_p) \
|
ENTRY(tune, sao_str_p, S32, MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_P, tune, sao_str_p) \
|
||||||
ENTRY(tune, rc_container, S32, MPP_ENC_TUNE_CFG_CHANGE_RC_CONTAINER, tune, rc_container) \
|
ENTRY(tune, rc_container, S32, MPP_ENC_TUNE_CFG_CHANGE_RC_CONTAINER, tune, rc_container) \
|
||||||
ENTRY(tune, vmaf_opt, S32, MPP_ENC_TUNE_CFG_CHANGE_VMAF_OPT, tune, vmaf_opt) \
|
ENTRY(tune, vmaf_opt, S32, MPP_ENC_TUNE_CFG_CHANGE_VMAF_OPT, tune, vmaf_opt) \
|
||||||
ENTRY(tune, motion_static_switch_enable, S32, MPP_ENC_TUNE_CFG_CHANGE_MOTION_STATIC_SWITCH_ENABLE, tune, motion_static_switch_enable) \
|
ENTRY(tune, motion_static_switch_enable, S32, MPP_ENC_TUNE_CFG_CHANGE_MOTION_STATIC_SWITCH_ENABLE, tune, motion_static_switch_enable) \
|
||||||
@@ -282,7 +282,8 @@ public:
|
|||||||
ENTRY(tune, static_frm_num, S32, MPP_ENC_TUNE_CFG_CHANGE_STATIC_FRM_NUM, tune, static_frm_num) \
|
ENTRY(tune, static_frm_num, S32, MPP_ENC_TUNE_CFG_CHANGE_STATIC_FRM_NUM, tune, static_frm_num) \
|
||||||
ENTRY(tune, madp16_th, S32, MPP_ENC_TUNE_CFG_CHANGE_MADP16_TH, tune, madp16_th) \
|
ENTRY(tune, madp16_th, S32, MPP_ENC_TUNE_CFG_CHANGE_MADP16_TH, tune, madp16_th) \
|
||||||
ENTRY(tune, skip16_wgt, S32, MPP_ENC_TUNE_CFG_CHANGE_SKIP16_WGT, tune, skip16_wgt) \
|
ENTRY(tune, skip16_wgt, S32, MPP_ENC_TUNE_CFG_CHANGE_SKIP16_WGT, tune, skip16_wgt) \
|
||||||
ENTRY(tune, skip32_wgt, S32, MPP_ENC_TUNE_CFG_CHANGE_SKIP32_WGT, tune, skip32_wgt)
|
ENTRY(tune, skip32_wgt, S32, MPP_ENC_TUNE_CFG_CHANGE_SKIP32_WGT, tune, skip32_wgt) \
|
||||||
|
ENTRY(tune, speed, S32, MPP_ENC_TUNE_CFG_CHANGE_SPEED, tune, speed)
|
||||||
|
|
||||||
MppEncCfgService::MppEncCfgService() :
|
MppEncCfgService::MppEncCfgService() :
|
||||||
mTrie(NULL)
|
mTrie(NULL)
|
||||||
|
@@ -414,6 +414,7 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info)
|
|||||||
RK_U32 flip;
|
RK_U32 flip;
|
||||||
RK_U32 gop_mode = p->gop_mode;
|
RK_U32 gop_mode = p->gop_mode;
|
||||||
MppEncRefCfg ref = NULL;
|
MppEncRefCfg ref = NULL;
|
||||||
|
|
||||||
/* setup default parameter */
|
/* setup default parameter */
|
||||||
if (p->fps_in_den == 0)
|
if (p->fps_in_den == 0)
|
||||||
p->fps_in_den = 1;
|
p->fps_in_den = 1;
|
||||||
@@ -427,40 +428,7 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info)
|
|||||||
if (!p->bps)
|
if (!p->bps)
|
||||||
p->bps = p->width * p->height / 8 * (p->fps_out_num / p->fps_out_den);
|
p->bps = p->width * p->height / 8 * (p->fps_out_num / p->fps_out_den);
|
||||||
|
|
||||||
if (cmd->rc_mode == MPP_ENC_RC_MODE_SMTRC) {
|
/* setup preprocess parameters */
|
||||||
mpp_enc_cfg_set_st(cfg, "hw:aq_thrd_i", aq_thd_smart);
|
|
||||||
mpp_enc_cfg_set_st(cfg, "hw:aq_thrd_p", aq_thd_smart);
|
|
||||||
mpp_enc_cfg_set_st(cfg, "hw:aq_step_i", aq_step_smart);
|
|
||||||
mpp_enc_cfg_set_st(cfg, "hw:aq_step_p", aq_step_smart);
|
|
||||||
} else {
|
|
||||||
mpp_enc_cfg_set_st(cfg, "hw:aq_thrd_i", aq_thd);
|
|
||||||
mpp_enc_cfg_set_st(cfg, "hw:aq_thrd_p", aq_thd);
|
|
||||||
mpp_enc_cfg_set_st(cfg, "hw:aq_step_i", aq_step_i_ipc);
|
|
||||||
mpp_enc_cfg_set_st(cfg, "hw:aq_step_p", aq_step_p_ipc);
|
|
||||||
}
|
|
||||||
|
|
||||||
mpp_enc_cfg_set_st(cfg, "hw:aq_rnge_arr", aq_rnge_arr);
|
|
||||||
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "rc:max_reenc_times", 0);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "tune:anti_flicker_str", p->anti_flicker_str);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "tune:atr_str_i", p->atr_str_i);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "tune:atr_str_p", p->atr_str_p);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "tune:atl_str", p->atl_str);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "tune:sao_str_i", p->sao_str_i);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "tune:sao_str_p", p->sao_str_p);
|
|
||||||
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "tune:scene_mode", p->scene_mode);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "tune:deblur_en", cmd->deblur_en);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "tune:deblur_str", cmd->deblur_str);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "tune:rc_container", cmd->rc_container);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "tune:vmaf_opt", 0);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "hw:qbias_en", 1);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "hw:qbias_i", cmd->bias_i);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "hw:qbias_p", cmd->bias_p);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "hw:skip_bias_en", 0);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "hw:skip_bias", 4);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "hw:skip_sad", 8);
|
|
||||||
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "prep:width", p->width);
|
mpp_enc_cfg_set_s32(cfg, "prep:width", p->width);
|
||||||
mpp_enc_cfg_set_s32(cfg, "prep:height", p->height);
|
mpp_enc_cfg_set_s32(cfg, "prep:height", p->height);
|
||||||
mpp_enc_cfg_set_s32(cfg, "prep:hor_stride", p->hor_stride);
|
mpp_enc_cfg_set_s32(cfg, "prep:hor_stride", p->hor_stride);
|
||||||
@@ -468,6 +436,15 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info)
|
|||||||
mpp_enc_cfg_set_s32(cfg, "prep:format", p->fmt);
|
mpp_enc_cfg_set_s32(cfg, "prep:format", p->fmt);
|
||||||
mpp_enc_cfg_set_s32(cfg, "prep:range", MPP_FRAME_RANGE_JPEG);
|
mpp_enc_cfg_set_s32(cfg, "prep:range", MPP_FRAME_RANGE_JPEG);
|
||||||
|
|
||||||
|
mpp_env_get_u32("mirroring", &mirroring, 0);
|
||||||
|
mpp_env_get_u32("rotation", &rotation, 0);
|
||||||
|
mpp_env_get_u32("flip", &flip, 0);
|
||||||
|
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "prep:mirroring", mirroring);
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "prep:rotation", rotation);
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "prep:flip", flip);
|
||||||
|
|
||||||
|
/* setup rate control parameters */
|
||||||
mpp_enc_cfg_set_s32(cfg, "rc:mode", p->rc_mode);
|
mpp_enc_cfg_set_s32(cfg, "rc:mode", p->rc_mode);
|
||||||
mpp_enc_cfg_set_u32(cfg, "rc:max_reenc_times", 0);
|
mpp_enc_cfg_set_u32(cfg, "rc:max_reenc_times", 0);
|
||||||
mpp_enc_cfg_set_u32(cfg, "rc:super_mode", 0);
|
mpp_enc_cfg_set_u32(cfg, "rc:super_mode", 0);
|
||||||
@@ -511,11 +488,7 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info)
|
|||||||
|
|
||||||
/* setup qp for different codec and rc_mode */
|
/* setup qp for different codec and rc_mode */
|
||||||
switch (p->type) {
|
switch (p->type) {
|
||||||
case MPP_VIDEO_CodingAVC : {
|
|
||||||
mpp_enc_cfg_set_st(cfg, "hw:qbias_arr", qbias_arr_avc);
|
|
||||||
} break;
|
|
||||||
case MPP_VIDEO_CodingHEVC : {
|
case MPP_VIDEO_CodingHEVC : {
|
||||||
mpp_enc_cfg_set_st(cfg, "hw:qbias_arr", qbias_arr_hevc);
|
|
||||||
switch (p->rc_mode) {
|
switch (p->rc_mode) {
|
||||||
case MPP_ENC_RC_MODE_FIXQP : {
|
case MPP_ENC_RC_MODE_FIXQP : {
|
||||||
RK_S32 fix_qp = cmd->qp_init;
|
RK_S32 fix_qp = cmd->qp_init;
|
||||||
@@ -627,14 +600,6 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info)
|
|||||||
mpp_enc_cfg_set_s32(cfg, "split:out", p->split_out);
|
mpp_enc_cfg_set_s32(cfg, "split:out", p->split_out);
|
||||||
}
|
}
|
||||||
|
|
||||||
mpp_env_get_u32("mirroring", &mirroring, 0);
|
|
||||||
mpp_env_get_u32("rotation", &rotation, 0);
|
|
||||||
mpp_env_get_u32("flip", &flip, 0);
|
|
||||||
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "prep:mirroring", mirroring);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "prep:rotation", rotation);
|
|
||||||
mpp_enc_cfg_set_s32(cfg, "prep:flip", flip);
|
|
||||||
|
|
||||||
// config gop_len and ref cfg
|
// config gop_len and ref cfg
|
||||||
mpp_enc_cfg_set_s32(cfg, "rc:gop", p->gop_len ? p->gop_len : p->fps_out_num * 2);
|
mpp_enc_cfg_set_s32(cfg, "rc:gop", p->gop_len ? p->gop_len : p->fps_out_num * 2);
|
||||||
|
|
||||||
@@ -650,6 +615,49 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info)
|
|||||||
mpp_enc_cfg_set_ptr(cfg, "rc:ref_cfg", ref);
|
mpp_enc_cfg_set_ptr(cfg, "rc:ref_cfg", ref);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* setup fine tuning paramters */
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "tune:speed", cmd->speed);
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "tune:anti_flicker_str", p->anti_flicker_str);
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "tune:atr_str_i", p->atr_str_i);
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "tune:atr_str_p", p->atr_str_p);
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "tune:atl_str", p->atl_str);
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "tune:sao_str_i", p->sao_str_i);
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "tune:sao_str_p", p->sao_str_p);
|
||||||
|
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "tune:scene_mode", p->scene_mode);
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "tune:deblur_en", cmd->deblur_en);
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "tune:deblur_str", cmd->deblur_str);
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "tune:rc_container", cmd->rc_container);
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "tune:vmaf_opt", 0);
|
||||||
|
|
||||||
|
/* setup hardware specified parameters */
|
||||||
|
if (cmd->rc_mode == MPP_ENC_RC_MODE_SMTRC) {
|
||||||
|
mpp_enc_cfg_set_st(cfg, "hw:aq_thrd_i", aq_thd_smart);
|
||||||
|
mpp_enc_cfg_set_st(cfg, "hw:aq_thrd_p", aq_thd_smart);
|
||||||
|
mpp_enc_cfg_set_st(cfg, "hw:aq_step_i", aq_step_smart);
|
||||||
|
mpp_enc_cfg_set_st(cfg, "hw:aq_step_p", aq_step_smart);
|
||||||
|
} else {
|
||||||
|
mpp_enc_cfg_set_st(cfg, "hw:aq_thrd_i", aq_thd);
|
||||||
|
mpp_enc_cfg_set_st(cfg, "hw:aq_thrd_p", aq_thd);
|
||||||
|
mpp_enc_cfg_set_st(cfg, "hw:aq_step_i", aq_step_i_ipc);
|
||||||
|
mpp_enc_cfg_set_st(cfg, "hw:aq_step_p", aq_step_p_ipc);
|
||||||
|
}
|
||||||
|
mpp_enc_cfg_set_st(cfg, "hw:aq_rnge_arr", aq_rnge_arr);
|
||||||
|
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "hw:qbias_en", 1);
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "hw:qbias_i", cmd->bias_i);
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "hw:qbias_p", cmd->bias_p);
|
||||||
|
|
||||||
|
if (p->type == MPP_VIDEO_CodingAVC) {
|
||||||
|
mpp_enc_cfg_set_st(cfg, "hw:qbias_arr", qbias_arr_avc);
|
||||||
|
} else if (p->type == MPP_VIDEO_CodingHEVC) {
|
||||||
|
mpp_enc_cfg_set_st(cfg, "hw:qbias_arr", qbias_arr_hevc);
|
||||||
|
}
|
||||||
|
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "hw:skip_bias_en", 0);
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "hw:skip_bias", 4);
|
||||||
|
mpp_enc_cfg_set_s32(cfg, "hw:skip_sad", 8);
|
||||||
|
|
||||||
ret = mpi->control(ctx, MPP_ENC_SET_CFG, cfg);
|
ret = mpi->control(ctx, MPP_ENC_SET_CFG, cfg);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
mpp_err("mpi control enc set cfg failed ret %d\n", ret);
|
mpp_err("mpi control enc set cfg failed ret %d\n", ret);
|
||||||
|
@@ -652,6 +652,23 @@ RK_S32 mpi_enc_opt_bias_p(void *ctx, const char *next)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
RK_S32 mpi_enc_opt_speed(void *ctx, const char *next)
|
||||||
|
{
|
||||||
|
MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
|
||||||
|
|
||||||
|
if (next) {
|
||||||
|
cmd->speed = atoi(next);
|
||||||
|
if (cmd->speed > 3 || cmd->speed < 0) {
|
||||||
|
cmd->speed = 0;
|
||||||
|
mpp_err("invalid speed %d set to default 0\n", cmd->speed);
|
||||||
|
}
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
mpp_err("invalid speed mode\n");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
RK_S32 mpi_enc_opt_kmpp(void *ctx, const char *next)
|
RK_S32 mpi_enc_opt_kmpp(void *ctx, const char *next)
|
||||||
{
|
{
|
||||||
MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
|
MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
|
||||||
@@ -706,6 +723,7 @@ static MppOptInfo enc_opts[] = {
|
|||||||
{"bc", "bitrate container", "rc_container, 0:off 1:weak 2:strong", mpi_enc_opt_bc},
|
{"bc", "bitrate container", "rc_container, 0:off 1:weak 2:strong", mpi_enc_opt_bc},
|
||||||
{"ibias", "bias i", "bias_i", mpi_enc_opt_bias_i},
|
{"ibias", "bias i", "bias_i", mpi_enc_opt_bias_i},
|
||||||
{"pbias", "bias p", "bias_p", mpi_enc_opt_bias_p},
|
{"pbias", "bias p", "bias_p", mpi_enc_opt_bias_p},
|
||||||
|
{"speed", "enc speed", "speed", mpi_enc_opt_speed},
|
||||||
{"kmpp", "kmpp path enable", "kmpp path enable", mpi_enc_opt_kmpp}
|
{"kmpp", "kmpp path enable", "kmpp path enable", mpi_enc_opt_kmpp}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@@ -88,7 +88,7 @@ typedef struct MpiEncTestArgs_t {
|
|||||||
RK_S32 atl_str;
|
RK_S32 atl_str;
|
||||||
RK_S32 sao_str_i;
|
RK_S32 sao_str_i;
|
||||||
RK_S32 sao_str_p;
|
RK_S32 sao_str_p;
|
||||||
|
RK_S32 speed;
|
||||||
/* -dbe deblur enable flag
|
/* -dbe deblur enable flag
|
||||||
* -dbs deblur strength
|
* -dbs deblur strength
|
||||||
*/
|
*/
|
||||||
|
Reference in New Issue
Block a user