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[mpeg4d]: update mpeg4 parser and hal for vpu2

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git-svn-id: https://10.10.10.66:8443/svn/MediaProcessPlatform/trunk/mpp@974 6e48237b-75ef-9749-8fc9-41990f28c85a
This commit is contained in:
ChenHengming
2016-07-01 09:54:42 +00:00
parent 15ce9ca949
commit dba5c94f8e
10 changed files with 2249 additions and 188 deletions
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2
inc/rk_mpi.h
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@@ -75,7 +75,7 @@ typedef enum {
MPP_DEC_CMD_BASE = 0x40000,
MPP_DEC_SET_EXT_BUF_GROUP, /* IMPORTANT: set external buffer group to mpp decoder */
MPP_DEC_USE_PRESENT_TIME_ORDER,
MPP_DEC_SET_INTERNAL_PTS_ENABLE,
MPP_DEC_SET_VC1_EXTRA_DATA,
MPP_DEC_SET_PARSER_SPLIT_MODE, /* Need to setup before init */
MPP_DEC_SET_PARSER_FAST_MODE, /* Need to setup before init */

33
mpp/codec/dec/mpg4/mpg4d_api.c
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@@ -19,10 +19,11 @@
#include <string.h>
#include "rk_mpi.h"
#include "mpp_log.h"
#include "mpp_mem.h"
#include "mpp_common.h"
#include "mpp_packet.h"
#include "mpg4d_api.h"
#include "mpg4d_parser.h"
@@ -43,6 +44,7 @@ typedef struct {
// runtime parameter
RK_U32 need_split;
RK_U32 frame_count;
RK_U32 internal_pts;
IOInterruptCB notify_cb;
// parser context
@@ -89,8 +91,9 @@ MPP_RET mpg4d_init(void *dec, ParserCfg *cfg)
p = (Mpg4dCtx *)dec;
p->frame_slots = cfg->frame_slots;
p->packet_slots = cfg->packet_slots;
p->need_split = cfg->need_split;
p->task_count = cfg->task_count = 2;
p->need_split = cfg->need_split;
p->internal_pts = cfg->internal_pts;
p->notify_cb = cfg->notify_cb;
p->stream = stream;
p->stream_size = stream_size;
@@ -140,7 +143,8 @@ MPP_RET mpg4d_reset(void *dec)
mpp_err_f("found NULL intput\n");
return MPP_ERR_NULL_PTR;
}
return MPP_OK;
return mpp_mpg4_parser_reset(dec);
}
@@ -150,17 +154,26 @@ MPP_RET mpg4d_flush(void *dec)
mpp_err_f("found NULL intput\n");
return MPP_ERR_NULL_PTR;
}
return MPP_OK;
return mpp_mpg4_parser_flush(dec);
}
MPP_RET mpg4d_control(void *dec, RK_S32 cmd_type, void *param)
{
Mpg4dCtx *p;
if (NULL == dec) {
mpp_err_f("found NULL intput\n");
return MPP_ERR_NULL_PTR;
}
(void)cmd_type;
p = (Mpg4dCtx *)dec;
switch (cmd_type) {
case MPP_DEC_SET_INTERNAL_PTS_ENABLE : {
mpp_mpg4_parser_set_pts_mode(p, 1);
} break;
}
(void)param;
return MPP_OK;
}
@@ -254,6 +267,7 @@ MPP_RET mpg4d_prepare(void *dec, MppPacket pkt, HalDecTask *task)
task->input_packet = p->task_pkt;
task->flags.eos = p->task_eos;
return MPP_OK;
}
@@ -271,14 +285,14 @@ MPP_RET mpg4d_parse(void *dec, HalDecTask *task)
if (ret) {
// found error on decoding drop this task and clear remaining length
task->output = -1;
mpp_packet_set_length(&task->input_packet, 0);
mpp_packet_set_length(task->input_packet, 0);
return MPP_NOK;
}
mpp_mpg4_parser_setup_syntax(p->parser, task->syntax);
mpp_mpg4_parser_setup_output(p->parser, &task->output);
mpp_mpg4_parser_setup_syntax(p->parser, &task->syntax);
mpp_mpg4_parser_setup_hal_output(p->parser, &task->output);
mpp_mpg4_parser_setup_refer(p->parser, task->refer, MAX_DEC_REF_NUM);
mpp_mpg4_parser_setup_display(p->parser);
mpp_mpg4_parser_update_dpb(p->parser);
p->frame_count++;
@@ -291,6 +305,7 @@ MPP_RET mpg4d_callback(void *dec, void *err_info)
(void)err_info;
return MPP_OK;
}
const ParserApi api_mpg4d_parser = {
"api_mpg4d_parser",
MPP_VIDEO_CodingMPEG4,

1354
mpp/codec/dec/mpg4/mpg4d_parser.c
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File diff suppressed because it is too large Load Diff

16
mpp/codec/dec/mpg4/mpg4d_parser.h
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@@ -18,20 +18,15 @@
#ifndef __MPG4D_PARSER_H__
#define __MPG4D_PARSER_H__
#include "mpp_log.h"
#include "mpp_packet.h"
#include "mpp_buf_slot.h"
#include "hal_task.h"
extern RK_U32 mpg4d_debug;
#define MPG4D_DBG_FUNCTION (0x00000001)
#define MPG4D_DBG_PPS (0x00000008)
#define MPG4D_DBG_SLICE_HDR (0x00000010)
#define MPG4D_DBG_REF (0x00000080)
#define MPG4D_DBG_STARTCODE (0x00000002)
#define MPG4D_DBG_BITS (0x00000004)
#define MPG4D_DBG_TIME (0x00000100)
#define mpg4d_dbg(flag, fmt, ...) _mpp_dbg(mpg4d_debug, flag, fmt, ## __VA_ARGS__)
typedef void* Mpg4dParser;
#ifdef __cplusplus
@@ -45,10 +40,11 @@ MPP_RET mpp_mpg4_parser_reset(Mpg4dParser ctx);
MPP_RET mpp_mpg4_parser_split(Mpg4dParser ctx, MppPacket dst, MppPacket src);
MPP_RET mpp_mpg4_parser_decode(Mpg4dParser ctx, MppPacket pkt);
MPP_RET mpp_mpg4_parser_setup_syntax(Mpg4dParser ctx, MppSyntax syntax);
MPP_RET mpp_mpg4_parser_setup_output(Mpg4dParser ctx, RK_S32 *output);
MPP_RET mpp_mpg4_parser_setup_syntax(Mpg4dParser ctx, MppSyntax *syntax);
MPP_RET mpp_mpg4_parser_setup_hal_output(Mpg4dParser ctx, RK_S32 *output);
MPP_RET mpp_mpg4_parser_setup_refer(Mpg4dParser ctx, RK_S32 *refer, RK_S32 max_ref);
MPP_RET mpp_mpg4_parser_setup_display(Mpg4dParser ctx);
MPP_RET mpp_mpg4_parser_update_dpb(Mpg4dParser ctx);
MPP_RET mpp_mpg4_parser_set_pts_mode(Mpg4dParser ctx, RK_U32 use_internal_pts);
#ifdef __cplusplus
}

72
mpp/common/mpg4d_syntax.h
View File

@@ -26,6 +26,44 @@
#ifndef __MPG4D_SYNTAX__
#define __MPG4D_SYNTAX__
#include "dxva_syntax.h"
#define MPEG4_VIDOBJLAY_AR_SQUARE 1
#define MPEG4_VIDOBJLAY_AR_625TYPE_43 2
#define MPEG4_VIDOBJLAY_AR_525TYPE_43 3
#define MPEG4_VIDOBJLAY_AR_625TYPE_169 8
#define MPEG4_VIDOBJLAY_AR_525TYPE_169 9
#define MPEG4_VIDOBJLAY_AR_EXTPAR 15
#define MPEG4_VIDOBJLAY_SHAPE_RECTANGULAR 0
#define MPEG4_VIDOBJLAY_SHAPE_BINARY 1
#define MPEG4_VIDOBJLAY_SHAPE_BINARY_ONLY 2
#define MPEG4_VIDOBJLAY_SHAPE_GRAYSCALE 3
/*video sprite specific*/
#define MPEG4_SPRITE_NONE 0
#define MPEG4_SPRITE_STATIC 1
#define MPEG4_SPRITE_GMC 2
/*video vop specific*/
typedef enum {
MPEG4_RESYNC_VOP = -2,
MPEG4_INVALID_VOP = -1,
MPEG4_I_VOP = 0,
MPEG4_P_VOP = 1,
MPEG4_B_VOP = 2,
MPEG4_S_VOP = 3,
MPEG4_N_VOP = 4,
MPEG4_D_VOP = 5, /*Drop Frame*/
} MPEG4VOPType;
#define MPEG4_HDR_ERR -2
#define MPEG4_DEC_ERR -4
#define MPEG4_VLD_ERR -5
#define MPEG4_FORMAT_ERR -6
#define MPEG4_DIVX_PBBI -7
#define MPEG4_INFO_CHANGE -10
/* MPEG4PT2 Picture Parameter structure */
typedef struct _DXVA_PicParams_MPEG4_PART2 {
RK_U8 short_video_header;
@@ -81,37 +119,27 @@ typedef struct _DXVA_PicParams_MPEG4_PART2 {
RK_U16 Reserved16BitsA;
RK_U16 Reserved16BitsB;
// add by lance 2016.04.15
RK_U32 consumed_bits;
RK_U32 buf_len;
// FIXME: added for rockchip hardware information
RK_U32 custorm_version;
RK_U32 prev_coding_type;
RK_U32 time_bp;
RK_U32 time_pp;
MppBuffer q_table_buffer;
RK_S32 quarterpel;
RK_U32 version;
RK_U32 intra_dc_threshold;
RK_U32 header_bits;
} DXVA_PicParams_MPEG4_PART2, *LPDXVA_PicParams_MPEG4_PART2;
typedef struct _DXVA_QmatrixData {
RK_U8 bNewQmatrix[4]; //intra Y, inter Y, intra chroma, inter chroma
RK_U16 Qmatrix[4][64];
RK_U8 bNewQmatrix[4]; // intra Y, inter Y, intra chroma, inter chroma
RK_U8 Qmatrix[4][64]; // NOTE: here we change U16 to U8
} DXVA_QmatrixData, *LPDXVA_QmatrixData;
typedef struct _DXVA_SliceInfo {
RK_U16 wHorizontalPosition;
RK_U16 wVerticalPosition;
RK_U32 dwSliceBitsInBuffer;
RK_U32 dwSliceDataLocation;
RK_U8 bStartCodeBitOffset;
RK_U8 bReservedBits;
RK_U16 wMBbitOffset;
RK_U16 wNumberMBsInSlice;
RK_U16 wQuantizerScaleCode;
RK_U16 wBadSliceChopping;
} DXVA_SliceInfo, *LPDXVA_SliceInfo;
typedef struct mpeg4d_dxva2_picture_context {
DXVA_PicParams_MPEG4_PART2 pp;
DXVA_QmatrixData qm;
// pointer and storage for buffer descriptor
DXVA2_DecodeBufferDesc *data[3];
DXVA2_DecodeBufferDesc desc[3];
RK_U32 frame_count;
const RK_U8 *bitstream;
RK_U32 bitstream_size;

5
mpp/hal/inc/hal_mpg4d_api.h
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@@ -32,12 +32,15 @@
#include "mpp_err.h"
#include "mpp_hal.h"
#define MPG4D_HAL_DBG_REG_PUT (0x00000001)
#define MPG4D_HAL_DBG_REG_GET (0x00000002)
#ifdef __cplusplus
extern "C" {
#endif
extern RK_U32 mpg4d_hal_debug;
extern const MppHalApi hal_api_mpg4d;
MPP_RET hal_vpu_mpg4d_init(void *hal, MppHalCfg *cfg);

465
mpp/hal/vpu/mpg4d/hal_mpg4d_reg.c
View File

@@ -1,19 +1,19 @@
/*
* *
* * Copyright 2016 Rockchip Electronics Co. LTD
* *
* * Licensed under the Apache License, Version 2.0 (the "License");
* * you may not use this file except in compliance with the License.
* * You may obtain a copy of the License at
* *
* * http://www.apache.org/licenses/LICENSE-2.0
* *
* * Unless required by applicable law or agreed to in writing, software
* * distributed under the License is distributed on an "AS IS" BASIS,
* * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* * See the License for the specific language governing permissions and
* * limitations under the License.
* */
*
* Copyright 2016 Rockchip Electronics Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* @file hal_vpu_mpg4d_reg.c
@@ -36,34 +36,341 @@
#include "mpp_env.h"
#include "mpp_buffer.h"
#include "vpu.h"
#include "mpp_dec.h"
#include "mpg4d_syntax.h"
#include "vpu.h"
#include "hal_mpg4d_api.h"
#include "hal_mpg4d_reg.h"
#define MPEG4_MAX_MV_BUF_SIZE ((1920/16)*(1088/16)*sizeof(RK_U32))
typedef struct mpeg4d_reg_context {
RK_S32 vpu_fd;
MppBufSlots slots;
MppBufSlots packet_slots;
RK_S32 mpg4d_fill_quantization_matrices;
MppBufSlots frm_slots;
MppBufSlots pkt_slots;
MppBufferGroup group;
MppBuffer directMV_Addr;
int addr_init_flag;
void* hw_regs;
IOInterruptCB int_cb;
// save fd for curr/ref0/ref1 for reg_gen
RK_S32 vpu_fd;
RK_S32 fd_curr;
RK_S32 fd_ref0;
RK_S32 fd_ref1;
// mv info buffer
// NOTE: mv buffer fix to 1080p size for convenience
MppBuffer mv_buf;
MppBuffer qp_table;
VpuMpg4dRegSet_t* regs;
} hal_mpg4_ctx;
RK_U32 mpg4d_hal_debug = 0;
static RK_U8 default_intra_matrix[64] = {
8, 17, 18, 19, 21, 23, 25, 27,
17, 18, 19, 21, 23, 25, 27, 28,
20, 21, 22, 23, 24, 26, 28, 30,
21, 22, 23, 24, 26, 28, 30, 32,
22, 23, 24, 26, 28, 30, 32, 35,
23, 24, 26, 28, 30, 32, 35, 38,
25, 26, 28, 30, 32, 35, 38, 41,
27, 28, 30, 32, 35, 38, 41, 45
};
static RK_U8 default_inter_matrix[64] = {
16, 17, 18, 19, 20, 21, 22, 23,
17, 18, 19, 20, 21, 22, 23, 24,
18, 19, 20, 21, 22, 23, 24, 25,
19, 20, 21, 22, 23, 24, 26, 27,
20, 21, 22, 23, 25, 26, 27, 28,
21, 22, 23, 24, 26, 27, 28, 30,
22, 23, 24, 26, 27, 28, 30, 31,
23, 24, 25, 27, 28, 30, 31, 33
};
static void vpu_mpg4d_get_buffer_by_index(hal_mpg4_ctx *ctx, RK_S32 index, MppBuffer *buffer)
{
if (index >= 0) {
mpp_buf_slot_get_prop(ctx->frm_slots, index, SLOT_BUFFER, buffer);
mpp_assert(*buffer);
}
}
static void vpu_mpg4d_setup_regs_by_syntax(hal_mpg4_ctx *ctx, MppSyntax syntax)
{
VpuMpg4dRegSet_t *regs = ctx->regs;
DXVA2_DecodeBufferDesc **data = syntax.data;
DXVA_PicParams_MPEG4_PART2 *pp = NULL;
DXVA_QmatrixData *qm = NULL;
RK_S32 mv_buf_fd = mpp_buffer_get_fd(ctx->mv_buf);
RK_U32 stream_length = 0;
RK_U32 stream_used = 0;
RK_U32 i;
for (i = 0; i < syntax.number; i++) {
DXVA2_DecodeBufferDesc *desc = data[i];
switch (desc->CompressedBufferType) {
case DXVA2_PictureParametersBufferType : {
pp = (DXVA_PicParams_MPEG4_PART2 *)desc->pvPVPState;
} break;
case DXVA2_InverseQuantizationMatrixBufferType : {
qm = (DXVA_QmatrixData *)desc->pvPVPState;
} break;
case DXVA2_BitStreamDateBufferType : {
stream_length = desc->DataSize;
stream_used = desc->DataOffset;
} break;
default : {
mpp_err_f("found invalid buffer descriptor type %d\n", desc->CompressedBufferType);
} break;
}
}
mpp_assert(pp);
mpp_assert(qm);
mpp_assert(stream_length);
mpp_assert(stream_used);
// copy qp table to buffer
{
RK_U8 *dst = (RK_U8 *)mpp_buffer_get_ptr(ctx->qp_table);
RK_U8 *src = (qm->bNewQmatrix[0]) ? (qm->Qmatrix[0]) : (default_intra_matrix);
memcpy(dst, src, 64);
dst += 64;
src = (qm->bNewQmatrix[1]) ? (qm->Qmatrix[1]) : (default_inter_matrix);
memcpy(dst, src, 64);
}
regs->reg120.sw_pic_mb_width = (pp->vop_width + 15) >> 4;
regs->reg120.sw_pic_mb_hight_p = (pp->vop_height + 15) >> 4;
if (pp->custorm_version == 4) {
regs->reg120.sw_mb_width_off = pp->vop_width & 0xf;
regs->reg120.sw_mb_height_off = pp->vop_height & 0xf;
} else {
regs->reg120.sw_mb_width_off = 0;
regs->reg120.sw_mb_height_off = 0;
}
regs->reg53_dec_mode = 1;
regs->reg120.sw_alt_scan_e = pp->alternate_vertical_scan_flag;
regs->reg52_error_concealment.sw_startmb_x = 0;
regs->reg52_error_concealment.sw_startmb_y = 0;
regs->reg50_dec_ctrl.sw_filtering_dis = 1;
regs->reg136.sw_rounding = pp->vop_rounding_type;
regs->reg122.sw_intradc_vlc_thr = pp->intra_dc_vlc_thr;
regs->reg51_stream_info.sw_init_qp = pp->vop_quant;
regs->reg122.sw_sync_markers_en = 1;
{
/*
* update stream base address here according to consumed bit length
* 1. hardware start address has to be 64 bit align
* 2. hardware need to know which is the start bit in
* 2. pass (10bit fd + (offset << 10)) register value to kernel
*/
RK_U32 val = regs->reg64_input_stream_base;
RK_U32 consumed_bytes = stream_used >> 3;
RK_U32 consumed_bytes_align = consumed_bytes & (~0x7);
RK_U32 start_bit_offset = stream_used & 0x3F;
RK_U32 left_bytes = stream_length - consumed_bytes_align;
val += (consumed_bytes_align << 10);
regs->reg64_input_stream_base = val;
regs->reg122.sw_stream_start_word = start_bit_offset;
regs->reg51_stream_info.sw_stream_len = left_bytes;
}
regs->reg122.sw_vop_time_incr = pp->vop_time_increment_resolution;
switch (pp->vop_coding_type) {
case MPEG4_B_VOP : {
RK_U32 time_bp = pp->time_bp;
RK_U32 time_pp = pp->time_pp;
RK_U32 trb_per_trd_d0 = ((((RK_S64)(1 * time_bp + 0)) << 27) + 1 * (time_pp - 1)) / time_pp;
RK_U32 trb_per_trd_d1 = ((((RK_S64)(2 * time_bp + 1)) << 27) + 2 * (time_pp - 0)) / (2 * time_pp + 1);
RK_U32 trb_per_trd_dm1 = ((((RK_S64)(2 * time_bp - 1)) << 27) + 2 * (time_pp - 1)) / (2 * time_pp - 1);
regs->reg57_enable_ctrl.sw_pic_b_e = 1;
regs->reg57_enable_ctrl.sw_pic_inter_e = 1;
regs->reg136.sw_rounding = 0;
regs->reg131_ref0_base = 1;
mpp_assert(ctx->fd_ref1 >= 0);
if (ctx->fd_ref1 >= 0) {
regs->reg131_ref0_base = (RK_U32)ctx->fd_ref1;
regs->reg148_ref1_base = (RK_U32)ctx->fd_ref1;
} else {
regs->reg131_ref0_base = (RK_U32)ctx->fd_curr;
regs->reg148_ref1_base = (RK_U32)ctx->fd_curr;
}
mpp_assert(ctx->fd_ref0 >= 0);
if (ctx->fd_ref0 >= 0) {
regs->reg134_ref2_base = (RK_U32)ctx->fd_ref0;
regs->reg135_ref3_base = (RK_U32)ctx->fd_ref0;
} else {
regs->reg134_ref2_base = (RK_U32)ctx->fd_curr;
regs->reg135_ref3_base = (RK_U32)ctx->fd_curr;
}
regs->reg136.sw_hrz_bit_of_fwd_mv = pp->vop_fcode_forward;
regs->reg136.sw_vrz_bit_of_fwd_mv = pp->vop_fcode_forward;
regs->reg136.sw_hrz_bit_of_bwd_mv = pp->vop_fcode_backward;
regs->reg136.sw_vrz_bit_of_bwd_mv = pp->vop_fcode_backward;
regs->reg57_enable_ctrl.sw_write_mvs_e = 0;
regs->reg62_directmv_base = mv_buf_fd;
regs->reg137.sw_trb_per_trd_d0 = trb_per_trd_d0;
regs->reg139.sw_trb_per_trd_d1 = trb_per_trd_d1;
regs->reg138.sw_trb_per_trd_dm1 = trb_per_trd_dm1;
} break;
case MPEG4_P_VOP : {
regs->reg57_enable_ctrl.sw_pic_b_e = 0;
regs->reg57_enable_ctrl.sw_pic_inter_e = 1;
if (ctx->fd_ref0 >= 0) {
regs->reg131_ref0_base = (RK_U32)ctx->fd_ref0;
regs->reg148_ref1_base = (RK_U32)ctx->fd_ref0;
} else {
regs->reg131_ref0_base = (RK_U32)ctx->fd_curr;
regs->reg148_ref1_base = (RK_U32)ctx->fd_curr;
}
regs->reg136.sw_hrz_bit_of_fwd_mv = pp->vop_fcode_forward;
regs->reg136.sw_vrz_bit_of_fwd_mv = pp->vop_fcode_forward;
regs->reg57_enable_ctrl.sw_write_mvs_e = 1;
regs->reg62_directmv_base = mv_buf_fd;
} break;
case MPEG4_I_VOP : {
regs->reg57_enable_ctrl.sw_pic_b_e = 0;
regs->reg57_enable_ctrl.sw_pic_inter_e = 0;
regs->reg131_ref0_base = (RK_U32)ctx->fd_curr;
regs->reg148_ref1_base = (RK_U32)ctx->fd_curr;
regs->reg57_enable_ctrl.sw_write_mvs_e = 0;
regs->reg62_directmv_base = mv_buf_fd;
regs->reg136.sw_hrz_bit_of_fwd_mv = 1;
regs->reg136.sw_vrz_bit_of_fwd_mv = 1;
} break;
default : {
/* no nothing */
} break;
}
if (pp->interlaced) {
regs->reg57_enable_ctrl.sw_pic_interlace_e = 1;
regs->reg57_enable_ctrl.sw_pic_fieldmode_e = 0;
regs->reg120.sw_topfieldfirst_e = pp->top_field_first;
}
regs->reg136.sw_prev_pic_type = pp->prev_coding_type;
regs->reg122.sw_quant_type_1_en = pp->quant_type;
regs->reg61_qtable_base = mpp_buffer_get_fd(ctx->qp_table);
regs->reg136.sw_fwd_mv_y_resolution = pp->quarter_sample;
}
MPP_RET hal_vpu_mpg4d_init(void *hal, MppHalCfg *cfg)
{
MPP_RET ret = MPP_OK;
hal_mpg4_ctx *reg_ctx = (hal_mpg4_ctx *)hal;
VpuMpg4dRegSet_t *regs = NULL;
MppBufferGroup group = NULL;
MppBuffer mv_buf = NULL;
MppBuffer qp_table = NULL;
hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal;
RK_S32 vpu_fd = -1;
if (NULL == reg_ctx) {
mpp_err("hal instan no alloc");
return MPP_ERR_UNKNOW;
mpp_assert(hal);
ret = mpp_buffer_group_get_internal(&group, MPP_BUFFER_TYPE_ION);
if (ret) {
mpp_err_f("failed to get buffer group ret %d\n", ret);
goto ERR_RET;
}
reg_ctx->slots = cfg->frame_slots;
reg_ctx->int_cb = cfg->hal_int_cb;
reg_ctx->packet_slots = cfg->packet_slots;
ret = mpp_buffer_get(group, &mv_buf, MPEG4_MAX_MV_BUF_SIZE);
if (ret) {
mpp_err_f("failed to get mv buffer ret %d\n", ret);
goto ERR_RET;
}
ret = mpp_buffer_get(group, &qp_table, 64 * 2 * sizeof(RK_U8));
if (ret) {
mpp_err_f("failed to get qp talbe buffer ret %d\n", ret);
goto ERR_RET;
}
regs = mpp_calloc(VpuMpg4dRegSet_t, 1);
if (NULL == regs) {
mpp_err_f("failed to malloc register ret\n");
ret = MPP_ERR_MALLOC;
goto ERR_RET;
}
#ifdef RKPLATFORM
vpu_fd = VPUClientInit(VPU_DEC);
if (vpu_fd < 0) {
mpp_err_f("failed to open vpu client\n");
ret = MPP_ERR_UNKNOW;
goto ERR_RET;
}
#endif
/*
* basic register configuration setup here
*/
regs->reg54_endian.sw_dec_out_endian = 1;
regs->reg54_endian.sw_dec_in_endian = 1;
regs->reg54_endian.sw_dec_inswap32_e = 1;
regs->reg54_endian.sw_dec_outswap32_e = 1;
regs->reg54_endian.sw_dec_strswap32_e = 1;
regs->reg54_endian.sw_dec_strendian_e = 1;
regs->reg56_axi_ctrl.sw_dec_max_burst = 16;
regs->reg52_error_concealment.sw_apf_threshold = 1;
regs->reg57_enable_ctrl.sw_dec_timeout_e = 1;
regs->reg57_enable_ctrl.sw_dec_clk_gate_e = 1;
regs->reg57_enable_ctrl.sw_dec_e = 1;
regs->reg59.sw_pred_bc_tap_0_0 = -1;
regs->reg59.sw_pred_bc_tap_0_1 = 3;
regs->reg59.sw_pred_bc_tap_0_2 = -6;
regs->reg153.sw_pred_bc_tap_0_3 = 20;
ctx->frm_slots = cfg->frame_slots;
ctx->pkt_slots = cfg->packet_slots;
ctx->int_cb = cfg->hal_int_cb;
ctx->group = group;
ctx->vpu_fd = vpu_fd;
ctx->mv_buf = mv_buf;
ctx->qp_table = qp_table;
ctx->regs = regs;
mpp_env_get_u32("mpg4d_hal_debug", &mpg4d_hal_debug, 0);
return ret;
ERR_RET:
if (regs) {
mpp_free(regs);
regs = NULL;
}
if (qp_table) {
mpp_buffer_put(qp_table);
qp_table = NULL;
}
if (mv_buf) {
mpp_buffer_put(mv_buf);
mv_buf = NULL;
}
if (group) {
mpp_buffer_group_put(group);
group = NULL;
}
return ret;
}
@@ -71,7 +378,36 @@ MPP_RET hal_vpu_mpg4d_init(void *hal, MppHalCfg *cfg)
MPP_RET hal_vpu_mpg4d_deinit(void *hal)
{
MPP_RET ret = MPP_OK;
(void) hal;
hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal;
mpp_assert(hal);
if (ctx->regs) {
mpp_free(ctx->regs);
ctx->regs = NULL;
}
if (ctx->qp_table) {
mpp_buffer_put(ctx->qp_table);
ctx->qp_table = NULL;
}
if (ctx->mv_buf) {
mpp_buffer_put(ctx->mv_buf);
ctx->mv_buf = NULL;
}
if (ctx->group) {
mpp_buffer_group_put(ctx->group);
ctx->group = NULL;
}
#ifdef RKPLATFORM
if (ctx->vpu_fd >= 0) {
VPUClientRelease(ctx->vpu_fd);
ctx->vpu_fd = -1;
}
#endif
return ret;
}
@@ -79,15 +415,57 @@ MPP_RET hal_vpu_mpg4d_deinit(void *hal)
MPP_RET hal_vpu_mpg4d_gen_regs(void *hal, HalTaskInfo *syn)
{
MPP_RET ret = MPP_OK;
(void) hal;
(void) syn;
hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal;
HalDecTask *task = &syn->dec;
MppBuffer buf_frm_curr = NULL;
MppBuffer buf_frm_ref0 = NULL;
MppBuffer buf_frm_ref1 = NULL;
MppBuffer buf_pkt = NULL;
VpuMpg4dRegSet_t *regs = ctx->regs;
mpp_assert(task->valid);
mpp_assert(task->input >= 0);
mpp_assert(task->output >= 0);
/* setup buffer for input / output / reference */
mpp_buf_slot_get_prop(ctx->pkt_slots, task->input, SLOT_BUFFER, &buf_pkt);
mpp_assert(buf_pkt);
vpu_mpg4d_get_buffer_by_index(ctx, task->output, &buf_frm_curr);
vpu_mpg4d_get_buffer_by_index(ctx, task->refer[0], &buf_frm_ref0);
vpu_mpg4d_get_buffer_by_index(ctx, task->refer[1], &buf_frm_ref1);
/* address registers setup first */
ctx->fd_curr = mpp_buffer_get_fd(buf_frm_curr);
ctx->fd_ref0 = (buf_frm_ref0) ? (mpp_buffer_get_fd(buf_frm_ref0)) : (-1);
ctx->fd_ref1 = (buf_frm_ref1) ? (mpp_buffer_get_fd(buf_frm_ref1)) : (-1);
regs->reg63_cur_pic_base = (RK_U32)ctx->fd_curr;
regs->reg64_input_stream_base = mpp_buffer_get_fd(buf_pkt);
/* setup other registers, here will update packet address */
vpu_mpg4d_setup_regs_by_syntax(ctx, task->syntax);
return ret;
}
MPP_RET hal_vpu_mpg4d_start(void *hal, HalTaskInfo *task)
{
MPP_RET ret = MPP_OK;
(void)hal;
hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal;
#ifdef RKPLATFORM
RK_U32 reg_count = (sizeof(*ctx->regs) / sizeof(RK_U32));
RK_U32* regs = (RK_U32 *)ctx->regs;
if (mpg4d_hal_debug & MPG4D_HAL_DBG_REG_PUT) {
RK_U32 i = 0;
for (i = 0; i < reg_count; i++) {
mpp_log("reg[%03d]: %08x\n", i, regs[i]);
}
}
ret = VPUClientSendReg(ctx->vpu_fd, regs, reg_count);
#endif
(void)ret;
(void)task;
return ret;
}
@@ -95,8 +473,27 @@ MPP_RET hal_vpu_mpg4d_start(void *hal, HalTaskInfo *task)
MPP_RET hal_vpu_mpg4d_wait(void *hal, HalTaskInfo *task)
{
MPP_RET ret = MPP_OK;
hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal;
#ifdef RKPLATFORM
VpuMpg4dRegSet_t reg_out;
RK_U32* regs = (RK_U32 *)&reg_out;
RK_U32 reg_count = (sizeof(reg_out) / sizeof(RK_U32));
VPU_CMD_TYPE cmd = 0;
RK_S32 length = 0;
ret = VPUClientWaitResult(ctx->vpu_fd, regs, (sizeof(reg_out) / sizeof(RK_U32)),
&cmd, &length);
if (mpg4d_hal_debug & MPG4D_HAL_DBG_REG_GET) {
RK_U32 i = 0;
for (i = 0; i < reg_count; i++) {
mpp_log("reg[%03d]: %08x\n", i, regs[i]);
}
}
#endif
(void)ret;
(void)task;
(void) hal;
return ret;
}

415
mpp/hal/vpu/mpg4d/hal_mpg4d_reg.h
View File

@@ -1,35 +1,398 @@
/*
* *
* * Copyright 2016 Rockchip Electronics Co. LTD
* *
* * Licensed under the Apache License, Version 2.0 (the "License");
* * you may not use this file except in compliance with the License.
* * You may obtain a copy of the License at
* *
* * http://www.apache.org/licenses/LICENSE-2.0
* *
* * Unless required by applicable law or agreed to in writing, software
* * distributed under the License is distributed on an "AS IS" BASIS,
* * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* * See the License for the specific language governing permissions and
* * limitations under the License.
* */
/*
* @file hal_mpeg4d_reg.h
* @brief
* @author gzl(lance.gao@rock-chips.com)
* @version 1.0.0
* @history
* 2016.04.11 : Create
*/
* Copyright 2016 Rockchip Electronics Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __HAL_MPG4D_REG_H__
#define __HAL_MPG4D_REG_H__
#include "mpp_log.h"
#include "rk_type.h"
typedef struct {
RK_U32 reg00_49[50];
struct {
RK_U32 sw_dec_out_tiled_e : 1;
RK_U32 sw_dec_latency : 6;
RK_U32 sw_pic_fixed_quant : 1;
RK_U32 sw_filtering_dis : 1;
RK_U32 sw_divx_enable : 1;
RK_U32 sw_dec_scmd_dis : 1;
RK_U32 sw_dec_adv_pre_dis : 1;
RK_U32 sw_priority_mode : 1;
RK_U32 sw_refbu2_thr : 12;
RK_U32 sw_refbu2_picid : 5;
RK_U32 reserve1 : 2;
} reg50_dec_ctrl;
struct {
RK_U32 sw_stream_len : 24;
RK_U32 reserve1 : 1;
RK_U32 sw_init_qp : 6;
RK_U32 reserve2 : 1;
} reg51_stream_info;
struct {
RK_U32 sw_startmb_y : 8;
RK_U32 sw_startmb_x : 9;
RK_U32 sw_apf_threshold : 14;
RK_U32 sw_reserve : 1;
} reg52_error_concealment;
RK_U32 reg53_dec_mode;
struct {
RK_U32 sw_dec_in_endian : 1;
RK_U32 sw_dec_out_endian : 1;
RK_U32 sw_dec_inswap32_e : 1;
RK_U32 sw_dec_outswap32_e : 1;
RK_U32 sw_dec_strswap32_e : 1;
RK_U32 sw_dec_strendian_e : 1;
RK_U32 reserve3 : 26;
} reg54_endian;
struct {
RK_U32 sw_dec_irq : 1;
RK_U32 sw_dec_irq_dis : 1;
RK_U32 reserve0 : 2;
RK_U32 sw_dec_rdy_int : 1;
RK_U32 sw_dec_bus_int : 1;
RK_U32 sw_dec_buf_empty_int: 1;
RK_U32 reserve1 : 1;
RK_U32 sw_dec_aso_int : 1;
RK_U32 sw_dec_slice_int : 1;
RK_U32 sw_dec_b_pic_inf : 1;
RK_U32 reserve2 : 1;
RK_U32 sw_dec_error_int : 1;
RK_U32 sw_dec_timeout : 1;
RK_U32 reserve3 : 18;
} reg55_Interrupt;
struct {
RK_U32 sw_dec_axi_rn_id : 8;
RK_U32 sw_dec_axi_wr_id : 8;
RK_U32 sw_dec_max_burst : 5;
RK_U32 reserve0 : 1;
RK_U32 sw_dec_data_disc_e : 1;
RK_U32 reserve1 : 9;
} reg56_axi_ctrl;
struct {
RK_U32 sw_dec_e : 1;
RK_U32 sw_refbu2_buf_e : 1;
RK_U32 sw_dec_out_dis : 1;
RK_U32 reserve : 1;
RK_U32 sw_dec_clk_gate_e : 1;
RK_U32 sw_dec_timeout_e : 1;
RK_U32 sw_picord_count_e : 1;
RK_U32 sw_seq_mbaff_e : 1;
RK_U32 sw_reftopfirst_e : 1;
RK_U32 sw_ref_topfield_e : 1;
RK_U32 sw_write_mvs_e : 1;
RK_U32 sw_sorenson_e : 1;
RK_U32 sw_fwd_interlace_e : 1;
RK_U32 sw_pic_topfield_e : 1;
RK_U32 sw_pic_inter_e : 1;
RK_U32 sw_pic_b_e : 1;
RK_U32 sw_pic_fieldmode_e : 1;
RK_U32 sw_pic_interlace_e : 1;
RK_U32 sw_pjpeg_e : 1;
RK_U32 sw_divx3_e : 1;
RK_U32 sw_rlc_mode_e : 1;
RK_U32 sw_ch_8pix_ileav_e : 1;
RK_U32 sw_start_code_e : 1;
RK_U32 reserve1 : 8;
RK_U32 sw_dec_ahb_hlock_e : 1;
} reg57_enable_ctrl;
struct {
RK_U32 sw_soft_rst : 1;
RK_U32 reverse0 : 31;
} reg58;
struct {
RK_U32 reserve : 2;
RK_U32 sw_pred_bc_tap_0_2 : 10;
RK_U32 sw_pred_bc_tap_0_1 : 10;
RK_U32 sw_pred_bc_tap_0_0 : 10;
} reg59;
RK_U32 reg60_addit_ch_st_base;
RK_U32 reg61_qtable_base;
RK_U32 reg62_directmv_base;
RK_U32 reg63_cur_pic_base;
RK_U32 reg64_input_stream_base;
struct {
RK_U32 sw_refbu_y_offset : 9;
RK_U32 sw_reserve : 3;
RK_U32 sw_refbu_fparmod_e : 1;
RK_U32 sw_refbu_eval_e : 1;
RK_U32 sw_refbu_picid : 5;
RK_U32 sw_refbu_thr : 12;
RK_U32 sw_refbu_e : 1;
} reg65_refpicbuf_ctrl;
struct {
RK_U32 build_version : 3;
RK_U32 product_IDen : 1;
RK_U32 minor_version : 8;
RK_U32 major_version : 4;
RK_U32 product_numer : 16;
} reg66_id;
struct {
RK_U32 sw_reserve : 25;
RK_U32 sw_dec_rtl_rom : 1;
RK_U32 sw_dec_rv_prof : 2;
RK_U32 sw_ref_buff2_exist : 1;
RK_U32 sw_dec_divx_prof : 1;
RK_U32 sw_dec_refbu_ilace : 1;
RK_U32 sw_dec_jpeg_exten : 1;
} reg67_synthesis_cfg;
struct {
RK_U32 sw_refbu_top_sum : 16;
RK_U32 sw_refbu_bot_sum : 16;
} reg68_sum_of_partitions;
struct {
RK_U32 sw_refbu_intra_sum : 16;
RK_U32 sw_refbu_hit_sum : 16;
} reg69_sum_inf;
struct {
RK_U32 sw_refbu_mv_sum : 22;
RK_U32 sw_reserve : 10;
} reg70_sum_mv;
RK_U32 reg71_119_reserve[49];
struct {
RK_U32 sw_reserve0 : 5;
RK_U32 sw_topfieldfirst_e : 1;
RK_U32 sw_alt_scan_e : 1;
RK_U32 sw_mb_height_off : 4;
RK_U32 sw_pic_mb_hight_p : 8;
RK_U32 sw_mb_width_off : 4;
RK_U32 sw_pic_mb_width : 9;
} reg120;
struct {
RK_U32 sw_reserve : 5;
RK_U32 sw_vp7_version : 1;
RK_U32 sw_dc_match0 : 3;
RK_U32 sw_dc_match1 : 3;
RK_U32 sw_eable_bilinear : 1;
RK_U32 sw_remain_mv : 1;
RK_U32 sw_reserve1 : 6;
RK_U32 sw_dct2_start_bit : 6;
RK_U32 sw_dct1_start_bit : 6;
} reg121;
struct {
RK_U32 sw_vop_time_incr : 16;
RK_U32 sw_intradc_vlc_thr : 3;
RK_U32 sw_ch_qp_offset : 5;
RK_U32 sw_quant_type_1_en : 1;
RK_U32 sw_sync_markers_en : 1;
RK_U32 sw_stream_start_word: 6;
} reg122;
struct {
RK_U32 sw_dc_comp1 : 16;
RK_U32 sw_dc_comp0 : 16;
} reg123;
struct {
RK_U32 sw_stream1_len : 24;
RK_U32 sw_coeffs_part_am : 4;
RK_U32 sw_reserve : 4;
} reg124;
struct {
RK_U32 reserve : 2;
RK_U32 sw_pred_bc_tap_5_3 : 10;
RK_U32 sw_pred_bc_tap_5_2 : 10;
RK_U32 sw_pred_bc_tap_5_1 : 10;
} reg125;
struct {
RK_U32 reserve : 2;
RK_U32 sw_pred_bc_tap_6_2 : 10;
RK_U32 sw_pred_bc_tap_6_1 : 10;
RK_U32 sw_pred_bc_tap_6_0 : 10;
} reg126;
struct {
RK_U32 reserve : 2;
RK_U32 sw_pred_bc_tap_7_1 : 10;
RK_U32 sw_pred_bc_tap_7_0 : 10;
RK_U32 sw_pred_bc_tap_6_3 : 10;
} reg127;
struct {
RK_U32 sw_pred_tap_6_4 : 2;
RK_U32 sw_pred_tap_6_M1 : 2;
RK_U32 sw_pred_tap_4_4 : 2;
RK_U32 sw_pred_tap_4_M1 : 2;
RK_U32 sw_pred_tap_2_4 : 2;
RK_U32 sw_pred_tap_2_M1 : 2;
RK_U32 sw_pred_bc_tap_7_3 : 10;
RK_U32 sw_pred_bc_tap_7_2 : 10;
} reg128;
struct {
RK_U32 sw_filt_level_3 : 6;
RK_U32 sw_filt_level_2 : 6;
RK_U32 sw_filt_level_1 : 6;
RK_U32 sw_filt_level_0 : 6;
RK_U32 reserve : 8;
} reg129;
struct {
RK_U32 sw_quant_1 : 11;
RK_U32 sw_quant_0 : 11;
RK_U32 sw_quant_delta_1 : 5;
RK_U32 sw_quant_delta_0 : 5;
} reg130;
RK_U32 reg131_ref0_base;
struct {
RK_U32 sw_filt_mb_adj_3 : 7;
RK_U32 sw_filt_mb_adj_2 : 7;
RK_U32 sw_filt_mb_adj_1 : 7;
RK_U32 sw_filt_mb_adj_0 : 7;
RK_U32 sw_filt_sharpness : 3;
RK_U32 sw_filt_type : 1;
} reg132;
struct {
RK_U32 sw_filt_ref_adj_3 : 7;
RK_U32 sw_filt_ref_adj_2 : 7;
RK_U32 sw_filt_ref_adj_1 : 7;
RK_U32 sw_filt_ref_adj_0 : 7;
RK_U32 sw_reserve : 4;
} reg133;
RK_U32 reg134_ref2_base;
RK_U32 reg135_ref3_base;
struct {
RK_U32 sw_prev_pic_type : 1;
RK_U32 sw_rounding : 1;
RK_U32 sw_fwd_mv_y_resolution : 1;
RK_U32 sw_vrz_bit_of_bwd_mv : 4;
RK_U32 sw_hrz_bit_of_bwd_mv : 4;
RK_U32 sw_vrz_bit_of_fwd_mv : 4;
RK_U32 sw_hrz_bit_of_fwd_mv : 4;
RK_U32 sw_alt_scan : 1;
RK_U32 sw_reserve : 12;
} reg136;
struct {
RK_U32 sw_trb_per_trd_d0 : 27;
RK_U32 sw_reserve : 5;
} reg137;
struct {
RK_U32 sw_trb_per_trd_dm1 : 27;
RK_U32 sw_reserve : 5;
} reg138;
struct {
RK_U32 sw_trb_per_trd_d1 : 27;
RK_U32 sw_reserve : 5;
} reg139;
RK_U32 reg_dct_strm_base[5];
RK_U32 reg145_bitpl_ctrl_base;
RK_U32 reg_dct_strm1_base[2];
RK_U32 reg148_ref1_base;
RK_U32 reg149_segment_map_base;
struct {
RK_U32 sw_dct_start_bit_7 : 6;
RK_U32 sw_dct_start_bit_6 : 6;
RK_U32 sw_dct_start_bit_5 : 6;
RK_U32 sw_dct_start_bit_4 : 6;
RK_U32 sw_dct_start_bit_3 : 6;
RK_U32 sw_reserve : 2;
} reg150;
struct {
RK_U32 sw_quant_3 : 11;
RK_U32 sw_quant_2 : 11;
RK_U32 sw_quant_delta_3 : 5;
RK_U32 sw_quant_delta_2 : 5;
} reg151;
struct {
RK_U32 sw_quant_5 : 11;
RK_U32 sw_quant_4 : 11;
RK_U32 sw_quant_delta_4 : 5;
RK_U32 sw_reserve : 5;
} reg152;
struct {
RK_U32 reserve : 2;
RK_U32 sw_pred_bc_tap_1_1 : 10;
RK_U32 sw_pred_bc_tap_1_0 : 10;
RK_U32 sw_pred_bc_tap_0_3 : 10;
} reg153;
struct {
RK_U32 reserve : 2;
RK_U32 sw_pred_bc_tap_2_0 : 10;
RK_U32 sw_pred_bc_tap_1_3 : 10;
RK_U32 sw_pred_bc_tap_1_2 : 10;
} reg154;
struct {
RK_U32 reserve : 2;
RK_U32 sw_pred_bc_tap_2_3 : 10;
RK_U32 sw_pred_bc_tap_2_2 : 10;
RK_U32 sw_pred_bc_tap_2_1 : 10;
} reg155;
struct {
RK_U32 reserve : 2;
RK_U32 sw_pred_bc_tap_3_2 : 10;
RK_U32 sw_pred_bc_tap_3_1 : 10;
RK_U32 sw_pred_bc_tap_3_0 : 10;
} reg156;
struct {
RK_U32 reserve : 2;
RK_U32 sw_pred_bc_tap_4_1 : 10;
RK_U32 sw_pred_bc_tap_4_0 : 10;
RK_U32 sw_pred_bc_tap_3_3 : 10;
} reg157;
struct {
RK_U32 reserve : 2;
RK_U32 sw_pred_bc_tap_5_0 : 10;
RK_U32 sw_pred_bc_tap_4_3 : 10;
RK_U32 sw_pred_bc_tap_4_2 : 10;
} reg158;
} VpuMpg4dRegSet_t;
#endif

2
mpp/legacy/vpu_api_legacy.cpp
View File

@@ -354,7 +354,7 @@ RK_S32 VpuApi::control(VpuCodecContext *ctx, VPU_API_CMD cmd, void *param)
break;
}
case VPU_API_USE_PRESENT_TIME_ORDER: {
mpicmd = MPP_DEC_USE_PRESENT_TIME_ORDER;
mpicmd = MPP_DEC_SET_INTERNAL_PTS_ENABLE;
break;
}
case VPU_API_SET_DEFAULT_WIDTH_HEIGH: {

13
mpp/mpp.cpp
View File

@@ -300,9 +300,14 @@ MPP_RET Mpp::control(MpiCmd cmd, MppParam param)
mpp_dec_control(mDec, cmd, param);
break;
}
case MPP_DEC_USE_PRESENT_TIME_ORDER: {
RK_U32 flag = *((RK_U32 *)param);
mParserInternalPts = flag;
case MPP_DEC_SET_INTERNAL_PTS_ENABLE: {
if (mType == MPP_CTX_DEC &&
(mCoding == MPP_VIDEO_CodingMPEG2 ||
mCoding == MPP_VIDEO_CodingMPEG4)) {
mpp_dec_control(mDec, cmd, param);
} else {
mpp_err("type %x coding %x does not support use internal pts control\n");
}
break;
}
case MPP_DEC_SET_PARSER_SPLIT_MODE: {
@@ -328,8 +333,6 @@ MPP_RET Mpp::control(MpiCmd cmd, MppParam param)
}
break;
}
default : {
} break;
}