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[h265e]: Add h265e codec config definition

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Change-Id: I6b8816ce94830df2d2a8e4139a7aa8ef6242225d
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>
This commit is contained in:
sayon.chen
2019-12-20 14:32:23 +08:00
committed by Herman Chen
parent 50645d3175
commit d5a97b5c2f
1 changed files with 139 additions and 36 deletions
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109
inc/rk_venc_cmd.h
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@@ -165,6 +165,7 @@ typedef enum MppEncRcCfgChange_e {
typedef enum MppEncRcMode_t {
MPP_ENC_RC_MODE_VBR,
MPP_ENC_RC_MODE_CBR,
MPP_ENC_RC_MODE_FIXQP,
MPP_ENC_RC_MODE_BUTT
} MppEncRcMode;
@@ -273,6 +274,11 @@ typedef struct MppEncRcCfg_t {
* 0 - frame skip is not allow
*/
RK_S32 skip_cnt;
/*
* stat_times - the time of bitrate statistics
*/
RK_S32 stat_times;
} MppEncRcCfg;
/*
@@ -774,9 +780,81 @@ typedef enum MppEncH265CfgChange_e {
MPP_ENC_H265_CFG_DEPEND_SLICE_CHANGE = (1 << 8),
MPP_ENC_H265_CFG_CTU_CHANGE = (1 << 9),
MPP_ENC_H265_CFG_ROI_CHANGE = (1 << 10),
MPP_ENC_H265_CFG_CU_CHANGE = (1 << 11),
MPP_ENC_H265_CFG_DBLK_CHANGE = (1 << 12),
MPP_ENC_H265_CFG_SAO_CHANGE = (1 << 13),
MPP_ENC_H265_CFG_TRANS_CHANGE = (1 << 14),
MPP_ENC_H265_CFG_SLICE_CHANGE = (1 << 15),
MPP_ENC_H265_CFG_ENTROPY_CHANGE = (1 << 16),
MPP_ENC_H265_CFG_MERGE_CHANGE = (1 << 17),
MPP_ENC_H265_CFG_CHANGE_ALL = (0xFFFFFFFF),
} MppEncH265CfgChange;
typedef struct MppEncH265SliceCfg_t {
/* default value: 0, means no slice split*/
RK_U32 split_enable;
/* 0: by bits number; 1: by lcu line number*/
RK_U32 split_mode;
/*
* when splitmode is 0, this value presents bits number,
* when splitmode is 1, this value presents lcu line number
*/
RK_U32 slice_size;
RK_U32 loop_filter_across_slices_enabled_flag;
} MppEncH265SliceCfg;
typedef struct MppEncH265CuCfg_t {
RK_U32 cu32x32_en; /*default: 1 */
RK_U32 cu16x16_en; /*default: 1 */
RK_U32 cu8x8_en; /*default: 1 */
RK_U32 cu4x4_en; /*default: 1 */
// intra pred
RK_U32 constrained_intra_pred_flag; /*default: 0 */
RK_U32 strong_intra_smoothing_enabled_flag; /*INTRA_SMOOTH*/
RK_U32 pcm_enabled_flag; /*default: 0, enable ipcm*/
RK_U32 pcm_loop_filter_disabled_flag;
// inter pred
RK_U32 max_num_merge_cand;
} MppEncH265CuCfg;
typedef struct MppEncH265RefCfg_t {
RK_U32 num_lt_ref_pic; /*default: 0*/
} MppEncH265RefCfg;
typedef struct MppEncH265DblkCfg_t {
RK_U32 slice_deblocking_filter_disabled_flag; /* default value: 0. {0,1} */
RK_S32 slice_beta_offset_div2; /* default value: 0. [-6,+6] */
RK_S32 slice_tc_offset_div2; /* default value: 0. [-6,+6] */
} MppEncH265DblkCfg_t;
typedef struct MppEncH265SaoCfg_t {
RK_U32 slice_sao_luma_flag;
RK_U32 slice_sao_chroma_flag;
} MppEncH265SaoCfg;
typedef struct MppEncH265TransCfg_t {
RK_U32 transquant_bypass_enabled_flag;
RK_U32 transform_skip_enabled_flag;
RK_U32 defalut_ScalingList_enable; /* default: 0 */
RK_U32 cb_qp_offset;
RK_U32 cr_qp_offset;
} MppEncH265TransCfg;
typedef struct MppEncH265MergeCfg_t {
RK_U32 fivm_max_mrg_cnd;
RK_U32 merge_up_flag;
RK_U32 merge_left_flag;
} MppEncH265MergesCfg;
typedef struct MppEncH265EntropyCfg_t {
RK_U32 cabac_init_flag; /* default: 0 */
} MppEncH265EntropyCfg;
typedef struct MppEncH265Cfg_t {
RK_U32 change;
@@ -784,19 +862,32 @@ typedef struct MppEncH265Cfg_t {
RK_S32 profile;
RK_S32 level;
RK_S32 tier;
RK_S32 const_intra_pred; /* constraint intra prediction flag */
/* constraint intra prediction flag */
RK_S32 const_intra_pred;
RK_S32 ctu_size;
RK_S32 max_cu_size;
RK_S32 tmvp_enable;
RK_S32 amp_enable;
RK_S32 wpp_enable;
RK_S32 merge_range;
RK_S32 sao_enable;
RK_U32 num_ref;
/* quality config */
RK_S32 max_qp;
RK_S32 min_qp;
RK_S32 max_i_qp;
RK_S32 min_i_qp;
RK_S32 ip_qp_delta;
RK_S32 max_delta_qp;
RK_S32 intra_qp;
RK_S32 gop_delta_qp;
RK_S32 qp_init;
RK_S32 qp_max_step;
RK_U8 qpmax_map[8];
RK_U8 qpmin_map[8];
RK_S32 qpmap_mode;
/* intra fresh config */
RK_S32 intra_refresh_mode;
@@ -808,6 +899,15 @@ typedef struct MppEncH265Cfg_t {
RK_S32 depend_slice_mode;
RK_S32 depend_slice_arg;
MppEncH265CuCfg cu_cfg;
MppEncH265SliceCfg slice_cfg;
MppEncH265EntropyCfg entropy_cfg;
MppEncH265TransCfg trans_cfg;
MppEncH265SaoCfg sao_cfg;
MppEncH265DblkCfg_t dblk_cfg;
MppEncH265RefCfg ref_cfg;
MppEncH265MergesCfg merge_cfg;
/* extra info */
MppEncH265VuiCfg vui;
MppEncH265SeiCfg sei;
@@ -949,7 +1049,10 @@ typedef struct MppEncROIRegion_t {
RK_U16 w; /**< width of ROI rectangle */
RK_U16 h; /**< height of ROI rectangle */
RK_U16 intra; /**< flag of forced intra macroblock */
RK_U16 quality; /**< absolute qp of macroblock */
RK_U16 quality; /**< qp of macroblock */
RK_U16 qp_area_idx; /**< qp min max area select*/
RK_U8 area_map_en; /**< enable area map */
RK_U8 abs_qp_en; /**< absolute qp enable flag*/
} MppEncROIRegion;
/**
@@ -957,7 +1060,7 @@ typedef struct MppEncROIRegion_t {
*/
typedef struct MppEncROICfg_t {
RK_U32 number; /**< ROI rectangle number */
MppEncROIRegion *regions;/**< ROI parameters */
MppEncROIRegion *regions; /**< ROI parameters */
} MppEncROICfg;
/*