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feat[mpp_dec_cfg]: Add disable dpb check config

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Change-Id: Ib93948bed0547bec9b2805f9f0e73d83b56226a7
Signed-off-by: Chen Jinsen <kevin.chen@rock-chips.com>
This commit is contained in:
Chen Jinsen
2024-05-08 09:44:28 +08:00
committed by Herman Chen
parent 3cf927ef14
commit d0a06d0bed
6 changed files with 43 additions and 25 deletions
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1
inc/rk_mpi_cmd.h
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@@ -107,6 +107,7 @@ typedef enum {
MPP_DEC_SET_MAX_USE_BUFFER_SIZE,
MPP_DEC_SET_ENABLE_MVC, /* enable MVC decoding*/
MPP_DEC_GET_THUMBNAIL_FRAME_INFO, /* update thumbnail frame info to user, for MPP_FRAME_THUMBNAIL_ONLY mode */
MPP_DEC_SET_DISABLE_DPB_CHECK, /* disable dpb discontinuous check */
MPP_DEC_CMD_QUERY = CMD_MODULE_CODEC | CMD_CTX_ID_DEC | CMD_DEC_QUERY,
/* query decoder runtime information for decode stage */

3
mpp/base/mpp_dec_cfg.cpp
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@@ -124,6 +124,7 @@ public:
ENTRY(base, enable_hdr_meta, U32, RK_U32, MPP_DEC_CFG_CHANGE_ENABLE_HDR_META, base, enable_hdr_meta) \
ENTRY(base, enable_thumbnail, U32, RK_U32, MPP_DEC_CFG_CHANGE_ENABLE_THUMBNAIL, base, enable_thumbnail) \
ENTRY(base, enable_mvc, U32, RK_U32, MPP_DEC_CFG_CHANGE_ENABLE_MVC, base, enable_mvc) \
ENTRY(base, disable_dpb_chk, U32, RK_U32, MPP_DEC_CFG_CHANGE_DISABLE_DPB_CHECK, base, disable_dpb_chk) \
ENTRY(base, disable_thread, U32, RK_U32, MPP_DEC_CFG_CHANGE_DISABLE_THREAD, base, disable_thread) \
ENTRY(cb, pkt_rdy_cb, Ptr, MppExtCbFunc, MPP_DEC_CB_CFG_CHANGE_PKT_RDY, cb, pkt_rdy_cb) \
ENTRY(cb, pkt_rdy_ctx, Ptr, MppExtCbCtx, MPP_DEC_CB_CFG_CHANGE_PKT_RDY, cb, pkt_rdy_ctx) \
@@ -232,7 +233,7 @@ MppDecCfgService::MppDecCfgService() :
* NOTE: The dec_node_len is not the real node count should be allocated
* The max node count should be stream lengthg * 2 if each word is different.
*/
ret = mpp_trie_init(&trie, 334, cfg_cnt);
ret = mpp_trie_init(&trie, 340, cfg_cnt);
if (ret) {
mpp_err_f("failed to init dec cfg set trie\n");
return ;

3
mpp/codec/dec/h264/h264d_init.c
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@@ -636,6 +636,7 @@ static MPP_RET alloc_decpic(H264_SLICE_t *currSlice)
H264dVideoCtx_t *p_Vid = currSlice->p_Vid;
H264_SPS_t *active_sps = p_Vid->active_sps;
H264_DpbBuf_t *p_Dpb = currSlice->p_Dpb;
H264_DecCtx_t *p_Dec = p_Vid->p_Dec;
dec_pic = alloc_storable_picture(p_Vid, currSlice->structure);
MEM_CHECK(ret, dec_pic);
@@ -718,7 +719,9 @@ static MPP_RET alloc_decpic(H264_SLICE_t *currSlice)
dec_pic->combine_flag = get_field_dpb_combine_flag(p_Dpb->last_picture, dec_pic);
/* malloc dpb_memory */
FUN_CHECK(ret = dpb_mark_malloc(p_Vid, dec_pic));
if (!p_Dec->cfg->base.disable_dpb_chk) {
FUN_CHECK(ret = check_dpb_discontinuous(p_Vid->last_pic, dec_pic, currSlice));
}
dec_pic->mem_malloc_type = Mem_Malloc;
dec_pic->colmv_no_used_flag = 0;
p_Vid->dec_pic = dec_pic;

11
mpp/codec/mpp_dec.cpp
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@@ -142,7 +142,8 @@ MPP_RET mpp_dec_proc_cfg(MppDecImpl *dec, MpiCmd cmd, void *param)
case MPP_DEC_SET_DISABLE_ERROR :
case MPP_DEC_SET_ENABLE_DEINTERLACE :
case MPP_DEC_SET_ENABLE_FAST_PLAY :
case MPP_DEC_SET_ENABLE_MVC : {
case MPP_DEC_SET_ENABLE_MVC :
case MPP_DEC_SET_DISABLE_DPB_CHECK: {
ret = mpp_dec_set_cfg_by_cmd(&dec->cfg, cmd, param);
mpp_dec_update_cfg(dec);
dec->cfg.base.change = 0;
@@ -534,6 +535,9 @@ MPP_RET mpp_dec_set_cfg(MppDecCfgSet *dst, MppDecCfgSet *src)
if (change & MPP_DEC_CFG_CHANGE_ENABLE_MVC)
dst_base->enable_mvc = src_base->enable_mvc;
if (change & MPP_DEC_CFG_CHANGE_DISABLE_DPB_CHECK)
dst_base->disable_dpb_chk = src_base->disable_dpb_chk;
if (change & MPP_DEC_CFG_CHANGE_DISABLE_THREAD)
dst_base->disable_thread = src_base->disable_thread;
@@ -1058,6 +1062,11 @@ MPP_RET mpp_dec_set_cfg_by_cmd(MppDecCfgSet *set, MpiCmd cmd, void *param)
cfg->change |= MPP_DEC_CFG_CHANGE_ENABLE_MVC;
dec_dbg_func("enable MVC decoder %d\n", cfg->enable_mvc);
} break;
case MPP_DEC_SET_DISABLE_DPB_CHECK : {
cfg->disable_dpb_chk = (param) ? (*((RK_U32 *)param)) : (0);
cfg->change |= MPP_DEC_CFG_CHANGE_DISABLE_DPB_CHECK;
dec_dbg_func("disable dpb discontinuous check %d\n", cfg->disable_dpb_chk);
} break;
default : {
mpp_err_f("unsupported cfg update cmd %x\n", cmd);
ret = MPP_NOK;

3
mpp/inc/mpp_dec_cfg.h
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@@ -38,6 +38,8 @@ typedef enum MppDecCfgChange_e {
MPP_DEC_CFG_CHANGE_ENABLE_HDR_META = (1 << 17),
MPP_DEC_CFG_CHANGE_ENABLE_THUMBNAIL = (1 << 18),
MPP_DEC_CFG_CHANGE_ENABLE_MVC = (1 << 19),
/* disable dpb discontinuous check */
MPP_DEC_CFG_CHANGE_DISABLE_DPB_CHECK = (1 << 20),
/* reserve high bit for global config */
MPP_DEC_CFG_CHANGE_DISABLE_THREAD = (1 << 28),
@@ -77,6 +79,7 @@ typedef struct MppDecBaseCfg_t {
RK_U32 enable_hdr_meta;
RK_U32 enable_thumbnail;
RK_U32 enable_mvc;
RK_U32 disable_dpb_chk;
RK_U32 disable_thread;
} MppDecBaseCfg;

3
mpp/mpp.cpp
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@@ -1260,7 +1260,8 @@ MPP_RET Mpp::control_dec(MpiCmd cmd, MppParam param)
case MPP_DEC_SET_DISABLE_ERROR :
case MPP_DEC_SET_ENABLE_DEINTERLACE :
case MPP_DEC_SET_ENABLE_FAST_PLAY :
case MPP_DEC_SET_ENABLE_MVC: {
case MPP_DEC_SET_ENABLE_MVC :
case MPP_DEC_SET_DISABLE_DPB_CHECK: {
/*
* These control may be set before mpp_init
* When this case happen record the config and wait for decoder init