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refactor[dec]: get deocder capability via common routine

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Change-Id: I9700a2418653a6d5a9a00b4c4c13f33022d2159b
Signed-off-by: Johnson Ding <johnson.ding@rock-chips.com>
This commit is contained in:
Johnson Ding
2024-05-10 10:11:03 +08:00
committed by Herman Chen
parent a61c310163
commit ccf8f46e78
25 changed files with 33 additions and 287 deletions
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2
mpp/hal/common/av1/hal_av1d_api_v2.c
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@@ -70,6 +70,8 @@ MPP_RET hal_av1d_init(void *hal, MppHalCfg *cfg)
mpp_err("mpp_dev_init failed ret: %d\n", ret); mpp_err("mpp_dev_init failed ret: %d\n", ret);
goto __FAILED; goto __FAILED;
} }
cfg->hw_info = mpp_get_dec_hw_info_by_client_type(type);
p_hal->hw_info = cfg->hw_info;
//< get buffer group //< get buffer group
if (p_hal->buf_group == NULL) { if (p_hal->buf_group == NULL) {

1
mpp/hal/common/av1/hal_av1d_common.h
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@@ -188,6 +188,7 @@ typedef struct av1d_hal_ctx_t {
MppDev dev; MppDev dev;
void *reg_ctx; void *reg_ctx;
RK_U32 fast_mode; RK_U32 fast_mode;
const MppDecHwCap *hw_info;
} Av1dHalCtx; } Av1dHalCtx;
#endif /* __HAL_AV1D_GLOBAL_H__ */ #endif /* __HAL_AV1D_GLOBAL_H__ */

18
mpp/hal/rkdec/av1d/hal_av1d_vdpu383.c
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@@ -1381,6 +1381,7 @@ MPP_RET vdpu383_av1d_init(void *hal, MppHalCfg *cfg)
MPP_RET ret = MPP_OK; MPP_RET ret = MPP_OK;
Av1dHalCtx *p_hal = (Av1dHalCtx *)hal; Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
INP_CHECK(ret, NULL == p_hal); INP_CHECK(ret, NULL == p_hal);
(void) cfg;
FUN_CHECK(hal_av1d_alloc_res(hal)); FUN_CHECK(hal_av1d_alloc_res(hal));
@@ -1388,23 +1389,6 @@ MPP_RET vdpu383_av1d_init(void *hal, MppHalCfg *cfg)
mpp_slots_set_prop(p_hal->slots, SLOTS_VER_ALIGN, rkv_ver_align); mpp_slots_set_prop(p_hal->slots, SLOTS_VER_ALIGN, rkv_ver_align);
mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align); mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align);
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
RK_U32 i;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
}
__RETURN: __RETURN:
return MPP_OK; return MPP_OK;
__FAILED: __FAILED:

2
mpp/hal/rkdec/avs2d/hal_avs2d_api.c
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@@ -103,6 +103,8 @@ MPP_RET hal_avs2d_init(void *hal, MppHalCfg *cfg)
mpp_err("mpp_dev_init failed. ret: %d\n", ret); mpp_err("mpp_dev_init failed. ret: %d\n", ret);
return ret; return ret;
} }
cfg->hw_info = mpp_get_dec_hw_info_by_client_type(VPU_CLIENT_RKVDEC);
p_hal->hw_info = cfg->hw_info;
cfg->support_fast_mode = 1; cfg->support_fast_mode = 1;
p_hal->cfg = cfg->cfg; p_hal->cfg = cfg->cfg;

16
mpp/hal/rkdec/avs2d/hal_avs2d_rkv.c
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@@ -551,22 +551,6 @@ MPP_RET hal_avs2d_rkv_init(void *hal, MppHalCfg *cfg)
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avs2d_ver_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avs2d_ver_align);
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avs2d_len_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avs2d_len_align);
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
}
__RETURN: __RETURN:
AVS2D_HAL_TRACE("Out. ret %d", ret); AVS2D_HAL_TRACE("Out. ret %d", ret);
(void)cfg; (void)cfg;

17
mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c
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@@ -618,23 +618,6 @@ MPP_RET hal_avs2d_vdpu382_init(void *hal, MppHalCfg *cfg)
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avs2d_ver_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avs2d_ver_align);
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avs2d_len_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avs2d_len_align);
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
p_hal->hw_info = hw_info;
}
__RETURN: __RETURN:
AVS2D_HAL_TRACE("Out. ret %d", ret); AVS2D_HAL_TRACE("Out. ret %d", ret);
(void)cfg; (void)cfg;

16
mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c
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@@ -513,22 +513,6 @@ MPP_RET hal_avs2d_vdpu383_init(void *hal, MppHalCfg *cfg)
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avs2d_ver_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avs2d_ver_align);
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avs2d_len_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avs2d_len_align);
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
}
__RETURN: __RETURN:
AVS2D_HAL_TRACE("Out. ret %d", ret); AVS2D_HAL_TRACE("Out. ret %d", ret);
(void)cfg; (void)cfg;

2
mpp/hal/rkdec/h264d/hal_h264d_api.c
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@@ -329,6 +329,8 @@ MPP_RET hal_h264d_init(void *hal, MppHalCfg *cfg)
mpp_err("mpp_dev_init failed ret: %d\n", ret); mpp_err("mpp_dev_init failed ret: %d\n", ret);
goto __FAILED; goto __FAILED;
} }
cfg->hw_info = mpp_get_dec_hw_info_by_client_type(client_type);
p_hal->hw_info = cfg->hw_info;
//!< callback function to parser module //!< callback function to parser module
p_hal->dec_cb = cfg->dec_cb; p_hal->dec_cb = cfg->dec_cb;

16
mpp/hal/rkdec/h264d/hal_h264d_rkv_reg.c
View File

@@ -583,22 +583,6 @@ MPP_RET rkv_h264d_init(void *hal, MppHalCfg *cfg)
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align);
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align);
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
}
(void)cfg; (void)cfg;
__RETURN: __RETURN:
return MPP_OK; return MPP_OK;

18
mpp/hal/rkdec/h264d/hal_h264d_vdpu1.c
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@@ -743,6 +743,7 @@ MPP_RET vdpu1_h264d_init(void *hal, MppHalCfg *cfg)
MPP_RET ret = MPP_ERR_UNKNOW; MPP_RET ret = MPP_ERR_UNKNOW;
H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
INP_CHECK(ret, NULL == hal); INP_CHECK(ret, NULL == hal);
(void) cfg;
//!< malloc init registers //!< malloc init registers
MEM_CHECK(ret, p_hal->priv = MEM_CHECK(ret, p_hal->priv =
@@ -777,23 +778,6 @@ MPP_RET vdpu1_h264d_init(void *hal, MppHalCfg *cfg)
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, vdpu_hor_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, vdpu_hor_align);
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, vdpu_ver_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, vdpu_ver_align);
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
RK_U32 i;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_VDPU1) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
}
__RETURN: __RETURN:
return MPP_OK; return MPP_OK;
__FAILED: __FAILED:

18
mpp/hal/rkdec/h264d/hal_h264d_vdpu2.c
View File

@@ -802,6 +802,7 @@ MPP_RET vdpu2_h264d_init(void *hal, MppHalCfg *cfg)
MPP_RET ret = MPP_ERR_UNKNOW; MPP_RET ret = MPP_ERR_UNKNOW;
H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
INP_CHECK(ret, NULL == hal); INP_CHECK(ret, NULL == hal);
(void) cfg;
MEM_CHECK(ret, p_hal->priv = mpp_calloc_size(void, MEM_CHECK(ret, p_hal->priv = mpp_calloc_size(void,
sizeof(H264dVdpuPriv_t))); sizeof(H264dVdpuPriv_t)));
@@ -835,23 +836,6 @@ MPP_RET vdpu2_h264d_init(void *hal, MppHalCfg *cfg)
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, vdpu_hor_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, vdpu_hor_align);
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, vdpu_ver_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, vdpu_ver_align);
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
RK_U32 i;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_VDPU2) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
}
__RETURN: __RETURN:
return MPP_OK; return MPP_OK;
__FAILED: __FAILED:

15
mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c
View File

@@ -747,21 +747,6 @@ MPP_RET vdpu34x_h264d_init(void *hal, MppHalCfg *cfg)
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align);
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align);
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
}
if (cfg->hal_fbc_adj_cfg) { if (cfg->hal_fbc_adj_cfg) {
cfg->hal_fbc_adj_cfg->func = vdpu34x_afbc_align_calc; cfg->hal_fbc_adj_cfg->func = vdpu34x_afbc_align_calc;
cfg->hal_fbc_adj_cfg->expand = 16; cfg->hal_fbc_adj_cfg->expand = 16;

18
mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c
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@@ -768,24 +768,6 @@ MPP_RET vdpu382_h264d_init(void *hal, MppHalCfg *cfg)
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align);
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align);
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
p_hal->hw_info = hw_info;
}
{ {
/* check kernel support err ref hack process */ /* check kernel support err ref hack process */
const MppServiceCmdCap *cap = mpp_get_mpp_service_cmd_cap(); const MppServiceCmdCap *cap = mpp_get_mpp_service_cmd_cap();

17
mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c
View File

@@ -632,6 +632,7 @@ MPP_RET vdpu383_h264d_init(void *hal, MppHalCfg *cfg)
H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal; H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
INP_CHECK(ret, NULL == p_hal); INP_CHECK(ret, NULL == p_hal);
(void) cfg;
MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu383H264dRegCtx))); MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu383H264dRegCtx)));
Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx; Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
@@ -670,22 +671,6 @@ MPP_RET vdpu383_h264d_init(void *hal, MppHalCfg *cfg)
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align);
mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align); mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align);
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
}
__RETURN: __RETURN:
return MPP_OK; return MPP_OK;
__FAILED: __FAILED:

2
mpp/hal/rkdec/h265d/hal_h265d_api.c
View File

@@ -54,6 +54,8 @@ MPP_RET hal_h265d_init(void *ctx, MppHalCfg *cfg)
mpp_err("mpp_dev_init failed ret: %d\n", ret); mpp_err("mpp_dev_init failed ret: %d\n", ret);
return ret; return ret;
} }
cfg->hw_info = mpp_get_dec_hw_info_by_client_type(client_type);
p->hw_info = cfg->hw_info;
hw_id = mpp_get_client_hw_id(client_type); hw_id = mpp_get_client_hw_id(client_type);
p->dev = cfg->dev; p->dev = cfg->dev;

19
mpp/hal/rkdec/h265d/hal_h265d_rkv.c
View File

@@ -210,25 +210,6 @@ MPP_RET hal_h265d_rkv_init(void *hal, MppHalCfg *cfg)
return ret; return ret;
} }
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
RK_U32 i = 0;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && ( info->dec_caps[i]->type == VPU_CLIENT_RKVDEC ||
info->dec_caps[i]->type == VPU_CLIENT_HEVC_DEC)) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
}
#ifdef dump #ifdef dump
fp = fopen("/data/hal.bin", "wb"); fp = fopen("/data/hal.bin", "wb");
#endif #endif

17
mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
View File

@@ -159,23 +159,6 @@ static MPP_RET hal_h265d_vdpu34x_init(void *hal, MppHalCfg *cfg)
return ret; return ret;
} }
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
RK_U32 i;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
}
if (cfg->hal_fbc_adj_cfg) { if (cfg->hal_fbc_adj_cfg) {
cfg->hal_fbc_adj_cfg->func = vdpu34x_afbc_align_calc; cfg->hal_fbc_adj_cfg->func = vdpu34x_afbc_align_calc;
cfg->hal_fbc_adj_cfg->expand = 16; cfg->hal_fbc_adj_cfg->expand = 16;

20
mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c
View File

@@ -159,26 +159,6 @@ static MPP_RET hal_h265d_vdpu382_init(void *hal, MppHalCfg *cfg)
return ret; return ret;
} }
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
RK_U32 i;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
//save hw_info to context
reg_ctx->hw_info = hw_info;
}
if (cfg->hal_fbc_adj_cfg) { if (cfg->hal_fbc_adj_cfg) {
cfg->hal_fbc_adj_cfg->func = vdpu382_afbc_align_calc; cfg->hal_fbc_adj_cfg->func = vdpu382_afbc_align_calc;
cfg->hal_fbc_adj_cfg->expand = 16; cfg->hal_fbc_adj_cfg->expand = 16;

17
mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c
View File

@@ -173,23 +173,6 @@ static MPP_RET hal_h265d_vdpu383_init(void *hal, MppHalCfg *cfg)
return ret; return ret;
} }
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
RK_U32 i;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
}
(void) cfg; (void) cfg;
return MPP_OK; return MPP_OK;
} }

2
mpp/hal/rkdec/vp9d/hal_vp9d_api.c
View File

@@ -42,6 +42,8 @@ MPP_RET hal_vp9d_init(void *ctx, MppHalCfg *cfg)
mpp_err("mpp_dev_init failed ret: %d\n", ret); mpp_err("mpp_dev_init failed ret: %d\n", ret);
return ret; return ret;
} }
cfg->hw_info = mpp_get_dec_hw_info_by_client_type(client_type);
p->hw_info = cfg->hw_info;
hw_id = mpp_get_client_hw_id(client_type); hw_id = mpp_get_client_hw_id(client_type);
p->dev = cfg->dev; p->dev = cfg->dev;

16
mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c
View File

@@ -258,22 +258,6 @@ static MPP_RET hal_vp9d_vdpu34x_init(void *hal, MppHalCfg *cfg)
} }
hw_ctx->last_segid_flag = 1; hw_ctx->last_segid_flag = 1;
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
RK_U32 i;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
}
if (cfg->hal_fbc_adj_cfg) { if (cfg->hal_fbc_adj_cfg) {
cfg->hal_fbc_adj_cfg->func = vdpu34x_afbc_align_calc; cfg->hal_fbc_adj_cfg->func = vdpu34x_afbc_align_calc;

17
mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.c
View File

@@ -259,23 +259,6 @@ static MPP_RET hal_vp9d_vdpu382_init(void *hal, MppHalCfg *cfg)
} }
hw_ctx->last_segid_flag = 1; hw_ctx->last_segid_flag = 1;
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
RK_U32 i;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
p_hal->hw_info = hw_info;
}
if (cfg->hal_fbc_adj_cfg) { if (cfg->hal_fbc_adj_cfg) {
cfg->hal_fbc_adj_cfg->func = vdpu382_afbc_align_calc; cfg->hal_fbc_adj_cfg->func = vdpu382_afbc_align_calc;

17
mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c
View File

@@ -341,6 +341,7 @@ static MPP_RET hal_vp9d_vdpu383_init(void *hal, MppHalCfg *cfg)
HalVp9dCtx *p_hal = (HalVp9dCtx*)hal; HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
MEM_CHECK(ret, p_hal->hw_ctx = mpp_calloc_size(void, sizeof(Vdpu383Vp9dCtx))); MEM_CHECK(ret, p_hal->hw_ctx = mpp_calloc_size(void, sizeof(Vdpu383Vp9dCtx)));
Vdpu383Vp9dCtx *hw_ctx = (Vdpu383Vp9dCtx*)p_hal->hw_ctx; Vdpu383Vp9dCtx *hw_ctx = (Vdpu383Vp9dCtx*)p_hal->hw_ctx;
(void) cfg;
hw_ctx->mv_base_addr = -1; hw_ctx->mv_base_addr = -1;
hw_ctx->pre_mv_base_addr = -1; hw_ctx->pre_mv_base_addr = -1;
@@ -362,22 +363,6 @@ static MPP_RET hal_vp9d_vdpu383_init(void *hal, MppHalCfg *cfg)
} }
hw_ctx->last_segid_flag = 1; hw_ctx->last_segid_flag = 1;
{
// report hw_info to parser
const MppSocInfo *info = mpp_get_soc_info();
const void *hw_info = NULL;
RK_U32 i;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
hw_info = info->dec_caps[i];
break;
}
}
mpp_assert(hw_info);
cfg->hw_info = hw_info;
}
return ret; return ret;
__FAILED: __FAILED:

1
osal/inc/mpp_soc.h
View File

@@ -103,6 +103,7 @@ RockchipSocType mpp_get_soc_type(void);
const MppSocInfo *mpp_get_soc_info(void); const MppSocInfo *mpp_get_soc_info(void);
RK_U32 mpp_check_soc_cap(MppCtxType type, MppCodingType coding); RK_U32 mpp_check_soc_cap(MppCtxType type, MppCodingType coding);
const MppDecHwCap* mpp_get_dec_hw_info_by_client_type(MppClientType client_type);
#ifdef __cplusplus #ifdef __cplusplus
} }

16
osal/mpp_soc.cpp
View File

@@ -1135,3 +1135,19 @@ RK_U32 mpp_check_soc_cap(MppCtxType type, MppCodingType coding)
return is_valid_cap_coding(cap, coding); return is_valid_cap_coding(cap, coding);
} }
const MppDecHwCap* mpp_get_dec_hw_info_by_client_type(MppClientType client_type)
{
const MppDecHwCap* hw_info = NULL;
const MppSocInfo *info = mpp_get_soc_info();
RK_U32 i = 0;
for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
if (info->dec_caps[i] && info->dec_caps[i]->type == client_type) {
hw_info = info->dec_caps[i];
break;
}
}
return hw_info;
}