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[jpege/h264e]: fix RGB encode config

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Change-Id: Iec9d928ad6fb1a31cbf6f224b264ebb6797294a3
Signed-off-by: Johnson Ding <johnson.ding@rock-chips.com>
This commit is contained in:
Johnson Ding
2020-06-16 11:18:48 +08:00
parent 4a61fda3cb
commit cba637c3f1
22 changed files with 355 additions and 421 deletions
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3
inc/mpp_frame.h
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@@ -168,6 +168,8 @@ typedef enum {
#define MPP_FRAME_FBC_NONE (0x00000000)
#define MPP_FRAME_FBC_AFBC_V1 (0x00100000)
#define MPP_FRAME_FMT_LE_MASK (0x01000000)
#define MPP_FRAME_FMT_IS_YUV(fmt) (((fmt & MPP_FRAME_FMT_COLOR_MASK) == MPP_FRAME_FMT_YUV) && \
((fmt & MPP_FRAME_FMT_MASK) < MPP_FMT_YUV_BUTT))
#define MPP_FRAME_FMT_IS_RGB(fmt) (((fmt & MPP_FRAME_FMT_COLOR_MASK) == MPP_FRAME_FMT_RGB) && \
@@ -178,6 +180,7 @@ typedef enum {
*/
#define MPP_FRAME_FMT_IS_FBC(fmt) (fmt & MPP_FRAME_FBC_MASK)
#define MPP_FRAME_FMT_IS_LE(fmt) ((fmt & MPP_FRAME_FMT_LE_MASK) == MPP_FRAME_FMT_LE_MASK)
/* mpp color format index definition */
typedef enum {

16
mpp/codec/enc/jpeg/jpege_api_v2.c
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@@ -108,6 +108,7 @@ static MPP_RET jpege_proc_prep_cfg(MppEncPrepCfg *dst, MppEncPrepCfg *src)
{
MPP_RET ret = MPP_OK;
RK_U32 change = src->change;
MppFrameFormat fmt = dst->format & MPP_FRAME_FMT_MASK;
mpp_assert(change);
if (change) {
@@ -143,13 +144,14 @@ static MPP_RET jpege_proc_prep_cfg(MppEncPrepCfg *dst, MppEncPrepCfg *src)
ret = MPP_NOK;
}
if (dst->format != MPP_FMT_YUV420SP &&
dst->format != MPP_FMT_YUV420P &&
dst->format != MPP_FMT_YUV422SP_VU &&
dst->format != MPP_FMT_YUV422_YUYV &&
dst->format != MPP_FMT_YUV422_UYVY &&
dst->format != MPP_FMT_RGB888 &&
dst->format != MPP_FMT_BGR888) {
if ((fmt != MPP_FMT_YUV420SP &&
fmt != MPP_FMT_YUV420P &&
fmt != MPP_FMT_YUV422SP_VU &&
fmt != MPP_FMT_YUV422_YUYV &&
fmt != MPP_FMT_YUV422_UYVY &&
fmt < MPP_FRAME_FMT_RGB) ||
fmt == MPP_FMT_RGB888 ||
fmt == MPP_FMT_BGR888) {
mpp_err_f("invalid format %d is not supportted\n", dst->format);
ret = MPP_NOK;
}

2
mpp/hal/vpu/CMakeLists.txt
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@@ -1,5 +1,7 @@
# vim: syntax=cmake
add_subdirectory(common)
if( HAVE_H263D )
add_subdirectory(h263d)
endif()

10
mpp/hal/vpu/common/CMakeLists.txt Normal file
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@@ -0,0 +1,10 @@
# vim: syntax=cmake
include_directories(.)
# hal vepu541 common module
add_library(hal_vepu_common STATIC
vepu_common.c vepu_common.h
)
target_link_libraries(hal_vepu_common mpp_base)
set_target_properties(hal_vepu_common PROPERTIES FOLDER "mpp/hal")

138
mpp/hal/vpu/common/vepu_common.c Normal file
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@@ -0,0 +1,138 @@
/*
* Copyright 2015 Rockchip Electronics Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#define MODULE_TAG "vepu_common"
#include <string.h>
#include "mpp_log.h"
#include "mpp_mem.h"
#include "mpp_common.h"
#include "mpp_frame.h"
#include "vepu_common.h"
static VepuFormatCfg vepu_yuv_cfg[MPP_FMT_YUV_BUTT] = {
//MPP_FMT_YUV420SP
{ .format = VEPU_FMT_YUV420SEMIPLANAR, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_YUV420SP_10BIT
{ .format = VEPU_FMT_BUTT, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_YUV422SP
{ .format = VEPU_FMT_BUTT, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_YUV422SP_10BIT
{ .format = VEPU_FMT_BUTT, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_YUV420P
{ .format = VEPU_FMT_YUV420PLANAR, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_YUV420SP_VU
{ .format = VEPU_FMT_BUTT, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_YUV422P
{ .format = VEPU_FMT_BUTT, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_YUV422SP_VU
{ .format = VEPU_FMT_BUTT, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_YUV422_YUYV
{ .format = VEPU_FMT_YUYV422INTERLEAVED, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_YUV422_YVYU
{ .format = VEPU_FMT_BUTT, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_YUV422_UYVY
{ .format = VEPU_FMT_UYVY422INTERLEAVED, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_YUV422_VYUY
{ .format = VEPU_FMT_BUTT, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_YUV400
{ .format = VEPU_FMT_BUTT, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_YUV440SP
{ .format = VEPU_FMT_BUTT, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_YUV411SP
{ .format = VEPU_FMT_BUTT, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_YUV444SP
{ .format = VEPU_FMT_BUTT, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
};
static VepuFormatCfg vepu_rgb_cfg[MPP_FMT_RGB_BUTT - MPP_FRAME_FMT_RGB] = {
//MPP_FMT_RGB565, ffmpeg: rgb565be, bin(rrrr,rggg,gggb,bbbb) mem MSB-->LSB(gggb,bbbb,rrrr,rggg)
{ .format = VEPU_FMT_RGB565, .r_mask = 15, .g_mask = 10, .b_mask = 4, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_BGR565, ffmpeg: bgr565be, bin(bbbb,bggg,gggr,rrrr) mem MSB-->LSB(gggr,rrrr,bbbb,bggg)
{ .format = VEPU_FMT_RGB565, .r_mask = 4, .g_mask = 10, .b_mask = 15, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_RGB555, ffmpeg: rgb555be, bin(0rrr,rrgg,gggb,bbbb) mem MSB-->LSB(gggb,bbbb,0rrr,rrgg)
{ .format = VEPU_FMT_RGB555, .r_mask = 14, .g_mask = 9, .b_mask = 4, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_BGR555, ffmpeg: bgr555be, bin(0bbb,bbgg,gggr,rrrr) mem MSB-->LSB(gggr,rrrr,0bbb,bbgg)
{ .format = VEPU_FMT_RGB555, .r_mask = 4, .g_mask = 9, .b_mask = 14, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_RGB444, ffmpeg: rgb444be, bin(0000,rrrr,gggg,bbbb)
{ .format = VEPU_FMT_RGB444, .r_mask = 11, .g_mask = 7, .b_mask = 3, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_BGR444, ffmpeg: bgr444be, bin(0000,bbbb,gggg,rrrr)
{ .format = VEPU_FMT_RGB444, .r_mask = 3, .g_mask = 7, .b_mask = 11, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_RGB888, ffmpeg: rgb24, bin(rrrr,rrrr,gggg,gggg,bbbb,bbbb)
{ .format = VEPU_FMT_BUTT, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 0, .swap_16_in = 0, .swap_32_in = 0, },
//MPP_FMT_BGR888, ffmpeg: bgr24, bin(bbbb,bbbb,gggg,gggg,rrrr,rrrr)
{ .format = VEPU_FMT_BUTT, .r_mask = 0, .g_mask = 0, .b_mask = 0, .swap_8_in = 0, .swap_16_in = 0, .swap_32_in = 0, },
//MPP_FMT_RGB101010, bin(00rr,rrrr,rrrr,gggg,gggg,ggbb,bbbb,bbbb)
{ .format = VEPU_FMT_RGB101010, .r_mask = 29, .g_mask = 19, .b_mask = 9, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_BGR101010, bin(00bb,bbbb,bbbb,gggg,gggg,ggrr,rrrr,rrrr)
{ .format = VEPU_FMT_RGB101010, .r_mask = 9, .g_mask = 19, .b_mask = 29, .swap_8_in = 1, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_ARGB8888, argb, bin(aaaa,aaaa,rrrr,rrrr,gggg,gggg,bbbb,bbbb)
{ .format = VEPU_FMT_RGB888, .r_mask = 15, .g_mask = 23, .b_mask = 31, .swap_8_in = 0, .swap_16_in = 0, .swap_32_in = 1, },
//MPP_FMT_ABGR8888, ffmepg: rgba, bin(aaaa,aaaa,bbbb,bbbb,gggg,gggg,rrrr,rrrr)
{ .format = VEPU_FMT_RGB888, .r_mask = 31, .g_mask = 23, .b_mask = 15, .swap_8_in = 0, .swap_16_in = 0, .swap_32_in = 1, },
//MPP_FMT_BGRA8888, ffmpeg: bgra, bin(bbbb,bbbb,gggg,gggg,rrrr,rrrr,aaaa,aaaa)
{ .format = VEPU_FMT_RGB888, .r_mask = 23, .g_mask = 15, .b_mask = 7, .swap_8_in = 0, .swap_16_in = 0, .swap_32_in = 1, },
//MPP_FMT_RGBA8888, ffmpeg: rgba, bin(rrrr,rrrr,gggg,gggg,bbbb,bbbb,aaaa,aaaa)
{ .format = VEPU_FMT_RGB888, .r_mask = 7, .g_mask = 15, .b_mask = 23, .swap_8_in = 0, .swap_16_in = 0, .swap_32_in = 1, },
};
static VepuFormatCfg vepu_rgb_le_cfg[MPP_FMT_RGB_BUTT - MPP_FRAME_FMT_RGB] = {
//for little endian format
//MPP_FMT_RGB565LE, ffmpeg: rgb565le, bin(gggb,bbbb,rrrr,rggg)
{ .format = VEPU_FMT_RGB565, .r_mask = 15, .g_mask = 10, .b_mask = 4, .swap_8_in = 0, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_BGR565LE, ffmpeg: bgr565le, bin(gggr,rrrr,bbbb,bggg)
{ .format = VEPU_FMT_RGB565, .r_mask = 4, .g_mask = 10, .b_mask = 15, .swap_8_in = 0, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_RGB555LE, ffmpeg: rgb555le, bin(gggb,bbbb,0rrr,rrgg)
{ .format = VEPU_FMT_RGB555, .r_mask = 14, .g_mask = 9, .b_mask = 4, .swap_8_in = 0, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_BGR555LE, ffmpeg: bgr555le, bin(gggr,rrrr,0bbb,bbgg)
{ .format = VEPU_FMT_RGB555, .r_mask = 4, .g_mask = 9, .b_mask = 14, .swap_8_in = 0, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_RGB444LE, ffmpeg: rgb444le, bin(gggg,bbbb,0000,rrrr)
{ .format = VEPU_FMT_RGB444, .r_mask = 11, .g_mask = 7, .b_mask = 3, .swap_8_in = 0, .swap_16_in = 1, .swap_32_in = 1, },
//MPP_FMT_BGR444LE, ffmpeg: bgr444le, bin(gggg,rrrr,0000,bbbb)
{ .format = VEPU_FMT_RGB444, .r_mask = 3, .g_mask = 7, .b_mask = 11, .swap_8_in = 0, .swap_16_in = 1, .swap_32_in = 1, },
};
MPP_RET get_vepu_fmt(VepuFormatCfg *cfg, MppFrameFormat format)
{
VepuFormatCfg *fmt_cfg = NULL;
MPP_RET ret = MPP_OK;
if (MPP_FRAME_FMT_IS_FBC(format)) {
mpp_err_f("unsupport frame format %x\n", format);
} else if (MPP_FRAME_FMT_IS_YUV(format)) {
if (!MPP_FRAME_FMT_IS_LE(format))
fmt_cfg = &vepu_yuv_cfg[format - MPP_FRAME_FMT_YUV];
} else if (MPP_FRAME_FMT_IS_RGB(format)) {
if (MPP_FRAME_FMT_IS_LE(format)) {
fmt_cfg = &vepu_rgb_le_cfg[(format & MPP_FRAME_FMT_MASK) - MPP_FRAME_FMT_RGB];
} else
fmt_cfg = &vepu_rgb_cfg[format - MPP_FRAME_FMT_RGB];
} else {
memset(cfg, 0, sizeof(*cfg));
cfg->format = VEPU_FMT_BUTT;
}
if (fmt_cfg && fmt_cfg->format != VEPU_FMT_BUTT) {
memcpy(cfg, fmt_cfg, sizeof(*cfg));
} else {
mpp_err_f("unsupport frame format %x\n", format);
cfg->format = VEPU_FMT_BUTT;
ret = MPP_NOK;
}
return ret;
}

46
mpp/hal/vpu/common/vepu_common.h Normal file
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@@ -0,0 +1,46 @@
/*
* Copyright 2015 Rockchip Electronics Co. LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __VEPU_COMMON_H__
#define __VEPU_COMMON_H__
#include "mpp_frame.h"
typedef enum VepuFormat_e {
VEPU_FMT_YUV420PLANAR, //0
VEPU_FMT_YUV420SEMIPLANAR, //1
VEPU_FMT_YUYV422INTERLEAVED, //2
VEPU_FMT_UYVY422INTERLEAVED, //3
VEPU_FMT_RGB565, //4
VEPU_FMT_RGB555, //5
VEPU_FMT_RGB444, //6
VEPU_FMT_RGB888, //7
VEPU_FMT_RGB101010, //8
VEPU_FMT_BUTT, //9
} VepuFmt;
typedef struct VepuFormatCfg_t {
VepuFmt format;
RK_U8 r_mask;
RK_U8 g_mask;
RK_U8 b_mask;
RK_U8 swap_8_in;
RK_U8 swap_16_in;
RK_U8 swap_32_in;
} VepuFormatCfg;
MPP_RET get_vepu_fmt(VepuFormatCfg *cfg, MppFrameFormat format);
#endif

3
mpp/hal/vpu/h264e/CMakeLists.txt
View File

@@ -2,6 +2,7 @@
include_directories(.)
include_directories(../../common/h264/)
include_directories(../../../codec/enc/h264/)
include_directories(../common/)
# hal h264 header
set(HAL_H264E_HDR
@@ -25,5 +26,5 @@ add_library(hal_h264e_vpu STATIC
${HAL_H264E_SRC}
)
target_link_libraries(hal_h264e_vpu hal_h264e ${CODEC_H264E})
target_link_libraries(hal_h264e_vpu hal_h264e hal_vepu_common ${CODEC_H264E})
set_target_properties(hal_h264e_vpu PROPERTIES FOLDER "mpp/hal")

3
mpp/hal/vpu/h264e/hal_h264e_vepu1_reg_tbl.h
View File

@@ -37,6 +37,7 @@
#define VEPU_REG_AXI_CTRL_READ_ID(x) (((x) & 0xff) << 16)
#define VEPU_REG_OUTPUT_SWAP16 BIT(15)
#define VEPU_REG_INPUT_SWAP16 BIT(14)
#define VEPU_REG_INPUT_SWAP16_(x) (((x) & 1) << 14)
#define VEPU_REG_AXI_CTRL_BURST_LEN(x) (((x) & 0x3f) << 8)
#define VEPU_REG_AXI_CTRL_BURST_DISABLE BIT(7)
#define VEPU_REG_AXI_CTRL_INCREMENT_MODE BIT(6)
@@ -44,8 +45,10 @@
#define VEPU_REG_CLK_GATING_EN BIT(4)
#define VEPU_REG_OUTPUT_SWAP32 BIT(3)
#define VEPU_REG_INPUT_SWAP32 BIT(2)
#define VEPU_REG_INPUT_SWAP32_(x) (((x) & 1) << 2)
#define VEPU_REG_OUTPUT_SWAP8 BIT(1)
#define VEPU_REG_INPUT_SWAP8 BIT(0)
#define VEPU_REG_INPUT_SWAP8_(x) ((x) & 1)
#define VEPU_REG_ADDR_OUTPUT_STREAM 0x014
#define VEPU_REG_ADDR_OUTPUT_CTRL 0x018

7
mpp/hal/vpu/h264e/hal_h264e_vepu1_v2.c
View File

@@ -26,6 +26,7 @@
#include "mpp_rc.h"
#include "mpp_enc_hal.h"
#include "vepu_common.h"
#include "h264e_debug.h"
#include "h264e_syntax_new.h"
#include "h264e_slice.h"
@@ -324,12 +325,12 @@ static MPP_RET hal_h264e_vepu1_gen_regs_v2(void *hal, HalEncTask *task)
val = VEPU_REG_AXI_CTRL_WRITE_ID(0)
| VEPU_REG_AXI_CTRL_READ_ID(0)
| VEPU_REG_OUTPUT_SWAP16
| VEPU_REG_INPUT_SWAP16
| VEPU_REG_INPUT_SWAP16_(hw_prep->swap_16_in)
| VEPU_REG_AXI_CTRL_BURST_LEN(16)
| VEPU_REG_OUTPUT_SWAP32
| VEPU_REG_INPUT_SWAP32
| VEPU_REG_INPUT_SWAP32_(hw_prep->swap_32_in)
| VEPU_REG_OUTPUT_SWAP8
| VEPU_REG_INPUT_SWAP8;
| VEPU_REG_INPUT_SWAP8_(hw_prep->swap_8_in);
H264E_HAL_SET_REG(reg, VEPU_REG_AXI_CTRL, val);
val = VEPU_REG_MAD_QP_ADJUSTMENT (hw_mbrc->mad_qp_change)

3
mpp/hal/vpu/h264e/hal_h264e_vepu2_reg_tbl.h
View File

@@ -274,8 +274,11 @@
#define VEPU_REG_MB_CNT_SET(x) (((x) & 0xffff) << 0)
#define VEPU_REG_DATA_ENDIAN 0x1a4
#define VEPU_REG_INPUT_SWAP8 BIT(31)
#define VEPU_REG_INPUT_SWAP8_(x) (((x) & 1) << 31)
#define VEPU_REG_INPUT_SWAP16 BIT(30)
#define VEPU_REG_INPUT_SWAP16_(x) (((x) & 1) << 30)
#define VEPU_REG_INPUT_SWAP32 BIT(29)
#define VEPU_REG_INPUT_SWAP32_(x) (((x) & 1) << 29)
#define VEPU_REG_OUTPUT_SWAP8 BIT(28)
#define VEPU_REG_OUTPUT_SWAP16 BIT(27)
#define VEPU_REG_OUTPUT_SWAP32 BIT(26)

19
mpp/hal/vpu/h264e/hal_h264e_vepu2_v2.c
View File

@@ -489,25 +489,12 @@ static MPP_RET hal_h264e_vepu2_gen_regs_v2(void *hal, HalEncTask *task)
val = VEPU_REG_ZERO_MV_FAVOR_D2(10);
H264E_HAL_SET_REG(reg, VEPU_REG_MVC_RELATE, val);
if (hw_prep->src_fmt < H264E_VPU_CSP_RGB565) {
val = VEPU_REG_OUTPUT_SWAP32
| VEPU_REG_OUTPUT_SWAP16
| VEPU_REG_OUTPUT_SWAP8
| VEPU_REG_INPUT_SWAP8
| VEPU_REG_INPUT_SWAP16
| VEPU_REG_INPUT_SWAP32;
} else if (hw_prep->src_fmt == H264E_VPU_CSP_ARGB8888) {
val = VEPU_REG_OUTPUT_SWAP32
| VEPU_REG_OUTPUT_SWAP16
| VEPU_REG_OUTPUT_SWAP8
| VEPU_REG_INPUT_SWAP32;
} else {
val = VEPU_REG_OUTPUT_SWAP32
| VEPU_REG_OUTPUT_SWAP16
| VEPU_REG_OUTPUT_SWAP8
| VEPU_REG_INPUT_SWAP16
| VEPU_REG_INPUT_SWAP32;
}
| VEPU_REG_INPUT_SWAP8_(hw_prep->swap_8_in)
| VEPU_REG_INPUT_SWAP16_(hw_prep->swap_16_in)
| VEPU_REG_INPUT_SWAP32_(hw_prep->swap_32_in);
H264E_HAL_SET_REG(reg, VEPU_REG_DATA_ENDIAN, val);
val = VEPU_REG_PPS_ID(pps->pps_id)

69
mpp/hal/vpu/h264e/hal_h264e_vepu_v2.c
View File

@@ -21,6 +21,8 @@
#include "mpp_common.h"
#include "mpp_buffer.h"
#include "vepu_common.h"
#include "h264e_slice.h"
#include "hal_h264e_debug.h"
#include "hal_h264e_com.h"
@@ -301,41 +303,11 @@ static H264eVpuCsp fmt_to_vepu_csp_yuv[MPP_FMT_YUV_BUTT] = {
H264E_VPU_CSP_NONE, // MPP_FMT_YUV444SP /* YYYY... UVUVUVUV... */
};
static H264eVpuCsp fmt_to_vepu_csp_rgb[MPP_FMT_RGB_BUTT - MPP_FRAME_FMT_RGB] = {
H264E_VPU_CSP_RGB565, // MPP_FMT_RGB565 /* 16-bit RGB */
H264E_VPU_CSP_RGB565, // MPP_FMT_BGR565 /* 16-bit RGB */
H264E_VPU_CSP_RGB555, // MPP_FMT_RGB555 /* 15-bit RGB */
H264E_VPU_CSP_RGB555, // MPP_FMT_BGR555 /* 15-bit RGB */
H264E_VPU_CSP_RGB444, // MPP_FMT_RGB444 /* 12-bit RGB */
H264E_VPU_CSP_RGB444, // MPP_FMT_BGR444 /* 12-bit RGB */
H264E_VPU_CSP_RGB888, // MPP_FMT_RGB888 /* 24-bit RGB */
H264E_VPU_CSP_RGB888, // MPP_FMT_BGR888 /* 24-bit RGB */
H264E_VPU_CSP_RGB101010, // MPP_FMT_RGB101010 /* 30-bit RGB */
H264E_VPU_CSP_RGB101010, // MPP_FMT_BGR101010 /* 30-bit RGB */
H264E_VPU_CSP_ARGB8888, // MPP_FMT_ARGB8888 /* 32-bit RGB */
H264E_VPU_CSP_ARGB8888, // MPP_FMT_ABGR8888 /* 32-bit RGB */
};
static RK_S32 fmt_to_vepu_mask_msb[MPP_FMT_RGB_BUTT - MPP_FRAME_FMT_RGB][3] = {
// R G B // mask msb position
{ 15, 10, 4, }, // MPP_FMT_RGB565 /* 16-bit RGB */
{ 4, 10, 15, }, // MPP_FMT_BGR565 /* 16-bit RGB */
{ 14, 9, 4, }, // MPP_FMT_RGB555 /* 15-bit RGB */
{ 4, 9, 14, }, // MPP_FMT_BGR555 /* 15-bit RGB */
{ 11, 7, 3, }, // MPP_FMT_RGB444 /* 12-bit RGB */
{ 3, 7, 11, }, // MPP_FMT_BGR444 /* 12-bit RGB */
{ 23, 15, 7, }, // MPP_FMT_RGB888 /* 24-bit RGB */
{ 7, 15, 23, }, // MPP_FMT_BGR888 /* 24-bit RGB */
{ 29, 19, 9, }, // MPP_FMT_RGB101010 /* 30-bit RGB */
{ 9, 19, 29, }, // MPP_FMT_BGR101010 /* 30-bit RGB */
{ 23, 15, 7, }, // MPP_FMT_ARGB8888 /* 32-bit RGB */
{ 7, 15, 23, }, // MPP_FMT_ABGR8888 /* 32-bit RGB */
};
MPP_RET h264e_vepu_prep_setup(HalH264eVepuPrep *prep, MppEncPrepCfg *cfg)
{
MPP_RET ret = MPP_OK;
MppFrameFormat format = cfg->format;
VepuFormatCfg fmt_cfg;
hal_h264e_dbg_buffer("enter\n");
@@ -343,16 +315,24 @@ MPP_RET h264e_vepu_prep_setup(HalH264eVepuPrep *prep, MppEncPrepCfg *cfg)
prep->src_w = cfg->width;
prep->src_h = cfg->height;
if (!get_vepu_fmt(&fmt_cfg, format)) {
prep->r_mask_msb = fmt_cfg.r_mask;
prep->g_mask_msb = fmt_cfg.g_mask;
prep->b_mask_msb = fmt_cfg.b_mask;
prep->swap_8_in = fmt_cfg.swap_8_in;
prep->swap_16_in = fmt_cfg.swap_16_in;
prep->swap_32_in = fmt_cfg.swap_32_in;
prep->src_fmt = fmt_cfg.format;
} else {
prep->src_fmt = H264E_VPU_CSP_NONE;
}
if (format < MPP_FRAME_FMT_RGB) {
// YUV case
prep->src_fmt = fmt_to_vepu_csp_yuv[format];
if (prep->src_fmt == H264E_VPU_CSP_NONE) {
mpp_err("vepu do not support input frame format %d\n", format);
ret = MPP_NOK;
}
prep->r_mask_msb = 0;
prep->g_mask_msb = 0;
prep->b_mask_msb = 0;
prep->color_conversion_coeff_a = 0;
prep->color_conversion_coeff_b = 0;
@@ -360,19 +340,11 @@ MPP_RET h264e_vepu_prep_setup(HalH264eVepuPrep *prep, MppEncPrepCfg *cfg)
prep->color_conversion_coeff_e = 0;
prep->color_conversion_coeff_f = 0;
} else {
// RGB case
RK_S32 rgb_idx = format - MPP_FRAME_FMT_RGB;
mpp_assert(rgb_idx < MPP_FMT_RGB_BUTT - MPP_FRAME_FMT_RGB);
prep->src_fmt = fmt_to_vepu_csp_rgb[rgb_idx];
if (prep->src_fmt == H264E_VPU_CSP_NONE) {
mpp_err("vepu do not support input frame format %d\n", format);
ret = MPP_NOK;
}
prep->r_mask_msb = fmt_to_vepu_mask_msb[rgb_idx][0];
prep->g_mask_msb = fmt_to_vepu_mask_msb[rgb_idx][1];
prep->b_mask_msb = fmt_to_vepu_mask_msb[rgb_idx][2];
switch (cfg->color) {
case MPP_FRAME_SPC_RGB : {
@@ -415,7 +387,7 @@ MPP_RET h264e_vepu_prep_setup(HalH264eVepuPrep *prep, MppEncPrepCfg *cfg)
prep->offset_cb = 0;
prep->offset_cr = 0;
switch (format) {
switch (format & MPP_FRAME_FMT_MASK) {
case MPP_FMT_YUV420SP : {
prep->offset_cb = hor_stride * ver_stride;
prep->size_y = hor_stride * MPP_ALIGN(prep->src_h, 16);
@@ -445,6 +417,10 @@ MPP_RET h264e_vepu_prep_setup(HalH264eVepuPrep *prep, MppEncPrepCfg *cfg)
cfg->hor_stride, cfg->width);
} break;
case MPP_FMT_RGB565 :
case MPP_FMT_BGR565 :
case MPP_FMT_RGB555 :
case MPP_FMT_BGR555 :
case MPP_FMT_RGB444 :
case MPP_FMT_BGR444 : {
prep->size_y = hor_stride * 2 * MPP_ALIGN(prep->src_h, 16);
prep->size_c = 0;
@@ -453,10 +429,11 @@ MPP_RET h264e_vepu_prep_setup(HalH264eVepuPrep *prep, MppEncPrepCfg *cfg)
mpp_log_f("vepu only support matched 16bit pixel horizontal stride %d vs width %d\n",
cfg->hor_stride, cfg->width);
} break;
case MPP_FMT_BGR888 :
case MPP_FMT_RGB888 :
case MPP_FMT_ARGB8888 :
case MPP_FMT_ABGR8888 :
case MPP_FMT_RGBA8888 :
case MPP_FMT_BGRA8888 :
case MPP_FMT_RGB101010 :
case MPP_FMT_BGR101010 : {
prep->size_y = hor_stride * 4 * MPP_ALIGN(prep->src_h, 16);
prep->size_c = 0;

9
mpp/hal/vpu/h264e/hal_h264e_vepu_v2.h
View File

@@ -40,9 +40,12 @@ typedef struct HalH264eVepuInput_t {
RK_U32 offset_cb;
RK_U32 offset_cr;
RK_S32 r_mask_msb;
RK_S32 g_mask_msb;
RK_S32 b_mask_msb;
RK_U8 r_mask_msb;
RK_U8 g_mask_msb;
RK_U8 b_mask_msb;
RK_U8 swap_8_in;
RK_U8 swap_16_in;
RK_U8 swap_32_in;
RK_U32 color_conversion_coeff_a;
RK_U32 color_conversion_coeff_b;

4
mpp/hal/vpu/jpege/CMakeLists.txt
View File

@@ -1,6 +1,8 @@
# vim: syntax=cmake
# hal jpeg reg
include_directories(../common/)
set(HAL_JPEGE_HDR
)
@@ -20,4 +22,4 @@ add_library(${HAL_JPEGE} STATIC
)
set_target_properties(${HAL_JPEGE} PROPERTIES FOLDER "mpp/hal")
target_link_libraries(${HAL_JPEGE} mpp_base)
target_link_libraries(${HAL_JPEGE} hal_vepu_common mpp_base)

109
mpp/hal/vpu/jpege/hal_jpege_vepu1.c
View File

@@ -27,6 +27,8 @@
#include "mpp_hal.h"
#include "vepu_common.h"
#include "hal_jpege_debug.h"
#include "hal_jpege_api.h"
#include "hal_jpege_hdr.h"
@@ -166,10 +168,8 @@ MPP_RET hal_jpege_vepu1_gen_regs(void *hal, HalTaskInfo *task)
RK_S32 bitpos;
RK_S32 bytepos;
RK_U32 deflt_cfg;
RK_U32 r_mask = 0;
RK_U32 g_mask = 0;
RK_U32 b_mask = 0;
RK_U32 x_fill = 0;
VepuFormatCfg fmt_cfg;
syntax->width = width;
syntax->height = height;
@@ -213,82 +213,13 @@ MPP_RET hal_jpege_vepu1_gen_regs(void *hal, HalTaskInfo *task)
((0 & (1)) << 6) |
((0 & (1)) << 5) |
((1 & (1)) << 4) |
((1 & (1)) << 3) |
((0 & (1)) << 3) |
((1 & (1)) << 1);
switch (fmt) {
case MPP_FMT_YUV420P : {
val32 = 0;
r_mask = 0;
g_mask = 0;
b_mask = 0;
} break;
case MPP_FMT_YUV420SP : {
val32 = 1;
r_mask = 0;
g_mask = 0;
b_mask = 0;
} break;
case MPP_FMT_YUV422_YUYV : {
val32 = 2;
r_mask = 0;
g_mask = 0;
b_mask = 0;
} break;
case MPP_FMT_YUV422_UYVY : {
val32 = 3;
r_mask = 0;
g_mask = 0;
b_mask = 0;
} break;
case MPP_FMT_RGB565 : {
val32 = 4;
r_mask = 4;
g_mask = 10;
b_mask = 15;
} break;
case MPP_FMT_RGB444 : {
val32 = 5;
r_mask = 3;
g_mask = 7;
b_mask = 11;
} break;
case MPP_FMT_RGB888 : {
val32 = 7;
r_mask = 7;
g_mask = 15;
b_mask = 23;
} break;
case MPP_FMT_BGR888 : {
val32 = 7;
r_mask = 23;
g_mask = 15;
b_mask = 7;
} break;
case MPP_FMT_RGB101010 : {
val32 = 8;
} break;
default : {
mpp_err_f("invalid input format %d\n", fmt);
val32 = 0;
} break;
}
if (val32 < 4) {
regs[2] = deflt_cfg |
((1 & (1)) << 14) |
((1 & (1)) << 2) |
(1 & (1));
} else if (val32 < 7) {
regs[2] = deflt_cfg |
((1 & (1)) << 14) |
((0 & (1)) << 2) |
(0 & (1));
} else {
regs[2] = deflt_cfg |
((0 & (1)) << 14) |
((0 & (1)) << 2) |
(0 & (1));
if (!get_vepu_fmt(&fmt_cfg, fmt)) {
regs[2] = deflt_cfg | (fmt_cfg.swap_8_in & 1) |
(fmt_cfg.swap_32_in & 1) << 2 |
(fmt_cfg.swap_16_in & 1) << 14;
}
regs[5] = mpp_buffer_get_fd(output) + (bytepos << 10);
@@ -305,7 +236,7 @@ MPP_RET hal_jpege_vepu1_gen_regs(void *hal, HalTaskInfo *task)
(prep->hor_stride << 12) |
(x_fill << 10) |
((ver_stride - height) << 6) |
(val32 << 2) | (0);
(fmt_cfg.format << 2) | (0);
{
RK_S32 left_byte = bytepos & 0x7;
@@ -391,9 +322,9 @@ MPP_RET hal_jpege_vepu1_gen_regs(void *hal, HalTaskInfo *task)
regs[53] = coeffA | (coeffB << 16);
regs[54] = coeffC | (coeffE << 16);
regs[55] = ((r_mask & 0x1f) << 26) |
((g_mask & 0x1f) << 21) |
((b_mask & 0x1f) << 16) | coeffF;
regs[55] = ((fmt_cfg.b_mask & 0x1f) << 26) |
((fmt_cfg.g_mask & 0x1f) << 21) |
((fmt_cfg.r_mask & 0x1f) << 16) | coeffF;
}
regs[14] |= 0x001;
@@ -532,6 +463,7 @@ MPP_RET hal_jpege_vepu1_control(void *hal, MpiCmd cmd, void *param)
switch (cmd) {
case MPP_ENC_SET_PREP_CFG : {
MppEncPrepCfg *cfg = (MppEncPrepCfg *)param;
MppFrameFormat fmt = cfg->format & MPP_FRAME_FMT_MASK;
if (cfg->width < 16 && cfg->width > 8192) {
mpp_err("jpege: invalid width %d is not in range [16..8192]\n", cfg->width);
ret = MPP_NOK;
@@ -542,13 +474,14 @@ MPP_RET hal_jpege_vepu1_control(void *hal, MpiCmd cmd, void *param)
ret = MPP_NOK;
}
if (cfg->format != MPP_FMT_YUV420SP &&
cfg->format != MPP_FMT_YUV420P &&
cfg->format != MPP_FMT_YUV422SP_VU &&
cfg->format != MPP_FMT_YUV422_YUYV &&
cfg->format != MPP_FMT_YUV422_UYVY &&
cfg->format != MPP_FMT_RGB888 &&
cfg->format != MPP_FMT_BGR888) {
if ((fmt != MPP_FMT_YUV420SP &&
fmt != MPP_FMT_YUV420P &&
fmt != MPP_FMT_YUV422SP_VU &&
fmt != MPP_FMT_YUV422_YUYV &&
fmt != MPP_FMT_YUV422_UYVY &&
fmt < MPP_FRAME_FMT_RGB) ||
fmt == MPP_FMT_RGB888 ||
fmt == MPP_FMT_BGR888) {
mpp_err("jpege: invalid format %d is not supportted\n", cfg->format);
ret = MPP_NOK;
}

93
mpp/hal/vpu/jpege/hal_jpege_vepu1_v2.c
View File

@@ -27,6 +27,8 @@
#include "mpp_enc_hal.h"
#include "vepu_common.h"
#include "hal_jpege_debug.h"
#include "hal_jpege_api.h"
#include "hal_jpege_hdr.h"
@@ -170,10 +172,8 @@ static MPP_RET hal_jpege_vepu1_gen_regs_v2(void *hal, HalEncTask *task)
RK_S32 bitpos;
RK_S32 bytepos;
RK_U32 deflt_cfg;
RK_U32 r_mask = 0;
RK_U32 g_mask = 0;
RK_U32 b_mask = 0;
RK_U32 x_fill = 0;
VepuFormatCfg fmt_cfg;
//hor_stride must be align with 8, and ver_stride mus align with 2
if ((syntax->hor_stride & 0x7) || (syntax->ver_stride & 0x1)) {
@@ -216,79 +216,10 @@ static MPP_RET hal_jpege_vepu1_gen_regs_v2(void *hal, HalEncTask *task)
((1 & (1)) << 3) |
((1 & (1)) << 1);
switch (fmt) {
case MPP_FMT_YUV420P : {
val32 = 0;
r_mask = 0;
g_mask = 0;
b_mask = 0;
} break;
case MPP_FMT_YUV420SP : {
val32 = 1;
r_mask = 0;
g_mask = 0;
b_mask = 0;
} break;
case MPP_FMT_YUV422_YUYV : {
val32 = 2;
r_mask = 0;
g_mask = 0;
b_mask = 0;
} break;
case MPP_FMT_YUV422_UYVY : {
val32 = 3;
r_mask = 0;
g_mask = 0;
b_mask = 0;
} break;
case MPP_FMT_RGB565 : {
val32 = 4;
r_mask = 4;
g_mask = 10;
b_mask = 15;
} break;
case MPP_FMT_RGB444 : {
val32 = 5;
r_mask = 3;
g_mask = 7;
b_mask = 11;
} break;
case MPP_FMT_RGB888 : {
val32 = 7;
r_mask = 7;
g_mask = 15;
b_mask = 23;
} break;
case MPP_FMT_BGR888 : {
val32 = 7;
r_mask = 23;
g_mask = 15;
b_mask = 7;
} break;
case MPP_FMT_RGB101010 : {
val32 = 8;
} break;
default : {
mpp_err_f("invalid input format %d\n", fmt);
val32 = 0;
} break;
}
if (val32 < 4) {
regs[2] = deflt_cfg |
((1 & (1)) << 14) |
((1 & (1)) << 2) |
(1 & (1));
} else if (val32 < 7) {
regs[2] = deflt_cfg |
((1 & (1)) << 14) |
((0 & (1)) << 2) |
(0 & (1));
} else {
regs[2] = deflt_cfg |
((0 & (1)) << 14) |
((0 & (1)) << 2) |
(0 & (1));
if (!get_vepu_fmt(&fmt_cfg, fmt)) {
regs[2] = deflt_cfg | (fmt_cfg.swap_8_in & 1) |
(fmt_cfg.swap_32_in & 1) << 2 |
(fmt_cfg.swap_16_in & 1) << 14;
}
regs[5] = mpp_buffer_get_fd(output) + (bytepos << 10);
@@ -302,10 +233,10 @@ static MPP_RET hal_jpege_vepu1_gen_regs_v2(void *hal, HalEncTask *task)
regs[15] = (0 << 29) |
(0 << 26) |
(syntax->hor_stride << 12) |
(MPP_ALIGN(width, 8) << 12) |
(x_fill << 10) |
((ver_stride - height) << 6) |
(val32 << 2) | (0);
(fmt_cfg.format << 2) | (0);
{
RK_S32 left_byte = bytepos & 0x7;
@@ -391,9 +322,9 @@ static MPP_RET hal_jpege_vepu1_gen_regs_v2(void *hal, HalEncTask *task)
regs[53] = coeffA | (coeffB << 16);
regs[54] = coeffC | (coeffE << 16);
regs[55] = ((r_mask & 0x1f) << 26) |
((g_mask & 0x1f) << 21) |
((b_mask & 0x1f) << 16) | coeffF;
regs[55] = ((fmt_cfg.b_mask & 0x1f) << 26) |
((fmt_cfg.g_mask & 0x1f) << 21) |
((fmt_cfg.r_mask & 0x1f) << 16) | coeffF;
}
regs[14] |= 0x001;

102
mpp/hal/vpu/jpege/hal_jpege_vepu2.c
View File

@@ -27,6 +27,8 @@
#include "mpp_hal.h"
#include "vepu_common.h"
#include "hal_jpege_debug.h"
#include "hal_jpege_api.h"
#include "hal_jpege_hdr.h"
@@ -158,10 +160,8 @@ MPP_RET hal_jpege_vepu2_gen_regs(void *hal, HalTaskInfo *task)
RK_U32 val32;
RK_S32 bitpos;
RK_S32 bytepos;
RK_U32 r_mask = 0;
RK_U32 g_mask = 0;
RK_U32 b_mask = 0;
RK_U32 x_fill = 0;
VepuFormatCfg fmt_cfg;
syntax->width = width;
syntax->height = height;
@@ -235,61 +235,7 @@ MPP_RET hal_jpege_vepu2_gen_regs(void *hal, HalTaskInfo *task)
regs[60] = (((bytepos & 7) * 8) << 16) |
(x_fill << 4) |
(ver_stride - height);
regs[61] = prep->hor_stride;
switch (fmt) {
case MPP_FMT_YUV420P : {
val32 = 0;
r_mask = g_mask = b_mask = 0;
} break;
case MPP_FMT_YUV420SP : {
val32 = 1;
r_mask = g_mask = b_mask = 0;
} break;
case MPP_FMT_YUV422_YUYV : {
val32 = 2;
r_mask = g_mask = b_mask = 0;
} break;
case MPP_FMT_YUV422_UYVY : {
val32 = 3;
r_mask = g_mask = b_mask = 0;
} break;
case MPP_FMT_RGB565 : {
val32 = 4;
r_mask = 15;
g_mask = 10;
b_mask = 4;
} break;
case MPP_FMT_RGB444 : {
val32 = 6;
r_mask = 11;
g_mask = 7;
b_mask = 3;
} break;
case MPP_FMT_RGB888 : {
val32 = 7;
r_mask = 7;
g_mask = 15;
b_mask = 23;
} break;
case MPP_FMT_BGR888 : {
val32 = 7;
r_mask = 23;
g_mask = 15;
b_mask = 7;
} break;
case MPP_FMT_RGB101010 : {
val32 = 8;
r_mask = 29;
g_mask = 19;
b_mask = 9;
} break;
default : {
mpp_err_f("invalid input format %d\n", fmt);
val32 = 0;
} break;
}
regs[74] = val32 << 4;
regs[61] = MPP_ALIGN(width, 8);
regs[77] = mpp_buffer_get_fd(output) + (bytepos << 10);
@@ -349,28 +295,20 @@ MPP_RET hal_jpege_vepu2_gen_regs(void *hal, HalTaskInfo *task)
regs[97] = coeffF;
}
/* TODO: 98 RGB bit mask */
regs[98] = (r_mask & 0x1f) << 16 |
(g_mask & 0x1f) << 8 |
(b_mask & 0x1f);
regs[103] = (hor_stride >> 4) << 8 |
(ver_stride >> 4) << 20 |
(1 << 6) | /* intra coding */
(2 << 4) | /* format jpeg */
1; /* encoder start */
if (!get_vepu_fmt(&fmt_cfg, fmt)) {
regs[74] = fmt_cfg.format << 4;
/* input byte swap configure */
regs[105] = 7 << 26;
if (fmt < MPP_FMT_RGB565) {
// YUV format
regs[105] |= (7 << 29);
} else if (fmt < MPP_FMT_RGB888) {
// 16bit RGB
regs[105] |= (2 << 29);
} else {
// 32bit RGB
regs[105] |= (0 << 29);
regs[98] = (fmt_cfg.b_mask & 0x1f) << 16 |
(fmt_cfg.g_mask & 0x1f) << 8 |
(fmt_cfg.r_mask & 0x1f);
regs[105] = 7 << 26 | (fmt_cfg.swap_32_in & 1) << 29 |
(fmt_cfg.swap_16_in & 1) << 30 |
(fmt_cfg.swap_8_in & 1) << 31;
}
/* encoder interrupt */
@@ -510,6 +448,7 @@ MPP_RET hal_jpege_vepu2_control(void *hal, MpiCmd cmd, void *param)
switch (cmd) {
case MPP_ENC_SET_PREP_CFG : {
MppEncPrepCfg *cfg = (MppEncPrepCfg *)param;
MppFrameFormat fmt = cfg->format & MPP_FRAME_FMT_MASK;
if (cfg->width < 16 && cfg->width > 8192) {
mpp_err("jpege: invalid width %d is not in range [16..8192]\n", cfg->width);
ret = MPP_NOK;
@@ -520,13 +459,14 @@ MPP_RET hal_jpege_vepu2_control(void *hal, MpiCmd cmd, void *param)
ret = MPP_NOK;
}
if (cfg->format != MPP_FMT_YUV420SP &&
cfg->format != MPP_FMT_YUV420P &&
cfg->format != MPP_FMT_YUV422SP_VU &&
cfg->format != MPP_FMT_YUV422_YUYV &&
cfg->format != MPP_FMT_YUV422_UYVY &&
cfg->format != MPP_FMT_RGB888 &&
cfg->format != MPP_FMT_BGR888) {
if ((fmt != MPP_FMT_YUV420SP &&
fmt != MPP_FMT_YUV420P &&
fmt != MPP_FMT_YUV422SP_VU &&
fmt != MPP_FMT_YUV422_YUYV &&
fmt != MPP_FMT_YUV422_UYVY &&
fmt < MPP_FRAME_FMT_RGB) ||
fmt == MPP_FMT_RGB888 ||
fmt == MPP_FMT_BGR888) {
mpp_err("jpege: invalid format %d is not supportted\n", cfg->format);
ret = MPP_NOK;
}

84
mpp/hal/vpu/jpege/hal_jpege_vepu2_v2.c
View File

@@ -27,6 +27,8 @@
#include "mpp_enc_hal.h"
#include "vepu_common.h"
#include "hal_jpege_debug.h"
#include "hal_jpege_api.h"
#include "hal_jpege_hdr.h"
@@ -162,10 +164,8 @@ MPP_RET hal_jpege_vepu2_gen_regs_v2(void *hal, HalEncTask *task)
RK_U32 val32;
RK_S32 bitpos;
RK_S32 bytepos;
RK_U32 r_mask = 0;
RK_U32 g_mask = 0;
RK_U32 b_mask = 0;
RK_U32 x_fill = 0;
VepuFormatCfg fmt_cfg;
//hor_stride must be align with 8, and ver_stride mus align with 2
if ((syntax->hor_stride & 0x7) || (syntax->ver_stride & 0x1)) {
@@ -237,60 +237,6 @@ MPP_RET hal_jpege_vepu2_gen_regs_v2(void *hal, HalEncTask *task)
(ver_stride - height);
regs[61] = syntax->hor_stride;
switch (fmt) {
case MPP_FMT_YUV420P : {
val32 = 0;
r_mask = g_mask = b_mask = 0;
} break;
case MPP_FMT_YUV420SP : {
val32 = 1;
r_mask = g_mask = b_mask = 0;
} break;
case MPP_FMT_YUV422_YUYV : {
val32 = 2;
r_mask = g_mask = b_mask = 0;
} break;
case MPP_FMT_YUV422_UYVY : {
val32 = 3;
r_mask = g_mask = b_mask = 0;
} break;
case MPP_FMT_RGB565 : {
val32 = 4;
r_mask = 15;
g_mask = 10;
b_mask = 4;
} break;
case MPP_FMT_RGB444 : {
val32 = 6;
r_mask = 11;
g_mask = 7;
b_mask = 3;
} break;
case MPP_FMT_RGB888 : {
val32 = 7;
r_mask = 7;
g_mask = 15;
b_mask = 23;
} break;
case MPP_FMT_BGR888 : {
val32 = 7;
r_mask = 23;
g_mask = 15;
b_mask = 7;
} break;
case MPP_FMT_RGB101010 : {
val32 = 8;
r_mask = 29;
g_mask = 19;
b_mask = 9;
} break;
default : {
mpp_err_f("invalid input format %d\n", fmt);
val32 = 0;
} break;
}
regs[74] = val32 << 4;
regs[77] = mpp_buffer_get_fd(output) + (bytepos << 10);
/* 95 - 97 color conversion parameter */
@@ -349,28 +295,20 @@ MPP_RET hal_jpege_vepu2_gen_regs_v2(void *hal, HalEncTask *task)
regs[97] = coeffF;
}
/* TODO: 98 RGB bit mask */
regs[98] = (r_mask & 0x1f) << 16 |
(g_mask & 0x1f) << 8 |
(b_mask & 0x1f);
regs[103] = (hor_stride >> 4) << 8 |
(ver_stride >> 4) << 20 |
(1 << 6) | /* intra coding */
(2 << 4) | /* format jpeg */
1; /* encoder start */
/* input byte swap configure */
regs[105] = 7 << 26;
if (fmt < MPP_FMT_RGB565) {
// YUV format
regs[105] |= (7 << 29);
} else if (fmt < MPP_FMT_RGB888) {
// 16bit RGB
regs[105] |= (2 << 29);
} else {
// 32bit RGB
regs[105] |= (0 << 29);
if (!get_vepu_fmt(&fmt_cfg, fmt)) {
regs[74] = fmt_cfg.format << 4;
regs[98] = (fmt_cfg.b_mask & 0x1f) << 16 |
(fmt_cfg.g_mask & 0x1f) << 8 |
(fmt_cfg.r_mask & 0x1f);
regs[105] = 7 << 26 | (fmt_cfg.swap_32_in & 1) << 29 |
(fmt_cfg.swap_16_in & 1) << 30 |
(fmt_cfg.swap_8_in & 1) << 31;
}
/* encoder interrupt */

2
test/mpi_enc_multi_test.c
View File

@@ -941,7 +941,7 @@ static RK_S32 mpi_enc_test_parse_options(int argc, char **argv, MpiEncTestCmd* c
case 'f':
if (next) {
cmd->format = (MppFrameFormat)atoi(next);
err = ((cmd->format >= MPP_FMT_YUV_BUTT && cmd->format < MPP_FRAME_FMT_RGB) ||
err = (!MPP_FRAME_FMT_IS_LE(cmd->format)) && ((cmd->format >= MPP_FMT_YUV_BUTT && cmd->format < MPP_FRAME_FMT_RGB) ||
cmd->format >= MPP_FMT_RGB_BUTT);
}

4
test/mpi_enc_test.c
View File

@@ -173,6 +173,10 @@ MPP_RET test_ctx_init(MpiEncTestData **data, MpiEncTestArgs *cmd)
case MPP_FMT_YUV422_VYUY :
case MPP_FMT_YUV422P :
case MPP_FMT_YUV422SP :
case MPP_FMT_RGB444 :
case MPP_FMT_BGR444 :
case MPP_FMT_RGB555 :
case MPP_FMT_BGR555 :
case MPP_FMT_RGB565 :
case MPP_FMT_BGR565 : {
p->frame_size = MPP_ALIGN(p->hor_stride, 64) * MPP_ALIGN(p->ver_stride, 64) * 2;

8
utils/mpi_enc_utils.c
View File

@@ -32,7 +32,7 @@ RK_S32 mpi_enc_width_default_stride(RK_S32 width, MppFrameFormat fmt)
{
RK_S32 stride = 0;
switch (fmt) {
switch (fmt & MPP_FRAME_FMT_MASK) {
case MPP_FMT_YUV420SP :
case MPP_FMT_YUV420P : {
stride = MPP_ALIGN(width, 16);
@@ -41,6 +41,10 @@ RK_S32 mpi_enc_width_default_stride(RK_S32 width, MppFrameFormat fmt)
case MPP_FMT_YUV422SP:
case MPP_FMT_RGB565:
case MPP_FMT_BGR565:
case MPP_FMT_RGB555:
case MPP_FMT_BGR555:
case MPP_FMT_RGB444:
case MPP_FMT_BGR444:
case MPP_FMT_YUV422_YUYV :
case MPP_FMT_YUV422_YVYU :
case MPP_FMT_YUV422_UYVY :
@@ -178,7 +182,7 @@ MPP_RET mpi_enc_test_cmd_update_by_args(MpiEncTestArgs* cmd, int argc, char **ar
/* decimal value, use atoi */
cmd->format = (MppFrameFormat)atoi(next);
}
ret = ((cmd->format >= MPP_FMT_YUV_BUTT && cmd->format < MPP_FRAME_FMT_RGB) ||
ret = (!MPP_FRAME_FMT_IS_LE(cmd->format)) && ((cmd->format >= MPP_FMT_YUV_BUTT && cmd->format < MPP_FRAME_FMT_RGB) ||
cmd->format >= MPP_FMT_RGB_BUTT);
}

10
utils/utils.c
View File

@@ -342,7 +342,7 @@ MPP_RET read_image(RK_U8 *buf, FILE *fp, RK_U32 width, RK_U32 height,
return MPP_OK;
}
switch (fmt) {
switch (fmt & MPP_FRAME_FMT_MASK) {
case MPP_FMT_YUV420SP : {
for (row = 0; row < height; row++) {
read_size = fread(buf_y + row * hor_stride, 1, width, fp);
@@ -388,11 +388,17 @@ MPP_RET read_image(RK_U8 *buf, FILE *fp, RK_U32 width, RK_U32 height,
case MPP_FMT_ARGB8888 :
case MPP_FMT_ABGR8888 :
case MPP_FMT_BGRA8888 :
case MPP_FMT_RGBA8888: {
case MPP_FMT_RGBA8888 :
case MPP_FMT_RGB101010 :
case MPP_FMT_BGR101010 : {
ret = read_with_pixel_width(buf_y, width, height, hor_stride, 4, fp);
} break;
case MPP_FMT_YUV422P :
case MPP_FMT_YUV422SP :
case MPP_FMT_BGR444 :
case MPP_FMT_RGB444 :
case MPP_FMT_RGB555 :
case MPP_FMT_BGR555 :
case MPP_FMT_RGB565 :
case MPP_FMT_BGR565 :
case MPP_FMT_YUV422_YUYV :