diff --git a/mpp/base/mpp_sys_cfg.c b/mpp/base/mpp_sys_cfg.c
index 04832339..0b5562c8 100644
--- a/mpp/base/mpp_sys_cfg.c
+++ b/mpp/base/mpp_sys_cfg.c
@@ -468,6 +468,7 @@ MPP_RET mpp_sys_dec_buf_chk_proc(MppSysDecBufChkCfg *cfg)
         aligned_height = cfg->v_stride ? cfg->v_stride : aligned_height;
 
         switch (type) {
+        case MPP_VIDEO_CodingAVC : /* ALIGN_64: for Hi10p/Hi422p + RGA3 use case */
         case MPP_VIDEO_CodingHEVC : {
             aligned_byte = mpp_sys_cfg_align(SYS_CFG_ALIGN_64, aligned_pixel_byte);
         } break;
@@ -479,8 +480,8 @@ MPP_RET mpp_sys_dec_buf_chk_proc(MppSysDecBufChkCfg *cfg)
                 aligned_byte = mpp_sys_cfg_align(SYS_CFG_ALIGN_256_ODD, aligned_pixel_byte);
         } break;
         case MPP_VIDEO_CodingAV1 : {
-            if (soc_type == ROCKCHIP_SOC_RK3588)
-                aligned_byte = mpp_sys_cfg_align(SYS_CFG_ALIGN_16, aligned_pixel_byte);
+            if (soc_type == ROCKCHIP_SOC_RK3588) /* ALIGN_64: for 10bit Main + RGA3 use case */
+                aligned_byte = mpp_sys_cfg_align(SYS_CFG_ALIGN_64, aligned_pixel_byte);
             else
                 aligned_byte = mpp_sys_cfg_align(SYS_CFG_ALIGN_128, aligned_pixel_byte);
         } break;
@@ -494,7 +495,7 @@ MPP_RET mpp_sys_dec_buf_chk_proc(MppSysDecBufChkCfg *cfg)
          * NOTE: rk3576 use 128 odd plus 64 for all non jpeg format
          * all the other socs use 256 odd on larger than 1080p
          */
-        if ((aligned_byte > 1920 || soc_type == ROCKCHIP_SOC_RK3576)
+        if (((aligned_byte * 8 / depth) > 1920 || soc_type == ROCKCHIP_SOC_RK3576)
             && type != MPP_VIDEO_CodingMJPEG) {
             rk_s32 update = 0;